Light emitting diode device having a multilayer composite film including a current spreading layer

Abstract

A light emitting diode (LED) device is described, comprising: a plurality of mesas defining pixels, each mesa comprising a semiconductor layer; an n-contact material in the spaces between each of the plurality of mesas; a dielectric material insulating a p-type layer and the sidewalls of an active region from the metal; and a multilayer composite film on the p-type layer, the multilayer composite film comprising: a current spreading layer on the p-type layer, the current spreading layer having a first portion and a second portion; a dielectric layer on the second portion of the current spreading layer; a via opening defined by the dielectric layer and the sidewalls in the first portion of the current spreading layer; and a p-contact layer in the via opening over the first portion of the current spreading layer, the sidewalls in the dielectric layer, and at least a portion of the dielectric layer.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to light emitting diode (LED) devices and methods of making the same. More particularly, embodiments relate to light emitting diode devices including a multilayer composite film including a current spreading layer. Background Art

[0002] A light-emitting diode (LED) is a semiconductor light source that emits visible light when an electric current flows through it. LEDs combine p-type and n-type semiconductors. LEDs typically use III-V compound semiconductors. III-V compound semiconductors offer stable operation at higher temperatures than devices using other semiconductors. III-V compounds are typically formed on substrates made of sapphire aluminum oxide (Al2O3) or silicon carbide (SiC).

[0003] A variety of emerging display applications—including wearables, head-mounted displays, and large-area displays—require miniaturized chips composed of high-density arrays of microLEDs (µLEDs or uLEDs) with lateral dimensions as low as less than 100µm by 100µm. MicroLEDs (uLEDs), typically about 50µm in diameter or less, are used to create color displays by closely arraying microLEDs encompassing red, blue, and green wavelengths. Generally, two methods have been used to assemble displays constructed from individual microLED dies. The first is a pick-and-place method, which involves picking up each individual blue, green, and red wavelength microLED, aligning each, and then attaching each to a backplane, which is then electrically connected to a driver integrated circuit. Due to the small size of each microLED, this assembly sequence is slow and prone to manufacturing errors. Furthermore, as die size decreases to meet ever-increasing display resolution requirements, an increasing number of dies must be transferred during each pick-and-place operation to fill the required display size. A second approach is to bond a group of LEDs (e.g., a monolithic die or an array or matrix) to a backplane, which eliminates the handling of individual LEDs associated with picking. Therefore, there is a need to develop methods for efficiently preparing groups of LEDs that can then be used for bonding to an LED backplane. Summary of the Invention

[0004] Embodiments of the present disclosure are directed to a light emitting diode (LED) device comprising: a plurality of mesas defining pixels, each mesa comprising a semiconductor layer including an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to its width; an n-contact material in the spaces between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along the sidewalls of the n-type layer; a dielectric material insulating the p-type layer and the sidewalls of the active region from the n-contact material; and a multilayer composite film on the p-type layer. The multilayer composite film comprises: a current spreading layer on the p-type layer, the current spreading layer having a first portion and a second portion; a dielectric layer on the second portion of the current spreading layer; a via opening defined by the dielectric layer and the sidewalls in the first portion of the current spreading layer; and a p-contact layer in the via opening on the first portion of the current spreading layer, the sidewalls in the dielectric layer, and at least a portion of the dielectric layer.

[0005] Additional embodiments are directed to a light emitting diode (LED) device comprising: a plurality of mesas defining pixels, each mesa comprising a semiconductor layer, the semiconductor layer comprising an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to its width; an n-contact material in the spaces between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along a sidewall of the n-type layer; a dielectric material insulating the p-type layer and the sidewalls of the active region from the n-contact material; a multilayer composite film on the p-type layer, the multilayer composite film comprising a first dielectric layer having a first dielectric layer directly on the p-type layer; a current spreading layer having a portion and a second portion, a dielectric layer on the second portion of the current spreading layer, the dielectric layer including sidewalls, wherein the first portion of the current spreading layer defines a via opening, and a p-type contact layer conformal with the dielectric layer and the via opening; a hard mask layer over the p-type contact layer over the second portion of the current spreading layer, the hard mask layer including sidewalls defining the hard mask opening; a liner layer conformally deposited in the hard mask opening and over the p-type contact layer, the p-type contact layer being over the first portion of the current spreading layer and on the sidewalls of the hard mask layer; a p-type metal material plug on the liner layer; a passivation layer on the hard mask layer; and an underbump metallization layer on the passivation layer.

[0006] Another embodiment is directed to a method of manufacturing a light emitting diode (LED) device, comprising: depositing a plurality of semiconductor layers including an n-type layer, an active region, and a p-type layer on a substrate; etching a portion of the semiconductor layer to form a trench defining a pixel and a plurality of mesas, each mesa including a semiconductor layer, and the height of each mesa being less than or equal to its width; depositing a first dielectric material in the trench; depositing an n-contact material in the space between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along a sidewall of the n-type layer, wherein the dielectric material insulates the p-type layer and the sidewalls of the active region from the n-contact material; and, depositing a multilayer composite film on the p-type layer, the multilayer composite film comprising: a current spreading layer on the p-type layer, the current spreading layer having a first portion and a second portion; a dielectric layer on the second portion of the current spreading layer; a through-hole opening defined by the dielectric layer and the sidewalls in the first portion of the current spreading layer; and a p-contact layer in the through-hole opening on the first portion of the current spreading layer, the sidewalls in the dielectric layer, and at least a portion of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To facilitate a detailed understanding of the features of the present disclosure enumerated above, the present disclosure, briefly summarized above, may be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments. The embodiments as described herein are illustrated in the figures of the accompanying drawings by way of example and not limitation, in which like reference numerals indicate similar elements.

[0008] Figure 1A shows a cross-sectional view of a stack of semiconductor layers, metal layers (eg, p-contact layers), and dielectric layers (eg, hard mask layers) deposited on a substrate according to one or more embodiments;

[0009] Figure 1B shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0010] Figure 1C shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0011] Figure 1D shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0012] Figure 1E shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0013] Figure 1F shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0014] Figure 1G shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0015] Figure 1H shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0016] Figure 1I shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0017] Figure 1J shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0018] Figure 1K shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0019] Figure 1L shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0020] Figure 1M shows a cross-sectional view of a stack after steps in fabricating an LED device according to one or more embodiments;

[0021] Figure 1N for the reason Figure 1E The dotted circle 1N indicates Figure 1E an enlarged view of a portion of the stack;

[0022] Figure 1O shows a cross-sectional view of a finished device in a step of manufacturing an LED device according to one or more embodiments;

[0023] Figure 2 shows a top view of an LED array according to one or more embodiments;

[0024] Figure 3A A process flow chart illustrating a manufacturing method according to one or more embodiments is shown;

[0025] Figure 3B A process flow chart illustrating a manufacturing method according to one or more embodiments is shown;

[0026] Figure 3CA process flow chart illustrating a manufacturing method according to one or more embodiments is shown;

[0027] Figure 3D A process flow chart illustrating a manufacturing method according to one or more embodiments is shown;

[0028] Figure 3E A process flow chart illustrating a manufacturing method according to one or more embodiments is shown;

[0029] Figure 3F A process flow chart illustrating a manufacturing method according to one or more embodiments is shown;

[0030] Figure 4 shows a cross-sectional view of an LED device according to one or more embodiments;

[0031] Figure 5A An embodiment for making a pixelated common cathode is shown. Figure 1G variations of ; and

[0032] Figure 5B Shown based on Figure 5A Further processing of the stack Figure 1O variants.

[0033] To facilitate understanding, identical reference numerals have been used, where possible, to denote identical elements common to the figures. The figures are not drawn to scale. For example, the height and width of the countertops are not drawn to scale. DETAILED DESCRIPTION

[0034] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0035] According to one or more embodiments, the term "substrate" as used herein refers to an intermediate or final structure having a surface or portion of a surface on which a process is performed. Additionally, in some embodiments, reference to a substrate also refers to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, according to some embodiments, reference to depositing on a substrate includes depositing on a bare substrate, or depositing on a substrate having one or more films, features, or materials deposited or formed thereon.

[0036] In one or more embodiments, "substrate" means any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. In exemplary embodiments, depending on the application, the substrate surface upon which processing is performed includes materials such as silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable material (such as metals, metal nitrides, Group III-nitrides (e.g., GaN, AlN, InN, and alloys), metal alloys, and other conductive materials). Substrates include, but are not limited to, light emitting diode (LED) devices. In some embodiments, the substrate is exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps is also performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such underlying layers as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has already been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0037] In this disclosure, the terms "wafer" and "substrate" will be used interchangeably. Thus, as used herein, a wafer serves as a substrate for forming the LED devices described herein.

[0038] Reference to a micro-LED (uLED) means a light-emitting diode having one or more characteristic dimensions (e.g., height, width, depth, thickness, etc.) less than 100 microns. In one or more embodiments, one or more of the height, width, depth, and thickness has a value in the range of 2 to 25 microns.

[0039] Figure 1A is a cross-sectional view of a stack of semiconductor layers, metal layers (eg, p-contact layers), and dielectric layers (eg, hard mask layers) deposited on a substrate during steps of fabricating an LED device according to one or more embodiments. Figure 1A , a semiconductor layer 104 is grown on the substrate 102. The semiconductor layer 104 according to one or more embodiments includes an epitaxial layer, a group III nitride layer, or an epitaxial group III nitride layer.

[0040] The substrate can be any substrate known to those skilled in the art. In one or more embodiments, the substrate includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, and the like. In one or more embodiments, the substrate is not patterned prior to the growth of the epitaxial layer(s). Thus, in some embodiments, the substrate is unpatterned and can be considered flat or substantially flat. In other embodiments, the substrate is patterned, such as a patterned sapphire substrate (PSS).

[0041] In one or more embodiments, semiconductor layer 104 comprises a Group III nitride material, and in specific embodiments, an epitaxial Group III nitride material. In some embodiments, the Group III nitride material includes one or more of gallium (Ga), aluminum (Al), and indium (In). Therefore, in some embodiments, semiconductor layer 104 includes one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), and the like. In one or more specific embodiments, semiconductor layer 104 includes a p-type layer, an active region, and an n-type layer. In one or more embodiments, semiconductor layer 104 comprises a Group III nitride material, and in specific embodiments, an epitaxial Group III nitride material. In some embodiments, the Group III nitride material includes one or more of gallium (Ga), aluminum (Al), and indium (In). Therefore, in some embodiments, the semiconductor layer 104 includes one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), etc. In one or more specific embodiments, the semiconductor layer 104 includes a p-type layer, an active region, and an n-type layer.

[0042] In one or more embodiments, the substrate 102 is placed in a metal organic vapor phase epitaxy (MOVPE) reactor for epitaxy of LED device layers to grow the semiconductor layer 104 .

[0043] In one or more embodiments, semiconductor layer 104 includes a stack of undoped Group III nitride material and doped Group III nitride material. Depending on whether a p-type or n-type Group III nitride material is desired, the Group III nitride material may be doped with one or more of silicon (Si), oxygen (O), boron (B), phosphorus (P), germanium (Ge), manganese (Mn), or magnesium (Mg). In a specific embodiment, semiconductor layer 104 includes an n-type layer 104n, an active region 106, and a p-type layer 104p.

[0044] In one or more embodiments, the combined thickness of the semiconductor layer 104 is in a range from about 2µm to about 10µm, wherein the range of about 2µm to about 10µm includes the following ranges: about 2µm to about 9µm, 2µm to about 8µm, 2µm to about 7µm, 2µm to about 6µm, 2µm to about 5µm, 2µm to about 4µm, 2µm to about 3µm, 3µm to about 10µm, 3µm to about 9µm, 3µm to about 8µm, 3µm to about 7µm, 3µm to about 6µm, 3µm to about 5µm. um, 3µm to about 4µm, 4µm to about 10µm, 4µm to about 9µm, 4µm to about 8µm, 4µm to about 7µm, 4µm to about 6µm, 4µm to about 5µm, 5µm to about 10µm, 5µm to about 9µm, 5µm to about 8µm, 5µm to about 7µm, 5µm to about 6µm, 6µm to about 10µm, 6µm to about 9µm, 6µm to about 8µm, 6µm to about 7µm, 7µm to about 10µm, 7µm to about 9µm, or 7µm to about 8µm.

[0045] In one or more embodiments, an active region 106 is formed between the n-type layer 104n and the p-type layer 104p. The active region 106 may include any suitable material known to those skilled in the art. In one or more embodiments, the active region 106 is composed of a III-nitride material multiple quantum well (MQW) and a III-nitride electron blocking layer.

[0046] In one or more embodiments, the p-contact layer 105 and the hardmask layer 108 are deposited on the p-type layer 104p. As shown, the p-contact layer is deposited on the p-type layer 104p, and the hardmask layer 108 is on the p-contact layer. In some embodiments, the p-contact layer 105 is deposited directly on the p-type layer 104p. In other embodiments not shown, one or more additional layers may be located between the p-type layer 104p and the p-contact layer 105. In some embodiments, the hardmask layer 108 is deposited directly on the p-contact layer 105. In other embodiments not shown, one or more additional layers may be located between the hardmask layer 108 and the p-contact layer 105. The hardmask layer 108 and the p-contact layer 105 may be deposited using any suitable technique known to those skilled in the art. In one or more embodiments, the hard mask layer 108 and the p-contact layer 105 are deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0047] As used herein, "sputter deposition" refers to a physical vapor deposition (PVD) method for thin film deposition by sputtering. In sputtering, a material, such as a Group III nitride, is ejected from a target source onto a substrate. This technique is based on ion bombardment of the source material (target). This ion bombardment generates vapor as a purely physical process: sputtering of the target material.

[0048] According to some embodiments herein, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a vapor-phase technique for depositing thin films on substrate surfaces. The ALD process involves exposing a substrate surface, or a portion thereof, to alternating precursors—two or more reactive compounds—to deposit a layer of material on the substrate surface. When exposing the substrate to the alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into a reaction zone of a processing chamber, and the substrate, or a portion thereof, is exposed to the precursors individually.

[0049] According to some embodiments, "chemical vapor deposition (CVD)," as used herein, refers to a process for depositing a thin film of material from a vapor phase by decomposing a chemical onto a substrate surface. In CVD, the substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" means that the exposure of the precursors occurs concurrently or overlaps.

[0050] According to some embodiments, "plasma enhanced atomic layer deposition (PEALD)" as used herein refers to a technique for depositing thin films on substrates. In some examples of PEALD processes relative to thermal ALD processes, materials can be formed from the same chemical precursors, but at a higher deposition rate and lower temperature. Generally speaking, the PEALD process sequentially introduces a reactant gas and a reactant plasma into a process chamber with a substrate in the chamber. A first reactant gas is pulsed in the process chamber and adsorbed onto the substrate surface. Thereafter, a reactant plasma is pulsed into the process chamber and reacts with the first reactant gas to form a deposited material, such as a thin film on the substrate. Similar to thermal ALD processes, a purge step can be performed between the delivery of each reactant.

[0051] According to one or more embodiments, "plasma-enhanced chemical vapor deposition (PECVD)" as used herein refers to a technique for depositing thin films on substrates. In the PECVD process, a source material in the gas or liquid phase—such as a vapor of a gaseous or liquid Group III nitride material—is introduced into a PECVD chamber, where the gaseous or liquid Group III nitride material is entrained in a carrier gas. A plasma-generating gas is also introduced into the chamber. The generation of a plasma in the chamber generates excited free radicals. The excited free radicals chemically bond to the surface of the substrate within the chamber, forming the desired film thereon.

[0052] In one or more embodiments, the hard mask layer 108 may be fabricated using materials and patterning techniques known in the art. In some embodiments, the hard mask layer 108 comprises a metal or a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlO x ), aluminum nitride (AlN), and combinations thereof. Those skilled in the art will recognize that the use of a chemical formula such as SiO to represent silicon oxide does not imply any specific stoichiometric relationship between the elements. This chemical formula merely identifies the primary elements of the film.

[0053] In one or more embodiments, the p-contact layer 105 may include any suitable metal known to those skilled in the art. In one or more embodiments, the p-contact layer 105 includes silver (Ag).

[0054] Figure 1B is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1B The hard mask layer 108 and the p-contact layer 105 are patterned to form at least one opening 110 therein, exposing the top surface 104t of the semiconductor layer 104 and sidewalls 108s, 105s of the hard mask layer 108 and the p-contact layer 105, respectively.

[0055] In one or more embodiments, the hard mask layer 108 and the p-contact layer 105 are patterned according to any suitable patterning technique known to those skilled in the art. In one or more embodiments, the hard mask layer 108 and the p-contact layer 105 are patterned by etching. According to one or more embodiments, conventional masking, wet etching, and / or dry etching processes can be used to pattern the hard mask layer 108 and the p-contact layer 105.

[0056] In other embodiments, nanoimprint lithography is used to transfer the pattern to hard mask layer 108 and p-contact layer 105. In one or more embodiments, substrate 102 is etched in a reactive ion etch (RIE) tool using conditions that effectively etch hard mask layer 108 and p-contact layer 105, but very slowly or not at all, while etching p-type layer 104p. In other words, the etch is selective to hard mask layer 108 and p-contact layer 105 relative to p-type layer 104p. During the patterning step, it should be understood that masking techniques can be used to achieve the desired pattern.

[0057] Figure 1C is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1C, inner spacers 112 are deposited on the top surface 104t of the semiconductor layer 104 and the sidewalls 108s, 105s of the hard mask layer 108 and the p-contact layer 105. The inner spacers 112 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the inner spacers 112 comprise a dielectric material. The deposition of the material forming the inner spacers is typically conformal to the substrate surface, followed by etching to obtain the inner spacers on the sidewalls 108s, 105s rather than on the top surface 104b of the semiconductor layer 104.

[0058] As used herein, the term "dielectric" refers to an electrical insulator material that can be polarized by an applied electric field. In one or more embodiments, the inner spacer 112 includes, but is not limited to, oxides such as silicon oxide (SiO2) and aluminum oxide (Al2O3); and nitrides such as silicon nitride (Si3N4). In one or more embodiments, the inner spacer 112 comprises silicon nitride (Si3N4). In other embodiments, the inner spacer 112 comprises silicon oxide (SiO2). In some embodiments, the composition of the inner spacer 112 is non-stoichiometric relative to the ideal chemical formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxycarbides (e.g., silicon oxycarbide (SiOC)), and oxynitrides (e.g., silicon oxycarbonitride (SiNCO)).

[0059] In some embodiments, the internal spacer 112 may be a distributed Bragg reflector (DBR). As used herein, a "distributed Bragg reflector" refers to a structure (e.g., a mirror) formed by a multilayer stack of alternating thin film materials with different refractive indices (e.g., a high refractive index film and a low refractive index film).

[0060] In one or more embodiments, the inner spacer 112 is deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0061] In one or more embodiments, the thickness of the inner spacer 112 ranges from about 200 nm to about 1 µm, for example, about 300 nm to about 1 µm, about 400 nm to about 1 µm, about 500 nm to about 1 µm, about 600 nm to about 1 µm, about 700 nm to about 1 µm, about 800 nm to about 1 µm, about 500 nm to about 1 µm, about 200 nm to about 900 nm, 300 nm to about 900 nm, about 400 nm to about 900 nm, about 500 nm to about 900 nm, about 600 nm to about 900 nm, about 700 nm to about 900 nm, about 800 nm to about 900 nm, about 200 nm to about 800 nm, 300 nm to about 800 nm, about 400 nm to about 800 nm, about 500 nm to about 800 nm, about 600 nm to about 800 nm, about 700 nm to about 800 nm, about 200 nm to about 800 nm. nm to about 700 nm, about 300 nm to about 700 nm, about 400 nm to about 700 nm, about 500 nm to about 700 nm, about 600 nm to about 700 nm, about 200 nm to about 600 nm, about 300 nm to about 600 nm, about 400 nm to about 600 nm, about 500 nm to about 500 nm, about 200 nm to about 500 nm, about 300 nm to about 500 nm, about 300 nm to about 400 nm, about 200 nm to about 400 nm, or about 300 nm to about 400 nm.

[0062] Figure 1D is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1D , the semiconductor layer 104 is etched to form at least one mesa, for example, a first mesa 150a and a second mesa 150b. Figure 1D In the embodiment shown, the first mesa 150a and the second mesa 150b are separated by a trench 111 (which will be referred to as trench 111 ). Each trench 111 has a sidewall 113 .

[0063] Figure 1E is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1E , an outer spacer 114 is deposited on the sidewalls 113 of the trench 111. The outer spacer 114 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the outer spacer 114 comprises a dielectric material. The dielectric material insulates the sidewalls (sidewalls 104s) of the p-type layer 104p and the active region 106 (sidewalls 106s) from the metal deposited in the trench 111, as described below with reference to Figure 1I The deposition of the material forming the outer spacers is typically conformal to the substrate surface and is subsequently etched to obtain the outer spacers on the sidewalls of the trenches, rather than on the bottom of the trenches or on top of the hard mask layer.

[0064] In one or more embodiments, the outer spacer 114 may be an oxide, such as silicon oxide (SiO2) or aluminum oxide (Al2O3); or a nitride, such as silicon nitride (Si3N4). In one or more embodiments, the outer spacer 114 comprises silicon nitride (Si3N4). In other embodiments, the outer spacer 114 comprises silicon oxide (SiO2). In some embodiments, the outer spacer 114 may be a distributed Bragg reflector (DBR).

[0065] In one or more embodiments, the outer spacer 114 is deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0066] Figure 1N for the reason Figure 1E The dotted circle 1N indicates Figure 1E A magnified view of a portion of the stack.

[0067] In one or more embodiments, Figure 1B 、 Figure 1E and Figure 1NAs shown, a dark space or dark space gap 117 is formed between adjacent edges 105e of the p-contact layer 105 on the first mesa 150a and the second mesa 150b. In one or more embodiments, the dark space gap 117 formed between adjacent edges 105e of the p-contact layer 105 on the first mesa 150a and the second mesa 150b is in the range of 10µm to 0.5µm, or in the range of 9µm to 0.5µm, or in the range of 8µm to 0.5µm, or in the range of 7µm to 0.5µm, or in the range of 6µm to 0.5µm, or in the range of 5µm to 0.5µm, or in the range of 4µm to 0.5µm, or in the range of 3µm to 0.5µm. In other embodiments, the dark space gap 117 formed between adjacent edges 105e of the p-contact layer 105 on the first and second mesas 150a, 150b is in a range from 10µm to 4µm, such as from 8µm to 4µm. In an embodiment of the LED device 100, each of the plurality of spaced-apart mesas 150a, 150b includes a p-contact layer 105 that is both conductive and reflective, extends across a portion of each of the plurality of mesas 150a, 150b, and includes an edge 105e; and the trenches 111 between each of the plurality of spaced-apart mesas result in a pixel pitch in the range from 1µm to 100µm (including from 40µm to 100µm, 41µm to 100µm, and all values ​​and subranges therebetween), and the dark space gap 117 between adjacent edges of the p-contact layer is less than 20% of the pixel pitch. In some embodiments, the pixel pitch is in the range of 5µm to 100µm, 10µm to 100µm, or 15µm to 100µm. In some embodiments, when the pixel pitch is in the range of 10µm to 100µm, the dark space gap 117 between adjacent edges of the p-contact layer is greater than 1% of the pixel pitch and less than 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, or 5% of the pixel pitch.

[0068] In one or more embodiments, each of the spaced-apart mesas 150a, 150b includes a sidewall 104s, each sidewall having a first segment 104s1 and a second segment 104s2 (e.g., Figure 1M The first segment 104s1 defines an angle "a" in the range of 60 to 90 degrees with a horizontal plane 129 parallel to the n-type layer 104n and the p-type layer 104p (as shown). Figure 1N). In some embodiments, the angle "a" is in the range of 60 to 85 degrees, 60 to 80 degrees, 60 to 75 degrees, 60 to 70 degrees, 65 to 90 degrees, 65 to 85 degrees, 65 to 80 degrees, 65 to 75 degrees, 65 to 70 degrees, 70 to 90 degrees, 70 to 85 degrees, 70 to 80 degrees, 70 to 75 degrees, 75 to 90 degrees, 75 to 85 degrees, 75 to 80 degrees, 80 to 90 degrees, or 80 to 85 degrees. In one or more embodiments, the second segment 104s2 of the sidewall forms an angle in the range of 75 degrees to less than 90 degrees with the top surface of the substrate on which the mesa is formed.

[0069] Figure 1F is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1F , the semiconductor layer 104 is etched, and the trench 111 is enlarged (i.e., the depth of the trench is increased) to expose the top surface 102t of the substrate 102. In one or more embodiments, the etching is selective, so that the outer spacer 114 remains on the sidewalls of the trench 111. In one or more embodiments, the trench 111 has a bottom 111b and sidewalls 113. In one or more embodiments, the depth of the trench 111 from the top surface 104t of the semiconductor layer forming the mesa is in a range from about 0.5µm to about 2µm.

[0070] Figure 1G is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1G The first mesas 150a and the second mesas 150b are patterned to form via openings 116 on the top surfaces of the mesas, which expose the top surface of the semiconductor layer 104 and / or the top surface of the p-contact layer 105. In one or more embodiments, the first mesas 150a and the second mesas 150b can be patterned according to any suitable technique known to those skilled in the art, such as masking and etching processes used in semiconductor processing.

[0071] Figure 1H is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1H A reflective liner 130 is deposited on the substrate, on the sidewalls 113 and bottom 111b of the trench 111, on the sidewalls of the outer spacer 114, along the surface of the hard mask layer 108, and on the top surface of the semiconductor layer 104 and / or the top surface of the p-contact layer 105. The reflective liner 130 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the reflective liner 130 comprises aluminum (Al).

[0072] In one or more embodiments, the reflective liner 130 is deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD). In one or more embodiments, the reflective liner 130 is deposited selectively, such that the reflective liner 130 is deposited only on the sidewalls 113 of the trench 111 and the sidewalls of the outer spacer 114.

[0073] Figure 1I FIG is a cross-sectional view of a stack after steps of manufacturing an LED device according to one or more embodiments. Figure 1I Electrode metal 118 is deposited on the substrate—including on top of mesas 150a, 150b, in via opening 116, and in trench 111—to produce, for example, n-contact material 118n and / or p-metal plug 118p and / or conductive metal 118c in the final product. Electrode metal 118 can include any suitable material known to those skilled in the art. In one or more embodiments, electrode metal 118 includes copper, and electrode metal material 118 is deposited by electrochemical deposition (ECD) of copper.

[0074] Figure 1J is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1J , electrode metal 118 is planarized, etched, or polished. Electrode metal 118 produces n-contact material 118n and p-metal plug 118p. As used herein, the term "planarization" refers to the process of smoothing a surface and includes, but is not limited to, chemical mechanical polishing / planarization (CMP), etching, and the like.

[0075] Figure 1K is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1K , a passivation layer 120 is deposited on the substrate. In some embodiments, passivation layer 120 is deposited directly on planarized n-contact material 118n, planarized p-metal plug 118p, the top surface of inner spacer 112, the top surface of outer spacer 114, and the top surface of hardmask layer 108. In other embodiments, one or more additional layers may be present between passivation layer 120 and the planarized n-contact material 118n, planarized p-metal plug 118p, the top surface of inner spacer 112, the top surface of outer spacer 114, and the top surface of hardmask layer 108. In some embodiments, the passivation material comprises the same material as hardmask layer 108. In other embodiments, passivation layer 120 comprises a different material than hardmask layer 108.

[0076] In one or more embodiments, the passivation layer 120 may be deposited by any suitable technique known to those skilled in the art. In one or more embodiments, the passivation layer 120 is deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0077] In one or more embodiments, the passivation layer 120 may be composed of any suitable material known to those skilled in the art. In one or more embodiments, the passivation layer 120 comprises a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlO x ), aluminum nitride (AlN) and combinations thereof.

[0078] Figure 1L is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1L , the passivation layer 120 is patterned to form at least one opening 122 that exposes the top surface of the p-metal plug 118p. Two openings 122 are shown. The passivation layer 120 can be patterned using any suitable technique known to those skilled in the art, including but not limited to photolithography, wet etching, or dry etching.

[0079] Figure 1M is a cross-sectional view of a stack after steps of manufacturing the LED device 100 according to one or more embodiments. Figure 1M , an under-bump metallization (UBM) material forms an under-bump metallization (UBM) layer 124a, which is deposited in the opening 122. As used herein, "under-bump metallization (UBM)" refers to the metal layer required to connect the die to the substrate using solder bumps in a flip-chip package. In one or more embodiments, the UBM layer 124a can be a patterned thin film stack material that provides electrical connection from the die to the solder bumps, provides a barrier function to limit unwanted diffusion from the bumps to the die, and provides mechanical interconnection of the solder bumps to the die by adhering to the die passivation and attaching to the solder bump pads. The UBM layer 124a can include any suitable metal known to those skilled in the art. In one or more embodiments, the UBM layer 124a can include gold (Au).

[0080] In one or more embodiments, under-bump metallization (UBM) can be implemented by any technique known to those skilled in the art, including but not limited to dry vacuum sputtering combined with electroplating. In one or more embodiments, the dry vacuum sputtering combined with electroplating consists of sputtering multiple metal layers in a high-temperature evaporation system.

[0081] exist Figure 1M In the embodiment of the present invention, UBM layer 124a is patterned (e.g., by masking and etching). UBM layer 124a can be patterned using any suitable technique known to those skilled in the art, including but not limited to photolithography, wet etching, or dry etching. The patterning of UBM layer 124a provides anode pads at first mesa 150a and second mesa 150b that contact p-metal plug 118p on p-contact layer 105.

[0082] Figure 1O is a cross-sectional view of a finished LED device according to one or more embodiments. Figure 1O , the finished LED device 100 includes Figure 1M , and also includes a common electrode (common cathode) 140 formed at one end of device 100 when viewed in cross-section. The UBM material has been patterned to provide an anode pad 124a, which contacts a p-metal plug 118p on p-contact layer 105 at first and second mesas 150a, 150b. Common cathode 140 includes conductive metal 118c. Under-bump metallization (UBM) material also provides a cathode pad 124c in contact with common cathode 140, similar in pattern to UBM layer 124a. In one or more embodiments, a plurality of spaced-apart mesas 150a, 150b define a pixel matrix, and the pixel matrix is ​​surrounded by common electrode 140.

[0083] In one or more embodiments, the common electrode 140 is a pixelated common cathode comprising a plurality of semiconductor stacks surrounded by a conductive metal. In one or more embodiments, the semiconductor stack comprises a semiconductor layer 104, which, according to one or more embodiments, comprises an epitaxial layer, a Group III nitride layer, or an epitaxial Group III nitride layer. In a specific embodiment, one or more semiconductor layers comprise GaN.

[0084] In order to make pixelated common electrodes, Figures 1A to 1F Processing is performed, where a portion of the mesa is etched to expose the top surface of the semiconductor layer, rather than preparing Figure 1G The through hole opening 116 is shown. Figure 5A , the third mesa 150c and the fourth mesa 150d are etched to expose the top surface 104t of the semiconductor layer 104, thereby forming semiconductor stacks 151c and 151d, respectively. That is, the inner spacer 112, the hard mask layer 108, and the p-contact layer 105 on the third mesa 150c and the fourth mesa 150d are removed. The sidewalls of the third mesa 150c and the fourth mesa 150d are exposed when the outer spacer 114 is etched. Thereafter, the third mesa 150c and the fourth mesa 150d are processed according to the following: Figure 1HAdding a reflective backing layer 130, Figure 1I depositing electrode material 118, and Figure 1J-1M Formed as Figure 5B The pixelated common cathode is shown.

[0085] exist Figure 5B In the embodiment, the finished LED device 101 includes Figure 5A The features shown hereafter Figures 1H-1M and Figure 1M Processing proceeds, including forming a common electrode (common cathode) 141 at the ends of device 101 (as shown in the cross-sectional view). The UBM material has been patterned to provide an anode pad 124a, which contacts a p-metal plug 118p on p-contact layer 105 at first and second mesas 150a and 150b. Third and fourth mesas 150c and 150d, respectively, define or form semiconductor stacks 151c and 151d, surrounded by conductive metal 118c. Semiconductor stacks 151c and 151d are passive, as they do not generate light. The under-bump metallization (UBM) material also provides a cathode pad 124c, similar in pattern to UBM layer 124a, that contacts common cathode 141.

[0086] Figure 2 A top view of a LED monolithic array 200 is shown, comprising a plurality of pixels 155 (of which 155a and 155b are examples) defined or formed by a plurality of spaced-apart mesas, as herein referred to Figures 1A-1O As described. For example, the first mesa 150a defines or forms a first pixel 155a, and the second mesa 150b defines or forms a second pixel 155b. The third mesa 150c and the fourth mesa 150d form or provide passive pixels or semiconductor stacks 151c and 151d. The pixels 155 are arranged in a grid and connected by a common cathode 140. In one or more embodiments, the array of spaced-apart mesas includes an arrangement of mesas in two directions. For example, the array may include an arrangement of 2×2 mesas, 4×4 mesas, 20×20 mesas, 50×50 mesas, 100×100 mesas, or n1×n2 mesas, where each of n1 and n2 is a number in the range of 2 to 1000, and n1 and n2 may be equal or unequal.

[0087] One or more embodiments provide a light emitting diode (LED) device 100 including a plurality of spaced-apart mesas 150 a, 150 b defining pixels 155 a, 155 b, each of the plurality of spaced-apart mesas 150 a, 150 b including a semiconductor layer 104 including an n-type layer 104 n, an active region 106, and a p-type layer 104 p, each of the spaced-apart mesas 150 a, 150 b having a height H and a width W, wherein the height H is less than or equal to the width W. The LED device 100 also includes a metal 118 in the form of trenches 111 between each of the plurality of spaced-apart mesas 150 a, 150 b, the metal 118 providing optical isolation between each of the spaced-apart mesas 150 a, 150 b and electrically contacting the n-type layer 104 n of each of the spaced-apart mesas 150 a, 150 b along sidewalls of the n-type layer 104 n. In one or more embodiments, the LED device 100 includes a first dielectric material 114 that insulates the sidewalls (sidewalls 104s) of the p-type layer 104p and the active region 106 (sidewalls 106s) from an n-contact material 118n. A p-metal plug 118p is in electrical communication with the p-contact layer 105. In embodiments of the LED device 100, each of the plurality of spaced-apart mesas 150a, 150b includes a conductive p-contact layer 105 that extends across a portion of each of the plurality of mesas 150a, 150b and includes an edge 105e. The trenches 111 between each of the plurality of spaced-apart mesas result in a pixel pitch ranging from 1µm to 100µm (including 51µm to 100µm and all values ​​and subranges therebetween), and a dark space gap 117 between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In some embodiments, the pixel pitch is in the range of 5µm to 100µm, 10µm to 100µm, or 15µm to 100µm. In other embodiments, the dark space gap 117 is in the range of 10µm to 0.5µm, in the range of 10µm to 4µm, for example, in the range of 8µm to 4µm. As used herein and in accordance with one or more embodiments Figure 1O As shown, "pixel pitch" refers to the distance or spacing 119 between the centers "C" of adjacent pixels provided or formed by the mesas 150a, 150b. In other words, the pixel pitch refers to the center-to-center spacing 119 of adjacent pixels. In one or more embodiments, for adjacent pixels 155a, 155b and all adjacent pixels of the array 200, as shown Figure 2The center-to-center spacing of the LED arrays shown is the same. In one or more embodiments, the pixel pitch is in the range of from 5µm to 100µm, such as in the following ranges: 5µm to 90µm, 5µm to 80µm, 5µm to 70µm, 5µm to 60µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 10µm to 90µm, 10µm to 80µm, 10µm to 70µm, 10µm to 60µm, 10µm to 50µm, 10µm to 40µm, 10µm to 30µm, 20µm to 90µm, 20µm to 80µm, 20µm to 70µm, 20µm to 60µm, 20µm to 50µm, 20µm to 40µm, 20µm to 30µm, 30µm to 90µm, 30µm to 80µm, 30µm to 70µm, 30µm to 60µm, 30µm to 50µm, 30µm to 40µm, 40µm to 90µm, 40µm to 80µm, 40µm to 70µm, 40µm to 60µm, 40µm to 50µm, 50µm to 90µm, 50µm to 80µm, 50µm to 70µm, or 50µm to 60µm.

[0088] In one or more embodiments, a light emitting diode (LED) device includes: a plurality of mesas defining pixels, each of the plurality of mesas comprising a semiconductor layer including an n-type layer, an active layer, and a p-type layer, the height of each mesa being less than or equal to its width; an n-contact material in the spaces between each of the plurality of mesas, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along the sidewalls of the n-type layer; a dielectric material insulating the p-type layer and the sidewalls of the active region from the n-contact material; and each of the plurality of mesas comprising a p-contact layer extending across a portion of each of the plurality of mesas and including an edge, wherein the spaces between each of the plurality of mesas result in a pixel pitch ranging from 10µm to 100µm and a dark space gap between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In one or more embodiments, the p-contact layer comprises a reflective metal. The LED device of claim 1, wherein the pixel pitch ranges from 40µm to 100µm. In one or more embodiments, the dark space gap between adjacent edges of the p-contact layer is less than 10% of the pixel pitch. The LED device according to claim 1, wherein the semiconductor layer is an epitaxial semiconductor layer having a thickness ranging from 2µm to 10µm. In one or more embodiments, the dielectric material is in the form of an external spacer, wherein the external spacer comprises a material selected from SiO2, AlO xand SiN, having a thickness ranging from 200 nm to 1 µm. In one or more embodiments, the n-contact material has a depth ranging from 0.5 µm to 2 µm from the top surface of the mesa. In one or more embodiments, each mesa includes a sidewall, each sidewall having a first segment and a second segment, wherein the first segment of the sidewall defines an angle ranging from 60 degrees to 90 degrees with respect to a horizontal plane parallel to the n-type layer and the p-type layer, and the second segment of the sidewall forms an angle ranging from 75 degrees to less than 90 degrees with the top surface of the substrate on which the mesa is formed.

[0089] In one or more embodiments, a light emitting diode (LED) device includes: a plurality of mesas defining pixels, each of the plurality of mesas including a semiconductor layer comprising an n-type layer, an active layer, and a p-type layer, the height of each mesa being less than or equal to its width; metal in the spaces between each of the plurality of mesas, the metal providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along the sidewalls of the n-type layer; a dielectric material insulating the sidewalls of the p-type layer and the active layer from the metal; and each of the plurality of mesas including a p-contact layer extending across a portion of each of the plurality of mesas and including an edge, the spaces between each of the plurality of mesas resulting in a pixel pitch ranging from 10µm to 100µm and a dark space gap between adjacent edges of the p-contact layer ranging from 4µm to 10µm. The plurality of mesas comprise a mesa array. In one or more embodiments, the dark space gap ranges from 4µm to 8µm. In one or more embodiments, the pixel pitch ranges from 40µm to 100µm.

[0090] One or more embodiments of the present disclosure provide a method of manufacturing an LED device. Figures 3A-3F A process flow diagram according to various embodiments is shown. Figure 3AMethod 200 includes fabricating a substrate at operation 202. Substrate fabrication may include depositing multiple semiconductor layers on the substrate, including but not limited to an n-type layer, an active region, and a p-type layer. Once the semiconductor layers are deposited on the substrate, a portion of the semiconductor layers is etched to form trenches and a plurality of spaced-apart mesas. At operation 204, a die is fabricated. Die fabrication includes depositing a (first) dielectric material to insulate the sidewalls of the epitaxial layers (e.g., the n-type layer, the active region, and the p-type layer), followed by depositing electrode metal in the trenches (e.g., the spaces between each of the plurality of spaced-apart mesas). In some embodiments, die fabrication also includes depositing a p-type contact layer and a hard mask, forming a current spreading film, plating a p-type metal plug, and then performing under-bump metallization (UBM). At operation 204, the die is fabricated. At operation 206, optional microbumps may be applied to a complementary metal oxide semiconductor (CMOS) backplane. At operation 208, back-end processing is optionally performed to connect the die to the CMOS backplane, provide underfill, perform laser lift-off, and optionally integrate phosphor.

[0091] refer to Figure 3B In one embodiment, method 210 includes, at 212, depositing a plurality of semiconductor layers including an n-type layer, an active region, and a p-type layer on a substrate. At 214, the method further includes etching a portion of the semiconductor layer to form a trench defining a pixel and a plurality of spaced-apart mesas, each of the plurality of spaced-apart mesas including a semiconductor layer, and a height of each spaced-apart mesa being less than or equal to its width. At 216, the method includes depositing a dielectric material that insulates the sidewalls of the p-type layer and the active region from the metal. At 218, the method includes depositing an electrode metal in a space between each of the plurality of spaced-apart mesas, the metal providing optical isolation between each of the spaced-apart mesas and electrically contacting the n-type layer of each spaced-apart mesa along the sidewalls of the n-type layer. In one or more embodiments, each of the plurality of spaced-apart mesas includes a conductive p-contact layer that extends across a portion of each of the plurality of mesas and includes an edge, and the space between each of the plurality of spaced-apart mesas results in a pixel pitch ranging from 1µm to 100µm and a dark space gap between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In some embodiments, the pixel pitch is in a range from 5µm to 100µm, 10µm to 100µm, or 15µm to 100µm. In other embodiments, the dark space gap is in a range from 10µm to 0.5µm, or in a range from 10µm to 4µm, such as in a range from 8µm to 4µm. According to one or more embodiments, the term "dark space gap" as used herein refers to a space between adjacent edges of the p-contact layer where no light is reflected.

[0092] In some embodiments, the method includes forming an array of spaced-apart mesas. In some embodiments, the metal includes a reflective metal. In some embodiments, the dark space gap is in a range of from 10 μm to 0.5 μm or in a range of from 10 μm to 4 μm. In some embodiments, the plurality of spaced-apart mesas are arranged into pixels, and the pixel pitch is in a range of from 5 μm to 100 μm or from 30 μm to 50 μm. In some embodiments, the semiconductor layer 104 has a thickness in a range of from 2 μm to 10 μm.

[0093] Reference Figure 3C , followed by Figure 3B After operations 212 to 218, method 220 includes forming a common electrode at operation 222. In one or more embodiments, the common electrode includes a plurality of semiconductor stacks surrounded by a conductive metal. In one or more embodiments, the semiconductor stacks include one or more layers of GaN.

[0094] refer to Figure 3D , followed by Figure 3B Following operations 212 through 218, method 224 includes depositing a current spreading layer at operation 226. Some method embodiments include forming a multilayer composite film on the p-type layer, the multilayer composite film comprising a current spreading layer, a p-contact layer on a first portion of the current spreading layer, and a (second) dielectric layer on a second portion of the current spreading layer beneath a hardmask layer. In one or more embodiments, the multilayer composite film comprises a current spreading layer on the p-type layer, the current spreading layer having a first portion and a second portion; a dielectric layer on the second portion of the current spreading layer; a via opening defined by the dielectric layer and sidewalls in the first portion of the current spreading layer; and a p-contact layer in the via opening on the first portion of the current spreading layer, the sidewalls of the dielectric layer, and at least a portion of a surface of the dielectric layer. In one or more embodiments, the multilayer composite film is formed directly on the p-type layer. In other embodiments, one or more additional layers may be formed between the multilayer composite film and the p-type layer. In one or more embodiments, the multilayer composite layer includes a protective layer on the p-contact layer.

[0095] Some method embodiments include depositing a current spreading layer on a p-type layer. Other method embodiments include depositing a current spreading layer on the p-type layer; depositing a dielectric layer on the current spreading layer; forming a via opening in the dielectric layer; conformally depositing a p-contact layer in the via opening and on a top surface of the dielectric layer; depositing a protective layer on the p-contact layer; depositing a hard mask layer on the protective layer; forming an opening in the hard mask layer; depositing a liner layer in the opening in the hard mask layer; and depositing a p-metal plug having a width on the liner layer; and forming a passivation layer on the p-metal plug, the passivation layer having an opening of a defined width therein, the width of the opening in the passivation layer being less than a combined width of the p-metal plug and the liner layer in the opening.

[0096] refer to Figure 3E Some method embodiments include method 230, which includes depositing a hard mask layer above or on the p-type layer at operation 232. At operation 234, an opening is formed in the hard mask layer. At operation 236, in one or more embodiments, a liner layer is deposited in the opening in the hard mask layer. At operation 238, in one or more embodiments, a p-metal plug is deposited on the liner layer, the p-metal plug having a width, and at operation 240, a passivation layer is formed on the p-metal plug, the passivation layer having an opening of a defined width therein, the width of the opening in the passivation layer being less than the width of the p-metal plug.

[0097] In one or more embodiments, a method for manufacturing a light emitting diode (LED) device includes: depositing a plurality of semiconductor layers including an n-type layer, an active region, and a p-type layer on a substrate; depositing a hard mask layer on the p-type layer; etching a portion of the semiconductor layer and the hard mask layer to form a trench and a plurality of mesas defining a pixel, each of the plurality of mesas including a semiconductor layer, and a height of each mesa being less than or equal to its width; depositing a dielectric material in the trench; forming an opening in the hard mask layer, and etching the semiconductor layer to expose a surface of the substrate and a sidewall of the n-type layer; depositing a liner layer on the substrate, including depositing the liner layer on the opening in the hard mask layer, the dielectric material, the n-type layer, and the surface of the substrate; depositing an electrode metal on the liner layer; planarizing the substrate to form an n-contact material of the n-type layer electrically contacting each mesa along the sidewall of the n-type layer, and a p-metal material plug on the liner layer in the opening of the hard mask layer, the combination of the p-metal material plug in the opening of the hard mask layer and the liner layer having a width; and forming a passivation layer on the substrate and forming an opening of a defined width in the passivation layer. In one or more embodiments, a width of each opening in the passivation layer is smaller than a width of a combination of the p-metal plug and the liner layer.

[0098] 3F, some method embodiments include a method 240 that includes depositing a semiconductor layer at operation 212, for example, as described in reference Figure 1A The method 240 further includes depositing a current spreading film or layer and / or a p-contact layer at operation 213, for example, as described in reference Figure 1A The method 240 further includes depositing and patterning a hard mask layer at operation 231, for example, as described in reference Figures 1A-1C At operation 233, a trench is formed in the semiconductor layer and a dielectric material is deposited, for example, as described in reference Figures 1D-1G At operation 234, an opening is formed in the hard mask layer, for example, as described in reference Figure 1H At operation 236, in one or more embodiments, a liner layer is deposited in the opening in the hard mask layer, for example, as described with reference to Figure 1HAt operation 237, metal is deposited in the trench and a p-metal plug is deposited, for example, as described in reference Figure 1I At operation 239, planarization is performed, for example, as described in reference Figure 1J At operation 241, a passivation layer is formed and patterned, for example, as described in reference Figure 1K and Figure 1L At operation 243, an under bump metallization layer is formed and patterned, for example, as described with reference to Figure 1M According to one or more embodiments, the operations of method 240 may be used to form Figure 1O or Figure 4 The device shown.

[0099] Another aspect of the present disclosure relates to electronic systems. In one or more embodiments, the electronic system includes the LED monolithic devices and arrays described herein and a driver circuit configured to provide independent voltages to one or more p-contact layers. In one or more embodiments, the electronic system is selected from the group consisting of an LED-based lamp, a light bar, a light sheet, an optical display, and a microLED display.

[0100] Figure 4 is a cross-sectional view of an LED device 300 showing a single mesa 350 of an LED device according to one or more embodiments. The device 300 is similar to Figure 1O The device 100 is shown as having either the first mesa 150a or the second mesa 150b. The device 300 includes a semiconductor layer 304 including an n-type layer 304n, a p-type layer 304p, and an active region 306 between the n-type layer 304n and the p-type layer 304p.

[0101] In the illustrated embodiment, a multilayer composite film 317 is disposed on the p-type layer 304p. As shown, the multilayer composite film 317 includes a current spreading layer 311 on the p-type layer 304p. The multilayer composite film also includes a dielectric layer 307 on the current spreading layer 311. In one or more embodiments, the current spreading layer 311 has a first portion 311y and a second portion 311z. The first portion 311y and the second portion 311z are lateral portions of the current spreading layer 311. The p-contact layer 305 is disposed on the first portion 311y of the current spreading layer 311 and within a via opening 319. The dielectric layer 307 is disposed on the second portion 311z of the current spreading layer 311. In one or more embodiments, the dielectric layer 307 is separated by a via opening 319. The via opening 319 has at least one sidewall 319s and a bottom 319b, with the bottom 319b exposing the current spreading layer 311. In the embodiment shown, the via opening 319 is defined by opposing sidewalls 319s of the dielectric layer 307 and a bottom 319b defined by the current spreading layer 311. Figure 4In the embodiment shown, the via opening 319 is filled with the p-contact layer 305 and the protective layer 309. Figure 4 As shown, the p-contact layer 305 is directly on the top surface of the dielectric layer 307, on the sidewalls 319s and bottom 319b of the via opening 319, and on the first portion 311y of the current spreading layer 311. Figure 4 As shown in the embodiment shown, the p-contact layer 305 is substantially conformal to the via opening 319. As used herein, a "substantially conformal" layer refers to a layer having approximately the same thickness everywhere (e.g., on the hardmask layer 308, on the sidewalls 319s, and on the bottom 319b of the via opening 319). A substantially conformal layer has a thickness variation of less than or equal to approximately 5%, 2%, 1%, or 0.5%. In one or more embodiments, a protective layer 309 is disposed on the p-contact layer 305. Without intending to be bound by theory, according to one or more embodiments, the protective layer 309 can prevent metal ions from the p-contact layer 305 from migrating and shorting the device 300. In one or more embodiments, the protective layer 309 covers the entire p-contact layer 305. In one or more embodiments, the protective layer 309 directly covers the entire p-contact layer 305.

[0102] In one or more embodiments, the current spreading layer comprises a transparent material. The current spreading layer is separate from the reflective layer. In this way, the current spreading function is implemented in a layer separate from the reflective function. In one or more embodiments, the current spreading layer 311 comprises indium tin oxide (ITO) or other suitable conductive transparent materials, such as transparent conductive oxides (TCOs) such as indium zinc oxide (IZO). The current spreading layer 311 has a thickness ranging from 5 nm to 100 nm. In some embodiments, the dielectric layer 307 comprises any suitable dielectric material, such as silicon dioxide (SiO2) or silicon oxynitride (SiON). In some embodiments, the protective layer 309 comprises titanium-platinum (TiPt), titanium-tungsten (TiW), or titanium-tungsten nitride (TiWN). In one or more embodiments, the p-contact layer 305 comprises a reflective metal. In one or more embodiments, the p-contact layer 305 comprises any suitable reflective material, such as, but not limited to, nickel (Ni) or silver (Ag).

[0103] Without intending to be bound by theory, according to some embodiments, the multilayer composite film 317 on the p-type layer 304p can balance absorption, reflection, and conductivity. In some embodiments, the p-contact layer 305 is a highly reflective layer. At angles near and above the critical angle, the dielectric layer 307 is a better reflector than the p-contact layer 305 and may not be particularly conductive. In some embodiments, the dielectric layer 307 can be composed of multiple dielectric layers to form a DBR (distributed Bragg reflector). In one or more embodiments, the current spreading layer 311 is optimized to minimize absorption and maximize conductivity.

[0104] In one or more embodiments, the mesa width spanned by the p-contact layer 305 is smaller than the width spanned by the current spreading layer 311 .

[0105] In the illustrated embodiment, a hard mask layer 308 is provided on a first portion of the protective layer 309, which is above a second portion 311z of the current spreading layer 311, and a hard mask opening 347 is defined in the hard mask layer 308. The hard mask layer 308 may include any suitable material, including a dielectric material. The hard mask layer 308 has been described above with reference to Figure 1A-Figure 1N The are masked and etched.

[0106] The hard mask opening 347 is partially filled with the liner layer 325 and partially filled with a p-metal plug 318p having a width 339. Figure 4 As shown in the embodiment, the liner layer 325 is substantially conformal to the hard mask opening 347. As used herein, a "substantially conformal" layer refers to a layer having a thickness that is substantially the same everywhere (e.g., on the sidewalls 347s and bottom 347b of the hard mask opening 347). A substantially conformal layer has a thickness variation of less than or equal to approximately 5%, 2%, 1%, or 0.5%. In one or more embodiments, the hard mask opening 347 has at least one sidewall 347s and a bottom surface 347b. In some embodiments, the bottom surface 347b exposes the protective layer 309. In one or more embodiments, the liner layer 325 is on at least one sidewall 347s and bottom 347b of the hard mask opening 347. In a specific embodiment, the liner layer 325 is substantially conformal to at least one sidewall 347s and bottom 347b of the hard mask opening 347. In the embodiment shown, there are two sidewalls 347, which are opposing sidewalls 347 defining the hard mask opening 347. In one or more embodiments, the thickness of the liner layer 325 ranges from approximately 5 nm to approximately 2 μm. In one or more embodiments, the liner layer 325 may include a seed material and may include any suitable material, including but not limited to aluminum (Al), titanium nitride, silver, indium tin oxide (ITO), titanium tungsten (TiW), and / or titanium platinum (TiPt). According to some embodiments, the seed material of the liner layer 325 may facilitate plating of the p-metal plug 318p. In one or more embodiments, the liner layer 325 serves as a bridge. The liner layer 325 may be formed by any means known to those skilled in the art, such as sputtering deposition.

[0107] like Figure 4As shown, a passivation film 321 is disposed on the hard mask layer 308. In one or more embodiments, the passivation film 321 includes a first passivation layer 320 and a second passivation layer 322. The first passivation layer 320 and the second passivation layer 322 may include any suitable material. In one or more embodiments, the first passivation layer 320 includes silicon oxide (SiO2), and the second passivation layer includes silicon nitride (SiN). In one or more embodiments, the passivation film 321 includes a passivation film opening 348 having a width 349, where the width 349 of the passivation film opening 348 is less than the combined width 339 of the p-metal plug 318p and the liner layer 325. In one or more embodiments, the passivation film 321 is sized to cover a surface 325f of the liner layer 325 and a portion of the p-metal plug 318p. In this manner, passivation film openings 348 smaller than the width 339 of the p-metal plug 318p and the liner layer 325 effectively protect the liner layer 325 while allowing access to the p-metal plug 318p. In one or more embodiments, each passivation film opening 348 is centered around the p-metal plug 318p.

[0108] like Figure 4 As shown, a layer of p-metal material, also referred to as a p-metal plug 318p, is formed on the liner layer 325. The p-metal plug 318p can include any suitable material. In one or more embodiments, the p-metal plug 318p includes copper (Cu). In one or more embodiments, the inner spacer 312 contacts the outer edges of the p-contact layer 305, the protective layer 309, and the hard mask layer 308. The outer spacer 314 is formed adjacent to the inner spacer 312.

[0109] In one or more embodiments, a reflective pad 330 is formed at the ends of the semiconductor layers 304n, 306, and 304p, separating them from the n-contact material 318n. Figure 4 The LED device 300 and Figure 1O The differences between the LED devices 300 shown in FIG. 3 are corresponding to Figure 1M The passivation layer 120 shown in FIG. 1 includes a first passivation layer 320 and a second passivation layer 322 that may include silicon nitride (SiN) in some embodiments. In some embodiments, only the first passivation layer 320 is present, but in other embodiments, both the first passivation layer 320 and the second passivation layer 322 are present. The first passivation layer 320 and the second passivation layer 322 have passivation film openings 348 therein. Figure 4 There is also an anode pad including under-bump metallization 324a, which is composed of reference Figure 1M324a, which forms an anode pad. In one or more embodiments, the width 349 of the opening 348 is smaller than the width 339 of the p-metal plug 318p. In some embodiments, the width of the p-metal plug 318p ranges from 2µm to 30µm (e.g., from 10µm to 20µm).

[0110] application

[0111] The LED devices disclosed herein may be in a monolithic array or matrix. The LED devices may be secured to a backplane for use in a final application. Lighting arrays and lens systems may be combined with the LED devices disclosed herein. Applications include, but are not limited to, beam steering or other applications that benefit from fine-grained intensity, spatial, and temporal control of light distribution. These applications may include, but are not limited to, precise spatial patterning of light emitted from a pixel block or individual pixels. Depending on the application, the emitted light may be spectrally distinct, adaptive over time, and / or environmentally responsive. Arrays of luminous pixels may provide pre-programmed light distributions in various intensity, spatial, or temporal patterns. The associated optical devices may be distinct at the pixel, pixel block, or device level. An example luminous pixel array may include a device having a commonly controlled center block of high-intensity pixels having associated common optical devices, while edge pixels may have separate optical devices. In addition to flashlights, common applications supported by luminous pixel arrays include video lighting, automotive headlights, architectural and area lighting, and street lighting. Example

[0112] Various embodiments are listed below. It will be understood that the embodiments listed below can be combined with all aspects and other embodiments according to the scope of the present disclosure.

[0113] Embodiment (a). A light emitting diode (LED) device comprises: a plurality of mesas defining pixels, each mesa comprising a semiconductor layer, the semiconductor layer comprising an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to its width; an n-contact material in the spaces between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along the sidewalls of the n-type layer; a dielectric material insulating the p-type layer and the sidewalls of the active region from the n-contact material; and a multilayer composite film on the p-type layer. The multilayer composite film comprises: a current spreading layer on the p-type layer, the current spreading layer having a first portion and a second portion; a dielectric layer on the second portion of the current spreading layer; a via opening defined by the dielectric layer and the sidewalls in the first portion of the current spreading layer; and a p-contact layer in the via opening on the first portion of the current spreading layer, the sidewalls in the dielectric layer, and at least a portion of the dielectric layer.

[0114] Embodiment (b) The LED device of embodiment (a), wherein the p-contact layer comprises a reflective metal, and the current spreading layer comprises a transparent material.

[0115] Embodiment (c) The LED device according to any one of embodiments (a) to (b), wherein the current spreading layer comprises a transparent conductive oxide (TCO).

[0116] Embodiment (d) The LED device according to any one of embodiments (a) to (c), wherein the current spreading layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).

[0117] Embodiment (e) The LED device according to any one of embodiments (a) to (d), wherein the p-contact layer comprises one or more of nickel (Ni) and / or silver (Ag), and the dielectric layer comprises silicon dioxide (SiO 2 ).

[0118] Embodiment (f) The LED device according to any one of embodiments (a) to (e), wherein the multilayer composite film further comprises a protective layer covering the p-contact layer.

[0119] Embodiment (g) The LED device according to embodiment (f), wherein the protective layer comprises one or more of titanium-platinum (TiPt), titanium-tungsten (TiW), and titanium-tungsten nitride (TiWN).

[0120] Embodiment (h) The LED device according to any one of embodiments (a) to (g), wherein the thickness of the semiconductor layer is in the range from 2 μm to 10 μm.

[0121] Embodiment (i) The LED device according to any one of embodiments (a) to (h), wherein the dielectric material is in the form of an outer spacer comprising a dielectric material selected from SiO2, AlO x and SiN, having a thickness ranging from 200 nm to 1 µm.

[0122] Embodiment (j) The LED device according to any one of embodiments (a) to (i), wherein the space between each mesa comprises a trench having a depth ranging from 0.5 μm to 2 μm from the top surface of each mesa.

[0123] Embodiment (k) The LED device of any one of embodiments (a) to (j), wherein each mesa comprises a sidewall of the semiconductor layer, each sidewall having a first segment and a second segment, wherein the first segment of the sidewall defines an angle in a range from 60 degrees to 90 degrees with a horizontal plane parallel to the n-type layer and the p-type layer; and the second segment of the sidewall forms an angle in a range from 75 degrees to less than 90 degrees with a top surface of the substrate on which the mesa is formed.

[0124] Embodiment (1). The LED device according to any one of embodiments (a) to (k), wherein the plurality of mesas comprises a mesa array.

[0125] Embodiment (m). A method of manufacturing a light emitting diode (LED) device, comprising: depositing a plurality of semiconductor layers including an n-type layer, an active region, and a p-type layer on a substrate; etching a portion of the semiconductor layer to form a trench defining a pixel and a plurality of mesas, each mesa including the semiconductor layer and having a height less than or equal to its width; depositing a dielectric material in the trench; depositing an n-contact material in a space between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along a sidewall of the n-type layer, wherein the dielectric material insulates the p-type layer and the sidewalls of the active region from the n-contact material; and depositing a multilayer composite film on the p-type layer, the multilayer composite film comprising: a current spreading layer on the p-type layer, the current spreading layer having a first portion and a second portion; a dielectric layer on the second portion of the current spreading layer; a via opening defined by the dielectric layer and the sidewalls in the first portion of the current spreading layer; and a p-contact layer in the via opening on the first portion of the current spreading layer, the sidewalls in the dielectric layer, and at least a portion of the dielectric layer.

[0126] Embodiment (n) The method of embodiment (m), wherein the p-contact layer comprises a reflective metal, and the current spreading layer comprises a transparent material.

[0127] Embodiment (o) The method of any one of embodiments (m) to (n), wherein the current spreading layer comprises a transparent conductive oxide (TCO).

[0128] Embodiment (p) The method according to any one of embodiments (m) to (o), wherein the current spreading layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).

[0129] Embodiment (q) The method of any one of embodiments (m) to (p), wherein the p-contact layer comprises one or more of nickel (Ni) and silver (Ag), and / or the dielectric layer comprises silicon dioxide (SiO 2 ).

[0130] Embodiment (r) The method according to any one of embodiments (m) to (q), wherein the multilayer composite film further comprises a protective layer on the p-contact layer.

[0131] Embodiments. The method of any one of embodiments (m) to (r), comprising forming the mesa array.

[0132] Embodiment (t). A light emitting diode (LED) device comprising: a plurality of mesas defining pixels, each mesa comprising a semiconductor layer, the semiconductor layer comprising an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to its width; an n-contact material in the spaces between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along a sidewall of the n-type layer; a dielectric material insulating the p-type layer and the sidewall of the active region from the n-contact material; a multilayer composite film on the p-type layer, the multilayer composite film comprising a current spreading member having a first portion and a second portion directly on the p-type layer; a diffusion layer, a dielectric layer on the second portion of the current spreading layer, the dielectric layer including sidewalls, wherein the first portion of the current spreading layer defines a via opening, and a p-contact layer conformal with the dielectric layer and the via opening; a hard mask layer over the p-contact layer over the second portion of the current spreading layer, the hard mask layer including sidewalls defining the hard mask opening; a liner layer conformally deposited in the hard mask opening and over the p-contact layer, the p-contact layer being over the first portion of the current spreading layer and on the sidewalls of the hard mask layer; a p-metal material plug on the liner layer; a passivation layer on the hard mask layer; and an underbump metallization layer on the passivation layer.

[0133] In the context of describing the materials and methods discussed herein (especially in the context of the following claims), the use of the terms "a," "an," "the," and similar referents should be interpreted to encompass both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into this specification as if it were individually recited herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by the context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illustrate the materials and methods and does not limit the scope unless otherwise claimed. No language in this specification should be construed to indicate that any unclaimed element is essential to practicing the disclosed materials and methods.

[0134] Throughout this specification, reference to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" throughout this specification is not necessarily referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0135] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that the present disclosure include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A light emitting diode (LED) device comprising: a plurality of mesas defining pixels, each mesa comprising a semiconductor layer including an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to the width thereof; an n-contact material in the space between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along a sidewall of the n-type layer; a dielectric material that insulates the p-type layer and sidewalls of the active region from the n-contact material; a multilayer composite film on the p-type layer, the multilayer composite film comprising: a current spreading layer on the p-type layer, the current spreading layer having a first portion and a second portion; a dielectric layer on the second portion of the current spreading layer; a via opening defined by the dielectric layer and sidewalls in the first portion of the current spreading layer; a p-contact layer in the via opening on the first portion of the current spreading layer, the sidewalls in the dielectric layer, and at least a portion of the dielectric layer; and a protective layer covering the p-contact layer, the protective layer in the via opening and over the dielectric layer on the second portion of the current spreading layer; and A p-metal plug is formed in the hard mask opening, over a portion of the protection layer in the via opening, and an underbump metallization layer contacts the p-metal plug. 2 . The LED device of claim 1 , wherein the p-contact layer comprises a reflective metal, and the current spreading layer comprises a transparent material. The LED device of claim 2 , wherein the plurality of mesas comprises an array of mesas. The LED device of claim 1 , wherein the current spreading layer comprises a transparent conductive oxide (TCO). The LED device according to claim 4 , wherein the current spreading layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO). 6 . The LED device of claim 1 , wherein the p-contact layer comprises one or more of nickel (Ni) and silver (Ag), and the dielectric layer comprises silicon dioxide (SiO 2 ). 7 . The LED device according to claim 1 , wherein the protective layer comprises one or more of titanium-platinum (TiPt), titanium-tungsten (TiW), and titanium-tungsten nitride (TiWN). 8 . The LED device according to claim 1 , wherein a thickness of the semiconductor layer is in a range from 2 μm to 10 μm.

9. The LED device of claim 1 , wherein the dielectric material is in the form of an outer spacer comprising a dielectric material selected from the group consisting of SiO 2 , AlO x and SiN, having a thickness ranging from 200 nm to 1 μm. 10 . The LED device of claim 1 , wherein the space between each mesa comprises a groove having a depth ranging from 0.5 μm to 2 μm from a top surface of each mesa.

11. The LED device of claim 1 , wherein each mesa comprises a sidewall of the semiconductor layer, each sidewall having a first segment and a second segment, wherein the first segment of the sidewall defines an angle in a range from 60 degrees to 90 degrees with a horizontal plane parallel to the n-type layer and the p-type layer; and the second segment of the sidewall forms an angle in a range from 75 degrees to less than 90 degrees with a top surface of a substrate on which the mesa is formed.

12. A method of manufacturing a light emitting diode (LED) device, comprising: depositing a plurality of semiconductor layers including an n-type layer, an active region, and a p-type layer on a substrate; etching a portion of the semiconductor layer to form a trench defining a pixel and a plurality of mesas, each mesa comprising the semiconductor layer and having a height less than or equal to a width thereof; depositing a dielectric material in the trench; depositing an n-contact material in the space between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along a sidewall of the n-type layer, wherein a dielectric material insulates the p-type layer and the sidewalls of the active region from the n-contact material; depositing a multilayer composite film on the p-type layer, the multilayer composite film comprising: a current spreading layer on the p-type layer, the current spreading layer having a first portion and a second portion; a dielectric layer on the second portion of the current spreading layer; a via opening defined by the dielectric layer and sidewalls in the first portion of the current spreading layer; a p-contact layer in the via opening on the first portion of the current spreading layer, the sidewalls in the dielectric layer, and at least a portion of the dielectric layer; and a protective layer covering the p-contact layer, the protective layer in the via opening and over the dielectric layer on the second portion of the current spreading layer; and A p-metal plug is deposited in the hard mask opening, over a portion of the protection layer in the via opening, and an underbump metallization layer is deposited in contact with the p-metal plug. 13 . The method of claim 12 , wherein the p-contact layer comprises a reflective metal, and the current spreading layer comprises a transparent material.

14. The method of claim 12, comprising forming an array of mesas.

15. The method of claim 13, wherein the current spreading layer comprises a transparent conductive oxide (TCO). 16 . The method of claim 13 , wherein the current spreading layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).

17. The method of claim 13, wherein the p-contact layer comprises one or more of nickel (Ni) and silver (Ag), and the dielectric layer comprises silicon dioxide (SiO2).

18. A light emitting diode (LED) device comprising: a plurality of mesas defining pixels, each mesa comprising a semiconductor layer including an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to the width thereof; an n-contact material in the space between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along a sidewall of the n-type layer; a dielectric material that insulates the p-type layer and sidewalls of the active region from the n-contact material; a multilayer composite film on the p-type layer, the multilayer composite film comprising: a current spreading layer having a first portion and a second portion directly on the p-type layer, a dielectric layer on the second portion of the current spreading layer, the dielectric layer including sidewalls, wherein the first portion of the current spreading layer defines a via opening, and a p-contact layer conformal to the dielectric layer and the via opening; a hard mask layer over the p-contact layer over the second portion of the current spreading layer, the hard mask layer including sidewalls defining a hard mask opening; a liner layer conformally deposited in the hard mask opening over the p-contact layer, the p-contact layer over the first portion of the current spreading layer and on sidewalls of the hard mask layer; a p-metal plug on the liner layer; a passivation layer on the hard mask layer; and An under bump metallization layer is formed on the passivation layer.

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