Light emitting diode device with common electrode

Abstract

A light-emitting diode (LED) device is described, comprising: a plurality of mesas defining pixels, each of the plurality of mesas including a semiconductor layer; an n-contact material in the space between each of the plurality of mesas; and a dielectric material insulating the sidewalls of the p-type layer and the active region from a metal. The plurality of mesas define a pixel matrix surrounded by a common electrode comprising a plurality of semiconductor stacks surrounded by a conductive metal. Each semiconductor stack is passive and includes at least one layer of GaN in one or more embodiments.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to light-emitting diode (LED) devices and methods of manufacturing the same. More particularly, the embodiments relate to LED devices including a common electrode. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor light source that emits visible light when an electric current flows through it. LEDs combine p-type and n-type semiconductors. LEDs typically use III-V compound semiconductors. III-V compound semiconductors provide stable operation at higher temperatures than devices using other semiconductors. III-V compounds are typically formed on substrates made of sapphire alumina (Al₂O₃) or silicon carbide (SiC).

[0003] Various emerging display applications—including wearable devices, head-mounted displays, and large-area displays—require miniaturized chips composed of high-density microLED (µLED or uLED) arrays with lateral dimensions as low as less than 100µm × 100µm. MicroLEDs (uLEDs), typically with a diameter or width of about 50µm or less, are used to fabricate color displays by closely packing microLEDs containing red, blue, and green wavelengths. Generally, two methods have been used to assemble displays composed of individual microLED dies. The first is a pick-and-place method, which involves picking up each individual blue, green, and red wavelength microLED, aligning each individual blue, green, and red wavelength microLED, and then attaching each individual blue, green, and red wavelength microLED to a backplane, followed by electrically connecting the backplane to a driver integrated circuit. Due to the small size of each microLED, this assembly sequence is slow and prone to manufacturing errors. Furthermore, as die sizes shrink to meet the ever-increasing resolution requirements of displays, an increasing number of dies must be moved in each pick-and-place operation to fill the required display size. The second approach is to integrate a group of LEDs (e.g., monolithic chips, arrays, or matrices) onto a backplane, which eliminates the handling of individual LEDs associated with pickup. Therefore, there is a need to develop efficient methods for fabricating LED assemblies that can then be integrated onto an LED backplane. Summary of the Invention

[0004] Embodiments of this disclosure pertain to a light-emitting diode (LED) device, comprising: a plurality of mesa defining pixels, each of the plurality of mesa including a semiconductor layer comprising an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to its width; an n-contact material between each of the plurality of mesa providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along the sidewalls of the n-type layer; a first dielectric material insulating the sidewalls of the p-type layer and the active region from the n-contact material; and a plurality of mesa defining a pixel matrix, the pixel matrix being surrounded by a common electrode and comprising a plurality of semiconductor stacks surrounded by a conductive metal.

[0005] Additional embodiments are directed to a light-emitting diode (LED) device, comprising: a plurality of mesa defining pixels, each of the plurality of mesa including a semiconductor layer comprising an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to its width; an n-contact material in the space between each of the plurality of mesa providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along the sidewalls of the n-type layer; a first dielectric material insulating the sidewalls of the p-type layer and the active region from the n-contact material; a current diffusion layer on the p-type layer having a first portion and a second portion; a hard mask layer above the second portion of the current diffusion layer; a p-metal material plug above the first portion of the current diffusion layer; a passivation layer on the hard mask layer; a bump-under metallization layer on the passivation layer; and a plurality of mesa defining a pixel matrix surrounded by a common electrode comprising a plurality of passive semiconductor stacks, each semiconductor stack comprising at least one layer of GaN, the plurality of passive semiconductor stacks being surrounded by a conductive metal.

[0006] Another embodiment relates to a method of manufacturing a light-emitting diode (LED) device, comprising: depositing a plurality of semiconductor layers including an n-type layer, an active region, and a p-type layer on a substrate; etching a portion of the semiconductor layers to form trenches defining a plurality of pixels and a plurality of mesas, each of the plurality of mesas including a semiconductor layer, and each mesas having a height less than or equal to its width; depositing a first dielectric material in the trenches; depositing an n-contact material on the first dielectric material, the n-contact material providing optical isolation between each mesas and electrically contacting the n-type layer of each mesas along the sidewalls of the n-type layer, wherein the dielectric material insulates the sidewalls of the p-type layer and the active region from the n-contact material; and forming a common electrode comprising a plurality of semiconductor stacks surrounded by a conductive metal, and a common cathode surrounding the plurality of pixels. Attached Figure Description

[0007] To facilitate a detailed understanding of the features listed above in this disclosure, a more specific description of the disclosure, which has been briefly summarized above, can be made with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the disclosure and should therefore not be considered as limiting its scope, as other equivalent embodiments are permissible. The embodiments described herein are shown in the figures by way of example rather than limitation, in which similar reference numerals indicate similar elements.

[0008] Figure 1A A cross-sectional view is shown of a stack of semiconductor layers, metal layers (e.g., p-contact layers), and dielectric layers (e.g., hard mask layers) deposited on a substrate according to one or more embodiments.

[0009] Figure 1B A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0010] Figure 1C A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0011] Figure 1D A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0012] Figure 1E A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0013] Figure 1F A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0014] Figure 1G A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0015] Figure 1H A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0016] Figure 1I A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0017] Figure 1J A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0018] Figure 1KA cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0019] Figure 1L A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0020] Figure 1M A cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments, is shown;

[0021] Figure 1N For the reason Figure 1E The dashed circle 1N indicates Figure 1E A magnified view of a portion of the stack;

[0022] Figure 10 A cross-sectional view of a finished device during the manufacturing process of an LED device, according to one or more embodiments, is shown.

[0023] Figure 2 A top view of an LED array according to one or more embodiments is shown;

[0024] Figure 3A A process flow diagram of a manufacturing method according to one or more embodiments is shown;

[0025] Figure 3B A process flow diagram of a manufacturing method according to one or more embodiments is shown;

[0026] Figure 3C A process flow diagram of a manufacturing method according to one or more embodiments is shown;

[0027] Figure 3D A process flow diagram of a manufacturing method according to one or more embodiments is shown;

[0028] Figure 3E A process flow diagram of a manufacturing method according to one or more embodiments is shown;

[0029] Figure 3F A process flow diagram of a manufacturing method according to one or more embodiments is shown;

[0030] Figure 4 A cross-sectional view of an LED device according to one or more embodiments is shown;

[0031] Figure 5A An embodiment for fabricating a pixelated common cathode is shown. Figure 1G Variations; and

[0032] Figure 5B It shows the basis according to Figure 5AFurther processing of the stack Figure 10 A variant of .

[0033] For ease of understanding, the same reference numerals have been used to denote the same common elements in the figures where possible. The figures are not drawn to scale. For example, the height and width of the tabletop are not drawn to scale. Detailed Implementation

[0034] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps set forth in the following description. This disclosure can have other embodiments and can be practiced or performed in various ways.

[0035] According to one or more embodiments, as used herein, the term "substrate" refers to an intermediate or final structure having a surface or a portion thereof, on which a process is performed. Additionally, in some embodiments, reference to a substrate also refers to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, according to some embodiments, reference to deposition on a substrate includes deposition on a bare substrate, or deposition on a substrate on which one or more films, features, or materials are deposited or formed.

[0036] In one or more embodiments, "substrate" means any substrate on which a film processing is performed during the fabrication process, or a material surface formed on a substrate. In exemplary embodiments, depending on the application, substrate surfaces on which processing is performed include materials such as silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable materials such as metals, metal nitrides, group III-nitrides (e.g., GaN, AlN, InN, and alloys), metal alloys, and other conductive materials. Substrates include, but are not limited to, light-emitting diode (LED) devices. In some embodiments, the substrate is exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or baking of the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps are also performed on an underlayer formed on the substrate, and the term "substrate surface" is intended to include such an underlayer as indicated by the context. Therefore, for example, in cases where a film / layer or part of a film / layer has already been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0037] In this disclosure, the terms "wafer" and "substrate" will be used interchangeably. Thus, as used herein, a wafer is used as a substrate for forming the LED device described herein.

[0038] Referring to a micro LED (uLED) means that the light-emitting diode has one or more characteristic dimensions (e.g., height, width, depth, thickness, etc.) of less than 100 micrometers. In one or more embodiments, the value of one or more of the height, width, depth, and thickness is in the range of 2 to 25 micrometers.

[0039] Figure 1A This is a cross-sectional view of a stack of semiconductor layers, metal layers (e.g., p-contact layers), and dielectric layers (e.g., hard mask layers) deposited on a substrate during the steps of manufacturing an LED device according to one or more embodiments. Reference Figure 1A The semiconductor layer 104 is grown on the substrate 102. According to one or more embodiments, the semiconductor layer 104 includes an epitaxial layer, a group III nitride layer, or an epitaxial group III nitride layer.

[0040] The substrate can be any substrate known to those skilled in the art. In one or more embodiments, the substrate includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate is not patterned prior to the growth of the epitaxial layer(s). Therefore, in some embodiments, the substrate is not patterned and can be considered flat or substantially flat. In other embodiments, the substrate is patterned, for example, a patterned sapphire substrate (PSS).

[0041] In one or more embodiments, the semiconductor layer 104 comprises a group III nitride material, and in a specific embodiment comprises an epitaxial group III nitride material. In some embodiments, the group III nitride material includes one or more of gallium (Ga), aluminum (Al), and indium (In). Therefore, in some embodiments, the semiconductor layer 104 comprises one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), and aluminum indium gallium nitride (AlInGaN). In one or more embodiments, the semiconductor layer 104 comprises a p-type layer, an active region, and an n-type layer. In one or more embodiments, the semiconductor layer 104 comprises a group III nitride material, and in a specific embodiment comprises an epitaxial group III nitride material. In some embodiments, the group III nitride material includes one or more of gallium (Ga), aluminum (Al), and indium (In). Therefore, in some embodiments, the semiconductor layer 104 includes one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), and aluminum indium gallium nitride (AlInGaN). In one or more specific embodiments, the semiconductor layer 104 includes a p-type layer, an active region, and an n-type layer.

[0042] In one or more embodiments, substrate 102 is placed in a metal-organic vapor phase epitaxy (MOVPE) reactor for epitaxy of an LED device layer to grow semiconductor layer 104.

[0043] In one or more embodiments, semiconductor layer 104 comprises a stack of undoped group III nitride material and doped group III nitride material. Depending on whether p-type or n-type group III nitride material is required, the group III nitride material may be doped with one or more of silicon (Si), oxygen (O), boron (B), phosphorus (P), germanium (Ge), manganese (Mn), or magnesium (Mg). In a specific embodiment, semiconductor layer 104 comprises an n-type layer 104n, an active region 106, and a p-type layer 104p.

[0044] In one or more embodiments, the combined thickness of the semiconductor layer 104 is in the range of about 2µm to about 10µm, the range of about 2µm to about 10µm including the following ranges: about 2µm to about 9µm, 2µm to about 8µm, 2µm to about 7µm, 2µm to about 6µm, 2µm to about 5µm, 2µm to about 4µm, 2µm to about 3µm, 3µm to about 10µm, 3µm to about 9µm, 3µm to about 8µm, 3µm to about 7µm, 3µm to about 6µm, 3µm to about 5µm, 3µm to about 5µm, 3µm to about 5µm, 3µm to about 6µm, 3µm to about 5µm. µm, 3µm to about 4µm, 4µm to about 10µm, 4µm to about 9µm, 4µm to about 8µm, 4µm to about 7µm, 4µm to about 6µm, 4µm to about 5µm, 5µm to about 10µm, 5µm to about 9µm, 5µm to about 8µm, 5µm to about 7µm, 5µm to about 6µm, 6µm to about 10µm, 6µm to about 9µm, 6µm to about 8µm, 6µm to about 7µm, 7µm to about 10µm, 7µm to about 9µm, or 7µm to about 8µm.

[0045] In one or more embodiments, an active region 106 is formed between an n-type layer 104n and a p-type layer 104p. The active region 106 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the active region 106 comprises a group III nitride material multiple quantum well (MQW) and a group III nitride electron blocking layer.

[0046] In one or more embodiments, a p-contact layer 105 and a hard mask layer 108 are deposited on a p-type layer 104p. As shown, the p-contact layer is deposited on the p-type layer 104p, and the hard mask layer 108 is on the p-contact layer. In some embodiments, the p-contact layer 105 is deposited directly on the p-type layer 104p. In other embodiments not shown, one or more additional layers may be present between the p-type layer 104p and the p-contact layer 105. In some embodiments, the hard mask layer 108 is deposited directly on the p-contact layer 105. In other embodiments not shown, one or more additional layers may be present between the hard mask layer 108 and the p-contact layer 105. The hard mask layer 108 and the p-contact layer 105 can be deposited using any suitable technique known to those skilled in the art. In one or more embodiments, the hard mask layer 108 and the p-contact layer 105 are deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0047] As used herein, “sputter deposition” refers to the physical vapor deposition (PVD) method for thin film deposition via sputtering. In sputter deposition, materials such as group III nitrides are ejected from a target, which serves as the source, onto a substrate. This technique is based on the bombardment of the source material (target) with ions. Due to the purely physical process of sputtering the target material, the ion bombardment generates vapor.

[0048] According to some embodiments herein, “atomic layer deposition” (ALD) or “cyclic deposition” refers to a vapor-phase technique for depositing thin films on a substrate surface. An ALD process involves exposing a substrate surface or a portion of a substrate to alternating precursors, i.e., two or more reactive compounds, to deposit a layer of material on the substrate surface. When the substrate is exposed to alternating precursors, the precursors are introduced sequentially or simultaneously. Precursors are introduced into the reaction zone of a processing chamber, and the substrate or a portion of the substrate is individually exposed to the precursors.

[0049] According to some embodiments, "chemical vapor deposition (CVD)" as used herein refers to the process of depositing a thin film of material from a vapor phase by decomposing chemicals on a substrate surface. In CVD, the substrate surface is simultaneously or substantially simultaneously exposed to a precursor and / or co-agent. As used herein, "substantially simultaneously" means that most of the precursor is exposed and flows or overlaps.

[0050] According to some embodiments, "plasma-enhanced atomic layer deposition (PEALD)" as used herein refers to a technique for depositing thin films on a substrate. In some examples of PEALD processes relative to thermal ALD processes, the material can be formed from the same chemical precursors, but at a higher deposition rate and lower temperature. Generally, a PEALD process sequentially introduces reactive gases and reactive plasmas into a process chamber containing a substrate. The first reactive gas is pulsed in the process chamber and adsorbed onto the substrate surface. Subsequently, the reactant plasma is pulsed into the process chamber and reacts with the first reactant gas to form a deposited material, such as a thin film on the substrate. Similar to thermal ALD processes, a purging step can be performed between each reactant delivery.

[0051] According to one or more embodiments, "plasma-enhanced chemical vapor deposition (PECVD)" as used herein refers to a technique for depositing thin films on a substrate. In a PECVD process, a gaseous or liquid source material—such as a vapor of a gaseous or liquid Group III nitride material already entrained in a carrier gas—is introduced into a PECVD chamber. Plasma-induced gases are also introduced into the chamber. The generation of plasma within the chamber produces excited free radicals. These excited free radicals chemically bond to the substrate surface located within the chamber, forming the desired film thereon.

[0052] In one or more embodiments, the hard mask layer 108 can be fabricated using materials and patterning techniques known in the art. In some embodiments, the hard mask layer 108 comprises a metallic or dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), and aluminum oxide (AlO). x ), aluminum nitride (AlN), and combinations thereof. Those skilled in the art will recognize that using a chemical formula such as SiO to represent silicon oxide does not imply any specific stoichiometric relationship between the elements. This chemical formula merely identifies the major elements of the film.

[0053] In one or more embodiments, the p-contact layer 105 may comprise any suitable metal known to those skilled in the art. In one or more embodiments, the p-contact layer 105 comprises silver (Ag).

[0054] Figure 1B This is a cross-sectional view of the stack after the steps of manufacturing LED device 100 according to one or more embodiments. Reference Figure 1B The hard mask layer 108 and the p-contact layer 105 are patterned to form at least one opening 110 in the hard mask layer 108 and the p-contact layer 105, respectively exposing the top surface 104t of the semiconductor layer 104 and the sidewalls 108s and 105s of the hard mask layer 108 and the p-contact layer 105.

[0055] In one or more embodiments, the hard mask layer 108 and the p-contact layer 105 are patterned according to any suitable patterning technique known to those skilled in the art. In one or more embodiments, the hard mask layer 108 and the p-contact layer 105 are patterned by etching. According to one or more embodiments, the hard mask layer 108 and the p-contact layer 105 can be patterned using conventional masking, wet etching, and / or dry etching processes.

[0056] In other embodiments, nanoimprint lithography is used to transfer the pattern to the hard mask layer 108 and the p-contact layer 105. In one or more embodiments, the substrate 102 is etched using reactive ion etching (RIE) tools under conditions that efficiently etch the hard mask layer 108 and the p-contact layer 105 but very slowly etch the p-type layer 104p or not etch the p-type layer 104p at all. In other words, the etching is selective for the hard mask layer 108 and the p-contact layer 105 relative to the p-type layer 104p. During the patterning step, it should be understood that masking techniques can be used to obtain the desired pattern.

[0057] Figure 1C This is a cross-sectional view of the stack after the steps of manufacturing LED device 100 according to one or more embodiments. Reference Figure 1CInternal spacers 112 are deposited on the top surface 104t of semiconductor layer 104 and the sidewalls 108s, 105s of hard mask layer 108 and p-contact layer 105. Internal spacers 112 may comprise any suitable material known to those skilled in the art. In one or more embodiments, internal spacers 112 comprise a dielectric material. The deposition of the material forming the internal spacers is typically conformal to the substrate surface, followed by etching to obtain the internal spacers on the sidewalls 108s, 105s, rather than on the top surface 104b of semiconductor layer 104.

[0058] As used herein, the term "dielectric" refers to an electrically insulating material that can be polarized by an applied electric field. In one or more embodiments, the internal spacer 112 includes, but is not limited to, oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3); and nitrides such as silicon nitride (Si3N4). In one or more embodiments, the internal spacer 112 comprises silicon nitride (Si3N4). In other embodiments, the internal spacer 112 comprises silicon oxide (SiO2). In some embodiments, the composition of the internal spacer 112 is non-stoichiometric with respect to an ideal chemical formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), carbon oxides (e.g., silicon oxycarbonate (SiOC)), and oxynitrides (e.g., silicon oxycarbonitrile (SiNCO)).

[0059] In some embodiments, the internal spacer 112 may be a distributed Bragg reflector (DBR). As used herein, a "distributed Bragg reflector" refers to a structure (e.g., a mirror) formed by a multilayer stack of alternating thin-film materials with different refractive indices (e.g., high-refractive-index films and low-refractive-index films).

[0060] In one or more embodiments, the internal spacer 112 is deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0061] In one or more embodiments, the thickness of the internal spacer 112 ranges from about 200 nm to about 1 µm, for example: about 300 nm to about 1 µm, about 400 nm to about 1 µm, about 500 nm to about 1 µm, about 600 nm to about 1 µm, about 700 nm to about 1 µm, about 800 nm to about 1 µm, about 500 nm to about 1 µm, about 200 nm to about 900 nm, 300 nm to about 900 nm, about 400 nm to about 900 nm, about 500 nm to about 900 nm, about 600 nm to about 900 nm, about 700 nm to about 900 nm, about 800 nm to about 900 nm, about 200 nm to about 800 nm, 300 nm to about 800 nm, about 400 nm to about 800 nm, about 500 nm to about 800 nm, about 600 nm to about 800 nm, about 700 nm to about 800 nm, about 2 ... nm to about 700 nm, about 300 nm to about 700 nm, about 400 nm to about 700 nm, about 500 nm to about 700 nm, about 600 nm to about 700 nm, about 200 nm to about 600 nm, about 300 nm to about 600 nm, about 400 nm to about 600 nm, about 500 nm to about 500 nm, about 200 nm to about 500 nm, about 300 nm to about 500 nm, about 300 nm to about 400 nm, about 200 nm to about 400 nm, or about 300 nm to about 400 nm.

[0062] Figure 1D This is a cross-sectional view of the stack after the steps of manufacturing LED device 100 according to one or more embodiments. Reference Figure 1D The semiconductor layer 104 is etched to form at least one mesa, such as a first mesa 150a and a second mesa 150b. Figure 1D In the embodiment shown, the first platform 150a and the second platform 150b are separated by a groove 111 (which will be referred to as groove 111). Each groove 111 has a sidewall 113.

[0063] Figure 1E This is a cross-sectional view of the stack after the steps of manufacturing LED device 100 according to one or more embodiments. Reference Figure 1E External spacers 114 are deposited on the sidewalls 113 of the trench 111. The external spacers 114 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the external spacers 114 comprise a dielectric material. The dielectric material insulates the sidewalls (sidewalls 104s) of the p-type layer 104p and the active region 106 (sidewalls 106s) from the metal deposited in the trench 111, as referenced below. Figure 1I The material forming the external spacers is typically deposited conformally to the substrate surface, followed by etching to obtain the external spacers on the sidewalls of the trench, rather than at the bottom of the trench or on top of the hard mask layer.

[0064] In one or more embodiments, the external spacer 114 may be an oxide, such as silicon oxide (SiO2) or aluminum oxide (Al2O3); or a nitride, such as silicon nitride (Si3N4). In one or more embodiments, the external spacer 114 comprises silicon nitride (Si3N4). In other embodiments, the external spacer 114 comprises silicon oxide (SiO2). In some embodiments, the external spacer 114 may be a distributed Bragg reflector (DBR).

[0065] In one or more embodiments, the external spacer 114 is deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0066] Figure 1N For the reason Figure 1E The dashed circle 1N indicates Figure 1E A magnified view of a portion of the stack.

[0067] In one or more embodiments, such as Figure 1B , Figure 1E and Figure 1NAs shown, a dark space or dark space gap 117 is formed between adjacent edges 105e of the p-contact layer 105 on the first surface 150a and the second surface 150b. In one or more embodiments, the dark space gap 117 formed between adjacent edges 105e of the p-contact layer 105 on the first surface 150a and the second surface 150b is in the range of 10µm to 0.5µm, or in the range of 9µm to 0.5µm, or in the range of 8µm to 0.5µm, or in the range of 7µm to 0.5µm, or in the range of 6µm to 0.5µm, or in the range of 5µm to 0.5µm, or in the range of 4µm to 0.5µm, or in the range of 3µm to 0.5µm. In other embodiments, the dark gap 117 formed between adjacent edges 105e of the p-contact layer 105 on the first mesa 150a and the second mesa 150b is in the range of 10µm to 4µm, for example, in the range of 8µm to 4µm. In embodiments of the LED device 100, each of the plurality of spaced-apart mesa 150a, 150b includes a p-contact layer 105 that is both conductive and reflective, extends across a portion of each of the plurality of mesa 150a, 150b, and includes an edge 105e; and a trench 111 between each of the plurality of spaced-apart mesa results in a pixel pitch in the range of 1µm to 100µm (including values ​​and subranges from 40µm to 100µm, 41µm to 100µm, and all values ​​and subranges therein), and the dark gap 117 between adjacent edges of the p-contact layer is less than 20% of the pixel pitch. In some embodiments, the pixel pitch is in the range of 5µm to 100µm, 10µm to 100µm, or 15µm to 100µm. In some embodiments, when the pixel pitch is in the range of 10µm to 100µm, the dark area gap 117 between adjacent edges of the p-contact layer is greater than 1% of the pixel pitch and less than 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, or 5% of the pixel pitch.

[0068] In one or more embodiments, each spaced-apart platform 150a, 150b includes a sidewall 104s, each sidewall having a first segment 104s1 and a second segment 104s2 (e.g., Figure 1M As shown). The first segment 104s1 and the horizontal plane 129 parallel to the n-type layer 104n and the p-type layer 104p define an angle "a" in the range of 60 to 90 degrees (as shown). Figure 1N(As shown). In some embodiments, angle "a" is in the range of 60 to 85 degrees, 60 to 80 degrees, 60 to 75 degrees, 60 to 70 degrees, 65 to 90 degrees, 65 to 85 degrees, 65 to 80 degrees, 65 to 75 degrees, 65 to 70 degrees, 70 to 90 degrees, 70 to 85 degrees, 70 to 80 degrees, 70 to 75 degrees, 75 to 90 degrees, 75 to 85 degrees, 75 to 80 degrees, 80 to 90 degrees, or 80 to 85 degrees. In one or more embodiments, the second segment 104s2 of the sidewall forms an angle from 75 degrees to less than 90 degrees with the top surface of the substrate on which the mesa is formed.

[0069] Figure 1F This is a cross-sectional view of the stack after the steps of manufacturing LED device 100 according to one or more embodiments. Reference Figure 1F The semiconductor layer 104 is etched, and the trench 111 is enlarged (i.e., the trench depth is increased) to expose the top surface 102t of the substrate 102. In one or more embodiments, the etching is selective, such that the external spacer 114 remains on the sidewalls of the trench 111. In one or more embodiments, the trench 111 has a bottom 111b and sidewalls 113. In one or more embodiments, the depth of the trench 111 from the top surface 104t of the semiconductor layer forming the mesa is in the range of about 0.5µm to about 2µm.

[0070] Figure 1G This is a cross-sectional view of the stack after the steps of manufacturing LED device 100 according to one or more embodiments. Reference Figure 1G The first mesa 150a and the second mesa 150b are patterned to form via openings 116 on the top surface of the mesa, which expose the top surface of the semiconductor layer 104 and / or the top surface of the p-contact layer 105. In one or more embodiments, the first mesa 150a and the second mesa 150b may be patterned according to any suitable technique known to those skilled in the art, such as masking and etching processes used in semiconductor processing.

[0071] Figure 1H This is a cross-sectional view of the stack after the steps of manufacturing LED device 100 according to one or more embodiments. Reference Figure 1H A reflective liner 130 is deposited on the substrate, on the sidewalls 113 and bottom 111b of the trench 111, on the sidewalls of the outer spacer 114, and along the surface of the hard mask layer 108, as well as the top surface of the semiconductor layer 104 and / or the top surface of the p-contact layer 105. The reflective liner 130 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the reflective liner 130 comprises aluminum (Al).

[0072] In one or more embodiments, the reflective pad 130 is deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD). In one or more embodiments, the deposition of the reflective pad 130 is selective, such that the reflective pad 130 is deposited only on the sidewalls 113 of the trench 111 and the sidewalls of the external spacer 114.

[0073] Figure 1I This is a cross-sectional view of the stack after the steps of manufacturing LED devices, according to one or more embodiments. Reference Figure 1I Electrode metal 118 is deposited on a substrate—including on top of mesa 150a, 150b, in via opening 116, and in trench 111—to, for example, create n-contact material 118n and / or p-metal plug 118p and / or conductive metal 118c in the final product. Electrode metal 118 may comprise any suitable material known to those skilled in the art. In one or more embodiments, electrode metal 118 comprises copper, and electrode metal material 118 is deposited by electrochemical deposition (ECD) of copper.

[0074] Figure 1J This is a cross-sectional view of the stack after the steps of manufacturing LED device 100 according to one or more embodiments. Reference Figure 1J Electrode metal 118 is planarized, etched, or polished. Electrode metal 118 produces n-contact material 118n and p-metal plug 118p. As used herein, the term "planarization" refers to a process that smooths a surface and includes, but is not limited to, chemical mechanical polishing / planarization (CMP), etching, etc.

[0075] Figure 1K This is a cross-sectional view of the stack after the steps of manufacturing the LED device 100 according to one or more embodiments. (Refer to...) Figure 1K A passivation layer 120 is deposited on a substrate. In some embodiments, the passivation layer 120 is deposited directly on the planarized n-contact material 118n, the planarized p-metal plug 118p, the top surface of the inner spacer 112, the top surface of the outer spacer 114, and the top surface of the hard mask layer 108. In other embodiments, one or more additional layers may be present between the passivation layer 120 and the planarized n-contact material 118n, the planarized p-metal plug 118p, the top surface of the inner spacer 112, the top surface of the outer spacer 114, and the top surface of the hard mask layer 108. In some embodiments, the passivation material comprises the same material as the hard mask layer 108. In other embodiments, the passivation layer 120 comprises a material different from the hard mask layer 108.

[0076] In one or more embodiments, the passivation layer 120 may be deposited using any suitable technique known to those skilled in the art. In one or more embodiments, the passivation layer 120 may be deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0077] In one or more embodiments, the passivation layer 120 may be made of any suitable material known to those skilled in the art. In one or more embodiments, the passivation layer 120 includes a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), and aluminum oxide (AlO). x ), aluminum nitride (AlN) and combinations thereof.

[0078] Figure 1L This is a cross-sectional view of the stack after the steps of manufacturing the LED device 100 according to one or more embodiments. (Refer to...) Figure 1L The passivation layer 120 is patterned to form at least one opening 122 that exposes the top surface of the p-metal plug 118p. Two openings 122 are shown. The passivation layer 120 can be patterned using any suitable technique known to those skilled in the art, including but not limited to photolithography, wet etching, or dry etching.

[0079] Figure 1M This is a cross-sectional view of the stack after the steps of manufacturing LED device 100 according to one or more embodiments. Reference Figure 1M Under-bump metallization (UBM) material forms an under-bump metallization (UBM) layer 124a, which is deposited in the opening 122. As used herein, "under-bump metallization (UBM)" refers to the metal layer required for solder bumps in flip-chip packaging to connect a die to a substrate. In one or more embodiments, UBM layer 124a may be a patterned thin-film stack material that provides electrical connectivity from the die to the solder bump, provides a barrier function to limit unwanted diffusion from the bump to the die, and provides mechanical interconnection from the solder bump to the die by adhering to die passivation and attaching to solder bump pads. UBM layer 124a may include any suitable metal known to those skilled in the art. In one or more embodiments, UBM layer 124a may include gold (Au).

[0080] In one or more embodiments, under-bump metallization (UBM) can be achieved by any technique known to those skilled in the art, including but not limited to dry vacuum sputtering combined with electroplating. In one or more embodiments, dry vacuum sputtering combined with electroplating consists of sputtering a multi-metal layer in a high-temperature evaporation system.

[0081] exist Figure 1M In this process, the UBM layer 124a is patterned (e.g., by masking and etching). The UBM layer 124a can be patterned using any suitable technique known to those skilled in the art (including, but not limited to, photolithography, wet etching, or dry etching). The patterning of the UBM layer 124a provides anode pads at the first mesa 150a and the second mesa 150b that contact the p-metal plug 118p on the p-contact layer 105.

[0082] Figure 10 This is a cross-sectional view of a finished LED device according to one or more embodiments. Reference Figure 10 100 finished LED devices include Figure 1M The features shown include, and also, when viewed in cross-section, a common electrode (common cathode) 140 formed at one end of the device 100. A UBM material has been patterned to provide an anode pad 124a that contacts a p-metal plug 118p on a p-contact layer 105 at a first mesa 150a and a second mesa 150b. The common cathode 140 includes conductive metal 118c. An under-bump metallization (UBM) material also provides a cathode pad 124c that contacts the common cathode 140, its pattern resembling that of the UBM layer 124a. In one or more embodiments, a plurality of spaced-apart mesa 150a, 150b define a pixel matrix, and the pixel matrix is ​​surrounded by the common electrode 140.

[0083] In one or more embodiments, the common electrode 140 is a pixelated common cathode comprising a plurality of semiconductor stacks surrounded by a conductive metal. In one or more embodiments, the semiconductor stacks include a semiconductor layer 104, which, according to one or more embodiments, includes an epitaxial layer, a group III nitride layer, or an epitaxial group III nitride layer. In a specific embodiment, one or more semiconductor layers include GaN.

[0084] To create pixelated common electrodes, according to Figures 1A to 1F During processing, partial mesa is etched to expose the top surface of the semiconductor layer, rather than fabricating it. Figure 1G The through-hole opening 116 is shown. (Turn) Figure 5A The third mesa 150c and the fourth mesa 150d are etched to expose the top surface 104t of the semiconductor layer 104, thereby forming semiconductor stacks 151c and 151d, respectively. That is, the internal spacer 112, the hard mask layer 108, and the p-contact layer 105 on the third mesa 150c and the fourth mesa 150d are removed. The sidewalls of the third mesa 150c and the fourth mesa 150d are exposed when the external spacer 114 is etched. Thereafter, the processing of the third mesa 150c and the fourth mesa 150d is performed as follows: Figure 1HAdd a reflective backing layer of 130. Figure 1I Deposited electrode material 118, and Figure 1J-Figure 1M Formation as Figure 5B The pixelated common cathode is shown.

[0085] exist Figure 5B In the embodiments, the finished LED device 101 includes Figure 5A The features shown, and then based on Figure 1H-1M and Figure 1M The fabrication process includes forming a common electrode (common cathode) 141 (as shown in the cross-sectional view) at the end of device 101. UBM material has been patterned to provide an anode pad 124a that contacts a p-metal plug 118p on the p-contact layer 105 at a first mesa 150a and a second mesa 150b. A third mesa 150c and a fourth mesa 150d define or form semiconductor stacks 151c and 151d, respectively, surrounded by conductive metal 118c. Semiconductor stacks 151c and 151d are passive because they do not generate light. Under-bump metallization (UBM) material also provides a cathode pad 124c that contacts the common cathode 141, its pattern resembling that of the UBM layer 124a.

[0086] Figure 2 A top view of an LED monolithic array 200 is shown, which includes a plurality of pixels 155 (where 155a and 155b are examples), the plurality of pixels 155 being defined or formed by a plurality of spaced-apart mesa, as referenced herein. Figure 1A-1O The first mesa 150a defines or forms a first pixel 155a, and the second mesa 150b defines or forms a second pixel 155b. The third mesa 150c and the fourth mesa 150d form or provide passive pixel or semiconductor stacks 151c and 151d. Pixels 155 are arranged in a grid and connected by a common cathode 140. In one or more embodiments, the spaced-apart mesa array comprises mesa arrangements in two directions. For example, the array may comprise arrangements of 2×2 mesa, 4×4 mesa, 20×20 mesa, 50×50 mesa, 100×100 mesa, or n1×n2 mesa, wherein each of n1 and n2 is a number in the range of 2 to 1000, and n1 and n2 may be equal or unequal.

[0087] One or more embodiments provide a light-emitting diode (LED) device 100 including a plurality of spaced-apart mesa 150a, 150b defining pixels 155a, 155b. Each of the plurality of spaced-apart mesa 150a, 150b includes a semiconductor layer 104, the semiconductor layer including an n-type layer 104n, an active region 106, and a p-type layer 104p. Each of the spaced-apart mesa 150a, 150b has a height H and a width W, wherein the height H is less than or equal to the width W. The LED device 100 also includes metal 118 in a trench 111 in the form of a trench 111 between each of the plurality of spaced-apart mesa 150a, 150b. The metal 118 provides optical isolation between each of the spaced-apart mesa 150a, 150b and electrically contacts the n-type layer 104n of each of the spaced-apart mesa 150a, 150b along the sidewalls of the n-type layer 104n. In one or more embodiments, the LED device 100 includes a first dielectric material 114 that insulates the sidewalls (sidewalls 104s) of the p-type layer 104p and the active region 106 (sidewalls 106s) from the n-contact material 118n. A p-metal plug 118p is electrically connected to the p-contact layer 105. In embodiments of the LED device 100, each of a plurality of spaced-apart mesa 150a, 150b includes a conductive p-contact layer 105 extending across a portion of each of the plurality of mesa 150a, 150b and including an edge 105e, and a trench 111 between each of the plurality of spaced-apart mesa results in a pixel pitch ranging from 1µm to 100µm (inclusive of 51µm to 100µm, and all values ​​and subranges therebetween), and a dark area gap 117 between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In some embodiments, the pixel pitch is in the range of 5µm to 100µm, 10µm to 100µm, or 15µm to 100µm. In other embodiments, the dark area gap 117 is in the range of 10µm to 0.5µm, in the range of 10µm to 4µm, for example, in the range of 8µm to 4µm. As used herein according to one or more embodiments and as Figure 10 As shown, "pixel pitch" refers to the distance or interval 119 between the centers "C" of adjacent pixels provided or formed by the platforms 150a and 150b. In other words, pixel pitch refers to the center-to-center interval 119 between adjacent pixels. In one or more embodiments, for adjacent pixels 155a, 155b and all adjacent pixels of array 200, as... Figure 2The center-to-center spacing of the LED array shown is uniform. In one or more embodiments, the pixel pitch ranges from 5µm to 100µm, for example, within the following ranges: 5µm to 90µm, 5µm to 80µm, 5µm to 70µm, 5µm to 60µm, 5µm to 50µm, 5µm to 40µm, 5µm to 30µm, 10µm to 90µm, 10µm to 80µm, 10µm to 70µm, 10µm to 60µm, 10µm to 50µm, 10µm to 40µm, 10µm to 30µm, 20µm to 90µm, 20µm to 80µm, 20µm Up to 70µm, 20µm to 60µm, 20µm to 50µm, 20µm to 40µm, 20µm to 30µm, 30µm to 90µm, 30µm to 80µm, 30µm to 70µm, 30µm to 60µm, 30µm to 50µm, 30µm to 40µm, 40µm to 90µm, 40µm to 80µm, 40µm to 70µm, 40µm to 60µm, 40µm to 50µm, 50µm to 90µm, 50µm to 80µm, 50µm to 70µm, or 50µm to 60µm.

[0088] In one or more embodiments, a light-emitting diode (LED) device includes: a plurality of mesas defining pixels, each of the plurality of mesas including a semiconductor layer comprising an n-type layer, an active layer, and a p-type layer, the height of each mesas being less than or equal to its width; an n-contact material in the space between each of the plurality of mesas providing optical isolation between each mesas and electrically contacting the n-type layer of each mesas along the sidewalls of the n-type layer; a dielectric material insulating the sidewalls of the p-type layer and the active region from the n-contact material; and each of the plurality of mesas including a p-contact layer extending across a portion of each of the plurality of mesas and including an edge, and the space between each of the plurality of mesas resulting in a pixel pitch ranging from 10 µm to 100 µm and a dark area gap between adjacent edges of the p-contact layer being less than 20% of the pixel pitch. In one or more embodiments, the p-contact layer includes a reflective metal. According to the LED device of claim 1, wherein the pixel pitch is in the range of 40 µm to 100 µm. In one or more embodiments, the dark area gap between adjacent edges of the p-contact layer is less than 10% of the pixel pitch. According to claim 1, the LED device wherein the semiconductor layer is an epitaxial semiconductor layer having a thickness ranging from 2µm to 10µm. In one or more embodiments, the dielectric material is in the form of an external spacer, the external spacer comprising materials such as SiO2 and Al2O3. xMaterials selected from the group consisting of SiN, with thicknesses ranging from 200 nm to 1 µm. In one or more embodiments, the depth of the n-contact material from the top surface of the mesa ranges from 0.5 µm to 2 µm. In one or more embodiments, each mesa includes a sidewall, each sidewall having a first segment and a second segment, wherein the first segment of the sidewall defines an angle ranging from 60 degrees to 90 degrees with respect to a horizontal plane parallel to the n-type and p-type layers, and the second segment of the sidewall forms an angle ranging from 75 degrees to less than 90 degrees with respect to the top surface of the substrate on which the mesa is formed.

[0089] In one or more embodiments, a light-emitting diode (LED) device includes: a plurality of mesas defining pixels, each of the plurality of mesas including a semiconductor layer comprising an n-type layer, an active layer, and a p-type layer, the height of each mesas being less than or equal to its width; a metal in the space between each of the plurality of mesas providing optical isolation between each mesas and electrically contacting the n-type layer of each mesas along the sidewalls of the n-type layer; a dielectric material insulating the sidewalls of the p-type layer and the active layer from the metal; and each of the plurality of mesas including a p-contact layer extending across a portion of each of the plurality of mesas and including an edge, and the space between each of the plurality of mesas resulting in a pixel pitch ranging from 10 µm to 100 µm and a dark zone gap between adjacent edges of the p-contact layer ranging from 4 µm to 10 µm. The plurality of mesas includes a mesas array. In one or more embodiments, the dark zone gap is in the range of 4 µm to 8 µm. In one or more embodiments, the pixel pitch is in the range of 40 µm to 100 µm.

[0090] One or more embodiments of this disclosure provide a method for manufacturing an LED device. Figures 3A-3F A process flow diagram according to various embodiments is shown. Reference Figure 3AMethod 200 includes fabricating a substrate in operation 202. Substrate fabrication may include depositing multiple semiconductor layers on the substrate, including but not limited to n-type layers, active regions, and p-type layers. Once the semiconductor layers are deposited on the substrate, a portion of the semiconductor layers is etched to form trenches and multiple spaced-apart mesa. In operation 204, a die is fabricated. Die fabrication includes depositing a (first) dielectric material to insulate the sidewalls of the epitaxial layers (e.g., n-type layers, active regions, and p-type layers), followed by depositing electrode metal in the trenches (e.g., the spaces between each of the multiple spaced-apart mesa). In some embodiments, die fabrication further includes depositing a p-contact layer and a hard mask to form a current diffusion film, depositing p-metal plugs, followed by under-bump metallization (UBM). In operation 204, a die is fabricated. In operation 206, optional microbumps may appear on a complementary metal-oxide-semiconductor (CMOS) backplane. In operation 208, optionally, backend processing is performed to attach the die to the CMOS backplane, providing underfill, laser lift-off, followed by optional phosphor integration.

[0091] refer to Figure 3B In one embodiment, method 210 includes, at 212, depositing a plurality of semiconductor layers comprising an n-type layer, an active region, and a p-type layer on a substrate. At 214, the method further includes etching a portion of the semiconductor layers to form trenches defining a pixel and a plurality of spaced-apart mesas, each of the plurality of spaced-apart mesas comprising a semiconductor layer, and the height of each spaced-apart mesas being less than or equal to its width. At 216, the method includes depositing a dielectric material insulating the sidewalls of the p-type layer and the active region from metal. At 218, the method includes depositing electrode metal in the space between each of the plurality of spaced-apart mesas, the metal providing optical isolation between each spaced-apart mesas and electrically contacting the n-type layer of each spaced-apart mesas along the sidewalls of the n-type layer. In one or more embodiments, each of the plurality of spaced-apart mesa includes a conductive p-contact layer extending across a portion of each of the plurality of mesa and including an edge, and the space between each of the plurality of spaced-apart mesa results in a pixel pitch ranging from 1µm to 100µm and a dark area gap between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In some embodiments, the pixel pitch is in the range of 5µm to 100µm, 10µm to 100µm, or 15µm to 100µm. In other embodiments, the dark area gap is in the range of 10µm to 0.5µm, or in the range of 10µm to 4µm, for example, in the range of 8µm to 4µm. According to one or more embodiments, the term "dark area gap" as used herein refers to a space between adjacent edges of the p-contact layer where no light is reflected.

[0092] In some embodiments, the method includes forming a spaced-apart mesa array. In some embodiments, the metal comprises a reflective metal. In some embodiments, the dark area gap is in the range of 10µm to 0.5µm or in the range of 10µm to 4µm. In some embodiments, a plurality of spaced-apart mesa are arranged as pixels, and the pixel pitch is in the range of 5µm to 100µm or in the range of 30µm to 50µm. In some embodiments, the semiconductor layer 104 has a thickness in the range of 2µm to 10µm.

[0093] Reference Figure 3C , following Figure 3B Following operations 212 to 218, method 220 includes forming a common electrode in operation 222. In one or more embodiments, the common electrode comprises a plurality of semiconductor stacks surrounded by a conductive metal. In one or more embodiments, the semiconductor stacks comprise one or more layers of GaN.

[0094] refer to Figure 3D , following Figure 3B Following operations 212 to 218, method 224 includes depositing a current diffusion layer in operation 226. Some method embodiments include forming a multilayer composite film on a p-type layer, the multilayer composite film including a current diffusion layer, a p-contact layer on a first portion of the current diffusion layer, and a (second) dielectric layer on a second portion of the current diffusion layer beneath a hard mask layer. In one or more embodiments, the multilayer composite film includes a current diffusion layer on a p-type layer having a first portion and a second portion; a dielectric layer on the second portion of the current diffusion layer; via openings defined by the dielectric layer and sidewalls in the first portion of the current diffusion layer; and p-contact layers in the via openings on at least a portion of the first portion of the current diffusion layer, the sidewalls of the dielectric layer, and the surface of the dielectric layer. In one or more embodiments, the multilayer composite film is formed directly on the p-type layer. In other embodiments, one or more additional layers may be formed between the multilayer composite film and the p-type layer. In one or more embodiments, the multilayer composite layer includes a protective layer on the p-contact layer.

[0095] Some method embodiments include depositing a current diffusion layer on a p-type layer. Other method embodiments include depositing a current diffusion layer on a p-type layer; depositing a dielectric layer on the current diffusion layer; forming a via opening in the dielectric layer; conformally depositing a p-contact layer in the via opening and on the top surface of the dielectric layer; depositing a protective layer on the p-contact layer; depositing a hard mask layer on the protective layer; forming an opening in the hard mask layer; depositing a pad layer in the opening in the hard mask layer; and depositing a p-metal plug having a width on the pad layer; and forming a passivation layer on the p-metal plug having an opening of a defined width, the width of the opening in the passivation layer being smaller than the width of the combination of the p-metal plug and the pad layer in the opening.

[0096] refer to Figure 3E Some method embodiments include method 230, which includes depositing a hard mask layer over or on a p-type layer in operation 232. In operation 234, an opening is formed in the hard mask layer. In operation 236, in one or more embodiments, a pad layer is deposited in the opening in the hard mask layer. In operation 238, in one or more embodiments, a p-metal plug is deposited on the pad layer, the p-metal plug having a width, and in operation 240, a passivation layer is formed on the p-metal plug, the passivation layer having an opening of a defined width, the width of the opening in the passivation layer being smaller than the width of the p-metal plug.

[0097] In one or more embodiments, a method of manufacturing a light-emitting diode (LED) device includes: depositing a plurality of semiconductor layers including an n-type layer, an active region, and a p-type layer on a substrate; depositing a hard mask layer on the p-type layer; etching a portion of the semiconductor layers and the hard mask layer to form trenches defining pixels and a plurality of mesas, each of the plurality of mesas including a semiconductor layer, and each mesas having a height less than or equal to its width; depositing a dielectric material in the trenches; forming an opening in the hard mask layer and etching the semiconductor layers to expose a surface of the substrate and a sidewall of the n-type layer; depositing a pad layer on the substrate, including depositing the pad layer on the opening in the hard mask layer, the dielectric material, the n-type layer, and the surface of the substrate; depositing an electrode metal on the pad layer; planarizing the substrate to form an n-contact material of the n-type layer electrically contacting each mesas along the sidewall of the n-type layer, and a p-metal material plug on the pad layer in the opening of the hard mask layer, the combination of the p-metal material plug in the opening of the hard mask layer and the pad layer having a width; and forming a passivation layer on the substrate and forming an opening defining a width in the passivation layer. In one or more embodiments, the width of each opening in the passivation layer is less than the width of the combination of the p-metal plug and the liner layer.

[0098] Referring to 3F, some method embodiments include method 240, which includes depositing a semiconductor layer in operation 212, for example, as referenced. Figure 1A The method 240 further includes depositing a current diffusion film or layer and / or a p-contact layer in operation 213, for example, as described in reference. Figure 1A The method 240 further includes depositing and patterning a hard mask layer in operation 231, for example, as described in reference. Figure 1A-1C As described above. In operation 233, trenches are formed in the semiconductor layer, and a dielectric material is deposited, for example, as referenced. Figure 1D-1G As described above. In operation 234, an opening is formed in the hard mask layer, for example, as referenced. Figure 1H As described above. In operation 236, in one or more embodiments, the padding layer is deposited in an opening in the hard mask layer, for example, as referenced. Figure 1HAs described above. In operation 237, metal is deposited in the trench, and p-metal material plugs are deposited, for example, as referenced. Figure 1I As described above. In operation 239, planarization is performed, for example, as referenced. Figure 1J As described above. In operation 241, a passivation layer is formed and patterned, for example, as referenced. Figure 1K and Figure 1L As described above. In operation 243, a metallization layer under the bumps is formed and patterned, for example, as shown in reference. Figure 1M As described above. According to one or more embodiments, the operation of method 240 can be used to form, as... Figure 10 or Figure 4 The device shown.

[0099] Another aspect of this disclosure relates to electronic systems. In one or more embodiments, the electronic system includes the LED monolithic devices and arrays described herein, and driver circuitry configured to provide independent voltages to one or more p-contact layers. In one or more embodiments, the electronic system is selected from the group consisting of LED-based luminaires, light strips, light-emitting sheets, optical displays, and microLED displays.

[0100] Figure 4 This is a cross-sectional view of LED device 300, showing a single mesa 350 of the LED device according to one or more embodiments. Device 300 is similar to... Figure 10 The device 100 shown has a first mesa 150a or a second mesa 150b. The device 300 includes a semiconductor layer 304, which includes an n-type layer 304n, a p-type layer 304p, and an active region 306 between the n-type layer 304n and the p-type layer 304p.

[0101] In the illustrated embodiment, a multilayer composite film 317 is disposed on a p-type layer 304p. As shown, the multilayer composite film 317 includes a current diffusion layer 311 on the p-type layer 304p. The multilayer composite film also includes a dielectric layer 307 on the current diffusion layer 311. In one or more embodiments, the current diffusion layer 311 has a first portion 311y and a second portion 311z. The first portion 311y and the second portion 311z are lateral portions of the current diffusion layer 311. A p-contact layer 305 is disposed on the first portion 311y of the current diffusion layer 311 and in a via opening 319. The dielectric layer 307 is disposed on the second portion 311z of the current diffusion layer 311. In one or more embodiments, the dielectric layer 307 is separated by the via opening 319. The via opening 319 has at least one sidewall 319s and a bottom 319b, the bottom 319b exposing the current diffusion layer 311. In the illustrated embodiment, the via opening 319 is defined by opposite sidewalls 319s of the dielectric layer 307 and a bottom 319b defined by the current diffusion layer 311. Figure 4In the illustrated embodiment, the through-hole opening 319 is filled with a p-contact layer 305 and a protective layer 309. For example... Figure 4 As shown, the p-contact layer 305 is directly on the top surface of the dielectric layer 307, the sidewalls 319s and bottom 319b of the via opening 319, and the first portion 311y of the current diffusion layer 311. Figure 4 As shown in the embodiments, the p-contact layer 305 is substantially conformal to the via opening 319. As used herein, a “substantially conformal” layer means a layer with a generally uniform thickness in all locations (e.g., on the hard mask layer 308, on the sidewalls 319s and bottom 319b of the via opening 319). The thickness variation of a substantially conformal layer is less than or equal to about 5%, 2%, 1%, or 0.5%. In one or more embodiments, a protective layer 309 is on the p-contact layer 305. Not intended to be theoretically rigid, according to one or more embodiments, the protective layer 309 can prevent the migration of metal ions from the p-contact layer 305 and short-circuit the device 300. In one or more embodiments, the protective layer 309 covers the entire p-contact layer 305. In one or more embodiments, the protective layer 309 directly covers the entire p-contact layer 305.

[0102] In one or more embodiments, the current diffusion layer comprises a transparent material. The current diffusion layer is separate from the reflective layer. In this way, the current diffusion function is achieved in a layer different from the reflective function. In one or more embodiments, the current diffusion layer 311 comprises indium tin oxide (ITO) or other suitable conductive transparent material, such as transparent conductive oxide (TCO) (e.g., indium zinc oxide (IZO)), and the current diffusion layer 311 has a thickness ranging from 5 nm to 100 nm. In some embodiments, the dielectric layer 307 comprises any suitable dielectric material, such as silicon dioxide (SiO2) or silicon oxynitride (SiON). In some embodiments, the protective layer 309 comprises titanium-platinum (TiPt), titanium-tungsten (TiW), or titanium-tungsten nitride (TiWN). In one or more embodiments, the p-contact layer 305 comprises a reflective metal. In one or more embodiments, the p-contact layer 305 comprises any suitable reflective material, such as, but not limited to, nickel (Ni) or silver (Ag).

[0103] Not intended to be bound by theory, according to some embodiments, the multilayer composite film 317 on the p-type layer 304p can balance absorption, reflection, and conductivity. In some embodiments, the p-contact layer 305 is a highly reflective layer. At angles close to and greater than the critical angle, the dielectric layer 307 is a better reflector than the p-contact layer 305 and may not be particularly conductive. In some embodiments, the dielectric layer 307 may consist of multiple dielectric layers to form a DBR (distributed Bragg reflector). In one or more embodiments, the current diffusion layer 311 is optimized to minimize absorption and increase conductivity.

[0104] In one or more embodiments, the width of the mesa spanned by the p-contact layer 305 is smaller than the width spanned by the current diffusion layer 311.

[0105] In the illustrated embodiment, a hard mask layer 308 is present on a first portion of the protective layer 309, over a second portion 311z of the current diffusion layer 311. A hard mask opening 347 is defined in the hard mask layer 308. The hard mask layer 308 may comprise any suitable material, including dielectric materials. The hard mask layer 308 has been referenced above. Figures 1A-1N The material was masked and etched.

[0106] The hard mask opening 347 is partially filled with a liner layer 325 and partially filled with a p-metal plug 318p, the p-metal plug 318p having a width 339. For example... Figure 4 As shown in the embodiments, the padding layer 325 is substantially conformal to the hard mask opening 347. As used herein, a “substantially conformal” layer means a layer whose thickness is substantially the same everywhere (e.g., on the sidewalls 347s and the bottom 347b of the hard mask opening 347). The thickness variation of a substantially conformal layer is less than or equal to about 5%, 2%, 1%, or 0.5%. In one or more embodiments, the hard mask opening 347 has at least one sidewall 347s and a bottom surface 347b. In some embodiments, the bottom surface 347b exposes the protective layer 309. In one or more embodiments, the padding layer 325 is on at least one sidewall 347s and the bottom 347b of the hard mask opening 347. In a specific embodiment, the padding layer 325 is substantially conformal to at least one sidewall 347s and the bottom 347b of the hard mask opening 347. In the illustrated embodiment, there are two sidewalls 347 that are opposite sidewalls 347 defining the hard mask opening 347. In one or more embodiments, the thickness of the liner layer 325 ranges from about 5 nm to about 2 μm. In one or more embodiments, the liner layer 325 may include a seed material, and the liner layer 325 may include any suitable material, including but not limited to aluminum (Al), titanium nitride, silver, indium tin oxide (ITO), titanium tungsten (TiW), and / or titanium platinum (TiPt). According to some embodiments, the seed material of the liner layer 325 may facilitate the plating of the p-metal plug 318p. In one or more embodiments, the liner layer 325 serves as a bridge. The liner layer 325 may be formed by any means known to those skilled in the art, such as sputter deposition.

[0107] like Figure 4As shown, a passivation film 321 is present on the hard mask layer 308. In one or more embodiments, the passivation film 321 includes a first passivation layer 320 and a second passivation layer 322. The first passivation layer 320 and the second passivation layer 322 may comprise any suitable material. In one or more embodiments, the first passivation layer 320 comprises silicon oxide (SiO2), and the second passivation layer comprises silicon nitride (SiN). In one or more embodiments, the passivation film 321 has a passivation film opening 348 defining a width 349, the width 349 of which is less than the width 339 of the combination of the p-metal plug 318p and the pad layer 325. In one or more embodiments, the passivation film 321 is sized to cover a portion of the surface 325f of the pad layer 325 and the p-metal plug 318p. In this manner, the passivation film opening 348, smaller than the width 339 of the p-metal plug 318p and the liner layer 325, effectively protects the liner layer 325 while allowing access to the p-metal plug 318p. In one or more embodiments, each passivation film opening 348 is centered on the p-metal plug 318p.

[0108] like Figure 4 As shown, a layer of p-metal material, which may also be referred to as p-metal material plug 318p, is formed on the liner layer 325. The p-metal material plug 318p may comprise any suitable material. In one or more embodiments, the p-metal material plug 318p comprises copper (Cu). In one or more embodiments, the inner spacer 312 contacts the outer edges of the p-contact layer 305, the protective layer 309, and the hard mask layer 308. An outer spacer 314 is formed adjacent to the inner spacer 312.

[0109] In one or more embodiments, reflective pads 330 are formed at the ends of semiconductor layers 304n, 306 and 304p, which separate them from the n-contact material 318n. Figure 4 LED device 300 and Figure 10 The differences between the LED devices 300 shown are corresponding to Figure 1M The passivation layer 120 shown includes a first passivation layer 320 and, in some embodiments, a second passivation layer 322, which may include silicon nitride (SiN). In some embodiments, only the first passivation layer 320 is present, but in other embodiments, both the first passivation layer 320 and the second passivation layer 322 are present. Both the first passivation layer 320 and the second passivation layer 322 have passivation film openings 348. Figure 4 The process also includes an anode pad containing under-bump metallization 324a, the composition of which is referenced. Figure 1MThe description is as follows. The p-metal plug 318p has a width 339 defined by a distance from the outer edge of the liner layer 325, and a passivation film opening 348 in the passivation layer is filled with under-bump metallization 324a, which forms an anode pad. In one or more embodiments, the width 349 of the opening 348 is smaller than the width 339 of the p-metal plug 318p. In some embodiments, the width of the p-metal plug 318p is in the range of 2µm to 30µm (e.g., from 10µm to 20µm).

[0110] application

[0111] The LED devices disclosed herein can be monolithic arrays or matrices. The LED devices can be mounted to a backplane for use in the final application. Illumination arrays and lens systems can be combined with the LED devices disclosed herein. Applications include, but are not limited to, beam control or other applications that benefit from fine-grained intensity, spatial, and temporal control of light distribution. These applications can include, but are not limited to, precise spatial patterning of light emitted from pixel blocks or individual pixels. Depending on the application, the emitted light can be spectrally distinct, time-adaptive, and / or environmentally responsive. The emitting pixel array can provide a pre-programmed light distribution in various intensity, spatial, or temporal modes. The associated optics can be distinct at the pixel, pixel block, or device level. Example emitting pixel arrays may include devices with a central block of high-intensity pixels having associated common optics, while edge pixels may have individual optics. Besides flashlights, common applications supported by emitting pixel arrays include video lighting, automotive headlights, architectural and area lighting, and street lighting. Example

[0112] Various embodiments are listed below. It will be understood that, within the scope of this disclosure, the embodiments listed below can be combined with all aspects and other embodiments.

[0113] Example (a). A light-emitting diode (LED) device includes: a plurality of mesa defining pixels, each mesa including a semiconductor layer including an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to its width; an n-contact material between each mesa providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along the sidewalls of the n-type layer; a first dielectric material insulating the sidewalls of the p-type layer and the active region from the n-contact material; and a plurality of mesa defining a pixel matrix, the pixel matrix being surrounded by a common electrode and including a plurality of semiconductor stacks surrounded by a conductive metal.

[0114] Example (b). The LED device according to Example (a), wherein each semiconductor stack is a passive semiconductor stack comprising at least one layer of GaN.

[0115] Example (c). The LED device according to any one of Examples (a) to (b) further includes a current diffusion layer on the p-type layer.

[0116] Example (d). The LED device according to Example (c) includes a multilayer composite film, the multilayer composite film including a current diffusion layer and a second dielectric layer, the current diffusion layer having a first portion and a second portion, and the LED device further includes: a hard mask layer above the second portion of the current diffusion layer; a p-metal plug above the first portion of the current diffusion layer; a passivation layer on the hard mask layer; and a bump under-metallization layer on the passivation layer.

[0117] Example (e). The LED device according to Example (d), wherein the width of the p-metal plug is in the range of 2µm to 30µm.

[0118] Example (f). An LED device according to one of Examples (a) to (e), wherein the pixel pitch of the plurality of mesa is in the range of 5µm to 100µm.

[0119] Example (g). An LED device according to one of Examples (a) to (f), wherein the thickness of the semiconductor layer is in the range of 2µm to 10µm.

[0120] Example (h). An LED device according to any one of Examples (a) to (g), wherein the first dielectric material is in the form of an external spacer, the external spacer comprising materials from SiO2, AlO2, etc. x The materials selected from the group consisting of SiN have a thickness ranging from 200 nm to 1 µm.

[0121] Example (i). An LED device according to any one of Examples (a) to (h) includes a trench with a depth from the top surface of the mesa in the range of 0.5µm to 2µm, the trench containing n contact material.

[0122] Example (j). An LED device according to any one of Examples (a) to (i), wherein each mesa includes a sidewall of a semiconductor layer, each sidewall having a first segment and a second segment, wherein the first segment of the sidewall defines an angle in the range of 60 degrees to 90 degrees with a horizontal plane parallel to the n-type layer and the p-type layer; and the second segment of the sidewall forms an angle in the range of 75 degrees to less than 90 degrees with the top surface of the substrate on which the mesa is formed.

[0123] Example (k). An LED device according to one of Examples (a) to (j), wherein the plurality of mesa includes a mesa array.

[0124] Example (l). A method of manufacturing a light-emitting diode (LED) device includes: depositing a plurality of semiconductor layers including an n-type layer, an active region, and a p-type layer on a substrate; etching a portion of the semiconductor layers to form trenches defining a plurality of pixels and a plurality of mesas, each mesas including a semiconductor layer and each mesas having a height less than or equal to its width; depositing a first dielectric material in the trenches; depositing an n-contact material on the first dielectric material, the n-contact material providing optical isolation between each mesas and electrically contacting the n-type layer of each mesas along the sidewalls of the n-type layer, wherein the dielectric material insulates the sidewalls of the p-type layer and the active region from the n-contact material; and forming a common electrode comprising a plurality of semiconductor stacks surrounded by a conductive metal, the common electrode surrounding the plurality of pixels.

[0125] Example (m). The method according to Example (l) wherein each semiconductor stack is a passive semiconductor stack comprising at least one layer of GaN.

[0126] Example (n). The method according to any one of Examples (l) to (m) further includes forming a mesa array.

[0127] Example (o). The method according to one of Examples (l) to (n), wherein the n contact material comprises a reflective metal.

[0128] Example (p). The method according to one of Examples (l) to (o) wherein the pixel pitch of the plurality of platforms is in the range of 5µm to 100µm.

[0129] Example (q). The method according to one of Examples (l) to (p), wherein the thickness of the semiconductor layer is in the range of 2µm to 10µm.

[0130] Example (r). A light-emitting diode (LED) device includes: a plurality of mesa defining pixels, each mesa including a semiconductor layer, the semiconductor layer including an n-type layer, an active region, and a p-type layer, the height of each mesa being less than or equal to its width; an n-contact material in the space between each mesa, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along the sidewalls of the n-type layer; a first dielectric material insulating the sidewalls of the p-type layer and the active region from the n-contact material; a current diffusion layer on the p-type layer, the current diffusion layer having a first portion and a second portion; a hard mask layer above the second portion of the current diffusion layer; a p-metal material plug above the first portion of the current diffusion layer; a passivation layer on the hard mask layer; a bump-under metallization layer on the passivation layer; and a plurality of mesa defining a pixel matrix, the pixel matrix being surrounded by a common electrode including a plurality of passive semiconductor stacks, each semiconductor stack including at least one layer of GaN, the plurality of passive semiconductor stacks being surrounded by a conductive metal.

[0131] Example (s). The LED device according to Example (r), wherein the plurality of mesa includes a mesa array.

[0132] Example (t). An LED device according to one of Examples (r) to (s), wherein the pixel pitch of the plurality of mesa is in the range of 5µm to 100µm.

[0133] In the context of describing the materials and methods discussed herein (especially in the context of the following claims), the terms “a,” “an,” and “the,” and similar designations, should be interpreted as encompassing both the singular and plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the description of ranges of values ​​herein is intended only as a shorthand method for individually referring to each individual value falling within that range, and each individual value is incorporated into this specification as if it were individually described herein. Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. The use of any and all example or exemplary language (e.g., “such as”) provided herein is intended only to better elucidate the materials and methods and does not constitute a limitation on the scope unless otherwise claimed. No language in this specification should be construed as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0134] Throughout this specification, references to "an embodiment," "some embodiments," "one or more embodiments," or "embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" throughout this specification does not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, a particular feature, structure, material, or characteristic is combined in any suitable manner.

[0135] Although this disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, it is intended that this disclosure include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting diode (LED) device, comprising: Multiple mesa of a defined pixel, each mesa including a semiconductor layer, the semiconductor layer including an n-type layer, an active region and a p-type layer, the height of each mesa being less than or equal to its width; An n-contact material is provided between each tabletop, which provides optical isolation between each tabletop and electrically contacts the n-type layer of each tabletop along the sidewalls of the n-type layer; A first dielectric material insulates the sidewalls of the p-type layer and the active region from the n-contact material; A current diffusion layer on the p-type layer, the current diffusion layer having a first portion and a second portion; A hard mask layer above the second portion of the current diffusion layer; A p-metallic material plug above the first portion of the current diffusion layer; A passivation layer on the hard mask layer; Metallization layer under bumps on the passivation layer; A reflective pad is deposited on the first dielectric material, on the sidewalls and bottom of the trench between the mesa, along the hard mask layer, and on the p-type layer; and The pixel matrix, which defines multiple mesas and is surrounded by a common electrode, comprises multiple semiconductor stacks surrounded by conductive metal.

2. The LED device of claim 1, wherein each semiconductor stack is a passive semiconductor stack comprising at least one layer of GaN.

3. The LED device according to claim 1, wherein the width of the p-metal plug is in the range of 2µm to 30µm.

4. The LED device according to claim 1, wherein the pixel pitch of the plurality of mesa is in the range of 5µm to 100µm.

5. The LED device according to claim 1, wherein the thickness of the semiconductor layer is in the range of 2µm to 10µm.

6. The LED device according to claim 1, wherein the first dielectric material is in the form of an external spacer, the external spacer comprising materials such as SiO2 and Al2O3. x The materials selected from the group consisting of SiN have a thickness ranging from 200 nm to 1 µm.

7. The LED device of claim 1, wherein the LED device includes a trench, the trench being at a depth from the top surface of the mesa in the range of 0.5µm to 2µm, the trench comprising n-contact material.

8. The LED device of claim 1, wherein each mesa includes a sidewall of the semiconductor layer, each sidewall having a first segment and a second segment, wherein the first segment of the sidewall defines an angle in the range of 60 degrees to 90 degrees with a horizontal plane parallel to the n-type layer and the p-type layer; and the second segment of the sidewall forms an angle in the range of 75 degrees to less than 90 degrees with the top surface of the substrate on which the mesa is formed.

9. The LED device according to claim 1, wherein the plurality of mesas comprises a mesa array.

10. A method for manufacturing a light-emitting diode (LED) device, comprising: Multiple semiconductor layers, including an n-type layer, an active region, and a p-type layer, are deposited on a substrate; A portion of a semiconductor layer is etched to form trenches defining a plurality of pixels and a plurality of mesas, each of the plurality of mesas including the semiconductor layer, and the height of each mesas being less than or equal to its width; A first dielectric material is deposited in the trench; A reflective pad is deposited in the trench and over the semiconductor layer; An n-contact material is deposited on the first dielectric material, the n-contact material providing optical isolation between each mesa and electrically contacting the n-type layer of each mesa along the sidewalls of the n-type layer, wherein the dielectric material insulates the p-type layer and the sidewalls of the active region from the n-contact material; as well as A common electrode is formed, the common electrode comprising a plurality of semiconductor stacks surrounded by a conductive metal, the common electrode surrounding the plurality of pixels.

11. The method of claim 10, wherein each semiconductor stack is a passive semiconductor stack comprising at least one layer of GaN.

12. The method of claim 10, further comprising forming a mesa array.

13. The method of claim 10, wherein the n-contact material comprises a reflective metal.

14. The method of claim 10, wherein the pixel pitch of the plurality of mesa is in the range of 5µm to 100µm.

15. The method of claim 10, wherein the thickness of the semiconductor layer is in the range of 2µm to 10µm.

16. A light-emitting diode (LED) device, comprising: Multiple mesa of a defined pixel, each mesa including a semiconductor layer, the semiconductor layer including an n-type layer, an active region and a p-type layer, the height of each mesa being less than or equal to its width; An n-contact material in the space between each tabletop, the n-contact material providing optical isolation between each tabletop and electrically contacting the n-type layer of each tabletop along the sidewalls of the n-type layer; A first dielectric material insulates the sidewalls of the p-type layer and the active region from the n-contact material; A current diffusion layer on the p-type layer, the current diffusion layer having a first portion and a second portion; A hard mask layer above the second portion of the current diffusion layer; A p-metallic material plug above the first portion of the current diffusion layer; A passivation layer on the hard mask layer; Metallization layer under bumps on the passivation layer; A reflective pad is deposited on the first dielectric material, on the sidewalls and bottom of the trench between the mesa, along the hard mask layer, and on the p-type layer; and The pixel matrix is ​​defined by multiple mesa, the pixel matrix being surrounded by a common electrode comprising multiple passive semiconductor stacks, each semiconductor stack comprising at least one layer of GaN, the multiple passive semiconductor stacks being surrounded by a conductive metal.

17. The LED device of claim 16, wherein the plurality of mesa comprises a mesa array.

18. The LED device of claim 16, wherein the pixel pitch of the plurality of mesa is in the range of 5µm to 100µm.

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