Wafer inspection method and apparatus therefor

Abstract

The present application provides a wafer detection method and a wafer detection device. The method comprises: receiving scanning information of at least one wafer, wherein the scanning information comprises a plurality of haze values; dividing the scanning information into a plurality of information blocks according to unit blocks, and calculating a characteristic value of each of the plurality of information blocks according to the plurality of haze values included in each of the plurality of information blocks; and converting the characteristic value into a color value according to an upper limit value of haze and a lower limit value of haze, and generating a color map corresponding to the at least one wafer according to the color value converted from the characteristic value, wherein the color map displays texture content of the at least one wafer.

Description

Technical Field

[0001] This invention relates to a defect detection technology for semiconductor wafers, and more particularly to a wafer inspection method and a wafer inspection device. Background Technology

[0002] Before electronic components leave the factory, visual inspection personnel typically perform a visual inspection to check for defects or ensure the flatness of the components. For example, when determining the flatness of a silicon carbide (SiC) wafer, an automated optical inspection (AOI) device is usually used to obtain a haze image of the silicon carbide wafer, which is then manually interpreted by the human eye.

[0003] However, there is no consistent standard for interpreting visual inspections by visual inspectors, which often leads to misjudgments due to the subjective interpretation of each inspector. Therefore, how to avoid the problem of overly subjective test results caused by relying on visual inspection is a matter of concern to those skilled in the art. Summary of the Invention

[0004] This invention provides a wafer inspection method and a wafer inspection device that can convert wafer scanning information into a color map to improve the accuracy and efficiency of wafer defect identification.

[0005] An embodiment of the present invention provides a wafer inspection method applicable to an electronic device including a processor. The method includes: receiving scan information of at least one wafer, wherein the scan information includes a plurality of haze values; dividing the scan information into a plurality of information blocks according to unit blocks, and calculating feature values ​​for each of the plurality of information blocks based on the plurality of haze values ​​included in each of the plurality of information blocks; converting the feature values ​​into color values ​​based on an upper haze value and a lower haze value, and generating a color map corresponding to the at least one wafer based on the color values ​​converted from the feature values, wherein the color map displays the texture content of the at least one wafer.

[0006] In an exemplary embodiment of the present invention, the aforementioned characteristic values ​​include at least one of the mean, standard deviation, and coefficient of variation.

[0007] In an exemplary embodiment of the present invention, in the single-piece defect test mode, the maximum value among the feature values ​​is set as the upper limit of haze, and the minimum value among the feature values ​​is set as the lower limit of haze.

[0008] In an exemplary embodiment of the present invention, in both the same-batch process testing mode and the multi-batch process testing mode, the upper limit value of haze is set according to a preset upper limit value, and the lower limit value of haze is set according to a preset lower limit value.

[0009] In an exemplary embodiment of the present invention, the method further includes: marking a plurality of information blocks whose feature values ​​are greater than the upper limit of haze and less than the lower limit of haze, and calculating the number of times the feature values ​​exceed the limit in the at least one wafer based on the number of markings; and marking a plurality of information blocks whose feature values ​​are not greater than the upper limit of haze and are within the distance difference value from the upper limit of haze, and a plurality of information blocks whose feature values ​​are not less than the lower limit of haze and are within the distance difference value from the lower limit of haze, and calculating the approximate number of times the feature values ​​exceed the limit in the at least one wafer based on the number of markings.

[0010] In an exemplary embodiment of the present invention, the method further includes: performing process analysis on the process to which the at least one wafer belongs based on the number of exceedances and the approximate number of exceedances, and determining process parameters based on the analysis results of the process analysis.

[0011] In an exemplary embodiment of the present invention, the step of converting the feature value into a color value based on the upper limit of haze and the lower limit of haze further includes: dividing the numerical range between the upper limit of haze and the lower limit of haze by equal intervals according to a set value to generate a plurality of sub-haze values; setting the plurality of sub-haze values ​​to correspond to color values ​​respectively; and converting the feature value into a corresponding color value based on the plurality of sub-haze values ​​corresponding to the feature value.

[0012] An embodiment of the present invention provides a wafer inspection apparatus, including a connection device, a storage device, and a processor. The connection device is configured to connect to a scanning device to receive scanning information generated by the scanning device scanning at least one wafer, wherein the scanning information includes multiple haze values. The storage device stores one or more instructions. The processor is coupled to the connection device and the storage device and configured to execute the instructions to: receive the scanning information; divide the scanning information into multiple information blocks according to unit blocks, and calculate feature values ​​for each of the multiple information blocks based on the multiple haze values ​​included in each of the multiple information blocks; convert the feature values ​​into color values ​​according to an upper haze value and a lower haze value, and generate a color map corresponding to the at least one wafer based on the color values ​​converted from the feature values, wherein the color map displays the texture content of the at least one wafer.

[0013] In an exemplary embodiment of the present invention, the aforementioned characteristic values ​​include at least one of the mean, standard deviation, and coefficient of variation.

[0014] In an exemplary embodiment of the present invention, in single-chip defect testing mode, the processor is configured to set the maximum value among the feature values ​​as the upper limit of haze and the minimum value among the feature values ​​as the lower limit of haze.

[0015] In an exemplary embodiment of the present invention, in both the same-batch process testing mode and the multi-batch process testing mode, the processor is configured to set the upper limit value of haze according to a preset upper limit value and to set the lower limit value of haze according to a preset lower limit value.

[0016] In an exemplary embodiment of the present invention, the processor is further configured to: mark a plurality of information blocks whose feature values ​​are greater than the upper haze value and less than the lower haze value, and calculate the number of times the feature values ​​exceed the limit in the at least one wafer based on the number of marks; and mark a plurality of information blocks whose feature values ​​are not greater than the upper haze value and are within the distance difference value from the upper haze value, and a plurality of information blocks whose feature values ​​are not less than the lower haze value and are within the distance difference value from the lower haze value, and calculate the approximate number of times the feature values ​​exceed the limit in the at least one wafer based on the number of marks.

[0017] In an exemplary embodiment of the present invention, the processor is further configured to: perform process analysis on the process to which the at least one wafer belongs based on the number of exceedances and the approximate number of exceedances, and determine process parameters based on the analysis results of the process analysis.

[0018] In an exemplary embodiment of the present invention, in the operation of converting the feature value into a color value according to the upper haze value and the lower haze value, the processor is further configured to: equally distinguish the numerical range between the upper haze value and the lower haze value according to a set value to generate a plurality of sub-haze values; set the plurality of sub-haze values ​​to correspond to color values ​​respectively; and convert the feature value into a corresponding color value according to the plurality of sub-haze values ​​corresponding to the feature value.

[0019] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a wafer scanning system according to an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of a wafer inspection apparatus according to an embodiment of the present invention;

[0022] Figure 3 This is a flowchart illustrating a wafer inspection method according to an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of segmented information blocks according to an embodiment of the present invention;

[0024] Figures 5 to 6 This is a schematic diagram of a color map of a wafer according to an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of the segmentation of the same batch of wafers according to an embodiment of the present invention. Detailed Implementation

[0026] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0027] Figure 1 This is a schematic diagram of a wafer scanning system according to an embodiment of the present invention. Please refer to... Figure 1 The wafer scanning system 100 can be applied to automated optical inspection equipment to scan semiconductor chips, wafers, circuit boards, panels, and other objects under test. In other words, the wafer scanning system 100 can be used to scan the surface of the object under test to obtain scanning information about the surface.

[0028] The wafer scanning system 100 may include a scanning device 110, a transfer device 120, and a light source device 130. The scanning device 110 has an optical lens 111. In one embodiment, the scanning device 110 may transmit control signals wired or wirelessly to control at least one of the optical lens 111, the transfer device 120, and the light source device 130. The optical lens 111 may be an area scan camera and / or a line scan camera. Line scan cameras are often used in conjunction with dynamic scanning inspection to capture images while the object under test 101 is moving. This ensures the continuity of the inspection process. The transfer device 120 is used to achieve fully automated inspection. For example, the transfer device 120 can transfer the object under test 101 to the inspection area and scan it via the optical lens 111 located on one side of the inspection area to obtain information about the object under test 101 for subsequent analysis.

[0029] In different embodiments, the wafer scanning system 100 may employ various wafer scanning systems, such as optical microscope systems, scanning electron microscope (SEM) systems, focused ion beam microscope (FIB) systems, laser microscope systems, transmission electron microscope (TEM) systems, scanning probe microscope (SPM) systems, or other suitable optical imaging systems. Accordingly, when employing different wafer scanning systems, the scanning information that the wafer scanning system 100 can obtain by scanning the surface of the object under test includes parameters such as haze value, surface roughness (Ra), brightness value, contrast value, RGB hue value, saturation value, color temperature value, and gamma value, etc., which are not limited in this respect.

[0030] The light source device 130 provides a light source to assist in illuminating the object under test 101. The type of light source device 130 may be, for example, a parallel light fixture, a diffused light fixture, or a dome light, and this invention is not limited thereto. The light source device 130 can emit various types of light, such as white light, red light, green light, blue light, ultraviolet light, and infrared light. Furthermore, the type of light source device 130 can be changed to suit different types of objects under test 101. It should be noted that this invention does not limit the number of scanning devices 110, transfer devices 120, and light source devices 130.

[0031] Figure 2 This is a schematic diagram of a wafer inspection apparatus according to an embodiment of the present invention. Please refer to... Figure 2 The wafer inspection device 200 includes, but is not limited to, a connection device 210, a storage device 220, and a processor 230. The wafer inspection device 200 can be any electronic device with computing capabilities, such as a personal computer, laptop computer, or server; this invention is not limited thereto. The connection device 210 is used to connect to the scanning device 110 via wired or wireless connection to receive scanning information generated by the scanning device 100 scanning the wafer.

[0032] Storage device 220 may include volatile storage media and / or non-volatile storage media and may be used to store data. For example, the volatile storage media may be random access memory (RAM), and the non-volatile storage media may be read-only memory (ROM), solid-state drive (SSD), or conventional hard disk drive (HDD) or other similar devices or combinations thereof, for storing one or more instructions executable by processor 230.

[0033] Processor 230 is coupled to connection device 210 and storage device 220, and can access and execute instructions recorded in storage device 220 to implement the wafer inspection method of the present invention. In different embodiments, processor 230 may be, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination thereof, and the present invention is not limited thereto.

[0034] Figure 3 This is a flowchart illustrating a wafer inspection method according to an embodiment of the present invention. Please also refer to... Figure 2 and Figure 3 The method of this embodiment is applicable to the wafer inspection apparatus 200 described above, and will be used in conjunction with it below. Figure 2 and Figure 3 The components of the wafer inspection device 200 are described, and the detailed process of the method in this embodiment is explained.

[0035] It should be noted that, Figure 3 Each step can be implemented as multiple codes or circuits, and this invention is not limited thereto. Furthermore, Figure 3 The methods described herein can be used in conjunction with the following exemplary embodiments, or they can be used alone; this invention does not impose any limitations.

[0036] First, in step S302, the processor 230 receives scan information from at least one wafer, wherein the scan information includes multiple haze values. Specifically, the scan information can be formatted as a pixel array, where each pixel in the pixel array represents a specific location on the corresponding wafer and contains a haze value. The number of pixels in the array can vary depending on the resolution capability of the scanning device.

[0037] Next, in step S304, the processor 230 divides the scan information into multiple information blocks according to unit blocks, and calculates the feature values ​​of each of the multiple information blocks based on the multiple haze values ​​included in each of the multiple information blocks. Specifically, the processor 230 can group pixels in the scan information formatted as a pixel array into multiple information blocks according to unit blocks. In different embodiments, the size and setting method of the unit block can be set according to user needs, and the present invention is not limited thereto. For example, the unit block can be an N-order matrix or an MxN matrix, where M and N are integers greater than 0. For example, the processor 230 can use a 10x10 matrix as the unit block to group the pixel array into multiple information blocks. In other words, these information blocks each include 100 pixels. On the other hand, the processor 230 can set the segmentation area (e.g., 3mm). 2 4mm 2 The number of pixels included in a unit block (i.e., the size of the unit block) is calculated based on the wafer size (e.g., 8 inches, 12 inches) and the partitioned area. It is worth noting that regardless of the wafer size, the length, width, and area of ​​each information block are the same.

[0038] Next, the processor 230 calculates the feature value of each information block based on the haze value contained in the pixels of the information block. Here, the feature value can be the mean, standard deviation, coefficient of variation, etc., and the present invention is not limited thereto.

[0039] For example, Figure 4 This is a schematic diagram illustrating the segmentation of information blocks according to an embodiment of the present invention. Please refer to... Figure 4 , Figure 4 Image 401 is included, which is a graphical schematic diagram of scan information corresponding to a wafer. In this embodiment, it is assumed that the processor 230 divides the scan information into multiple information blocks BK11 to BKmn according to unit blocks, wherein each information block BK11 to BKmn includes the same number of pixels. The processor 230 can calculate the average of the haze values ​​corresponding to each pixel contained in the information block BK11, and use the calculated average as the feature value of the information block BK11. Similarly, the processor 230 can calculate the feature value corresponding to each information block BK11 to BKmn respectively. The processor 230 can store the feature values ​​as an array, wherein each element in the array represents a specific information block and contains a feature value. However, the processor 230 can also use a table to store the feature values, and the present invention does not limit the method of storing feature values.

[0040] Back Figure 3The flowchart is as follows. In step S306, the processor 230 converts the feature value into a color value based on the upper and lower haze limits, and generates a color map corresponding to the at least one wafer based on the color value converted from the feature value. The color map displays the texture content of the at least one wafer.

[0041] Specifically, the processor 230 can set an upper limit and a lower limit for haze, and, based on a set value, equally space the numerical range between the upper and lower limits to generate multiple sub-haze values. The set value can be set according to user needs, and this invention is not limited thereto. For example, the set value can be set to 0.01, 0.05, or other values. Next, the processor 230 sets each generated sub-haze value to correspond to a color value. Furthermore, the processor 230 can convert the feature value into the corresponding color value based on the sub-haze value corresponding to the feature value. The color value can be, for example, a color parameter in a color space of YCbCr, RGB, YUV, CMYK, HSV, or other formats, and this invention is not limited thereto.

[0042] In addition, process analysis can be performed on single wafers, wafers from the same batch, or wafers from different batches during wafer fabrication. In different embodiments, the present invention can set different upper and lower haze limits for different test modes. In this way, by setting appropriate upper and lower haze limits for different test modes based on their characteristics in wafer process analysis, the wafer scanning information can be converted into a color map suitable for that test mode.

[0043] In one embodiment, during single-wafer defect testing mode, the processor 230 sets the maximum value among the feature values ​​as the upper limit of haze and the minimum value among the feature values ​​as the lower limit of haze. It should be noted that, since scanning the wafer corresponds to areas outside the wafer (such as…) Figure 4 The haze value of the diagonal area in image 401 is 0, therefore the feature value of the information block outside the wafer (e.g., information block BK11) will also be calculated to be 0. The processor 230 can exclude information blocks with a feature value of 0 and set the minimum feature value among information blocks with a non-zero feature value as the lower limit of haze.

[0044] Continued Figure 4In this embodiment, for ease of explanation, it is assumed that in information blocks BK11 to BKmn, the maximum value of the feature value of the information blocks with non-zero feature values ​​is 8.00 and the minimum value is 4.00. Therefore, the processor 230 sets an upper limit for haze of 8.00 and a lower limit for haze of 4.00. Next, the processor 230 equally divides the numerical range of the upper and lower haze limits, 4.00 to 8.00, according to the set value to generate multiple sub-haze values. Specifically, assuming the set value in this embodiment is 0.01, the processor 230 can use 0.01 as the interval to equally divide the numerical range of 4.00 to 8.00 into sub-haze values ​​such as 4.00, 4.01, 4.02…7.98, 7.99, and 8.00.

[0045] After distinguishing multiple sub-haze values, the processor 230 assigns these sub-haze values ​​to color values ​​and converts the feature values ​​of the information blocks into corresponding color values. In this embodiment, color values ​​include, for example, hue, saturation, and value in the HSV color space. Specifically, the processor 230 may assign a sub-haze value of 8.00, close to the upper limit of haze, to a hue angle of 0° (i.e., red), assign a sub-haze value of 4.00, close to the lower limit of haze, to a hue angle of 240° (i.e., blue), and assign other sub-haze values ​​between 4.00 and 8.00 to colors between hue angles of 0° and 240° at equal intervals. Next, the processor 230 converts the feature values ​​of information blocks BK11 to BKmn into corresponding color values ​​based on the color values ​​corresponding to the aforementioned sub-haze values, and reassembles each information block to generate a color map for the corresponding wafer.

[0046] Figures 5 to 6 This is a schematic diagram of a color map of a wafer according to an embodiment of the present invention. Through the above steps S302 to S306, the processor 230 can convert the scan information into... Figure 5 and Figure 6 The color maps IMG_1 and IMG_2 are generated in this way. This produces color maps that can display the texture content of the wafer. For example, color map IMG_1 shows that its corresponding wafer has zebra stripes, and color map IMG_2 shows that its corresponding wafer has sunburst patterns. The converted color maps can be further provided to machines or visual inspectors for wafer defect identification, as needed.

[0047] As described in the above embodiments, setting upper and lower haze limits based on the maximum and minimum values ​​of the characteristic values ​​of each wafer allows for a rich color map for each wafer, which is beneficial for judging the defect patterns of individual wafers. However, the above method may result in different upper and lower haze limits for each wafer, making it difficult to judge the quality of the process between different wafers. Therefore, this embodiment of the invention also provides another method for setting upper and lower haze limits.

[0048] In another embodiment, in both the same-batch process testing mode and the multi-batch process testing mode, the processor 230 sets an upper limit value for haze based on a preset upper limit value and a lower limit value for haze based on a preset lower limit value. The same-batch process testing mode refers to analyzing the processing performance of multiple wafers from the same ingot, while the multi-batch process testing mode refers to analyzing the processing performance of multiple wafers processed according to different process parameters.

[0049] For ease of explanation, this embodiment assumes a preset upper limit of 8.00 and a preset lower limit of 4.00. Here, the processor 230 sets the haze upper limit to 8.00 based on the preset upper limit and the haze lower limit to 4.00 based on the preset lower limit. The specific details of converting the feature values ​​into color values ​​and generating a color map based on the haze upper and lower limits in this embodiment can be found in the above embodiment and will not be repeated here. However, it should be noted that since this embodiment sets the haze upper and lower limits based on preset values, some feature values ​​in the information block may exceed the haze upper and lower limits. Therefore, the processor 230 can mark information blocks with feature values ​​greater than the haze upper limit and less than the haze lower limit. Specifically, the processor 230 can convert feature values ​​greater than the haze upper limit into a first independent color value (e.g., white) and feature values ​​less than the haze lower limit into a second independent color value (e.g., black), where the first and second independent color values ​​may be the same or different.

[0050] In other embodiments, processor 230 may mark information blocks whose feature values ​​are not greater than the upper haze limit and are within a gap value from the upper haze limit, and information blocks whose feature values ​​are not less than the lower haze limit and are within the gap value from the lower haze limit. Specifically, processor 230 may mark feature values ​​that are not greater than the upper haze limit and not less than the lower haze limit, but close to the upper and lower haze limits, with specific color parameters, but the present invention does not limit the color parameters used for marking.

[0051] For example, assuming the upper limit of haze is 8.00 and the lower limit of haze is 4.00, the processor 230 can label feature values ​​that are not greater than the upper limit of haze and within a first difference value from the upper limit of haze, and feature values ​​that are not less than the lower limit of haze and within a first difference value from the lower limit of haze, with lower saturation. In this embodiment, the first difference value is, for example, 20% of the difference between the upper limit of haze and the lower limit of haze, i.e., 0.80. Thus, the processor 230 can convert information blocks with feature values ​​of 4.00 to 4.80 and 7.20 to 8.00 into color values ​​containing lower saturation.

[0052] In addition to converting scanned information into a color map according to the above embodiments, embodiments of the present invention can also perform process performance analysis based on various information recorded during the color map conversion. For example, when marking information blocks with feature values ​​greater than the upper haze limit and less than the lower haze limit, the processor 230 can calculate the number of feature values ​​exceeding the limit in the wafer based on the number of markings. Furthermore, when marking information blocks with feature values ​​not greater than the upper haze limit and within the distance difference value from the upper haze limit, and information blocks with feature values ​​not less than the lower haze limit and within the distance difference value from the lower haze limit, the processor 230 can calculate the approximate number of feature values ​​exceeding the limit in the wafer based on the number of exceeding the limit and / or the approximate number of exceeding the limit. In this way, the processor 230 can perform process analysis on the process to which the wafer belongs based on the number of exceeding the limit and / or the approximate number of exceeding the limit, and determine the process parameters based on the analysis results of the process analysis.

[0053] Figure 7 This is a schematic diagram illustrating the segmentation of a batch of wafers in a process according to an embodiment of the present invention. Please refer to... Figure 7 The ingot 70 can be divided into three segments: a head segment 71, a middle segment 72, and a tail segment 73. If the current wafer process testing mode is a batch process testing mode, the processor 230 can first set the number of wafers included in each segment. For example, the segmentation can be recorded such that the head segment 71 contains 3 wafers, the middle segment 72 contains 4 wafers, and the tail segment 73 contains 3 wafers. Then, the processor 230 can record the number of wafers exceeding the standard (non-zero) and the number of wafers approximately exceeding the standard (non-zero) in each segment, and perform process analysis. For example, the number of wafers, the number of wafers exceeding the standard, and the number of wafers approximately exceeding the standard in each segment in this embodiment can be recorded as shown in Table 1 below.

[0054] Table 1

[0055] Head section middle section tail section Number of wafers 3 4 3 Excessive number of wafers 1 0 0 Approximate number of wafers exceeding the standard 2 1 0

[0056] As shown in Table 1 above, the quality performance of the head section 71 is poor in the process analysis results. The processor 230 can send a notification to the testing personnel to inform them to pay attention to the process parameters of the head section 71.

[0057] On the other hand, if the current wafer fabrication process testing mode is a multi-batch process testing mode, the processor 230 can record the number of wafers exceeding the standard and / or the number of wafers approximately exceeding the standard in each batch and perform process analysis. If the analysis results show that the number of wafers exceeding the standard in the first batch is 3 and the number of wafers exceeding the standard in the second batch is 1, the processor 230 can decide to use the process parameters of the second batch for subsequent wafer processing based on the analysis results.

[0058] In summary, embodiments of the present invention propose a wafer inspection method that converts wafer scanning information into a color map, which reflects the texture content of the wafer. In one embodiment of the present invention, when converting the color map, the characteristics of different test modes in wafer process analysis are taken into account to set appropriate upper and lower haze limits for each test mode. This allows the wafer scanning information to be converted into a color map suitable for that test mode, which is beneficial to improving the accuracy of subsequent wafer defect identification. Furthermore, in one embodiment, the wafer inspection method of the present invention also records the number of wafers marked as exceeding the standard and / or approximately exceeding the standard, enabling quality analysis between different segments of the same batch of processes, or comparison and analysis between different batches of processes. Accordingly, the wafer processing status can be automatically detected, improving the efficiency of wafer inspection.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wafer inspection method, applicable to an electronic device including a processor, the method comprising: Receive scan information from at least one wafer, wherein the scan information is formatted as a pixel array, the pixel array comprising a plurality of pixels and a plurality of haze values ​​respectively corresponding to the pixels; The plurality of pixels are divided into a plurality of information blocks according to the unit block, and each plurality of information blocks includes a plurality of the pixels; Calculate the feature value of each of the plurality of information blocks based on the plurality of haze values ​​included in each of the plurality of information blocks; The upper and lower limits of haze are set according to the test mode in the wafer process analysis. The test mode is either the same batch process test mode or the multi-batch process test mode. as well as The feature values ​​of each of the plurality of information blocks are converted into color values ​​according to the upper and lower haze values, and a color map corresponding to the at least one wafer is generated based on the color values ​​of each of the plurality of information blocks, wherein the color map displays the texture content of the at least one wafer. When the test mode is a same batch process test mode or a multi-batch process test mode, the upper limit value of haze is set according to a preset upper limit value, and the lower limit value of haze is set according to a preset lower limit value.

2. The wafer inspection method according to claim 1, wherein the feature value includes at least one of the mean, standard deviation and coefficient of variation.

3. The wafer inspection method according to claim 1, wherein the method further comprises: The plurality of information blocks whose feature values ​​are greater than the upper limit of haze and less than the lower limit of haze are marked, and the number of feature values ​​exceeding the limit in the at least one wafer is calculated based on the number of marks; as well as The plurality of information blocks whose feature values ​​are not greater than the upper limit of haze and are within the distance difference value from the upper limit of haze, and the plurality of information blocks whose feature values ​​are not less than the lower limit of haze and are within the distance difference value from the lower limit of haze, are marked, and the approximate number of times the feature values ​​in the at least one wafer exceed the standard is calculated based on the number of markings.

4. The wafer inspection method according to claim 3, wherein the method further comprises: Based on the number of defects exceeding the standard and the number of near defects exceeding the standard, process analysis is performed on the process to which the at least one wafer belongs, and process parameters are determined based on the analysis results of the process analysis.

5. The wafer inspection method according to claim 1, wherein the step of converting the feature value into a color value based on the upper limit of haze and the lower limit of haze further includes: Based on a set value, the numerical range between the upper limit value and the lower limit value of fog is divided at equal intervals to generate multiple sub-fog values; The multiple sub-haze values ​​are respectively assigned to color values; as well as Based on the plurality of sub-haze values ​​corresponding to the feature value, the feature value is converted into a corresponding color value.

6. A wafer inspection device, comprising: A connection device for connecting to a scanning device to receive scanning information generated by the scanning device scanning at least one wafer, wherein the scanning information is formatted as a pixel array, the pixel array including a plurality of pixels and a plurality of haze values ​​respectively corresponding to the pixels; Storage device, storing one or more instructions; as well as A processor, coupled to the connectivity device and the storage device, and configured to execute the instructions to: Receive the scan information; The plurality of pixels are divided into a plurality of information blocks according to the unit block, and each plurality of information blocks includes a plurality of the pixels; Calculate the feature value of each of the plurality of information blocks based on the plurality of haze values ​​included in each of the plurality of information blocks; The upper and lower limits of haze are set according to the test mode in the wafer process analysis. The test mode is either the same batch process test mode or the multi-batch process test mode. as well as The feature values ​​of each of the plurality of information blocks are converted into color values ​​based on the upper and lower haze limits, and a color map corresponding to the at least one wafer is generated based on the color values ​​of each of the plurality of information blocks, wherein the color map displays the texture content of the at least one wafer. When the test mode is a same batch process test mode or a multi-batch process test mode, the processor is configured to set the haze upper limit value according to a preset upper limit value and set the haze lower limit value according to a preset lower limit value.

7. The wafer inspection apparatus according to claim 6, wherein the characteristic value includes at least one of the mean, standard deviation, and coefficient of variation.

8. The wafer inspection apparatus of claim 6, wherein the processor is further configured to: Mark the plurality of information blocks whose feature values ​​are greater than the upper limit of haze and less than the lower limit of haze, and calculate the number of feature values ​​exceeding the limit in the at least one wafer based on the number of markings; and The plurality of information blocks whose feature values ​​are not greater than the upper limit of haze and are within the distance difference value from the upper limit of haze, and the plurality of information blocks whose feature values ​​are not less than the lower limit of haze and are within the distance difference value from the lower limit of haze, are marked, and the approximate number of times the feature values ​​in the at least one wafer exceed the standard is calculated based on the number of markings.

9. The wafer inspection apparatus of claim 8, wherein the processor is further configured to: Based on the number of defects exceeding the standard and the number of near defects exceeding the standard, process analysis is performed on the process to which the at least one wafer belongs, and process parameters are determined based on the analysis results of the process analysis.

10. The wafer inspection apparatus of claim 6, wherein in the operation of converting the feature value into a color value according to the upper haze value and the lower haze value, the processor is further configured to: Based on a set value, the numerical range between the upper limit value and the lower limit value of fog is divided at equal intervals to generate multiple sub-fog values; The plurality of sub-haze values ​​are respectively assigned to color values; and Based on the plurality of sub-haze values ​​corresponding to the feature value, the feature value is converted into a corresponding color value.

Images