A DC parameter testing system and method

Abstract

The present invention discloses a DC parameter testing system and method. The system includes: a host computer, configured to generate a first parameter using a data compression algorithm and transmit the result to a TMU control board, and to map a second test result to the memory corresponding to each test channel; a TMU control board, configured to parse the first parameter according to a first data format to obtain a second parameter, read the first test result, and package the result according to a second data format to generate a second test result; a PEC module, configured to configure the channel parameters of a PMU test chip according to the second parameter, read the first test result according to a configuration end signal, and save the first test result according to the test channel; and a PMU test chip, configured to perform a DC parameter test on a chip under test according to the channel parameters and generate a first test result after the test is completed. The present invention implements efficient multi-channel DC parameter testing and multi-test station parallel testing, and can be widely applied in the field of testing technology.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a DC parameter testing system and method. Background Art

[0002] During mass production chip testing (including CP / FT testing), a number of DC parameter tests are typically required, such as open / short circuit (OS) testing and leakage current testing. These tests often involve a large number of chip pins. When testing a large number of chips, DC parameter testing can take up a significant amount of time, impacting chip testing costs and production efficiency.

[0003] In traditional DC parameter testing methods, the host computer configures the slave computer channel by channel based on the channels to be tested and serially reads back the test results after a delay. Each time a channel's DC parameter is tested, the host computer must send channel configuration information to perform the channel configuration. Furthermore, because the generation time for each channel's DC parameter test result is not fixed, the host computer's delay is often set to a long time, significantly increasing the DC parameter test time. Furthermore, when performing parallel DC parameter testing at multiple test stations, each test station must be tested individually, and the host computer also needs to delay and wait for a period of time before serially reading back the test results, resulting in low efficiency for parallel DC parameter testing at multiple test stations. Summary of the Invention

[0004] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0005] Therefore, an object of the embodiments of the present invention is to provide a DC parameter testing system and method, which realizes efficient multi-channel DC parameter testing.

[0006] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include:

[0007] In a first aspect, an embodiment of the present invention provides a DC parameter testing system, comprising:

[0008] The host computer is configured to generate a first parameter using a data compression algorithm and send the first parameter to the TMU control board, wherein the first parameter includes a compressed second parameter, and the second parameter includes a test channel, a corresponding test mode, and a corresponding configuration parameter; and is configured to map the second test result to a memory corresponding to each test channel according to the test channel;

[0009] The TMU control board is configured to parse the first parameter according to a first data format to obtain the second parameter; and to read the first test result saved by the PEC module, and package the first test result according to a second data format to generate the second test result, where the first data format and the second data format are data formats agreed upon by the host computer and the TMU control board;

[0010] a PEC module, configured to configure the channel parameters of the PMU test chip according to the second parameters; and to read the first test result after performing internal FPGA delay processing according to a configuration end signal, and save the first test result according to the test channel, wherein the configuration end signal is a signal generated by the PEC module after completing the configuration of the channel parameters of the PMU test chip;

[0011] The PMU test chip is used to perform a DC parameter test on each of the test channels of the chip under test according to the channel parameters, and generate the first test result after the test is completed.

[0012] In addition, a DC parameter testing system according to the above embodiment of the present invention may also have the following additional technical features:

[0013] Furthermore, in a DC parameter test system according to an embodiment of the present invention, the PEC module includes a plurality of PEC boards, and the PEC board includes 32 channels;

[0014] The PEC board configures the channel parameters using a state machine stepping method according to the second parameters.

[0015] Furthermore, in one embodiment of the present invention, the PMU test chip configures the working mode of each of the test channels according to the channel parameters, and the working modes include applying voltage to measure current, applying voltage to measure voltage, applying current to measure voltage, and applying current to measure current, and the DC parameter test of the chip to be tested is performed through each of the test channels according to the working mode.

[0016] Furthermore, in one embodiment of the present invention, the DC parameter testing system further includes an ADC module;

[0017] The PEC module performs FPGA internal delay processing according to the configuration end signal and then sends a start signal. The ADC module reads the first test result in the PMU test chip in parallel according to the start signal and generates a first notification. The PEC module reads the first test result according to the first notification.

[0018] In a second aspect, an embodiment of the present invention provides a DC parameter testing method, which is applied to a DC parameter testing system. The DC parameter testing system includes a host computer, a TMU control board, a PEC module, and a PMU test chip. The method includes:

[0019] The host computer generates a first parameter using a data compression algorithm and sends the first parameter to the TMU control board, wherein the first parameter includes a compressed second parameter, and the second parameter includes a test channel, a corresponding test mode, and a corresponding configuration parameter;

[0020] Parsing the first parameter by the TMU control board according to a first data format to obtain the second parameter, wherein the first data format is a data format agreed upon by the host computer and the TMU control board;

[0021] According to the second parameter, configuring the channel parameters of the PMU test chip through the PEC module;

[0022] According to the channel parameters, the PMU test chip performs a DC parameter test on the chip to be tested, and generates a first test result after the test is completed;

[0023] According to a configuration end signal, the PEC module performs internal FPGA delay processing and then reads the first test result, and saves the first test result according to the test channel. The configuration end signal is a signal generated by the PEC module after completing the configuration of the channel parameters of the PMU test chip;

[0024] Reading the first test result saved by the PEC module through the TMU control board, and packaging the first test result according to a second data format to generate a second test result, where the second data format is a data format agreed upon by the host computer and the TMU control board;

[0025] According to the test channels, the second test results are mapped to memories corresponding to the respective test channels by the host computer.

[0026] Furthermore, in one embodiment of the present invention, the PEC module includes a plurality of PEC boards, each of which includes 32 channels;

[0027] Configuring the channel parameters of the PMU test chip through the PEC module according to the second parameter includes:

[0028] According to the second parameter, the channel parameters are configured through the PEC board using a state machine stepping.

[0029] Furthermore, in one embodiment of the present invention, configuring the channel parameters by the PEC board using a state machine stepwise according to the second parameter includes:

[0030] According to the initial state of the state machine, a first channel is selected as the current channel, where the first channel is the first channel on the PEC board;

[0031] According to the test channel, determining whether the current channel needs to be configured;

[0032] If so, configuring the current channel according to the test mode and the configuration parameters;

[0033] Confirm that the current channel configuration is complete and the current channel is not the last channel on the PEC board, select the second channel as the current channel, and return to the step of determining whether the current channel needs to be configured based on the test channel. The second channel is the next channel of the current channel on the PEC board.

[0034] Furthermore, in one embodiment of the present invention, after the step of determining whether the current channel needs to be configured based on the test channel, the method further includes:

[0035] If not, confirm that the current channel is not the last channel on the PEC board, select the second channel as the current channel, and return to the step of determining whether the current channel needs to be configured based on the test channel.

[0036] Furthermore, in one embodiment of the present invention, performing a DC parameter test of each test channel on the chip to be tested by the PMU test chip according to the channel parameters includes:

[0037] Configure the working mode of each test channel according to the channel parameters, wherein the working modes include applying voltage to measure current, applying voltage to measure voltage, applying current to measure voltage, and applying current to measure current;

[0038] Perform a DC parameter test on the chip to be tested through each of the test channels according to the working mode.

[0039] Furthermore, in one embodiment of the present invention, the DC parameter testing system further includes an ADC module;

[0040] The step of reading the first test result through the PEC module according to the configuration end signal includes:

[0041] According to the configuration end signal, the PEC module performs internal delay processing on the FPGA and then sends a start signal;

[0042] According to the start signal, reading the first test result in the PMU test chip in parallel through the ADC module and generating a first notification;

[0043] According to the first notification, the first test result is read through the PEC module.

[0044] The advantages and benefits of the present invention will be described in part in the following description and will become apparent from the following description or learned through practice of the present application:

[0045] In an embodiment of the present invention, a host computer compresses a second parameter of a multi-channel test to obtain a first parameter, and sends the first parameter to a TMU control board for parsing to obtain a second parameter. Furthermore, channel parameters for a multi-channel test of a PMU test chip are configured based on the second parameter, thereby enabling the host computer to send single channel configuration information in a multi-channel DC parameter test scenario, thereby improving channel configuration efficiency and thus DC parameter test efficiency. After the PMU test chip completes parameter configuration, it generates a configuration completion signal to a PEC module, while simultaneously performing a DC parameter test of the chip under test. The PEC module performs internal FPGA delay processing based on the test response time of the PMU test chip, and then reads the first test result, thereby achieving precise delay in reading the test result and further shortening the time consumption of the DC parameter test process. The first test result is read in parallel, packaged into a second test result by the TMU control board, and then read back to the host computer, thereby achieving rapid reading of the DC parameters of the test channel. The PEC module saves the first test result based on the test channel, enabling the TMU control board to read data of any test channel in parallel, thereby enabling simultaneous testing of the same DC parameter of each test station during parallel testing of multiple test stations, thereby improving the efficiency of parallel testing of multiple test stations. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following introduction is made to the drawings of the embodiments of the present application or the related technical solutions in the prior art. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 The figure is a flow chart of a specific embodiment of a DC parameter testing method of the present invention. DETAILED DESCRIPTION

[0048] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. The step numbers in the following embodiments are provided only for the convenience of explanation and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0049] The terms "first," "second," "third," and "fourth," etc., in the specification, claims, and accompanying drawings of the present invention are used to distinguish between different items, not to describe a specific order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0050] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0051] During DC parameter testing of chips, open / short (OS) and leakage current tests are often performed frequently. These tests often involve a large number of chip pins. When testing a large number of devices, DC parameter testing can take up a significant amount of time, increasing chip testing costs and impacting chip production efficiency.

[0052] In traditional DC parameter testing methods, the host computer configures the slave computer channel by channel based on the channels to be tested and serially reads back the test results after a delay. Each time a channel's DC parameter is tested, the host computer must send channel configuration information to perform the channel configuration. Furthermore, because the generation time for each channel's DC parameter test result is not fixed, the host computer's delay is often set to a long time, significantly increasing the DC parameter test time. Furthermore, when performing parallel DC parameter testing at multiple test stations, each test station must be tested individually, and the host computer also needs to delay and wait for a period of time before serially reading back the test results, resulting in low efficiency for parallel DC parameter testing at multiple test stations.

[0053] To this end, the present invention proposes a DC parameter testing system and method. A host computer compresses a second parameter of a multi-channel test to obtain a first parameter, and sends the first parameter to a TMU control board for parsing to obtain a second parameter. Then, channel parameters of a PMU test chip multi-channel test are configured according to the second parameter, thereby achieving single channel configuration information sending by the host computer in a multi-channel DC parameter test scenario, improving channel configuration efficiency, and thus improving DC parameter testing efficiency. After the PMU test chip completes parameter configuration, it generates a configuration end signal to a PEC module, and simultaneously performs a DC parameter test of the chip under test. The PEC module performs internal FPGA delay processing according to the test response time of the PMU test chip, and then reads the first test result, thereby achieving precise delay in reading the test result and further shortening the time consumption of the DC parameter testing process. The first test result is read in parallel, packaged into a second test result by the TMU control board, and then read back to the host computer. Combined with the channel parameter configuration of the PMU test chip multi-channel test, simultaneous testing of the same DC parameter of each test station during parallel testing of multiple test stations is achieved, thereby improving the parallel testing efficiency of multiple test stations.

[0054] A DC parameter testing system and method according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. First, a DC parameter testing system according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0055] A DC parameter testing system according to an embodiment of the present invention includes:

[0056] The host computer is configured to generate a first parameter using a data compression algorithm and send the first parameter to the TMU control board, wherein the first parameter includes a compressed second parameter, and the second parameter includes a test channel, a corresponding test mode, and a corresponding configuration parameter; and is configured to map the second test result to a memory corresponding to each test channel according to the test channel;

[0057] The TMU control board is configured to parse the first parameter according to a first data format to obtain the second parameter; and to read the first test result saved by the PEC module, and package the first test result according to a second data format to generate the second test result, where the first data format and the second data format are data formats agreed upon by the host computer and the TMU control board;

[0058] a PEC module, configured to configure the channel parameters of the PMU test chip according to the second parameters; and to read the first test result after performing internal FPGA delay processing according to a configuration end signal, and save the first test result according to the test channel, wherein the configuration end signal is a signal generated by the PEC module after completing the configuration of the channel parameters of the PMU test chip;

[0059] The PMU test chip is used to perform a DC parameter test on each of the test channels of the chip under test according to the channel parameters, and generate the first test result after the test is completed.

[0060] The host computer and the TMU control board agree on a set of data formats, including the first data format and the second data format.

[0061] Specifically, in an embodiment of the present invention, the first data format is the format of the channel configuration information generated by the host computer, that is, the format of the second parameter, including an indication of each test channel and the corresponding channel configuration (test mode and test parameters), as follows:

[0062] Test channel indication (channel per bit) + basic configuration (common configuration) + proprietary configuration 1 + ... + proprietary configuration n

[0063] Channel per Bit: "1" means that this channel needs to be configured, "0" means that this channel does not need to be configured

[0064] In one embodiment of the present invention, the basic configuration includes a 32-bit address (including a board address and a register address) + 32-bit data.

[0065] In one embodiment of the present invention, if the host computer needs to send configuration information for 256 channels, the second parameter is:

[0066] 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF+0x1000000000000000+0x1000000000000001+...+0x10000000000000ff

[0067] The data length of the second parameter is 256bit+64bit*256=16640bit. The first parameter is generated by the host computer using a data compression algorithm:

[0068] 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF+0x1000000000000000+0x01+...+0xff

[0069] The data length of the first parameter is 256 bits + 64 bits + 8 bits * 256 = 2368 bits.

[0070] It can be seen from this that the embodiment of the present invention obtains the first parameter by compressing the second parameter, and sends the first parameter with a shorter data length to the TMU control board. The TMU control board parses the first parameter according to the agreed first data format and restores the second parameter, which greatly reduces the amount of data sent by the host computer, improves the transmission efficiency of the channel configuration information, and thus improves the channel configuration efficiency.

[0071] In an embodiment of the present invention, the second data format is a format for reading data agreed upon by the host computer and the TMU control board, specifically as follows:

[0072] Test channel 1 data + test channel 2 data + ... + test channel n data

[0073] Based on the number of test channels and the second data format sent by the host computer, the TMU control board sequentially packages the test channel data into a series of data (the second test results) and sends it to the host computer. The host computer constructs a memory parsing pattern corresponding to the number of test channels in its memory. Using this memory parsing pattern, the host computer directly populates the second test results into the corresponding memory of the test channels, thereby quickly obtaining the test results for each test channel.

[0074] In an embodiment of the present invention, if the number of test channels sent by the host computer is 8, and the second test result is 0x0123456789abcdef 0123456789abcdef, the second test result is filled in the format of the constructed memory parsing mode:

[0075]

[0076] It can be seen from this that the embodiment of the present invention obtains the second test result by packaging the first test result according to the second data format through the TMU control board, and maps the second test result to the memory corresponding to each test channel through rapid parsing by the host computer, thereby realizing efficient reading of the test results of each test channel and improving the efficiency of DC parameter testing.

[0077] Wherein, as an optional embodiment, the PEC module includes multiple PEC boards, and the PEC board includes 32 channels;

[0078] The PEC board configures the channel parameters using a state machine stepping method according to the second parameters.

[0079] Specifically, each PEC board includes 32 channels and 32 independent registers for storing test channel data. The host computer can read the test channel data stored in the registers and read the test results of any test channel, thereby achieving the effect of simultaneous testing at multiple test stations and improving test efficiency.

[0080] As an optional implementation, the PMU test chip configures the working mode of each of the test channels according to the channel parameters, and the working modes include applying voltage to measure current, applying voltage to measure voltage, applying current to measure voltage, and applying current to measure current, and performs DC parameter testing on the chip to be tested through each of the test channels according to the working mode.

[0081] Specifically, in an embodiment of the present invention, the PMU test chip has five different ranges of gear testing. The PMU test chip configures the operating mode of each test channel based on channel parameters, further comprising configuring the range and clamping voltage / current of each test channel. After configuration is complete, the PMU test chip automatically tests the corresponding DC parameters of the chip under test through each test channel according to the configured operating mode. After completing the testing of each test channel, the PMU test chip converts the DC parameter (current or voltage) of each test channel into the first test result (voltage value) using a conversion formula and outputs the first test result to a specific pin for reading.

[0082] As an optional implementation, the DC parameter testing system further includes an ADC module;

[0083] The PEC module performs FPGA internal delay processing according to the configuration end signal and then sends a start signal. The ADC module reads the first test result in the PMU test chip in parallel according to the start signal and generates a first notification. The PEC module reads the first test result according to the first notification.

[0084] Specifically, the PEC module activates the ADC module. The activation signal controls the ADC module via the SPI interface to concurrently read the first test result from the PMU test chip. After the ADC module completes the reading, it raises the ad2_data_valid signal (generating the first notification) to notify the PEC module to read the first test result. After reading the first test result, the PEC board in the PEC module stores the DC parameters of each test channel in a corresponding register, waiting for the TMU control board to read it.

[0085] In summary, a DC parameter testing system according to an embodiment of the present invention compresses the second parameter of a multi-channel test by a host computer to obtain a first parameter, and sends the first parameter to the TMU control board for parsing to obtain a second parameter. Then, the channel parameters of the multi-channel test of the PMU test chip are configured according to the second parameter, thereby achieving single-shot channel configuration information sending by the host computer in a multi-channel DC parameter test scenario, improving channel configuration efficiency, and thus improving DC parameter testing efficiency. When the configuration is completed, a configuration completion signal is generated to notify the PEC module, and the PEC module performs internal FPGA delay processing and then reads the first test result, thereby achieving precise delay in reading the test result and further shortening the time consumption of the DC parameter testing process. The first test result is read in parallel and packaged into a second test result by the TMU control board and then read back to the host computer, thereby achieving fast reading of the DC parameters of the test channel. The PEC module saves the first test result according to the test channel, allowing the TMU control board to read data of any test channel in parallel, achieving simultaneous testing of the same DC parameter of each test station when multiple test stations are tested in parallel, and improving the efficiency of parallel testing of multiple test stations.

[0086] Secondly, refer to Figure 1 The embodiment of the present invention provides a DC parameter testing method, which is applied to a DC parameter testing system. The DC parameter testing system includes a host computer, a TMU control board, a PEC module, and a PMU test chip. The method includes:

[0087] S101, the host computer uses a data compression algorithm to generate a first parameter and sends it to the TMU control board;

[0088] The first parameters include compressed second parameters, and the second parameters include a test channel, a corresponding test mode, and a corresponding configuration parameter.

[0089] S102: Parsing the first parameter by the TMU control board according to the first data format to obtain the second parameter;

[0090] The first data format is a data format agreed upon by the host computer and the TMU control board.

[0091] Specifically, in an embodiment of the present invention, the first data format is the format of the channel configuration information generated by the host computer, that is, the format of the second parameter, including an indication of each test channel and the corresponding channel configuration (test mode and test parameters), as follows:

[0092] Test channel indication (channel per bit) + basic configuration (common configuration) + proprietary configuration 1 + ... + proprietary configuration n

[0093] In one embodiment of the present invention, the basic configuration includes a 32-bit address (including a board address and a register address) + 32-bit data.

[0094] In one embodiment of the present invention, if the host computer needs to send configuration information for 256 channels, the second parameter is:

[0095] 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF+0x1000000000000000+0x1000000000000001+...+0x0x10000000000000ff

[0096] The data length of the second parameter is 256bit+64bit*256=16640bit. The first parameter is generated by the host computer using a data compression algorithm:

[0097] 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF+0x1000000000000000+0x01+...+0xff

[0098] The data length of the first parameter is 256 bits + 64 bits + 8 bits * 256 = 2368 bits.

[0099] It can be seen from this that the embodiment of the present invention obtains the first parameter by compressing the second parameter, and sends the first parameter with a shorter data length to the TMU control board. The TMU control board parses the first parameter according to the agreed first data format and restores the second parameter, which greatly reduces the amount of data sent by the host computer, improves the transmission efficiency of the channel configuration information, and thus improves the channel configuration efficiency.

[0100] S103: Configure the channel parameters of the PMU test chip through the PEC module according to the second parameters;

[0101] The PEC module includes multiple PEC boards, each of which has 32 channels. If the PEC module has eight PEC boards (PEC0-7), there are a total of 256 channels. PEC0 has channels 0-31, PEC1 has channels 32-63, PEC2 has channels 64-95, PEC3 has channels 96-127, PEC4 has channels 128-159, PEC5 has channels 160-191, PEC6 has channels 192-223, and PEC7 has channels 224-255.

[0102] Specifically, according to the second parameter, the channel parameters are configured step by step using a state machine through the PEC board.

[0103] S103 can be further divided into the following steps S1031-S1034:

[0104] Step S1031: Select the first channel as the current channel according to the initial state of the state machine;

[0105] The first channel is the first channel on the PEC board.

[0106] Specifically, in the embodiment of the present invention, IDLE_STATE is the initial state of the state machine, CONT<=0, Setting_flag<=32'hffffffff, set_done<=1'b1. The first channel is selected as the current channel through Jump_0_state.

[0107] Step S1032: Determine whether the current channel needs to be configured based on the test channel;

[0108] Specifically, let CONT<=1, set_done<=1'b0, start step configuration, and determine whether the current channel needs to be configured through the indication of the test channel (channel per Bit), that is, determine whether the current channel is in the test channel.

[0109] Step S1033: If yes, configure the current channel according to the test mode and the configuration parameters;

[0110] Specifically, if yes, jump to Setting_N_state (N=0,…,31) state and start configuring the current channel.

[0111] If not, confirm that the current channel is not the last channel on the PEC board, select the second channel as the current channel through Jump_N+1_state, and return to step S1032. The second channel is the next channel of the current channel on the PEC board.

[0112] Step S1034: Confirm that the current channel configuration is complete and that the current channel is not the last channel on the PEC board, select the second channel as the current channel, and return to step S1032.

[0113] The second channel is the next channel of the current channel on the PEC board.

[0114] Specifically, the second channel is selected as the current channel through Jump_N+1_state.

[0115] It is understandable that each PEC board can configure the channel parameters of 32 test channels. After each test channel is configured, the setting_flag flag is used to accurately jump to the next channel configuration, making the channel configuration seamless and improving efficiency.

[0116] After each test channel is configured, set_done is set to 1 to generate a configuration end signal. The PEC module performs internal FPGA delay processing based on the configuration end signal and then starts the ADC module to read the first test result.

[0117] S104: Perform a DC parameter test of each test channel on the chip under test using the PMU test chip according to the channel parameters, and generate a first test result after the test is completed;

[0118] Specifically, performing a DC parameter test on each test channel of the chip to be tested by the PMU test chip includes the following steps:

[0119] (1) configuring the working mode of each test channel according to the channel parameters, wherein the working modes include applying voltage to measure current, applying voltage to measure voltage, applying current to measure voltage, and applying current to measure current;

[0120] (2) Performing DC parameter testing on the chip to be tested through each of the test channels according to the working mode.

[0121] Specifically, in an embodiment of the present invention, the PMU test chip has five different ranges of gear testing. The PMU test chip configures the operating mode of each test channel based on channel parameters, further comprising configuring the range and clamping voltage / current of each test channel. After configuration is complete, the PMU test chip automatically tests the corresponding DC parameters of the chip under test through each test channel according to the configured operating mode. After completing the testing of each test channel, the PMU test chip converts the DC parameter (current or voltage) of each test channel into the first test result (voltage value) using a conversion formula and outputs the first test result to a specific pin for reading.

[0122] S105: According to the configuration end signal, the PEC module performs FPGA internal delay processing according to the test response time of the PMU test chip and then reads the first test result, and saves the first test result according to the test channel.

[0123] The configuration completion signal is a signal generated after the PEC module completes the configuration of the channel parameters of the PMU test chip. In an embodiment of the present invention, the DC parameter test system further includes an ADC module.

[0124] S105 can be further divided into the following steps S1051-S1053:

[0125] Step S1051: According to the configuration end signal, the PEC module performs internal delay processing on the FPGA and then sends an ADC start signal;

[0126] Step S1052: Read the first test result in the PMU test chip in parallel through the ADC module according to the start signal and generate a first notification;

[0127] Specifically, the PEC module starts the ADC module. The start signal controls the ADC module to read the first test result in parallel in the PMU test chip via the SPI interface. After the ADC module completes the reading, it pulls high the ad2_data_valid signal (generating the first notification) to notify the PEC module to read the first test result.

[0128] Step S1053: Read the first test result through the PEC module according to the first notification.

[0129] Specifically, after the PEC board in the PEC module reads the first test result, it stores the DC parameters of each test channel in a corresponding register, waiting for the TMU control board to read it.

[0130] S106. Reading the first test result saved by the PEC module through the TMU control board, and packaging the first test result according to a second data format to generate a second test result;

[0131] The second data format is a data format agreed upon by the host computer and the TMU control board.

[0132] Specifically, in an embodiment of the present invention, the second data format is a format for reading data from the host computer agreed upon by the host computer and the TMU control board, specifically as follows:

[0133] Test channel 1 data + test channel 2 data + ... + test channel n data

[0134] The TMU control board packages the test channel data in sequence into a series of data (the second test result) according to the number of test channels and the second data format sent by the host computer and sends it to the host computer.

[0135] S107 . Map the second test result to a memory corresponding to each test channel through the host computer according to the test channel.

[0136] Specifically, in combination with step S106, it can be seen that the host computer constructs a memory parsing mode corresponding to the number of test channels in the memory, and directly fills the second test result into the corresponding memory of the test channel through the memory parsing mode to quickly obtain the test results of each test channel.

[0137] In an embodiment of the present invention, if the number of test channels sent by the host computer is 8, and the second test result is 0x0123456789abcdef 0123456789abcdef, the second test result is filled in the format of the constructed memory parsing mode:

[0138]

[0139] It can be seen from this that the embodiment of the present invention obtains the second test result by packaging the first test result according to the second data format through the TMU control board, and maps the second test result to the memory corresponding to each test channel through rapid parsing by the host computer, thereby realizing efficient reading of the test results of each test channel and improving the efficiency of DC parameter testing.

[0140] Taking the TWS247 chip test project as an example, Table 1 shows the test time of a traditional DC parameter test method, where P01 / P02 represent the OS test and current test, respectively. Table 2 shows the details of the OS test and current test in the traditional DC parameter test method. Table 3 shows the test time of a DC parameter test method for steps S101-S107 according to an embodiment of the present invention, where P01 / P02 represent the OS test and current test, respectively. Table 4 shows the details of the OS test and current test in a DC parameter test method for steps S101-S107 according to an embodiment of the present invention.

[0141] Table 1

[0142]

[0143] Table 2

[0144]

[0145]

[0146] Table 3

[0147]

[0148] Table 4

[0149]

[0150]

[0151] With reference to Table 1, Table 2, Table 3, and Table 4, a comparison of the test time of a DC parameter test method in steps S101-S107 of an embodiment of the present invention and a traditional DC parameter test method is shown in Table 5:

[0152] Table 5

[0153]

[0154] It can be seen that, compared with the traditional DC parameter testing method, the DC parameter testing method according to the embodiment of the present invention greatly improves the efficiency of DC parameter testing, and the more pins are tested, the more obvious the improvement effect is.

[0155] The contents of the above method embodiments are all applicable to the present system embodiments. The functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0156] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiments presented and described in the flow chart of the present application are provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operations and logical flows presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0157] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present application. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the routine skills of an engineer. Therefore, a person skilled in the art can implement the present application as set forth in the claims using ordinary techniques without undue experimentation. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the appended claims and their equivalents.

[0158] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having logic gate circuits for implementing logical functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0159] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples.

[0160] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0161] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A DC parameter test system, characterized in that: include: The host computer is configured to generate a first parameter using a data compression algorithm and send the first parameter to the TMU control board, wherein the first parameter includes a compressed second parameter, and the second parameter includes a test channel, a corresponding test mode, and a corresponding configuration parameter; and is configured to map the second test result to a memory corresponding to each test channel according to the test channel; A TMU control board, configured to parse the first parameter according to a first data format to obtain the second parameter; Used to read the first test result saved by the PEC module, and package the first test result according to the second data format to generate the second test result, where the first data format and the second data format are the data formats agreed upon by the host computer and the TMU control board; A PEC module, configured to configure channel parameters of the PMU test chip according to the second parameters; for reading the first test result after performing internal delay processing on the FPGA according to a configuration end signal, and saving the first test result according to the test channel, wherein the configuration end signal is a signal generated after the PEC module completes the configuration of the channel parameters of the PMU test chip; The PMU test chip is used to perform a DC parameter test on each of the test channels of the chip under test according to the channel parameters, and generate the first test result after the test is completed.

2. A DC parameter testing system according to claim 1, characterized in that: The PEC module includes a plurality of PEC boards, each of which includes 32 channels; The PEC board configures the channel parameters using a state machine stepping method according to the second parameters.

3. A DC parameter testing system according to claim 1, characterized in that: The PMU test chip configures the working mode of each of the test channels according to the channel parameters. The working modes include applying voltage to measure current, applying voltage to measure voltage, applying current to measure voltage, and applying current to measure current. The DC parameter test of the chip to be tested is performed through each of the test channels according to the working mode.

4. A DC parameter testing system according to claim 1, characterized in that: Also includes ADC module; The PEC module performs FPGA internal delay processing according to the configuration end signal and then sends a start signal. The ADC module reads the first test result in the PMU test chip in parallel according to the start signal and generates a first notification. The PEC module reads the first test result according to the first notification.

5. A DC parameter testing method, characterized in that: The method is applied to a DC parameter test system, which includes a host computer, a TMU control board, a PEC module, and a PMU test chip. The method includes: The host computer generates a first parameter using a data compression algorithm and sends the first parameter to the TMU control board, wherein the first parameter includes a compressed second parameter, and the second parameter includes a test channel, a corresponding test mode, and a corresponding configuration parameter; Parsing the first parameter by the TMU control board according to a first data format to obtain the second parameter, wherein the first data format is a data format agreed upon by the host computer and the TMU control board; According to the second parameter, configuring the channel parameters of the PMU test chip through the PEC module; According to the channel parameters, the PMU test chip performs a DC parameter test on the chip to be tested, and generates a first test result after the test is completed; According to a configuration end signal, the PEC module performs internal FPGA delay processing and then reads the first test result, and saves the first test result according to the test channel. The configuration end signal is a signal generated by the PEC module after completing the configuration of the channel parameters of the PMU test chip. Reading the first test result saved by the PEC module through the TMU control board, and packaging the first test result according to a second data format to generate a second test result, where the second data format is a data format agreed upon by the host computer and the TMU control board; According to the test channels, the second test results are mapped to memories corresponding to the respective test channels by the host computer.

6. A DC parameter testing method according to claim 5, characterized in that: The PEC module includes a plurality of PEC boards, each of which includes 32 channels; Configuring the channel parameters of the PMU test chip through the PEC module according to the second parameter includes: According to the second parameter, the channel parameters are configured through the PEC board using a state machine stepping.

7. A DC parameter testing method according to claim 6, characterized in that: The stepping of configuring the channel parameters by the PEC board using a state machine according to the second parameter includes: According to the initial state of the state machine, a first channel is selected as the current channel, where the first channel is the first channel on the PEC board; According to the test channel, determining whether the current channel needs to be configured; If so, configuring the current channel according to the test mode and the configuration parameters; Confirm that the current channel configuration is complete and the current channel is not the last channel on the PEC board, select the second channel as the current channel, and return to the step of determining whether the current channel needs to be configured based on the test channel. The second channel is the next channel of the current channel on the PEC board.

8. A DC parameter testing method according to claim 7, characterized in that: After the step of determining whether the current channel needs to be configured according to the test channel, the method further includes: If not, confirm that the current channel is not the last channel on the PEC board, select the second channel as the current channel, and return to the step of determining whether the current channel needs to be configured based on the test channel.

9. A DC parameter testing method according to claim 5, characterized in that: The performing a DC parameter test of each test channel on the chip to be tested by the PMU test chip according to the channel parameters includes: Configure the working mode of each test channel according to the channel parameters, wherein the working modes include applying voltage to measure current, applying voltage to measure voltage, applying current to measure voltage, and applying current to measure current; Perform a DC parameter test on the chip to be tested through each of the test channels according to the working mode.

10. A DC parameter testing method according to claim 5, characterized in that: The DC parameter testing system also includes an ADC module; The step of reading the first test result through the PEC module according to the configuration end signal includes: According to the configuration end signal, the PEC module performs internal delay processing on the FPGA and then sends a start signal; According to the start signal, reading the first test result in the PMU test chip in parallel through the ADC module and generating a first notification; According to the first notification, the first test result is read through the PEC module.

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