Memory system and operating method thereof

Abstract

This disclosure relates to a memory system and a method of operating the same. A memory controller for controlling a memory device may include: a model manager configured to acquire log information about the use of the memory device over a predetermined time period and to generate a regression model based on the log information to predict the lifetime of the memory device; and a performance manager configured to determine a degradation range of the memory device's performance based on the regression model and to adjust parameter values ​​related to the operation of the memory device within the degradation range.

Description

[0001] Related cross-references

[0002] This application claims priority to Korean Patent Application No. 10-2021-0044875, filed on April 6, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to an electronic device, and more particularly, to a memory system and a method of operating the same. Background Technology

[0004] A memory system is a device that stores data under the control of a host device such as a computer or smartphone. This memory device may include a memory storage device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are devices that store data only when powered on and lose the stored data when power is off. Volatile memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Non-volatile memory devices are devices that do not lose data even when power is off. Non-volatile memory devices include, for example, read-only memory (ROM), programmable memory (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0007] One embodiment of this disclosure provides a memory system and its operation method for compensating for performance degradation of a memory device.

[0008] According to one embodiment of the present disclosure, a memory controller for controlling a memory device may include: a model manager configured to acquire log information about the use of the memory device over a predetermined time period and generate a regression model based on the log information to predict the lifetime of the memory device; and a performance manager configured to determine a degradation range of the memory device's performance based on the regression model and adjust parameter values ​​related to the operation of the memory device within the degradation range.

[0009] According to another embodiment of this disclosure, the memory system may include a memory device and a memory controller for controlling the memory device. The memory controller may include: a model manager configured to generate a regression model predicting the performance of the memory device based on log information regarding the use of the memory device; and a performance manager configured to determine a degradation range of the memory device's performance based on the regression model, and to adjust parameter values ​​related to the operation of the memory device within the degradation range.

[0010] According to another embodiment of this disclosure, a method for a memory controller to operate a memory device may include: acquiring log information about the use of the memory device over a predetermined time period, generating a regression model based on the log information to predict the lifetime of the memory device, determining a degradation range of the memory device's performance degradation based on the regression model, and adjusting parameter values ​​related to the operation of the memory device within the degradation range.

[0011] According to another embodiment of this disclosure, an operation method of a management device includes: obtaining a linear regression relationship between the average erase count of storage blocks included in a target device and the cumulative power-on time of the target device; determining an interval of power-on time in which the performance of the target device is predicted to deteriorate in terms of the average erase count based on the linear regression relationship and a predetermined first threshold and second threshold of the average erase count; and adjusting the operating parameters of the target device to compensate for the predicted performance degradation when the power-on time falls into the interval.

[0012] According to this technology, a memory system and its operation method can be provided to compensate for performance degradation of memory devices. Attached Figure Description

[0013] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0014] Figure 2 It is shown Figure 1 A diagram of a memory device.

[0015] Figure 3 It is shown Figure 2 A diagram illustrating the configuration of any one of the storage blocks.

[0016] Figure 4 This is a table showing log information about the use of the memory device according to another embodiment of this disclosure.

[0017] Figure 5 This is a diagram illustrating the generation of a regression model according to an embodiment of the present disclosure.

[0018] Figure 6This is a block diagram illustrating a method for compensating for performance degradation of a memory device according to another embodiment of the present disclosure.

[0019] Figure 7 This is a diagram illustrating a method for determining degradation ranges based on a regression model and adjusting parameter values ​​related to the operation of a memory device according to yet another embodiment of the present disclosure.

[0020] Figure 8 This is a diagram illustrating a method for dividing a deterioration zone into multiple sub-zones according to an embodiment of the present disclosure.

[0021] Figure 9 This is a flowchart illustrating a method for compensating for performance degradation of a memory device according to another embodiment of the present disclosure.

[0022] Figure 10 This is a flowchart illustrating a method for adjusting parameter values ​​related to the operation of a memory device according to yet another embodiment of the present disclosure.

[0023] Figure 11 This is an exemplary diagram illustrating a data processing system including a solid-state drive according to an embodiment of the present disclosure.

[0024] Figure 12 This is an example shown Figure 11 A diagram illustrating the configuration of the controller.

[0025] Figure 13 This is a diagram illustrating a data processing system including a data storage device according to another embodiment of the present disclosure.

[0026] Figure 14 This is an illustrative diagram showing a data processing system including a data storage device according to yet another embodiment of the present disclosure.

[0027] Figure 15 This is an illustrative diagram of a network system including a data storage device according to yet another embodiment of the present disclosure. Detailed Implementation

[0028] The specific structural or functional descriptions illustrating embodiments based on the concepts disclosed in this specification or application are for illustrative purposes only. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0029] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or any other element besides those described herein. Because the algorithms underlying the methods (or the operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of the method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0030] When implemented at least in part in software, the controller, processor, device, module, unit, multiplexer, generator, logic circuit, interface, decoder, driver, generator, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device.

[0031] Figure 1 This is a diagram illustrating a memory system 50 including a memory device according to an embodiment of the present disclosure.

[0032] Reference Figure 1 The memory system 50 may include a memory device 100 and a memory controller 200 for controlling the operation of the memory device 100. The memory system 50 may be a device for storing data under the control of a host 300 such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0033] The memory system 50 can be manufactured as one of various types of storage devices depending on the host interface, which is the communication standard or interface with the host 300. For example, the memory system 50 can be configured as any of the following types of storage devices: solid-state drives (SSDs), multimedia cards in the form of MMC, embedded eMMC, reduced-size RS-MMC and micro MMC, secure digital cards in the form of SD, mini SD and / or micro SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-e or PCIe) card-type storage devices, compact flash memory (CF) cards, smart media cards and memory sticks.

[0034] The memory system 50 can be manufactured in any of the following package types: Point-of-Package (POP), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), or Wafer-Level Stacked Package (WSP).

[0035] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array comprising a plurality of memory cells for storing data.

[0036] At least one of the memory cells can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, and / or a four-level cell (QLC) that can store four data bits.

[0037] The memory cell array may include multiple memory blocks. At least one memory block may include multiple memory cells. A memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0038] In one embodiment, the memory device 100 may be, for example, dual data rate synchronous dynamic random access memory (DDR SDRAM), fourth generation low power double data rate (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. In this specification, for ease of description, it is assumed that the memory device 100 is NAND flash memory.

[0039] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access a region in a memory cell array selected by the address. Memory device 100 can perform operations instructed by commands on the region selected by the address. For example, memory device 100 can perform programming operations, read operations, and erase operations. During a programming operation, memory device 100 can store data in the region selected by the address. In this disclosure, the operation of storing data can be represented as a programming operation or a write operation. During a read operation, memory device 100 can read data from the region selected by the address. During an erase operation, memory device 100 can erase the data stored in the region selected by the address.

[0040] In one embodiment, the memory device 100 may include multiple planes. A plane may be a unit capable of independently performing one or more operations. For example, the memory device 100 may include two, four, or eight planes. The multiple planes may simultaneously and independently perform at least one or more of programming, reading, or erasing operations.

[0041] The memory controller 200 can control the overall operation of the memory system 50.

[0042] When power is supplied to the memory system 50, the memory controller 200 can execute instructions such as firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300, and the memory controller 200 may include a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0043] The memory controller 200 can receive the data to be stored and the logical block address (LBA) from the host 300 and can convert the LBA to a physical block address (PBA). The physical block address (PBA) indicates the address of the memory cell containing the data included in the memory device 100 to be stored. In this specification, LBA and "logical address" or "logical address" can be used to mean the same thing. In this specification, PBA and "physical address" or "physical address" can be used to mean the same thing.

[0044] The memory controller 200 can control the memory device 100 to perform one or more of the following operations, such as programming, reading, or erasing, upon request from the host 300. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, a PBA (Programming Interface), and data. During a reading operation, the memory controller 200 can provide the memory device 100 with a read command and a PBA. During an erasing operation, the memory controller 200 can provide the memory device 100 with both an erase command and a PBA.

[0045] In one embodiment, the memory controller 200 can generate commands, addresses, and data independently of requests from the host 300, and transmit the commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 for performing one or more read operations and programming operations accompanied by wear leveling, read recycling, garbage collection, etc.

[0046] In another embodiment, the memory controller 200 can control at least two or more memory devices 100. In this embodiment, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operational performance. The interleaving method can be a method of controlling the operation of at least two memory devices 100 to overlap with each other. Alternatively, the interleaving method can be a method of operating at least two or more memory devices 100 in parallel.

[0047] The buffer memory can temporarily store data provided from the host 300, i.e., data to be stored in the memory device 100, or can temporarily store data read from the memory device 100. In one embodiment, the buffer memory can be a volatile memory device. For example, the buffer memory can be dynamic random access memory (DRAM) or static random access memory (SRAM). In this disclosure, buffer memory can be used for the same purpose as a buffer.

[0048] The host 300 can communicate with the memory system 50 using at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0049] Figure 2 It is shown Figure 1 A diagram of the memory device 100.

[0050] Reference Figure 2 The memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, control logic 140, a voltage generator 150, and a current sensing circuit 160. The address decoder 120, the read and write circuit 130, the voltage generator 150, and the current sensing circuit 160 may be referred to herein as peripheral circuitry controlled by the control logic 140.

[0051] Memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to address decoder 120 via word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to read and write circuitry 130 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In one embodiment, the plurality of memory cells are non-volatile memory cells and may be configured as non-volatile memory cells with a vertical channel structure. Memory cell array 110 may be configured as a two-dimensional memory cell array. According to one embodiment, memory cell array 110 may be configured as a three-dimensional memory cell array. On the other hand, at least one of the plurality of memory cells included in the memory cell array may store at least one bit of data. In one embodiment, at least one of the plurality of memory cells included in the memory cell array may be an SLC storing one bit of data. In another embodiment, at least one of the plurality of memory cells included in the memory cell array may be an MLC storing two bits of data. In yet another embodiment, at least one of the plurality of memory cells included in the memory cell array may be a TLC storing three bits of data. In another embodiment, at least one of the plurality of memory cells included in the memory cell array may be a QLC storing four bits of data. According to another embodiment, the memory cell array 110 may include a plurality of memory cells storing five or more bits of data.

[0052] Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 is configured to operate in response to control of control logic 140. Address decoder 120 receives addresses via input / output buffers within memory device 100.

[0053] Address decoder 120 is configured to decode block addresses among received addresses. Address decoder 120 selects at least one memory block based on the decoded block address. Additionally, during a read operation, address decoder 120 applies a read voltage Vread generated in voltage generator 150 to the selected word line in the selected memory block during a read voltage application operation, and applies a voltage Vpass to the remaining unselected word lines. Furthermore, during a program verification operation, address decoder 120 applies a verification voltage generated in voltage generator 150 to the selected word line in the selected memory block, and applies a voltage Vpass to the remaining unselected word lines.

[0054] Address decoder 120 can be configured to decode the column address of a received address. Address decoder 120 transmits the decoded column address to read and write circuitry 130.

[0055] In one embodiment, read and program operations on memory device 100 are performed on a page-by-page basis. The address received when requesting a read or program operation may include a block address, a row address, and a column address. Address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by address decoder 120 and provided to read and write circuitry 130. In this specification, a memory cell connected to a word line may be referred to as a "physical page."

[0056] The read and write circuit 130 includes multiple page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cell, the multiple page buffers PB1 to PBm continuously supply sensing current to the bit lines connected to the memory cell while sensing changes in the amount of current flowing according to the programming state of the corresponding memory cell through sensing nodes, and latching the sensed changes as sensed data. The read and write circuit 130 operates in response to a page buffer control signal output from control logic 140. In this specification, the write operation of the write circuit can be used to mean the same thing as a programming operation that stores data in the memory cell.

[0057] During a read operation, the read and write circuit 130 senses data in the memory cell, temporarily stores the read data, and outputs the data to the input / output buffer of the memory device 100. As an exemplary embodiment, the read and write circuit 130 may include column selection circuitry, etc., in addition to a page buffer (or page register). According to embodiments of this disclosure, the read and write circuit 130 may be a page buffer.

[0058] Control logic 140 is connected to address decoder 120, read and write circuitry 130, voltage generator 150, and current sensing circuitry 160. Control logic 140 receives commands CMD and control signals CTRL via input / output buffers of memory device 100. Control logic 140 is configured to control all operations of memory device 100 in response to control signal CTRL. Additionally, control logic 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read and write circuitry 130 to perform read operations on memory cell array 110.

[0059] On the other hand, control logic 140 can determine whether the verification operation for a specific target programming state passes or fails in response to a pass signal PASS or a failure signal FAIL received from current sensing circuit 160.

[0060] Voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from control logic 140. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage, and generate multiple voltages by selectively activating the multiple pump capacitors in response to control by control logic 140.

[0061] The current sensing circuit 160 can generate a reference current and a reference voltage in response to the enable bit VRY_BTI<#> received from the control logic 140 during the verification operation. By comparing the generated reference voltage with the sensed voltage VPB received from the page buffers PB1 to PBm included in the read and write circuit 130, or by comparing the generated reference current with the sensed current received from the page buffers PB1 to PBm included in the read and write circuit 130, a pass signal PASS or a failure signal FAIL can be output.

[0062] The address decoder 120, read and write circuitry 130, voltage generator 150, and current sensing circuitry 160 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry performs read, write, and erase operations on the memory cell array 110 based on the control logic 140.

[0063] Figure 3 It is shown Figure 2 A diagram illustrating the configuration of any one of the storage blocks.

[0064] Storage block BLKz is Figure 2 Any one of the storage blocks BLK1 to BLKz.

[0065] Reference Figure 3 Multiple word lines arranged in parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKz can include multiple strings (ST) connected between bit lines BL1 to BLm and the source line SL. Bit lines BL1 to BLm can be connected to these strings (ST) individually, while the source line SL can be connected to these strings (ST) collectively. Since these strings (ST) can be configured to be identical to each other, the string connected to the first bit line BL1 is described specifically as an example.

[0066] The string may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A string may include at least one or more of the source selection transistor SST and the drain selection transistor DST, and may include more than the number of memory cells MC1 to MC16 shown in the figure.

[0067] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST can be connected to the source select line SSL, the gates of the drain select transistor DST can be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells in different strings ST that are connected to the same word line can be referred to as a page PG. Therefore, the memory block BLKz can include the number of pages PG corresponding to word lines WL1 to WL16.

[0068] In one embodiment, a memory cell can store one bit of data. This is often referred to as SLC. In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0069] In another embodiment, a memory cell can store two or more bits of data. In this case, a physical page (PG) can store two or more logical pages (LPG) of data.

[0070] Figure 4 This is a table showing log information about the use of a memory device according to one embodiment of the present disclosure.

[0071] Reference Figure 4 It can retrieve log information about the use of the storage device. Data can be stored in the storage device or erased at the user's request. User usage patterns can be reflected in the log information.

[0072] Log information regarding the use of the memory device may include information about usage time, write volume, and average erase count. Usage time can represent the cumulative amount of time power is applied to the memory device (i.e., the data in the "POH" column represents the cumulative power-on time). Write volume can represent the amount of data written to the memory device during the usage time (i.e., the data in the "Host Writes [GB]" column represents the write volume). Average erase count can represent the average number of times the memory blocks included in the memory device are erased during the usage time (i.e., the data in the "E / W" column represents the average erase count).

[0073] It is possible to retrieve log information about the use of the memory device within one or more predetermined time periods. For example, it can be assumed that log information about the use of the memory device is retrieved every three days at a predetermined time. Figure 4 In the first time period, log information with a usage time of 1 hour and an average number of erases of 1 can be retrieved. In the second time period, log information with a usage time of 20 hours and an average number of erases of 2 can be retrieved. In the twentieth time period, log information with a usage time of 500 hours and an average number of erases of 70 can be retrieved.

[0074] Self-Monitoring, Analysis, and Reporting Technology (SMART) can be used to obtain log information about the use of memory devices. SMART is a technology that diagnoses and reports the probability of potential failures by checking the reliability of memory devices. When SMART predicts a failure, the user can replace the memory device to prevent data loss due to unexpected problems.

[0075] exist Figure 4 In the table, when the usage time is 1 hour, the average number of erases can be 1, while when the usage time is 500 hours, the average number of erases can be 70. This invention is not limited to... Figure 4 The exact data shown. For example, the average number of erases may differ even with the same amount of usage time, depending on the user's usage patterns. Depending on the user's usage patterns, the average number of erases may be 3 or more when the usage time is 1 hour, while the average number of erases may be 50 or less when the usage time is 500 hours.

[0076] In another embodiment of this disclosure, the write volume can be 256 gigabytes when the usage time is 1 hour. The write volume may vary even with the same usage time, depending on the user's usage pattern of the memory device.

[0077] Log information obtained through Self-Monitoring, Analysis and Reporting Technology (SMART) can vary depending on the usage patterns of different users using the memory device.

[0078] Figure 5 This is a diagram illustrating the generation of a regression model according to an embodiment of the present disclosure.

[0079] Reference Figure 5 A regression model 510 can be generated based on information about usage time and average number of erases included in log information about the use of the memory device obtained at each predetermined time period.

[0080] Based on Figure 4 The log information includes information about usage time and average number of erases to generate [the data]. Figure 5 The regression model 510 can be generated, for example, based on log information acquired up to 500 hours of usage. For instance, when 20 log entries are acquired up to 500 hours of usage, the increment in the average number of erases for each of the 20 log entries can be obtained. The regression model 510 can be generated as a linear function, with the average of the 20 increments used as its slope.

[0081] After generating regression model 510, regression model 510 can be used to calculate the average number of erases on the memory device. Specifically, when the usage time reaches 1000 hours, regression model 510 generated based on the average number of erases on the memory device after 500 hours of user usage can be used, for example, to calculate the average number of erases on the memory device.

[0082] According to another embodiment of this disclosure, a regression model can be generated based on information about usage time and write volume included in log information about the use of the memory device. The generated regression model can then be used to predict the write volume of the memory device after the regression model has been generated.

[0083] Figure 6 This is a block diagram illustrating a method for compensating for performance degradation of a memory device according to an embodiment of the present disclosure.

[0084] Reference Figure 6 The memory controller 200 can generate a regression model predicting the lifetime or performance of the memory device 100 and can adjust parameter values ​​related to the operation of the memory device 100. The memory controller 200 may include a model manager 210 and a performance manager 220, wherein the model manager 210 generates a regression model predicting the lifetime or performance of the memory device 100, and the performance manager 220 adjusts parameter values ​​related to the operation of the memory device 100.

[0085] Model manager 210 can acquire log information about the usage of memory device 100 within any predetermined time period. Model manager 210 can generate a regression model based on the log information to predict the lifetime or performance of memory device 100. The log information about the usage of memory device 100 may include usage time indicating the cumulative amount of time for which power is applied to memory device 100, and the average number of erases of memory blocks included in memory device 100 during the usage time.

[0086] Model manager 210 can acquire log information for each predetermined time period until the usage time reaches a predetermined reference value, and calculate each increment of the average erase count for the usage time of the acquired log information. Model manager 210 can generate a regression model predicting the lifetime of storage device 100 based on the average of the increments. Model manager 210 can update the regression model based on the acquired log information after generating the regression model. Model manager 210 can acquire log information on the usage of storage device 100 through Self-Monitoring, Analysis and Reporting Technology (SMART).

[0087] According to another embodiment of this disclosure, log information regarding the use of the memory device 100 may include information about usage time and write volume. Usage time indicates the cumulative amount of time for which power is applied to the memory device 100, and write volume indicates the cumulative amount of data written to the memory device 100 during the usage time. The model manager 210 can acquire log information for each predetermined time period until the usage time reaches a predetermined reference value, and calculate each increment of the write volume for the usage time of multiple log entries. The model manager 210 can generate a regression model predicting the lifetime of the memory device 100 based on the average of the increments.

[0088] Performance manager 220 can determine the degradation range of memory device 100's performance degradation based on a regression model and adjust parameter values ​​related to the operation of memory device 100 within the degradation range. Performance manager 220 may include range manager 221 and parameter manager 223.

[0089] By using a regression model, the interval manager 221 can calculate the degradation start point and the lifetime end point. The degradation start point is the amount of usage time corresponding to a predetermined threshold of the average number of erases, and the lifetime end point is the amount of usage time corresponding to a predetermined limit of the average number of erases. The interval manager 221 can define the interval from the degradation start point to the lifetime end point as the degradation interval.

[0090] According to another embodiment of this disclosure, by using a regression model, performance manager 220 can calculate a degradation start point and a lifetime end point, where the degradation start point is the amount of usage time corresponding to a predetermined threshold of write volume, and the lifetime end point is the amount of usage time corresponding to a predetermined limit value of write volume. Interval manager 221 can define the interval from the degradation start point to the lifetime end point as a degradation interval.

[0091] The parameter manager 223 can adjust the parameter values ​​(3) related to the operation of the memory device 100 in the degradation range in response to the average number of erases of the memory device 100. The parameter values ​​related to the operation of the memory device 100 can be at least one of the parameter values ​​that determine the internal power supply voltage of the memory device 100, the parameter values ​​that determine the command processing speed of the memory device 100, and / or the parameter values ​​that determine the number of retries for read operations of the memory device 100. The operations performed in the memory device 100 can be stably executed in response to the parameter value adjustment of the parameter manager 223.

[0092] When parameter manager 223 increases the parameter value that determines the internal power supply voltage of memory device 100, the amplitude of the voltage generated by the voltage generator of memory device 100 can be increased. Specifically, the amplitude of the read voltage or programming voltage generated by the voltage generator can be increased. When parameter manager 223 increases the parameter value that determines the command processing speed of memory device 100, the command processing speed of memory device 100 can be decreased. The parameter value that determines the command processing speed can be the micro-oscillator tuning period. When the command processing speed of memory device 100 is reduced, the speed at which the reference clock is input to memory device 100 can be reduced. When a read operation is performed in memory device 100, the peak current of memory device 100 can decrease in response to the decrease in clock speed. When the command processing speed of memory device 100 is reduced, read operations can be performed stably in memory device 100. When parameter manager 223 increases the parameter value that determines the number of retries for read operations of memory device 100, the number of retries for read operations performed in response to read operation failures increases.

[0093] The parameter manager 223 can adjust parameter values ​​related to the operation of the memory device 100 differently based on the parameter values. The parameter manager 223 can also determine the degree of adjustment based on the type of the parameter. For example, for the same average erase count of 700, the parameter manager 223 can increase the internal power supply voltage of the memory device 100 by 700% and increase the number of read operation retries for the memory device 100 by 450%.

[0094] The degradation range can vary depending on parameter values ​​related to the operation of the memory device 100. The range manager 221 can set different degradation ranges based on parameter values ​​adjusted by the parameter manager 223. For example, the degradation start point of the degradation range corresponding to a parameter value that determines the internal power supply voltage of the memory device 100 may be different from the degradation start point of the degradation range corresponding to a parameter value that determines the command processing speed of the memory device 100.

[0095] The interval manager 221 can divide the degradation interval into multiple sub-intervals according to a preset ratio of a threshold for the average number of erases. The degree of degradation of the memory device 100 can correspond to the average number of erases within the degradation interval. The interval manager 221 can divide the degradation interval into a first sub-interval near the start of degradation and a second sub-interval near the end of its lifespan. The parameter manager 223 can adjust parameters using a compensation ratio obtained by multiplying the average number of erases of the memory device 100 by a predetermined value in the first sub-interval. The parameter manager 223 can determine the compensation ratio by assigning weights to the average number of erases of the memory device 100 and multiplying the predetermined value by the average number of erases assigned weights in the second sub-interval. That is, in the second sub-interval, the parameter manager 223 can adjust the parameter value by applying a compensation ratio greater than that of the first sub-interval.

[0096] In another embodiment of this disclosure, parameter manager 223 may adjust parameter values ​​related to the operation of memory device 100 in a degradation range in response to the amount of writes to memory device 100. Parameter manager 223 may adjust at least one of parameter values ​​that determine the internal power supply voltage of memory device 100, parameter values ​​that determine the command processing speed of memory device 100, and / or parameter values ​​that determine the number of retries for read operations of memory device 100. Operations performed in memory device 100 may be stably executed in response to parameter value adjustments by parameter manager 223.

[0097] Figure 7 This is a diagram illustrating a method for determining degradation ranges based on a regression model and adjusting parameter values ​​related to the operation of a memory device according to an embodiment of the present disclosure.

[0098] Reference Figure 7 This can be described by a regression model used to predict the amount of time spent erasing the average number of erases. Figure 7 You can refer to this. Figure 5 and Figure 6 The description is as follows. Regarding the average number of erases, the limit value E / W_EOL of the average number of erases can be determined based on the memory device 100. The threshold value E / W_Threshold of the average number of erases can be determined based on the limit value E / W_EOL. For example, when the limit value E / W_EOL of the average number of erases is 1000 times, the threshold value E / W_Threshold of the average number of erases can be 400 times, that is, 40% of the limit value E / W_EOL of the average number of erases. When the limit value E / W_EOL of the average number of erases is 2000 times, the threshold value E / W_Threshold of the average number of erases can be 800 times.

[0099] Model Manager 210 can generate Figure 5The regression model 510 is shown. The generated regression model 510 can be extended to the lifetime endpoint POH_EOL (point 715) of the memory device 100. The performance manager 220 can calculate the lifetime endpoint POH_EOL (point 715) corresponding to the limit value E / W_EOL of the average erase count and the degradation starting point POH_Threshold (starting point 710) corresponding to the threshold value E / W_Threshold of the average erase count based on the regression model 510. The interval manager 221 can determine the interval from the degradation starting point POH_Threshold (starting point 710) to the lifetime endpoint POH_EOL (end point 715) as the degradation interval P1 (sustained interval 730). The interval manager 221 can determine the degradation starting point POH_Threshold (starting point 710) as the normal interval P0 (sustained interval 720) starting from the usage time of 0 hours.

[0100] In another embodiment of this disclosure, the degradation range can vary based on parameter values ​​related to the operation of the memory device 100. The range manager 221 can determine different degradation ranges based on parameter values ​​adjusted by the parameter manager 223. For example, when the limit value of the average erase count E / W_EOL is equal to 1000 times, 700 times (i.e., 70% of the limit value of the average erase count E / W_EOL) can be the threshold value E / W_Threshold for the average erase count, which determines the internal power supply voltage. For the parameter value determining the command processing speed of the memory device, 500 times (i.e., 50% of the limit value of the average erase count E / W_EOL) can be the threshold value E / W_Threshold for the average erase count. The range manager 221 can set the range corresponding to an average erase count of 700 to 1000 times as the degradation range for the parameter value determining the internal power supply voltage, and can determine the range corresponding to an average erase count of 500 to 1000 times as the degradation range for the parameter value determining the command processing speed of the memory device.

[0101] The parameter manager 223 can adjust the operation-related parameter values ​​of the memory device 100 in response to the average number of erases corresponding to the current usage time in the degradation interval P1 (duration interval 730). The parameter manager 223 can adjust at least one of the following: a parameter value determining the internal power supply voltage of the memory device, a parameter value determining the command processing speed of the memory device 100, or a parameter value determining the number of read operation retries for the memory device. The parameter manager 223 may not adjust the operation-related parameter values ​​of the memory device 100 in the normal interval P0 (duration interval 720).

[0102] The parameter manager 223 can determine the compensation ratio 740, which is the degree to which the parameter value is adjusted in response to the average number of erases. Figure 7 In this context, the maximum compensation ratio corresponding to the limit value of the average erase count, E / W_EOL, is 1000%. Although... Figure 7 A compensation ratio of 740 is shown, but the compensation ratio 740 can vary depending on the adjusted parameters. For example, when the parameter value of the internal power supply voltage that determines the same average number of erases is increased by 500%, the parameter that determines the number of read operation retries for the memory device can be increased by 300%. The maximum compensation ratio can also vary depending on the adjusted parameters.

[0103] The compensation ratio 740 can be the degree to which the parameter value adjusted by the parameter manager 223 is modified. For example, when the compensation ratio is 500%, the internal power supply voltage of the memory device can be increased by 500%, the command processing speed of the memory device can be increased by 500%, or the number of read operation retries of the memory device can be increased by 500%. As the amount of time the memory device 100 is used approaches the end of its lifespan, POH_EOL (time point 715), the compensation ratio 740 increases.

[0104] Figure 8 This is a diagram illustrating a method for dividing a deterioration zone into multiple sub-zones according to an embodiment of the present disclosure.

[0105] Reference Figure 8 The deterioration range can be divided into a first sub-range P2 (duration 820) and a second sub-range P3 (duration 830). Figure 8 You can refer to this. Figure 6 and Figure 7 The description.

[0106] As the average number of erases of the memory device 100 approaches its limit value E / W_EOL, the compensation ratio 740 determined by the parameter manager 223 can increase rapidly in response to the degradation of the memory device 100. The interval manager 221 can define the interval where the compensation ratio 740 increases significantly as the second sub-interval P3 (sustained interval 830). The interval manager 221 can define the interval where the compensation ratio 740 increases gradually as the first sub-interval P2 (sustained interval 820).

[0107] The boundary value E / W_pre for dividing the first sub-interval P2 (duration interval 820) and the second sub-interval P3 (duration interval 830) can be predetermined based on the limit value E / W_EOL of the average number of erases. For example, when the limit value E / W_EOL of the average number of erases is 1000 times, 90% of the limit value E / W_EOL, i.e., 900 times, can be determined as the boundary value E / W_pre. The interval manager 221 can calculate the boundary time POH_pre (time point 810) corresponding to the boundary value E / W_pre based on a regression model, and determine the first sub-interval P2 (duration interval 820) and the second sub-interval P3 (duration interval 830).

[0108] exist Figure 8 The diagram shows a deteriorated interval divided into a first sub-interval P2 (duration 820) and a second sub-interval P3 (duration 830), but the deteriorated interval can be divided into multiple sub-intervals. The compensation ratio 740 corresponding to each of the multiple sub-intervals can be different from each other.

[0109] The boundary value E / W_pre can be determined differently depending on the parameter type controlled by parameter manager 223. Since the boundary value E / W_pre varies depending on the parameter type, the boundary time POH_pre (time point 810) corresponding to the boundary value E / W_pre can be determined differently depending on the parameter type.

[0110] The regression model for predicting the usage time of writes according to another embodiment of this disclosure can also be used to adjust parameter values, similar to... Figure 7 and Figure 8 The regression model described in [the document] is used to predict the amount of time spent using the average number of erasures.

[0111] Figure 9 This is a flowchart illustrating a method for compensating for performance degradation of a memory device according to an embodiment of the present disclosure.

[0112] Reference Figure 9 The memory controller 200 can generate a regression model predicting the lifetime or performance of the memory device 100 and adjust at least one parameter related to the operation of the memory device 100 based on the regression model. Since the memory controller 200 compensates for performance degradation, the memory device 100 can be driven stably. Figure 9 The operations performed in can correspond to Figure 6 The description.

[0113] In operation S901, the model manager 210 can obtain log information about the usage of the memory device 100 within each predetermined time period. The model manager 210 can obtain multiple log entries until the predetermined usage time is reached. The model manager 210 can obtain log information about the usage of the memory device 100 through Self-Monitoring, Analysis and Reporting Technology (SMART).

[0114] In operation S903, model manager 210 can generate a regression model predicting the lifetime or performance of memory device 100 based on multiple log messages acquired. The log information regarding the use of memory device 100 can include usage time indicating the cumulative amount of time for which power is applied to memory device 100, and the average number of erases of memory blocks included in memory device 100 during the usage time. Model manager 210 can calculate each increment of the average number of erases for the usage time of the multiple log messages and generate a regression model based on the average of the increments. The lifetime or performance of memory device 100 predicted by the regression model can vary depending on the log information regarding the use of memory device 100.

[0115] In operation S905, performance manager 220 can determine the degradation range of memory device 100's performance degradation based on a regression model. Based on the regression model, a degradation start point and a lifetime end point can be calculated, where the degradation start point is the amount of usage time corresponding to a predetermined threshold of the average number of erases, and the lifetime end point is the amount of usage time corresponding to a predetermined limit of the average number of erases. Performance manager 220 can define the interval from the degradation start point to the lifetime end point as the degradation range. Range manager 221 can determine each degradation range based on the type of adjusted parameters. Range manager 221 can divide the degradation range into multiple sub-ranges.

[0116] In operation S907, the performance manager 220 can adjust parameter values ​​related to the operation of the memory device 100 within the degradation range. The performance manager 220 can adjust the parameter values ​​of the memory device 100 according to a compensation ratio. The compensation ratio varies depending on the type of parameter being adjusted.

[0117] Figure 10 This is a flowchart illustrating a method for adjusting parameter values ​​related to the operation of a memory device according to an embodiment of the present disclosure.

[0118] Reference Figure 10 The performance manager 220 can identify the degradation range and adjust the parameters of the memory device 100. Figure 10 The operations performed in can correspond to Figures 6 to 8 The description.

[0119] In operation S1001, the interval manager 221 can calculate the degradation start point and lifetime end point of the memory device 100. The interval manager 221 can calculate the degradation start point and lifetime end point using a regression model, where the degradation start point is the amount of usage time corresponding to a predetermined threshold of the average number of erases, and the lifetime end point is the amount of usage time corresponding to a predetermined limit value of the average number of erases. The interval manager 221 can define the interval from the degradation start point to the lifetime end point as the degradation interval.

[0120] In operation S1003, parameter manager 223 can compare the current usage time with the degradation start point. When the current usage time is less than the degradation start point, the parameter values ​​of memory device 100 can be left unchanged, and the operation can therefore be terminated. When the current usage time is greater than the degradation start point, parameter manager 223 can adjust the parameter values ​​of memory device 100.

[0121] In operation S1005, parameter manager 223 can adjust at least one of the following parameter values: a parameter value determining the internal power supply voltage of the memory device, a parameter value determining the command processing speed of the memory device, and / or a parameter value determining the number of read operation retries for the memory device. Parameter manager 223 can determine a compensation ratio, which is the degree to which the parameter value is adjusted in response to the average number of erases corresponding to the current amount of usage time. Parameter manager 223 can adjust the parameters of memory device 100 according to the determined compensation ratio. Parameter manager 223 can determine the compensation ratio differently depending on the type of parameter being adjusted.

[0122] Figure 11 This is an exemplary illustration of a data processing system 2000 including a solid-state drive (SSD) according to an embodiment of the present disclosure. (Refer to...) Figure 11 The data processing system 2000 may include a host device 2100 and an SSD 2200.

[0123] SSD 2200 may include controller 2210, buffer memory device 2220, non-volatile memory 2231 to 223n, power supply 2240, signal connector 2250, and power connector 2260.

[0124] The controller 2210 can control the overall operation of the SSD 2200.

[0125] The buffer memory device 2220 can temporarily store data to be stored in the non-volatile memories 2231 to 223n. Additionally, the buffer memory device 2220 can temporarily store data read from the non-volatile memories 2231 to 223n. Under the control of the controller 2210, the data temporarily stored in the buffer memory device 2220 can be transferred to the host device 2100 or the non-volatile memories 2231 to 223n.

[0126] Non-volatile memories 2231 to 223n can be used as storage media for the SSD 2200. Each of the non-volatile memories 2231 to 223n can be connected to the controller 2210 through multiple channels CH1 to CHn. One or more non-volatile memories can be connected to one channel. Non-volatile memories connected to one channel can be connected to the same signal bus and data bus.

[0127] Power supply 2240 can provide power PWR input to SSD 2200 via power connector 2260. Power supply 2240 may include auxiliary power supply 2241. Auxiliary power supply 2241 can provide power so that SSD 2200 can stop normally in the event of a sudden power failure. Auxiliary power supply 2241 may include a large-capacity capacitor capable of charging power PWR.

[0128] The controller 2210 can exchange signals SGL with the host device 2100 via signal connector 2250. Here, signal SGL may include commands, addresses, data, etc. Depending on the interface method between the host device 2100 and the SSD 2200, signal connector 2250 can be configured as various types of connectors.

[0129] Figure 12 This is an example shown Figure 11 A diagram illustrating the configuration of the controller 2210. (Refer to...) Figure 12 The controller 2210 may include a host interface unit 2211, a control unit 2212, a random access memory 2213, an error correction code (ECC) unit 2214, and a memory interface unit 2215.

[0130] According to the protocol of host device 2100, host interface unit 2211 can interface with host device 2100 and SSD 2200. For example, host interface unit 2211 can communicate with host device 2100 through any of the following communication standards or interfaces: Secure Digital (SD), Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), PCMCIA, Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial SCSI (SAS), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-e or PCIe), Universal Flash Memory (UFS), etc. In addition, host interface unit 2211 can perform disk emulation functions, which allow host device 2100 to recognize SSD 2200 as a general-purpose data storage device, such as a hard disk drive (HDD).

[0131] Control unit 2212 can analyze and process the signal SGL input from host device 2100. Control unit 2212 can control the operation of internal function blocks according to instructions such as firmware and / or software driving SDD 2200. Random access memory 2213 can be used as working memory to drive such firmware or software.

[0132] ECC unit 2214 can generate check data for data to be transferred to non-volatile memories 2231 to 223n. The generated check data can be stored together with the data in non-volatile memories 2231 to 223n. ECC unit 2214 can detect errors in the data read from non-volatile memories 2231 to 223n based on the check data. When the detected error is within a correctable range, ECC unit 2214 can correct the detected error.

[0133] Under the control of the control unit 2212, the memory interface unit 2215 can provide control signals such as commands and addresses to the non-volatile memories 2231 to 223n. Additionally, under the control of the control unit 2212, the memory interface unit 2215 can exchange data with the non-volatile memories 2231 to 223n. For example, the memory interface unit 2215 can provide data stored in the buffer memory device 2220 to the non-volatile memories 2231 to 223n, or provide data read from the non-volatile memories 2231 to 223n to the buffer memory device 2220.

[0134] Figure 13 This is a diagram illustrating a data processing system 3000 including a data storage device according to an embodiment of the present disclosure. (Refer to...) Figure 13The data processing system 3000 may include a host device 3100 and a data storage device 3200.

[0135] The host device 3100 can be configured in the form of a board, such as a printed circuit board. The host device 3100 may include internal function blocks for performing the functions of the host device.

[0136] The host device 3100 may include connection terminals 3110, such as sockets, slots, or connectors. The data storage device 3200 may be mounted on the connection terminals 3110.

[0137] The data storage device 3200 can be configured in the form of a board, such as a printed circuit board. The data storage device 3200 can be referred to as a memory module or a memory card. The data storage device 3200 may include a controller 3210, a buffer memory device 3220, non-volatile memories 3231 and 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

[0138] The controller 3210 can control the overall operation of the data storage device 3200. It can be connected with... Figure 11 The controller 2210 shown is configured similarly to the controller 3210.

[0139] The buffer memory device 3220 can temporarily store data to be stored in the non-volatile memories 3231 and 3232. Additionally, the buffer memory device 3220 can temporarily store data read from the non-volatile memories 3231 and 3232. Under the control of the controller 3210, the data temporarily stored in the buffer memory device 3220 can be transferred to the host device 3100 or the non-volatile memories 3231 and 3232.

[0140] Non-volatile memories 3231 and 3232 can be used as storage media for data storage device 3200.

[0141] The PMIC 3240 can provide power input to the data storage device 3200 via the connection terminal 3250. The PMIC 3240 can manage the power supply of the data storage device 3200 under the control of the controller 3210.

[0142] Connection terminal 3250 can be connected to connection terminal 3110 of the host device. Power and signals such as commands, addresses, and data can be transmitted between the host device 3100 and the data storage device 3200 via connection terminal 3250. Connection terminal 3250 can be configured in various forms depending on the interface connection method between the host device 3100 and the data storage device 3200. Connection terminal 3250 can be located on either side of the data storage device 3200.

[0143] Figure 14 This is a diagram illustrating a data processing system 4000 including a data storage device according to an embodiment of the present disclosure. (Refer to...) Figure 14 The data processing system 4000 may include a host device 4100 and a data storage device 4200.

[0144] The host device 4100 may be configured in the form of a board, such as a printed circuit board. The host device 4100 may include internal function blocks for performing the functions of the host device.

[0145] The data storage device 4200 can be configured in a surface mount package. The data storage device 4200 can be mounted on the host device 4100 via solder ball connections 4250. The data storage device 4200 may include a controller 4210, a buffer memory device 4220, and a non-volatile memory 4230.

[0146] The controller 4210 can control the overall operation of the data storage device 4200. It can be connected with... Figure 11 The controller 2210 shown is configured similarly to the controller 4210.

[0147] The buffer memory device 4220 can temporarily store data to be stored in the non-volatile memory 4230. Additionally, the buffer memory device 4220 can temporarily store data read from the non-volatile memory 4230. Under the control of the controller 4210, the data temporarily stored in the buffer memory device 4220 can be transferred to the host device 4100 or the non-volatile memory 4230.

[0148] The non-volatile memory 4230 can be used as the storage medium of the data storage device 4200.

[0149] Figure 15 This is an exemplary diagram illustrating a network system 5000 including a data storage device according to an embodiment of the present disclosure. (Refer to...) Figure 15 The network system 5000 may include a server system 5300 and multiple client systems 5410 to 5430 connected via the network 5500.

[0150] Server system 5300 can serve data in response to requests from multiple client systems 5410 to 5430. For example, server system 5300 can store data provided by multiple client systems 5410 to 5430. Furthermore, server system 5300 can provide data to multiple client systems 5410 to 5430.

[0151] Server system 5300 may include host device 5100 and data storage device 5200. Data storage device 5200 may include... Figure 1Data system 50 Figure 11 SSD 2200, Figure 13 Data storage device 3200 and Figure 14 Data storage device 4200.

[0152] According to one embodiment of this disclosure, since the regression model is generated based on log information about the use of the memory device, the reliability of the memory device's lifetime end predicted by the regression model can be ensured. User usage patterns of the memory device can be reflected in the log information. A regression model generated based on log information of users who frequently perform data storage and erasure operations on the memory device and a regression model generated based on log information of users who primarily perform read operations may differ from each other, and the device lifetimes may also differ.

[0153] According to one embodiment of this disclosure, since the parameters related to the operation of the memory device are adjusted according to the degradation of the memory device, the memory device can operate stably. Because the memory device can operate stably, it can continue to function normally even after its lifespan has expired. Adjusting the parameters related to the operation of the memory device can achieve the same effect as extending the lifespan of the memory device.

[0154] Since this disclosure can be implemented in other specific forms without changing the technical concept or essential characteristics of this disclosure, those skilled in the art to which this disclosure pertains should understand that the above embodiments are exemplary and not limiting in any way. The scope of this disclosure is defined by the claims described later rather than the specific embodiments, and all changes or modifications derived from the meaning and scope of the claims and their equivalents, other than those disclosed herein and the following claims, are to be understood as included within the scope of this disclosure. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A memory controller that controls a memory device, the memory controller comprising: The model manager retrieves log information about the use of the memory device within a predetermined time period and generates a regression model to predict the lifetime of the memory device based on the log information. as well as The performance manager determines the degradation range of the memory device's performance based on the regression model, and adjusts parameter values ​​related to the operation of the memory device within the degradation range. The log information includes the amount of time used and the average number of erases on the memory blocks included in the memory device during the amount of time used, the amount of time used indicating the cumulative amount of time for which power was applied to the memory device. The model manager mentioned above: The log information within the predetermined time period is retrieved until the usage time reaches a predetermined reference amount. For each of the acquired log entries, the increment of the average number of erases is calculated based on the usage time. The regression model is generated based on the average of the increments.

2. The memory controller of claim 1, wherein the performance manager includes a range manager, the range manager: The degradation start point and lifetime end point are calculated using the regression model, where the degradation start point is the amount of usage time corresponding to a predetermined threshold of the average number of erases, and the lifetime end point is the amount of usage time corresponding to a predetermined limit of the average number of erases. The interval from the starting point of degradation to the end point of the lifetime is defined as the degradation interval.

3. The memory controller according to claim 2, The performance manager further includes a parameter manager that adjusts parameter values ​​related to the operation of the memory device in response to the average number of erases, and The parameter value related to the operation of the memory device is at least one of the following: a parameter value for determining the internal power supply voltage of the memory device, a parameter value for determining the command processing speed of the memory device, and a parameter value for determining the number of retries for the read operation of the memory device.

4. The memory controller of claim 3, wherein the degradation range varies according to parameter values ​​related to the operation of the memory device.

5. The memory controller of claim 3, wherein the parameter manager adjusts parameter values ​​related to the operation of the memory device according to different parameters of the parameter values.

6. The memory controller of claim 3, wherein the interval manager further divides the deterioration interval into a plurality of sub-intervals at least according to a preset ratio of the limit value.

7. The memory controller of claim 6, wherein the parameter manager adjusts parameter values ​​related to the operation of the memory device differently for each of the plurality of sub-intervals.

8. The memory controller of claim 1, wherein the model manager further updates the regression model based on log information obtained after the regression model is generated.

9. The memory controller of claim 1, wherein the model manager acquires the log information by using self-monitoring, analysis, and reporting techniques for the memory device.

10. A memory system, comprising: Memory devices; as well as The memory controller controls the memory device. The memory controller includes: The model manager generates a regression model to predict the performance of the memory device based on log information about the use of the memory device. as well as The performance manager determines the degradation range of the memory device's performance based on the regression model, and adjusts parameter values ​​related to the operation of the memory device within the degradation range. The log information includes information about usage time and write volume, wherein the usage time indicates the cumulative amount of time for which power is applied to the memory device, and the write volume indicates the amount of data written to the memory device during the usage time. The model manager further states: Obtain the log information within the predetermined time period until the usage time reaches a predetermined reference amount, and For each of the multiple log entries obtained, calculate the increment of the write volume based on the usage time. The regression model is generated based on the average of the increments.

11. The memory system of claim 10, wherein the performance manager includes a interval manager, the interval manager: The degradation start point and lifetime end point are calculated using the regression model, where the degradation start point is the amount of usage time corresponding to a predetermined threshold of the write volume, and the lifetime end point is the amount of usage time corresponding to a predetermined limit of the write volume. The interval from the starting point of degradation to the end point of the lifetime is defined as the degradation interval.

12. The memory system according to claim 11, The performance manager further includes a parameter manager that adjusts parameter values ​​related to the operation of the memory device in response to the write volume. The parameter value related to the operation of the memory device is at least one of the following: a parameter value for determining the internal power supply voltage of the memory device, a parameter value for determining the command processing speed of the memory device, and a parameter value for determining the number of retries for the read operation of the memory device.

13. A method for operating a memory controller of a memory device, the method comprising: Obtain log information regarding the use of the memory device within a predetermined time period; Calculate the increment of the average number of erases for each of the multiple log entries obtained, based on the usage time. A regression model for predicting the lifetime of the memory device is generated based on the log information; The degradation range of the memory device's performance degradation is determined based on the regression model. and Adjust the parameter values ​​related to the operation of the memory device within the degradation range. The log information includes the amount of time used and the average number of erases on the memory blocks included in the memory device during the amount of time used, the amount of time used indicating the cumulative amount of time for which power was applied to the memory device. The process involves acquiring the log information within the predetermined time period until the usage time reaches a predetermined reference amount. The regression model is generated based on the average of the increments.

14. The method of claim 13, wherein determining the degradation range comprises: The degradation start point and lifetime end point are calculated using the regression model, where the degradation start point is the amount of usage time corresponding to a predetermined threshold of the average erase count, and the lifetime end point is the amount of usage time corresponding to a predetermined limit of the average erase count; and The interval from the starting point of degradation to the end point of the lifetime is defined as the degradation interval.

15. The method of claim 14, wherein adjusting the parameter value comprises: In response to the average number of erases, at least one of the following parameters is adjusted: the parameter value used to determine the internal power supply voltage of the memory device, the parameter value used to determine the command processing speed of the memory device, and the parameter value used to determine the number of read operation retries of the memory device.

16. The method of claim 13, further comprising: The regression model is updated based on log information obtained after the regression model is generated.

17. The method according to claim 13, wherein obtaining the log information includes: Information about the amount of time used and the average number of erases is obtained by using self-monitoring, analysis, and reporting techniques on the memory device.

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