System, storage media, and method of generating a die block map upon detection of a fault

Abstract

The present disclosure relates to systems, storage media, and methods of generating a die block map after detecting a failure. A memory device includes a plurality of memory die blocks and a plurality of memory channels operably coupled to the plurality of memory die blocks and a memory controller configured to identify one or more memory die blocks as invalid. The memory controller obtains a first matrix storing a mapping of memory channels to memory die blocks and creates a new mapping of memory channels to memory die blocks that does not include the invalid memory die blocks. The new mapping is stored in a second matrix and one or more operations are performed on the memory die blocks based on the new mapping.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to generating a die block map upon detection of a die block fault, the die block being a part of the memory subsystem. Background Technology

[0002] A memory subsystem may include one or more memory components for storing data. Memory devices may be, for example, non-volatile memory components and volatile memory components. Generally, a host system can utilize a memory subsystem to store data at memory components and retrieve data from memory components. Summary of the Invention

[0003] Embodiments of this disclosure provide a system comprising: a memory device including a plurality of memory die blocks and a plurality of memory channels operatively coupled to the plurality of memory die blocks; and a memory controller configured to perform operations including: identifying one or more memory die blocks of the memory device as invalid; obtaining a first matrix storing a mapping of memory channels to memory die blocks; creating a new mapping of memory channels to memory die blocks, the new mapping not including the invalid one or more memory die blocks; storing the new mapping in a second matrix; and performing one or more operations on the one or more memory die blocks based on the new mapping.

[0004] Another embodiment of this disclosure provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing means of a memory device, cause the processing means to perform operations including: receiving an indication at a memory controller of the memory device that a bus contention error has occurred on a memory channel; identifying one or more memory die blocks of the memory device as invalid; acquiring a first matrix storing a mapping of memory channels to memory die blocks; creating a new mapping of memory channels to memory die blocks, the new mapping not including the invalid one or more memory die blocks; storing the new mapping in a second matrix; and performing one or more operations on the one or more memory die blocks based on the new mapping.

[0005] Another embodiment of this disclosure provides a method comprising: receiving a request to perform a memory operation at a memory device comprising a plurality of die blocks and a plurality of memory channels operatively coupled to the plurality of die blocks; identifying, at a memory controller of the memory device, that one or more memory die blocks of the memory device are invalid; obtaining a first matrix storing a mapping of memory channels to memory die blocks; creating a new mapping of memory channels to memory die blocks, the new mapping not including the invalid one or more memory die blocks; storing the new mapping in a second matrix; and performing the memory operation on the one or more memory die blocks based on the new mapping. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 An example computing environment including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart illustrating an example method for generating a raw die block map after detecting a fault, according to some embodiments of the present disclosure.

[0009] Figure 3 A diagram illustrating instance die block mappings on a memory device according to some embodiments of the present disclosure.

[0010] Figures 4A-4E Examples of methods for generating a bare die block map after a fault is detected by an apparatus, according to some embodiments of the present disclosure, are shown.

[0011] Figures 5A-5B A flowchart illustrating an example method for generating a bare die block map after detecting a fault, according to some embodiments of the present disclosure.

[0012] Figure 6 An interaction diagram is shown that provides an interaction between components that provide a computing environment in the context of some embodiments, wherein a method using a die block mapping technique on a memory device described herein is performed.

[0013] Figure 7 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0014] This disclosure relates to generating a die block map after a fault is detected on a memory device, which may be part of a memory subsystem, wherein the operation enables the memory device to maintain optimal operation when one or more die blocks are detected as invalid, damaged, or otherwise taken offline. The memory subsystem may be a storage device, a memory module, or a mixture of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more memory components (hereinafter also referred to as "memory devices"). The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0015] Memory devices can be non-volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device. (The following text is in conjunction with...) Figure 1 Other examples of non-volatile memory devices are described. Some memory devices, such as NAND memory devices, contain arrays of memory cells (e.g., flash memory cells) for storing data. Each cell contains a transistor, and within each cell, data is stored as a threshold voltage of the transistor based on the cell's logic value (e.g., 0 or 1). Memory cells in these devices can be grouped into pages that refer to the logical cells of the memory device used for storing data. For example, memory cells in a NAND memory device are horizontally connected to word lines at their control gates to form pages. For some types of memory devices (e.g., NAND), pages are grouped to form blocks (also referred to herein as "memory blocks").

[0016] The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem, read data from a memory device at the memory subsystem, or construct read / write operations relative to a memory device at the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may include error handling data (e.g., error correction code (ECC) codewords, parity check codes), data version (e.g., expiration date used to distinguish the data being written), a validity bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0017] Data operations can be performed by the memory subsystem. Data operations can be host-initiated. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on the memory devices located in the memory subsystem and to read data from the memory devices on the memory subsystem.

[0018] The memory subsystem can initiate media management operations, such as write operations, on host data stored on the memory device. For example, the firmware of the memory subsystem can rewrite previously written host data from one location on the memory device to a new location as part of a garbage collection management operation. The rewritten data (e.g., as initiated by the firmware) is referred to below as "garbage collection data".

[0019] In the following text, "user data" generally refers to host data and garbage collection data. "System data" refers to data created and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Instances of system data include, but are not limited to, system tables (e.g., logical-to-physical memory address mapping tables, also referred to herein as L2P tables), data from logging, high-speed scratchpad data, etc.

[0020] The memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. For some memory devices, a block is the smallest erasable area. Each block consists of a set of pages. Each page consists of a set of memory cells that store data bits. The memory device can be a raw memory device (e.g., NAND), which is externally managed, for example, by an external controller. The memory device can be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller for memory management within the same device package.

[0021] Traditional computer systems, such as conventional supercomputers, "consume" memory allocation during manufacturing. However, such static memory allocation is not suitable for adaptation after memory die blocks fail and can lead to problems including memory channel conflicts and data degradation. The system may also encounter errors, such as bus contention errors, when the processor attempts to access a non-existent or incorrectly responding memory location. Conventional memory systems contain NAND devices consisting of an arbitrary number of total die blocks spanning an arbitrary number of channels. This configuration is due to the influence of various NAND materials and packaging configurations on device design specifications, requirements, and budget constraints.

[0022] Typically, each solid-state drive (SSD) can be created from any number of die blocks spanning any number of memory channels. This is commonly seen because of the various NAND materials produced by different manufacturers, packaged together. In one example, a 64-layer TCL NAND device contains six 48GB die blocks each to create 256GB. In another example, a 96-layer TLC NAND device contains four 64GB die blocks to create a 256GB device. In a third example, a 96-layer TLC NAND device can contain six 64GB die blocks to create 240GB, and nine die blocks to create 480GB. Based on the various die block sizes, NAND devices have a variety of configurations.

[0023] To control operations on a NAND device, the memory controller communicates with die blocks using memory channels. In some NAND devices, the memory controller has four memory channels and up to 16 chip enable (CE) lines. Each memory die block connected to a memory channel has its own CE signal, which selects the specific die block the controller is communicating with. On the channel, the bus broadcasts addresses, data, and flash commands to all die blocks within the channel, but only to the die blocks whose CE signals are active. These CE-activated die blocks will read information from the bus and perform the corresponding operations. For this purpose, each die block is addressed by a channel and a CE line.

[0024] Traditionally, die mappings are statically defined and stored in the memory controller's firmware. Die mappings are typically broken in or preset before delivery to the customer and cannot be upgraded or replaced. Furthermore, static die mappings present performance and degradation issues when die block recovery failures occur. These performance and degradation issues may be caused by channel conflicts resulting from repeated memory commands being issued to the die block using the same channel. However, it is difficult to determine die mappings using exhaustive methods. In a typical NAND device with over 100 die blocks, there will be countless possible unique die mappings. Moreover, storing all possible die mappings on the drive itself is impractical. Static die mappings are undesirable in the event of die failures because they can lead to LUN degradation.

[0025] Conversely, one approach and corresponding system considers dynamic die mapping to improve die mapping, even in the event of detected die block failures. Improved die mapping extends SSD lifespan, improves performance, and enhances the overall quality of the device.

[0026] The improved mapping takes physical location information into account to determine an improved mapping solution, thus avoiding performance degradation. Typically, when a die block fails or goes offline for various reasons, the data cursor in the Flash Translation Layer (FTL) firmware skips the failed / offline die block. This can cause problems with sequential write and / or read operations in terms of bandwidth and Quality of Service (QoS).

[0027] Various aspects of this disclosure address the aforementioned and other problems by enabling the memory subsystem to generate a die block map upon detecting a memory die block fault. Specifically, various embodiments enable "on-the-go" optimized mapping of die blocks to effectively mitigate channel collision issues, thereby improving the bandwidth, performance, and lifespan of the memory device itself.

[0028] Although various embodiments are described herein with respect to memory subsystem controllers, some embodiments implement the features described herein (e.g., operations for generating new mappings) as part of a memory device (e.g., a controller, processor, or state machine of a memory die). For example, various embodiments implement mapping operations as part of a controller, processor, or state machine for each bank of memory within the memory device.

[0029] Benefits include the ability to continue data operations even when one or more memory die blocks are detected to be faulty, and the flexibility to generate new mappings throughout the lifespan of the memory device, which improves device lifespan and the quality of service provided by the device.

[0030] Figure 1An example computing environment 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0031] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0032] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0033] Host system 120 may include a processor chipset and a software stack executed by said processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110. Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, or such a computing device that includes memory and processing power.

[0034] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Low Power Dual Data Rate (LPDDR), or any other suitable interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is shown as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices (such as memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in the memory bank resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more arrays of memory cells, such as single-level cell (SLC) or multi-level cell (MLC) arrays (e.g., three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC) arrays), each capable of storing multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory component may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages or blocks of memory that may refer to cells of a memory component used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0038] While non-volatile memory components such as non-volatile memory cell 3D cross-point arrays and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The memory subsystem controller 115 may be a microcontroller, a special-purpose logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and correction coding (ECC) operations, encryption, caching, and address translation between logical block addresses and physical block addresses associated with memory device 130. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing memory device 130 and responses associated with memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0044] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device that is combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0045] The memory subsystem controller 115 includes a mapping matrix component 113, which can generate (2) update and (3) store one or more mapping matrices (1) of memory die blocks into memory channels on memory devices (e.g., memory devices 130, 140). In some embodiments, the mapping matrix component 113 can identify damaged, corrupted, or otherwise offline memory die blocks. The data manipulation component 113 enables the memory system to maintain a healthy level of operating memory cells to perform data operations such as read, write, and erase operations. The data manipulation component 113 enables the memory subsystem 110 to perform operations including garbage collection operations (via the memory subsystem controller 115). Further details regarding the operation of the data manipulation component 113 are described below. (The text here refers to...) Figure 2 and Figures 4A-4E An example of this situation is shown and described.

[0046] Figure 2 A flowchart illustrating an example method for generating a die block map based on memory cell fault detection according to some embodiments of this disclosure is shown. In operation 202, method 200 begins with a power-on / reset when the die map table is loaded from non-volatile memory (or other suitable memory storing the die map table). In operation 206, the die map table (also referred to herein as a die map matrix) is cached in memory.

[0047] When the host system requests to perform a data operation (also referred to herein as a memory operation), the die map is queried to determine how, when, and from where data is retrieved, written, or erased. In some embodiments, before performing a data operation received from the host system, at operation 208, it is determined whether a new die map is needed. At operation 210, a die scan is performed to check the health of the die blocks. In some embodiments, a scan such as a bad block scan is performed while the device is powered on. If the memory device passes the die scan, a test read operation is performed at operation 212. If the test read operation is successful, the memory device proceeds to the next operation at 214, where a test program operation is performed. If the test program operation is successful, the memory device proceeds to the next operation at 216, where a test erase operation is performed. If the memory device passes all tests 210 through 216, the data operation from the host system is performed using the current die map. However, if the memory device fails in any of operations 210-216, a new die map is generated. A failure of any of operations 210-216 indicates a failure to address the memory die block being addressed in order to avoid channel conflicts and other unnecessary errors. Regarding Figures 4A-4D Discuss the details of how to generate new bare-metal maps.

[0048] After creating the new die mapping in operation 218, the host-requested data operations are performed using the new die mapping. Before the method terminates in operation 224, the new die mapping is stored in non-volatile memory or any other suitable memory location in operation 222.

[0049] Figure 3 This illustration shows an example memory die block group 300 before remapping occurs, according to some embodiments of the present disclosure. The memory die block group 300 includes a die package 302 with eight die blocks, a die package 304 with four die blocks, a die package 306 with four die blocks, and a die package 308 with two die blocks. As shown in the example group, channel 0 is coupled to the four die blocks of die package 302 and the two die blocks of die package 304, for a total of six die blocks, indicated by identifier 310. Similarly, channel 1 is coupled to a total of six die blocks, indicated by identifier 312. Channel 2 is coupled to a total of two die blocks, indicated by identifier 314, and channel 3 is coupled to a total of three die blocks, indicated by identifier 316. If any die block of the die package connected via channels 0-3 becomes inoperable, the channel-to-die-block mapping is rearranged to provide the optimal path for channel communication to the die blocks. A channel can only serve one raw block at a time, and serving one block at a time becomes very important for avoiding data congestion and maintaining consistent data throughput for offline raw blocks.

[0050] Figure 4A It is a graphical representation of how a new mapping is generated after a fault is detected in the memory system. For example... Figure 3 As shown, a memory die package group containing die blocks is coupled to a memory channel. The mapping from die package / die block to memory channel is stored in memory in matrix format. Figure 4AIn this process, to begin generating a new mapping that does not contain offline memory blocks, multiple bare blocks coupled to each memory channel are computed. In this example, CH0 has 6 bare blocks, CH1 has 6 bare blocks, CH2 has 2 bare blocks, and CH3 has 3 bare blocks. A channel-to-bare-block mapping sequence is generated by following an algorithmic approach that assigns weights to each channel and allocates costs for each sequential connection between a channel and a bare block. For the generated sequence, moving to the most recently assigned channel is more “expensive” because the move increases the “cost.” The “cheapest” move is to the channel with the fewest recently assigned channels and / or the channel with the most bare blocks. After the next two selections, the increased cost gradually decreases. The prices are reflected in Table 404, and this table shows the travel cost from one channel to another. When assigning two or more channels to the same number of bare blocks, any channel can be chosen as the initial channel. In this example, both channel 0 and channel 1 are assigned 6 bare blocks. For simplicity, channel 0 is chosen. Imagine the paths from channel 0 to channel 1, channel 2, and channel 3. Based on Table 404, which reflects the cost of moving from channel 0, channel 1 is selected as the "cheapest" option. Channel 0 has now been added to the sequence, reducing the number of bare blocks allocated to 5, and channel 1 has also been added to the sequence, reducing the number of bare blocks allocated to channel 1 to 5. Starting with channel 1, it is determined whether to proceed to channel 0, 2, or 3. The cheapest option is to establish a connection between channels 2 and 3. Similarly, any choice is acceptable when the cost of proceeding to the next channel is the same. The process of selecting the next channel and reducing the bare block allocation count will continue until each channel has been traveled the corresponding number of times equal to the number of bare blocks allocated to each channel.

[0051] In some embodiments, to complete the channel sequence, the possibility of starting and ending with the same channel is addressed. A check and swap operation is performed to complete the first step of generating a new die block map. The first and last channels are checked; if the first and last channels of the sequence refer to the same channel, the last channel of the sequence is swapped with the penultimate channel. In this way, the first and last channels of the sequence are different. From there, the check and swap operation is performed on the channel sequence proceeding backward from the last channel of the sequence. After this step, the generation of the channel sequence is complete.

[0052] Figure 4B This is a graphical representation of the second step in generating a new bare die block map according to some embodiments. In obtaining... Figure 4A Following the channel sequence in the code, the channel sequence is mapped to a chip enable line (e.g., a die block enable input). For example... Figure 3 As shown, each die block is mapped to a channel and a chip enable line.

[0053] To obtain the chip enable line mapping, the first channel of the sequence (e.g., CH0) and multiple chip enable lines (e.g., CE0, CE1, CE2, and CE3, a total of four CE lines) are identified. Starting with the first channel of the sequence, CE lines are assigned sequentially, beginning with CE0. As shown in step 1, for each instance of CH0, CE lines are mapped starting with CE0. In step 2, the next channel of the sequence (e.g., CH1) is identified, and the process is repeated. In step 3, the third channel of the sequence (CH3) is identified, and the CE line-to-channel mapping continues for CH3. In step 4, the next identified channel of the sequence (CH2) is identified, and the CE line-to-channel mapping continues in the same manner. At the end of step 4, the channel sequence contains the corresponding CE line for each channel instance.

[0054] For example, using Figure 4A The generated channel sequence is loaded into the array. For each channel, the current CE is set as the first valid CE in the channel. For each entry in the array, if the entry is a channel, the current CE value is entered. The current CE is updated to the next valid CE, and the process wraps around the next valid CE after reaching the maximum CE.

[0055] Figure 4C This is a graphical representation of the third step in generating a new bare die block map according to some embodiments. Figure 4C Add the logical unit number to the channel / CE sequence to form the channel / CE / LUN sequence that forms the raw die block mapping. Figure 4B The process described in [the original text] is similar; each step selects the first channel sequence and adds the corresponding current LUN value until each channel / CE pair has a corresponding LUN mapping. For example, using [the original text]... Figure 4B The generated channel sequence is loaded into the array. For each CE, the current LUN is set as the first valid LUN in the CE. For each entry in the array, if the entry is both a channel and a CE entry, the current LUN value is input. The current LUN is updated to the next valid LUN in the CE, wrapping around the next valid LUN after reaching the maximum LUN. Channel / CE / LUN mapping representation Figure 3 The mapping of raw chip blocks 1 to 16 identified in the code.

[0056] Figure 4D This shows a physical view of the channel / CE / LUN mapping for each die block. Each die block is mapped to a channel in a specific order to avoid channel conflicts, bus contention errors, and other failures caused when one or more die blocks automatically become unavailable.

[0057] Figure 4EThis diagram shows a logical view of the new channel / CE / LUN mapping for each die block. As shown, each die block is assigned or mapped to a channel, CE, and LUN. Each die block is assigned once in an optimized mapping that provides stable access to the memory die block through various channels and chip enable lines of the memory device.

[0058] Figure 5A This is a flowchart of a method 500 for generating a bare die block map after detecting a fault, according to some embodiments. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The data manipulation component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0059] Now for reference Figure 5A Method 500 illustrates an example of generating a bare die block map after a fault is detected, according to some embodiments. In operation 505, the processing device receives a request to perform a data operation.

[0060] In operation 510, the processing device identifies one or more memory die blocks as invalid. In some embodiments, invalid blocks are identified by performing a memory die block scan to identify offline, invalid, or damaged memory die blocks. In some embodiments, any combination of read, write, or erase operations is performed on the memory device, and in response to determining that an operation has failed, the processing device creates a new mapping.

[0061] In operation 515, the processing apparatus creates a new mapping of memory channels to memory die blocks. In some embodiments, creating a new mapping of memory channels to memory die blocks includes removing one or more memory die blocks identified as invalid from the plurality of memory die blocks to be mapped. In some embodiments, one or more other memory die blocks identified as unstable or risky are also removed from the plurality of memory die blocks to be mapped.

[0062] In operation 520, the processing device performs the requested data operation based on the new mapping. In some embodiments, the requested data operation is a read, write, or erase operation.

[0063] exist Figure 5BIn the process, the processing device at method 500 performs as follows: Figure 5A The additional and / or alternative operations shown.

[0064] In operation 516, method 500 continues with the processing apparatus acquiring a first matrix mapping the storage memory channels to memory die blocks.

[0065] In operation 517-A, the processing device calculates a channel sequence from the first memory die block to the last memory die block. In some embodiments, a first memory channel is identified among a plurality of memory channels. The first memory channel is mapped to the memory die block with the highest count in a first matrix. A second memory channel is selected from the channel sequence. Each memory channel has a set number of memory die blocks to be mapped (e.g., ...). Figure 3 (as described in the previous section), and the selected second memory channel has a second minimum number of memory blocks to be mapped among multiple memory channels. After selecting the second memory channel, the number of memory blocks to be mapped for the selected channel is updated to reflect the current remaining number of memory blocks to be mapped for the second channel in order to complete the channel sequence. For example, if the selected memory channel is to be mapped to 6 different memory blocks, the count decreases from 6 to 5 after the selected memory channel is entered at the second position in the memory channel sequence. After selecting the second memory channel, a third memory channel of the channel sequence is selected. The third memory channel has the current maximum number of memory blocks to be mapped among multiple memory channels. After selecting the channel sequence, the number of memory blocks to be mapped for the third memory channel is updated. In some embodiments, the foregoing steps are repeated until each memory block has been assigned to a selected memory channel.

[0066] In operation 517-B, the processing device adds a die block enable parameter to each combination of memory die block and memory channel. In some embodiments, the die block enable parameter is referred to as a chip enable line (CE line). In operation 517-C, the processing device adds a logical unit number (LUN) parameter to each memory die block to map each memory die block / channel / and die enable parameter to a LUN.

[0067] In operation 518, the processing device stores the new mapping in the second matrix. In some embodiments, the new mapping is stored in memory together with the original mapping.

[0068] Return to Figure 5A The operation described herein, in operation 520, involves the processing device performing data operations based on the new mapping.

[0069] Figure 6Interaction diagrams are provided to illustrate interactions between components of a computing environment in the context of some embodiments, wherein methods are performed using data allocation techniques on memory devices as described herein. The operation of the methods may be performed by processing logic, which may include hardware (e.g., processing devices, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, the methods are performed by a host system (e.g., 120), a memory subsystem controller (e.g., 115), a memory device (e.g., 130 or 140), or a combination thereof. While operations are shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Additionally and / or alternatively, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. Figure 6 In the context of the example shown, the host system may include host system 120, the memory subsystem controller may include memory subsystem controller 115, and the memory device may include memory device 140.

[0070] like Figure 6 As shown, in operation 602, the host system sends a memory command associated with a memory cell to the memory subsystem 110. In operation 604, the memory subsystem controller 115 receives a memory command associated with one or more memory die blocks. In operation 606, the memory device provides a mapping allocation for the memory die blocks.

[0071] In response to a memory command received in operation 604, memory subsystem controller 115 creates a new mapping allocation. In operation 610, the new mapping allocation is stored.

[0072] The memory controller determines whether the target block is ready to be erased (e.g., whether all valid data has been relocated), and erases the target block based on the determination that the target block is ready to be erased (see Operation 612).

[0073] Based on operation 612 determining that a memory command can be executed, in operation 614, the memory subsystem controller executes the memory command received from the host system based on the new mapping allocation. After executing the memory command, in operation 614, the memory subsystem controller executes and sends an indication that the memory command has been executed, and in operation 616, the host system receives the indication.

[0074] Any or all combinations of steps 602-616 may be repeated as needed, depending on the determination that one or more memory die blocks are offline, damaged, or unavailable.

[0075] Figure 7 An example machine of computer system 700 is shown, within which an instruction set is executable to cause the machine to perform any one or more methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., execute an operating system based on...). Figure 1 The data operator component 113 performs operations corresponding to the data operators. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0076] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0077] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0078] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 702 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 communicating via network 720.

[0079] The data storage system 718 may include a machine-readable storage medium 724 (also called a computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, the main memory 704 and processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0080] In one embodiment, instruction 726 includes a component for calculating effective memory counts (e.g., Figure 1 The data operator component 113 implements instructions corresponding to data operations. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "computer-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0081] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0082] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0083] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk or media suitable for storing electronic instructions, each coupled to a computer system bus, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards.

[0084] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to execute the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0085] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0086] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: A memory device comprising a plurality of memory die blocks and a plurality of memory channels operatively coupled to the plurality of memory die blocks; as well as A memory controller configured to perform operations including the following: One or more memory die blocks of the memory device are identified as invalid; Obtain the first matrix of the die mapping from the storage memory channel to the memory die block; Creating a new die mapping from a memory channel to a memory die block, wherein the new die mapping does not contain invalid one or more memory die blocks, the creation of the new die mapping includes: Generate a channel sequence, the channel sequence defining the order in which individual memory channels are assigned to individual memory blocks among the plurality of memory blocks; and The new die mapping is generated based on the channel sequence; The new die mapping is stored in the second matrix; and One or more operations are performed on the one or more memory die blocks based on the new die mapping.

2. The system of claim 1, wherein the channel sequence is generated from the first memory die block to the last memory die block among the plurality of memory die blocks, and wherein the creation of the new die mapping from memory channel to memory die block comprises: Add a die block enable parameter for each memory die block to map each combination of memory die block and memory channel to one of multiple die block enable inputs for each memory die block; as well as Add a Logical Unit Number (LUN) parameter for each memory die block to map each memory die block to one or more LUNs in the memory device of each memory die block.

3. The system of claim 2, wherein the generation of the channel sequence comprises: Remove one or more invalid memory blocks from the plurality of memory blocks to be mapped; A first memory channel among the plurality of memory channels is identified, and the first memory channel is mapped to the highest-counted memory die block in the first matrix; Select a second memory channel of the channel sequence, each memory channel having a plurality of memory die blocks to be mapped, the second memory channel being different from the first memory channel, and the second memory channel having a second minimum number of memory die blocks to be mapped among the plurality of memory channels; as well as Update the number of memory die blocks to be mapped for the second memory channel.

4. The system of claim 3, wherein the generation of the channel sequence comprises: After selecting the second memory channel: Select a third memory channel of the channel sequence, the third memory channel having the highest current number of memory die blocks to be mapped among the plurality of memory channels; as well as Update the number of memory die blocks to be mapped for the third memory channel.

5. The system of claim 2, wherein generating the channel sequence comprises: Remove one or more invalid memory blocks from the plurality of memory blocks to be mapped; as well as Repeat the following steps until each memory die block has been assigned to a selected memory channel: Select a single memory channel from the channel sequence, the single memory channel having the minimum number of memory die blocks of the plurality of memory channels to be mapped; as well as Update the number of memory die blocks to be mapped for the individual memory channel.

6. The system of claim 1, wherein identifying the one or more memory die blocks as invalid comprises performing a memory die block scan to identify memory die blocks that are at least one of being offline, invalid, or damaged.

7. The system of claim 1, wherein the operation includes: Perform a read operation on the memory device; as well as In response to the determination that the read operation failed, the new die mapping is created.

8. The system of claim 1, wherein the operation includes: Perform a write operation on the memory device; as well as In response to determining that the write operation has failed, the new die mapping is created.

9. The system according to claim 1, wherein the operation includes: An erase operation is performed on the memory device; as well as In response to the determination that the erase operation has failed, the new die mapping is created.

10. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means of a memory device, cause the processing means to perform operations including: The memory controller of the memory device receives an indication that a bus contention error has occurred on the memory channel; The identification of one or more memory die blocks of the memory device is invalid; Obtain the first matrix of the die mapping from the storage memory channel to the memory die block; Creating a new die mapping from a memory channel to a memory die block, wherein the new die mapping does not contain invalid one or more memory die blocks, the creation of the new die mapping includes: Generate a channel sequence, the channel sequence defining the order in which individual memory channels are assigned to individual memory blocks among multiple memory blocks; and The new die mapping is generated based on the channel sequence; The new die mapping is stored in the second matrix; and One or more operations are performed on the one or more memory die blocks based on the new die mapping.

11. The storage medium of claim 10, wherein the channel sequence is generated from the first memory die block to the last memory die block among the plurality of memory die blocks, and wherein the creation of the new die mapping from memory channels to memory die blocks comprises: Add a die block enable parameter for each memory die block to map each combination of memory die block and memory channel to one of multiple die block enable inputs for each memory die block; as well as Add a Logical Unit Number (LUN) parameter for each memory die block to map each memory die block to one or more LUNs in the memory device of each memory die block.

12. The storage medium of claim 11, wherein the generation of the channel sequence comprises: Remove one or more invalid memory blocks from the plurality of memory blocks to be mapped; A first memory channel among a plurality of memory channels of the memory device is identified, and the first memory channel is mapped to the highest-counted memory die block in the first matrix; Select a second memory channel of the channel sequence, each memory channel having a plurality of memory die blocks to be mapped, the second memory channel being different from the first memory channel, and the second memory channel having the minimum number of memory die blocks to be mapped among the plurality of memory channels; as well as Update the number of memory die blocks to be mapped for the second memory channel.

13. A method comprising: Receive a request to perform memory operations at a memory device comprising multiple memory blocks and multiple memory channels operatively coupled to the multiple memory blocks; At the memory controller of the memory device, one or more memory die blocks of the memory device are identified as invalid. Obtain the first matrix of the die mapping from the storage memory channel to the memory die block; Creating a new die mapping from a memory channel to a memory die block, wherein the new die mapping does not contain invalid one or more memory die blocks, the creation of the new die mapping includes: Generate a channel sequence, the channel sequence defining the order in which individual memory channels are assigned to individual memory blocks among the plurality of memory blocks; and The new die mapping is generated based on the channel sequence; The new die mapping is stored in the second matrix; and The memory operations are performed on the one or more memory die blocks based on the new die mapping.

14. The method of claim 13, wherein the channel sequence is generated from a first memory die block to a last memory die block among the plurality of memory die blocks, and wherein the creation of the new die mapping from memory channels to memory die blocks comprises: Add a die block enable parameter for each memory die block to map each combination of memory die block and memory channel to one of multiple die block enable inputs for each memory die block; as well as Add a Logical Unit Number (LUN) parameter for each memory die block to map each memory die block to one or more LUNs in the memory device of each memory die block.

15. The method of claim 14, wherein the generation of the channel sequence comprises: Remove one or more invalid memory blocks from the plurality of memory blocks to be mapped; A first memory channel among the plurality of memory channels is identified, and the first memory channel is mapped to the highest-counted memory die block in the first matrix; Select a second memory channel of the channel sequence, each memory channel having a plurality of memory die blocks to be mapped, the second memory channel being different from the first memory channel, and the second memory channel having the minimum number of memory die blocks to be mapped among the plurality of memory channels; as well as Update the number of memory die blocks to be mapped for the second memory channel.

16. The method of claim 15, wherein the generation of the channel sequence comprises: After selecting the second memory channel: Select a third memory channel of the channel sequence, the third memory channel having the minimum number of memory die blocks to be mapped among the plurality of memory channels; as well as Update the number of memory die blocks to be mapped for the third memory channel.

17. The method of claim 16, wherein the generation of the channel sequence comprises repeating the following steps until each memory die block has been assigned to a selected memory channel: Select a single memory channel from the channel sequence, the single memory channel having the minimum number of memory die blocks to be mapped among the plurality of memory channels; and Update the number of memory die blocks to be mapped for the individual memory channel.

18. The method of claim 13, wherein the identification of one or more invalid memory die blocks comprises performing a memory die block scan to identify memory die blocks that are at least one of being offline, invalid, or damaged.

19. The method of claim 13, further comprising: Perform a read operation or a write operation on the memory device; as well as In response to determining that the read operation or the write operation has failed, the new die mapping is created.

20. The method of claim 13, further comprising: An erase operation is performed on the memory device; as well as In response to the determination that the erase operation has failed, the new die mapping is created.

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