A layer assignment method that simultaneously considers the optimization of slew and the number of vias
By adopting non-default regular lines and multiple optimization strategies in the layer allocation process of ultra-large-scale integrated circuits, the optimization problems of the number of wire-network through-holes and slew violations are solved, and a high-quality wiring solution is achieved and circuit performance is improved.
Patent Information
- Application Number
- CN202210874217.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-22
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2042-07-22
AI Technical Summary
During the layer allocation process of ultra-large-scale integrated circuits, it is difficult for the prior art to effectively optimize the number of wire-network through-holes and slew violations, resulting in a degradation of circuit performance.
A layer allocation method that considers both slew and through hole optimization is adopted. Through non-default regular lines, network adjustment strategies, rewinding sorting adjustments and through hole optimization strategies, post-optimization adjustments and dynamic planning target parameter optimization strategies, the number of through holes and network slew violations of the final wiring scheme are reduced.
High-quality layer allocation results are achieved, reducing the number of through holes and slew violations, and improving circuit performance.
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Figure CN115204099B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of computer-aided design of integrated circuits, and particularly relates to a layer assignment method that simultaneously considers slew and via count optimization. Background Art
[0002] With the development of very large scale integrated circuits, the scale of the netlist is increasing day by day, and the impact of the number of via holes in the netlist and the number of slew violations on the performance of the routing result is also increasing. Therefore, in the research field of very large scale integrated circuits, researchers pay more and more attention to optimizing the number of via holes in the netlist and the number of slew violations during the layer assignment process to improve the circuit performance. In layer assignment, the use of vias is essential, and generating a large number of vias during the layer assignment process will lead to a significant increase in the manufacturing cost of the circuit. At the same time, the slew constraint is also an important constraint that the layer assignment method needs to consider. In the design process of very large scale integrated circuits, a 2D routing scheme is generated into a 3D routing scheme through the layer assignment method. By introducing an efficient layer assignment method, it is possible to effectively optimize indicators such as the number of vias and slew in the physical design process and improve the circuit performance. Summary of the Invention
[0003] The purpose of the present invention is to provide a layer assignment method that simultaneously considers slew and via count optimization, which can reduce the number of via holes and the number of slew violations in the final routing scheme, thereby obtaining a high-quality layer assignment result.
[0004] Optimizing the net delay can often effectively reduce the number of slew violations. Therefore, the present invention adopts an advanced process of non-default rule lines during the routing process to optimize the delay, and further reduce the number of slew violations. Non-default rule lines are mainly divided into two types: parallel lines and wide lines. Due to manufacturing process limitations, parallel lines are used in the lower layers to achieve the purpose of optimizing the delay, while wide lines are used in the higher layers to achieve the purpose of optimizing the delay.
[0005] To achieve the above purpose, the technical solution of the present invention is: a layer assignment method that simultaneously considers slew and via count optimization, including the following steps:
[0006] S1. Initial layer assignment stage;
[0007] S2. Negotiation-based slew-aware via reduction layer assignment stage;
[0008] S3. Post-optimization stage.
[0009] Compared with the prior art, the present invention has the following beneficial effects: the method of the present invention can reduce the number of via holes and the number of slew violations in the final routing scheme, thereby obtaining a high-quality layer assignment result. Brief Description of the Drawings
[0010] Figure 1 are different types of wires; Figure 1 (a) Default rule line, Figure 1 (b) Wide line, Figure 1 (c) Parallel lines, Figure 1 (d) Combined use.
[0011] Figure 2 is the wiring space; Figure 2 (a) Two-dimensional wiring space, Figure 2 (b) Three-dimensional wiring space.
[0012] Figure 3 is a layer assignment instance; Figure 3 (a) Two-dimensional wiring scheme, Figure 3 (b) Three-dimensional wiring scheme.
[0013] Figure 4 is the flowchart of the present invention. Detailed implementation manners
[0014] The technical solution of the present invention will be specifically described below with reference to the accompanying drawings.
[0015] As Figure 1 shown, Figure 1 a wiring instance of a three-layer wiring area is shown. Among them, the vertical rectangles on both sides represent the bottom pins, the horizontal rectangle represents the second-layer wire, and the middle rectangle represents the third-layer wire.
[0016] A. Default rule line:
[0017] In Figure 1 (a), the wiring effect of using the default-width line is shown.
[0018] B. Wide line:
[0019] Figure 1 (b) shows the wiring effect of using a wide line. Using a wire with a larger line width for wiring is beneficial to optimizing the wire net delay.
[0020] C. Parallel lines:
[0021] Figure 1 (c) uses parallel lines to achieve the optimization effect of the wide line on the delay during the wiring process.
[0022] D. Combined use:
[0023] Figure 1 (d) combines the use of parallel lines and default rule lines to complete an actual wiring process.
[0024] The present invention proposes a layer assignment method that simultaneously considers the optimization of slew and the number of vias.
[0025] The present invention specifically includes the following improvement strategies:
[0026] (1) Netlist adjustment strategy. The present invention optimizes the number of vias and the number of slew violations in the netlist by adjusting the large-scale netlist.
[0027] (2) Rewiring sorting adjustment and via optimization strategy. The present invention optimizes the number of vias and the number of slew violations in the netlist by adjusting the netlist sorting strategy and the rewiring strategy for specific netlists.
[0028] (3) Late-stage optimization adjustment strategy. The present invention realizes the optimization of the number of vias by rewiring some netlists.
[0029] (4) Dynamic programming target parameter optimization strategy. The present invention further reduces the number of slew violations by introducing a slew optimization term into the objective function.
[0030] The present invention integrates the above strategies to obtain a layer assignment method that can simultaneously optimize the number of vias and the number of slew violations.
[0031] 1. Overall routing model:
[0032] The layer assignment adopts the routing model as Figure 2 shown, where Figure 2 (a) represents the 2D routing area, Figure 2 (b) represents the 3D routing area. As Figure 2 shown, the routing space is a multi-layer structure with each layer having its own routing direction, and the routing directions of adjacent layers are perpendicular to each other. Since the track width of the upper layer is greater than that of the lower layer, the wires located in the upper layer of the routing area have a wider line width and a larger wire spacing than the wires in the lower layer, which makes the resistance corresponding to the upper-layer wires less than that of the lower-layer wires. On the other hand, since the upper-layer tracks are wider, the corresponding number of upper-layer tracks is less than that of the lower layer.
[0033] In the routing instance of a specific netlist, each g-cell in the 2D routing area is abstracted into a point, and adjacent points on the same routing layer are connected by edges. In the abstraction process from the 2D routing scheme to the 3D routing scheme, the routing directions of each routing layer in the 3D routing scheme are the same and the routing directions of adjacent routing layers are perpendicular to each other. At the same time, each netlist has a signal transmitter source and multiple signal receivers sink.
[0034] 2. Netlist delay calculation:
[0035] During the routing process of very large scale integrated circuits, the delay of each net is calculated through the Elmore delay model. The routed nets are stored in the form of a tree with a signal transmitter and one or more signal receivers. Among them, the signal transmitter has a driver resistance and each signal receiver has a load capacitance of the receiver. In the 3D routing tree of each net, each edge represents a wire segment or a via, and both are regarded as independent resistor-capacitor units. The delay d(s) of the wire segment s of the net can be calculated according to formula (1) through the Elmore delay model:
[0036] d(s) = R(s) × (C(s) / 2 + C down (s))(1)
[0037] In formula (1), R(s) represents the resistance of the wire segment, and C(s) and C down (s) represent the capacitance of the wire segment s and the downstream capacitance of the wire segment s respectively.
[0038] At the same time, the delay of the receiver s can be obtained from the Elmore delay formula. That is, by adding up the delays of all wire segments s from the signal transmitter to the receiver s i , the delay d(s i ) of the receiver s can be obtained, as shown in formula (2): i d(s i )
[0039]
[0040] By multiplying the delays of all receivers of the net by the user-defined net weight and accumulating them, the delay d(N) of the net can be obtained. The calculation formula is as shown in formula (3):
[0041]
[0042] Among them, S(N) is the set composed of all receivers of the net N, and α si represents the weight of the receiver s i . α is a user-defined parameter. To make each pin equally important, it is usually set to 1 / S(N), and S(N) represents the number of pins of the net N.
[0043] 3. Net slew calculation:
[0044] Slew is also known as the signal transition time. A too long signal transition time indicates a relatively long delay inside the circuit. For the calculation of slew, the PERI model is adopted, and this model has been proven to have an error of no more than 1%. Since the wiring nets are stored in the form of a tree, it is essentially a tree topology. The calculation of slew traverses the wires from the signal transmitter to each signal receiver in a breadth-first traversal manner and calculates the slew values of each pin. In this process, the input slew of each wire is the slew of the upstream pin of this wire, and the output slew is the slew of the downstream pin of this wire. The output signal transition time Slw(P out (s)) of each wire segment s is calculated as shown in Equation (4):
[0045]
[0046] where Slw(P in (s)) represents the input signal transition time of wire segment s, and Slw(P step (s)) represents the signal transition time at both ends of wire segment s. The calculation formula of Slw(P step (s)) is shown in Equation (5).
[0047] Slw step (s) = ln9 × D(p in , p out ) (5)
[0048] where D(P in , P out ) represents the Elmore delay at both ends of wire segment s.
[0049] 4. Congestion constraint:
[0050] Since the wiring space capacity of each wiring layer is different and the wiring space is limited, if too many wires are distributed on the same wiring layer during the wiring process or non-default rule wires are overused, it will cause overflow, which will in turn affect the routability of the circuit. Therefore, the following congestion constraint is introduced in the layer assignment method:
[0051] TWO(S k ) = TWO(S) (6)
[0052]
[0053] where S represents the wiring result of the initial 2D wiring scheme, S kIt represents the result of the 3D routing scheme obtained by the layer assignment method for S. TWO represents the total wire overflow, and MWO represents the maximum wire overflow. Among them, formula (6) is introduced to ensure that the wire overflow in the 3D routing scheme does not exceed that in the 2D routing scheme. Formula (7) is to ensure that the corresponding wire overflow in the 3D routing scheme can meet the maximum wire overflow in the corresponding 2D routing scheme.
[0054] 5. Layer Assignment Objectives:
[0055] The layer assignment problem can be described as: V K represents the set of grid cells, E K represents the set of grid edges, G K (V K , E K ) represents the K-layer routing area. G(V, K), where V and K respectively represent G K (V K , E K ), V K , E K 's horizontal projection. S represents the 2D global routing result, and S K represents the 3D global routing result. The task of layer assignment is to assign each wire in S to an appropriate grid edge in G K (V K , E K ), so as to obtain S K . e i is a grid edge of G(V, K), and e i,j is the corresponding grid edge in G K (V K , E K ), where j represents the j-th layer. Figure 3 (a) represents a 2D routing instance, Figure 3 (b) is Figure 3 (a) the 3D routing instance obtained after routing by the layer assignment method.
[0056] With the development of very large scale integrated circuits, the scale of the netlist is increasing day by day, and the impact of the number of net vias and slew violations on the performance of the routing scheme is also increasing. Therefore, the present invention effectively reduces the number of net vias and slew violations through multiple reasonable strategies, so as to obtain a high-quality layer assignment result.
[0057] 6. Algorithm Overview:
[0058] (1) Overall Process
[0059] The present invention optimizes the number of vias in a netlist and the slew violation number of a netlist based on the idea of dynamic programming. The present invention abstracts the 2D routing scheme of a single net into a corresponding 2D routing tree. Then, through dynamic programming, each edge of the obtained 2D routing tree is assigned to a 3D routing area to obtain a 3D routing tree, and then the final result, the 3D routing scheme, is obtained.
[0060] The layer assignment method that comprehensively considers via number optimization and slew constraint mainly consists of three stages, namely the initial layer assignment stage, the via reduction layer assignment stage based on negotiation-based slew awareness, and the late optimization stage. The flowchart of the layer assignment that comprehensively considers via number optimization and slew constraint is as Figure 4 shown.
[0061] The primary task in the initial layer assignment stage is to find the minimum delay layer assignment scheme for each net. Therefore, in this stage, congestion constraints and the use of special lines such as non-default rules lines are not considered, but the delay of each net is fairly evaluated in order to find the layer assignment scheme with the minimum delay.
[0062] In the via number reduction layer assignment stage based on negotiation-based slew awareness, the violated nets are reassigned, and through iteration, these violated nets are made to satisfy the line constraints and the number of vias in the net and the slew violation number are optimized. At the same time, in this stage, non-default rules lines are used to further utilize the routing resources so as to reduce the net delay and thus optimize the slew. Each iteration is divided into three steps:
[0063] A. The PERI model and the Elmore model are used to calculate the slew inside the net, and at the same time, the violated nets are identified and sorted according to a certain strategy. The sorting strategy needs to comprehensively consider the number of vias in the net and the slew violation number. In this step, the nets are sorted, and the slew factor is incorporated into the layer assignment method design step, so that while optimizing the number of vias in the net, the slew violation number generated in this process is minimized as much as possible.
[0064] B. The slew-aware via number optimization process disassembles and re-routes the violated nets one by one according to the sorting result obtained in A.
[0065] C. When the layer assignment for all violated nets is completed, the nets with the number of vias greater than the average number of vias in the net are disassembled and re-routed. If the re-routing has an optimization effect on the number of vias in the net or has an optimization effect on the slew violation number of the net, the re-routing scheme is retained, otherwise the original routing scheme is restored.
[0066] In the later optimization stage, the present invention sorts all the nets according to a certain sorting strategy, and then removes and rewires the nets one by one according to the sorting order. If, after rewiring, the number of vias of a net increases or the number of slew violations of the net increases, the layer assignment scheme before the net was removed is restored. If, after rewiring, the number of vias of the net decreases and the number of slew violations of the net decreases, the layer assignment scheme after the net was rewired is retained. All nets in the later optimization stage always satisfy the line congestion constraint. In this stage, each net is reassigned, but the definition of the congestion cost in the objective function is different from that in the negotiation-based slew-aware via reduction layer assignment stage. If there is an overflow in the routing edge, the congestion cost of the routing edge is set to a very large value. At this time, when performing layer assignment for a single net, it is possible to avoid nets in the final routing scheme that violate the line congestion constraint.
[0067] (2) Net adjustment strategy
[0068] In the initial layer assignment stage, since the line congestion constraint and the use of special lines such as non-default rule lines are not considered, there is a large amount of line congestion in the nets in the 3D routing scheme obtained after the initial layer assignment stage. At the same time, since the line width and routing space in the upper routing area are larger than those in the lower routing area, after completing the routing work in this stage, the nets are all concentrated in the upper routing area. Therefore, at this time, adjusting all the nets is of great significance for the negotiation-based slew-aware via reduction layer assignment stage. The net adjustment strategy removes and rewires the nets whose number of vias is greater than the average number of vias of all nets or whose number of slew violations is greater than the average number of slew violations of all nets, so that larger nets can be assigned to the lower layer of the routing area, thereby enabling the upper layer of the routing area to accommodate more small-scale nets, and further reducing the number of layers of a single net across the routing area, achieving the purpose of optimizing the number of vias of the nets. By reducing the number of vias, the via delay of the routing scheme can be reduced, and according to the PERI model, the optimization of the number of slew violations of the nets can be achieved.
[0069] (3) Rewiring sorting adjustment and via optimization strategy
[0070] In the negotiation-based slew-aware via reduction layer assignment stage, the present invention optimizes illegal nets in an iterative manner. First, the slew inside the net is calculated according to the PERI model and the Elmore model, and at the same time, the default nets are identified and sorted according to a certain strategy. The calculation formula for the sorting strategy of the nets is shown in formula (8).
[0071] sort(N) = 1000×d(N)+#vc(N)+10000×#sv(N)(8)
[0072] Among them, d(N) represents the delay of the wire network N, #vc(N) represents the number of vias of the wire network N, and #sv(N) represents the number of slew violations of the wire network N. In the via reduction layer assignment stage of negotiation-based slew-aware, all the violated wire networks are sorted in descending order according to the sort(N) value calculated by the above formula, and each violated wire network is disassembled and re-routed. If, after re-routing, the number of vias of the wire network increases or the number of slew violations of the wire network increases, then the wire network is removed and the layer assignment scheme before the later optimization stage is restored for this wire network.
[0073] Meanwhile, in order to further optimize the number of vias in the present invention, after each illegal wire network is re-routed in the iteration, all wire networks are traversed. If the number of vias of the current wire network is greater than the average number of vias of all wire networks, then this wire network is disassembled and re-routed. If, after the re-routing process, the number of vias of this wire network increases compared with the original wire network, then this wire network is disassembled and the original routing scheme of this wire network is restored. Meanwhile, in order to avoid an increase in the number of slew violations of the wire network during this process, if the number of slew violations of this wire network increases compared with the original wire network before re-routing after re-routing, this wire network is also disassembled and the original routing scheme of this wire network is restored.
[0074] (4) Later optimization strategy
[0075] In the later optimization stage, in order to further reduce the total number of vias of the wire networks in the final routing scheme, the layer assignment method disassembles and re-routes each wire network in a certain order. The calculation formula for the sorting strategy of the wire networks is shown in formula (9).
[0076] sort(N) = d(N) + #vc(N) + 10000×#sv(N) (9)
[0077] Among them, d(N) represents the delay of the wire network N, # vc (N) represents the number of vias of the wire network N, #s v (N) represents the number of slew violations of the wire network N. In the later optimization stage, each wire network is sorted in descending order according to the sort(N) value calculated by the above formula, and each wire network is disassembled and re-routed. If, after re-routing, the number of vias of the wire network increases, then the wire network is removed and the layer assignment scheme before the later optimization stage is restored for this wire network.
[0078] In the later optimization stage, the sorting strategy takes into account the number of vias in the netlist and the number of slew violations of the netlist. After the initial layer assignment stage and the via reduction layer assignment stage based on negotiated slew awareness, there is still available routing area in the upper part of the routing region. At this time, rerouting the nets with a larger number of slew violations or a larger number of vias helps to utilize this upper routing area.
[0079] (5) Dynamic programming target parameter optimization strategy
[0080] In the initial layer assignment stage, each net is assigned to the best position to find the minimum delay layer assignment scheme. The routing scheme of a single net is obtained through the dynamic programming routing algorithm, specifically by minimizing the tar(N) value calculated for net N according to formula (10).
[0081] tar(N) = β × [d(N) + #sv(N)] + 2 × #vc(N) (10)
[0082] where d(N) represents the delay of net N, # vc (N) represents the number of vias in net N, #s v (N) represents the number of slew violations of net N.
[0083] Similarly, in the via reduction layer assignment stage based on negotiated slew awareness, each net is assigned to the best position to find the minimum delay layer assignment scheme. The routing scheme of a single net is obtained through dynamic programming, specifically by minimizing the tar(N) value calculated for net N according to formula (11).
[0084] tar(N) = β × [d(N) + #sv(N)] + 2 × #vc(N) + ∑ s∈N cong(e s )(11)
[0085] where ∑ s∈N cong(e s ) represents the congestion cost corresponding to the wire segment s of net N in 3D routing.
[0086] In previous work, the slew constraint was not incorporated into the objective function of the dynamic programming routing. Therefore, incorporating the number of slew violations of the net into the objective function helps to optimize the number of slew violations of the net in the final 3D routing scheme obtained by the dynamic programming routing algorithm. At the same time, increasing the proportion of the influencing factor of the number of vias in the objective function of the dynamic programming process helps to reduce the number of vias in the net while reducing the number of slew violations of the net.
[0087] The above are the preferred embodiments of the present invention. All changes made according to the technical solutions of the present invention, as long as the functions and effects produced do not exceed the scope of the technical solutions of the present invention, fall within the protection scope of the present invention.
Claims
1. A layer assignment method that simultaneously considers the optimization of slew and the number of vias, characterized in that, It includes the following steps: S1. Initial layer assignment stage; the specific implementation method is as follows: The primary task in the initial layer assignment stage is to find the minimum delay layer assignment scheme for each net, that is, in this stage, congestion constraints and the use of non-default rules lines are not considered, but the delay of each net is fairly evaluated in order to find the layer assignment scheme with the minimum delay; S2. Negotiation-based slew-aware via reduction layer assignment stage; the specific implementation method is as follows: The negotiation-based slew-aware via count reduction layer assignment stage reassigns the default-violating nets, and through iteration, makes these default-violating nets meet the line constraints and optimizes the via count and slew violation count of the nets; meanwhile, in this stage, non-default rules lines are used to further utilize the routing resources so as to reduce the net delay, and further optimize the slew; each iteration is divided into three steps: A. Use the PERI model and the Elmore model to calculate the slew inside the net, and at the same time identify the violating nets and sort them according to the sorting strategy. The sorting strategy needs to comprehensively consider the via count and slew violation count of the net, and incorporate the slew factor, so that the net reduces the slew violation count generated during the process of optimizing the via count; B. Slew-aware via count optimization process, disassemble and re-route the default-violating nets one by one according to the sorting result obtained in step A; C. After the layer assignment of all default-violating nets is completed, disassemble and re-route the nets whose via count is greater than the average via count of the net; if the re-routing has an optimization effect on the via count of the net or has an optimization effect on the slew violation count of the net, then retain the re-routing scheme, otherwise restore the original routing scheme; S3. Late optimization stage; the specific implementation method is as follows: In the late optimization stage, all nets are sorted according to the sorting strategy, and then the nets are disassembled and re-routed one by one according to the sorting order; if after re-routing, the via count of the net increases or the slew violation count of the net increases, then restore the layer assignment scheme of the net before disassembly; if after re-routing, the via count of the net decreases and the slew violation count of the net decreases, then retain the layer assignment scheme of the net after re-routing; All nets in the late optimization stage always meet the line congestion constraints; in this stage, each net is re-assigned, but the definition of the congestion cost in the objective function is different from that in the negotiation-based slew-aware via count reduction layer assignment stage. If there is an overflow on the routing edge, the congestion cost of the routing edge is set to a very large value.
2. The layer assignment method for simultaneously optimizing slew and via count according to claim 1, characterized in that In the process of finding the minimum delay layer assignment scheme for each net in the initial layer assignment stage, the routing scheme of a single net is obtained through the dynamic programming routing algorithm. The specific implementation is to make the tar(N) value calculated by the net N according to the following formula the smallest: tar(N) = β × [d(N) + #sv(N)] + 2 × #vc(N) Among them, d(N) represents the delay of the wire network N, # vc (N) represents the number of vias in the wire network N, #s v (N) represents the number of slew violations in the wire network N.
3. A layer assignment method that simultaneously considers slew and via count optimization according to claim 1, characterized in that, In the negotiation-based slew-aware via count reduction layer assignment stage, the routing scheme of a single net is obtained through the dynamic programming routing algorithm. The specific implementation is to make the tar(N) value calculated by the net N according to the following formula the smallest: tar(N) = β × [d(N) + #sv(N)] + 2 × #vc(N) + ∑ s∈N cong(e s ) Among them, Σ s∈N cong(e s ) represents the congestion cost corresponding to the wire segment s of the wire network N in 3D routing.
4. A layer assignment method that simultaneously considers slew and via count optimization according to claim 1, characterized in that In step A, the sorting strategy calculation formula is as follows: sort(N) = 1000 × d(N) + #vc(N) + 10000 × #sv(N) Among them, d(N) represents the delay of the wire network N. # vc (N) represents the number of vias in the wire network N. #s v (N) represents the number of slew violations in the wire network N.
5. A layer assignment method that simultaneously considers slew and via count optimization according to claim 1, characterized in that In the later optimization stage, the sorting strategy calculation formula is as follows: sort(N) = d(N) + #vc(N) + 10000 × #sv(N) Among them, d(N) represents the delay of the wire network N, # vc (N) represents the number of vias in the wire network N, #s v (N) represents the number of slew violations in the wire network N.
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