Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels located on the base substrate, each sub-pixel includes a pixel circuit, and the plurality of pixel circuits are distributed in a plurality of rows and columns along a first direction and a second direction. The plurality of sub-pixels include a first sub-pixel, the display substrate also includes a first data line connected to the first sub-pixel, the first data line extends along the first direction and is electrically connected to the first sub-pixel; the plurality of sub-pixels also include a second sub-pixel directly adjacent to the first sub-pixel in the second direction; the first capacitor electrode in the first sub-pixel and the first capacitor electrode in the second sub-pixel are arranged in the same layer and are spaced from each other; and the first capacitor electrode in the first sub-pixel and the first data line overlap with each other in a direction perpendicular to the base substrate to provide a first capacitor. The display substrate helps to improve the quality of the display image.

Description

[0001] This application is a divisional application of the invention patent application with application number 201980002728.9 filed on November 29, 2019 and invention name “Display substrate and display device”. Technical Field

[0002] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0003] In the field of OLED (Organic Light-Emitting Diode) display, with the rapid development of high-resolution products, higher requirements are placed on the structural design of display substrates, such as the arrangement of pixels and signal lines. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a display substrate, including a substrate and a plurality of sub-pixels located on the substrate. Each of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit is used to drive a light-emitting element to emit light; the plurality of pixel circuits of the plurality of sub-pixels are distributed in a plurality of rows and columns along a first direction and a second direction; the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a storage sub-circuit; the driving sub-circuit includes a control terminal, a first terminal and a second terminal, and is configured to couple with the light-emitting element and control the driving current flowing through the light-emitting element; the data writing sub-circuit includes a control terminal, a first terminal and a second terminal, the control terminal of the data writing sub-circuit is configured to receive a first scanning signal, the first terminal of the data writing sub-circuit is configured to receive a data signal, the second terminal of the data writing sub-circuit is electrically connected to the driving sub-circuit, and the data writing sub-circuit is configured to write the data signal to the first terminal of the driving sub-circuit in response to the first scanning signal; the compensation sub-circuit includes a control terminal, a first terminal and a second terminal, the control terminal of the compensation sub-circuit is configured to receive a second scanning signal, and the first terminal and the second terminal of the compensation sub-circuit are respectively connected to the control terminal of the driving sub-circuit The first terminal is electrically connected to the second terminal, and the compensation subcircuit is configured to perform threshold compensation on the driving subcircuit in response to the second scanning signal; the storage subcircuit is electrically connected to the control terminal and the first voltage terminal of the driving subcircuit, and is configured to store the data signal; the storage subcircuit includes a storage capacitor, a first capacitor electrode of the storage capacitor is coupled to the first voltage terminal, and a second capacitor electrode is coupled to the control terminal of the driving subcircuit; the multiple sub-pixels include a first sub-pixel, the display substrate also includes a first data line connected to the first sub-pixel, the first data line extends along the first direction and is connected to the first end of the data writing subcircuit of the first sub-pixel to provide the data signal; the multiple sub-pixels also include a second sub-pixel directly adjacent to the first sub-pixel in the second direction; the first capacitor electrode in the first sub-pixel and the first capacitor electrode in the second sub-pixel are arranged in the same layer and are spaced from each other; and the first capacitor electrode in the first sub-pixel and the first data line overlap with each other in a direction perpendicular to the substrate to provide a first capacitor.

[0005] In some examples, the first capacitor electrode in the first sub-pixel includes an extension portion, and the extension portion and the first data line overlap each other in a direction perpendicular to the base substrate to provide the first capacitor.

[0006] In some examples, the first data line is located between the pixel circuit of the first sub-pixel and the pixel circuit of the second sub-pixel.

[0007] In some examples, the driving subcircuit in the second sub-pixel includes a first transistor, the first transistor includes a gate, a first electrode, and a second electrode, the second electrode serving as a second end of the driving subcircuit; the second electrode of the first transistor does not overlap with the first capacitor electrode in the first sub-pixel in a direction perpendicular to the substrate.

[0008] In some examples, a ratio of an area of ​​the extension portion to an area of ​​the first capacitor electrode is in a range of 1 / 10-1 / 3.

[0009] In some examples, in the first direction, a ratio of a maximum dimension of the extension portion to a maximum dimension of the first capacitor electrode is in a range of 1 / 4-1 / 2.

[0010] In some examples, the first sub-pixel further includes a second capacitor; a first end and a second end of the second capacitor are electrically connected to the first data line and a second capacitor electrode of the first sub-pixel, respectively.

[0011] In some examples, the second capacitor includes a first sub-capacitor and a second sub-capacitor connected in series; the display substrate also includes a first scan line extending along the second direction, the first scan line is connected to the control end of the compensation sub-circuit to provide the second scan signal, and the first scan line and the first data line overlap with each other in a direction perpendicular to the base substrate to form the first sub-capacitor; the first sub-pixel also includes a first connecting electrode, the first connecting electrode is respectively connected to the second capacitor electrode and the second end of the compensation sub-circuit, and the first scan line and the first connecting electrode overlap with each other in a direction perpendicular to the base substrate to form the second sub-capacitor.

[0012] In some examples, in a direction perpendicular to the substrate, the first connecting electrode is located on a side of the first capacitor electrode away from the second capacitor electrode; the first capacitor electrode includes a first via hole, and the first connecting electrode is electrically connected to the second capacitor electrode through the first via hole.

[0013] In some examples, the display substrate further includes a plurality of first power lines extending along the first direction, connected to the first voltage terminal, and configured to provide a first power voltage to the plurality of sub-pixels.

[0014] In some examples, the multiple first power lines are located on a side of the first capacitor electrode away from the base substrate, and the display substrate also includes an interlayer insulating layer located between the first capacitor electrode and the multiple first power lines, and two of the multiple first power lines are electrically connected to the first capacitor electrodes in the first sub-pixel and the second sub-pixel through second vias in the interlayer insulating layer to provide the first power supply voltage.

[0015] In some examples, the display substrate further includes a second power line extending along the second direction and electrically connecting the plurality of first power lines.

[0016] In some examples, the second power line does not overlap with the opening area of ​​each sub-pixel in a direction perpendicular to the base substrate.

[0017] In some examples, the display substrate also includes a plurality of third power lines extending along the first direction, the plurality of third power lines are electrically connected to the plurality of first power lines one by one, and each third power line at least partially overlaps with the corresponding first power line in a direction perpendicular to the base substrate.

[0018] In some examples, the plurality of third power lines are disposed on the same layer as the second power line and are an integrated structure.

[0019] In some examples, the plurality of third power lines are located on a side of the plurality of first power lines away from the base substrate; the display substrate also includes a flat layer located between the plurality of third power lines and the plurality of first power lines, and each third power line is electrically connected to the corresponding first power line through a third via hole in the flat layer, thereby electrically connecting the second power line to the plurality of first power lines.

[0020] In some examples, each sub-pixel further includes a second connecting electrode and a third connecting electrode,

[0021] Among them, the second connecting electrode is insulated and arranged on the same layer as the multiple first power lines, the third connecting electrode is insulated and arranged on the same layer as the second power lines, the second connecting electrode and the pixel circuit of each sub-pixel are electrically connected through a fourth via hole, the first connecting electrode and the second connecting electrode of each sub-pixel are electrically connected through a fifth via hole, and the third connecting electrode of each sub-pixel is configured to be electrically connected to the light-emitting element through a sixth via hole.

[0022] In some examples, the orthographic projection of the fifth via hole on the base substrate and the orthographic projection of the sixth via hole on the base substrate do not overlap with the orthographic projection of the opening area of ​​the corresponding sub-pixel on the base substrate.

[0023] In some examples, the orthographic projection of the fifth via hole on the substrate substrate is closer to the opening area of ​​the sub-pixel to which it belongs than the orthographic projection of the sixth via hole on the substrate substrate.

[0024] At least one embodiment of the present disclosure further provides a display device, comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments or related technical descriptions will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and are not limitations of the present disclosure.

[0026] Figure 1A One of the schematic diagrams of a display substrate provided by at least one embodiment of the present disclosure;

[0027] Figure 1B One of the pixel circuit diagrams in the display substrate provided by at least one embodiment of the present disclosure;

[0028] Figure 1C A second pixel circuit diagram in a display substrate provided by at least one embodiment of the present disclosure;

[0029] Figure 2 A second schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0030] Figure 3A A third schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0031] Figure 3B A fourth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0032] Figure 3C A fifth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0033] Figure 3D A sixth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0034] Figure 3E for Figure 3D A cross-sectional view along the section line C-C';

[0035] Figure 4 A seventh schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0036] Figure 5 for Figure 4 A cross-sectional view along the section line AA';

[0037] Figure 6 An eighth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0038] Fig. 7A for Figure 2 A cross-sectional view along the section line BB';

[0039] Figure 7BA third pixel circuit diagram in a display substrate provided by at least one embodiment of the present disclosure;

[0040] Figure 8 A schematic diagram of a first capacitor electrode provided in at least one embodiment of the present disclosure;

[0041] Fig. 9 A schematic diagram of a display panel provided for at least one embodiment of the present disclosure; and

[0042] Fig.10 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. With reference to the non-limiting exemplary embodiments shown in the accompanying drawings and described in detail in the following description, the exemplary embodiments of the present disclosure and their various features and advantageous details are more fully described. It should be noted that the features shown in the figures are not necessarily drawn to scale. The present disclosure omits the description of known materials, components and process technologies so as not to obscure the exemplary embodiments of the present disclosure. The examples given are only intended to facilitate the understanding of the implementation of the exemplary embodiments of the present disclosure, and to further enable those skilled in the art to implement the exemplary embodiments. Therefore, these examples should not be construed as limiting the scope of the embodiments of the present disclosure.

[0044] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0045] In the field of OLED (Organic Light-Emitting Diode) display, with the rapid development of high-resolution products, higher requirements are put forward for the structural design of the display substrate, such as the arrangement of pixels and signal lines. For example, compared with an OLED display device with a resolution of 4K, a large-size OLED display device with a resolution of 8K has a doubling of the number of sub-pixel units that need to be set, and the pixel density increases accordingly. On the one hand, the line width of the signal line also becomes smaller, resulting in a larger resistance of the signal line; on the other hand, the overlap between the signal lines increases, resulting in a larger parasitic capacitance of the signal line, which leads to a larger resistance-capacitance load of the signal line. Correspondingly, the signal delay (RC delay) caused by the resistance-capacitance load, as well as the voltage drop (IR drop), voltage rise (IR rise) and other phenomena will also become serious. These phenomena will seriously affect the display quality of the display product.

[0046] Figure 1A is a block diagram of a display substrate provided by at least one embodiment of the present disclosure. Figure 1A As shown, the display substrate 20 includes a plurality of sub-pixels 100 distributed in an array, a plurality of gate lines 11 and a plurality of data lines 12. Each sub-pixel 100 includes a light-emitting element and a pixel circuit driving the light-emitting element. The plurality of gate lines 11 and the plurality of data lines 12 cross each other to define a plurality of pixel areas distributed in an array in the display area, and a pixel circuit of a sub-pixel 100 is arranged in each pixel area. The pixel circuit is, for example, a conventional pixel circuit, for example, a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C, etc. nTmC (n, m are positive integers) pixel circuit, and in different embodiments, the pixel circuit may further include a compensation sub-circuit, the compensation sub-circuit includes an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include a transistor, a capacitor, etc. For example, as required, the pixel circuit may further include a reset circuit, a light-emitting control sub-circuit, a detection circuit, etc. For example, the display substrate may also include a gate drive sub-circuit 13 and a data drive sub-circuit 14 located in the non-display area. The gate driving subcircuit 13 is connected to the pixel circuit via the gate line 11 to provide various scanning signals, and the data driving subcircuit 14 is connected to the pixel circuit via the data line 12 to provide data signals. Figure 1A The positional relationship between the gate driving sub-circuit 13 and the data driving sub-circuit 14, the gate lines 11 and the data lines 12 in the display substrate shown in the figure is only an example, and the actual arrangement positions can be designed as needed.

[0047] For example, the display substrate 20 may further include a control circuit (not shown). For example, the control circuit is configured to control the data drive subcircuit 14 to apply the data signal, and control the gate drive subcircuit to apply the scan signal. An example of the control circuit is a timing control circuit (T-con). The control circuit may be in various forms, such as including a processor and a memory, the memory including an executable code, and the processor runs the executable code to execute the above-mentioned detection method.

[0048] For example, the processor may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0049] For example, the storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may run the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium.

[0050] The pixel circuit may include a driving subcircuit, a data writing subcircuit, a compensation subcircuit and a storage subcircuit, and may also include a light emitting control subcircuit, a reset circuit, etc. as required. Figure 1B A schematic diagram of a pixel circuit is shown.

[0051] like Figure 1B As shown, the pixel circuit includes a driving subcircuit 122 , a data writing subcircuit 126 , a compensation subcircuit 128 , a storage subcircuit 127 , a first light-emitting control subcircuit 123 , a second light-emitting control subcircuit 124 and a reset circuit 129 .

[0052] For example, the driving subcircuit 122 includes a control terminal 131, a first terminal 132 and a second terminal 133, which is configured to control a driving current flowing through the light-emitting element 120, and the control terminal 131 of the driving subcircuit 122 is connected to the first node N1, the first terminal 132 of the driving subcircuit 122 is connected to the second node N2, and the second terminal 133 of the driving subcircuit 122 is connected to the third node N3.

[0053] For example, the data writing subcircuit 126 includes a control terminal, a first terminal, and a second terminal, wherein the control terminal is configured to receive a first scanning signal, the first terminal is configured to receive a data signal, and the second terminal is connected to the first terminal 132 (the second node N2) of the driving subcircuit 122, and is configured to write the data signal to the first terminal 132 of the driving subcircuit 122 in response to the first scanning signal Ga1. For example, the first terminal of the data writing subcircuit 126 is connected to the data line 12 to receive the data signal, and the control terminal is connected to the scanning line 11 to receive the first scanning signal Ga1.

[0054] For example, in the data writing stage, the data writing sub-circuit 126 can be turned on in response to the first scanning signal Ga1, so that the data signal can be written to the first end 132 (the second node N2) of the driving sub-circuit 122, and the data signal can be stored in the storage sub-circuit 127, so that a driving current can be generated according to the data signal to drive the light-emitting element 120 to emit light, for example, in the light-emitting stage.

[0055] For example, the compensation sub-circuit 128 includes a control end, a first end, and a second end. The control end is configured to receive a second scanning signal Ga2, and the first end and the second end are electrically connected to the control end 131 and the second end 133 of the driving sub-circuit 122, respectively. The compensation sub-circuit is configured to perform threshold compensation on the driving sub-circuit 120 in response to the second scanning signal.

[0056] For example, the storage subcircuit 127 is electrically connected to the control terminal 131 and the first voltage terminal VDD of the driving subcircuit 122, and is configured to store the data signal written by the data writing subcircuit 126. For example, in the data writing and compensation stage, the compensation subcircuit 128 can be turned on in response to the second scanning signal Ga2, so that the data signal written by the data writing subcircuit 126 can be stored in the storage subcircuit 127. For example, in the data writing and compensation stage, the compensation subcircuit 128 can electrically connect the control terminal 131 and the second terminal 133 of the driving subcircuit 122, so that the relevant information of the threshold voltage of the driving subcircuit 122 can also be correspondingly stored in the storage subcircuit, so that, for example, in the light emitting stage, the stored data signal and the threshold voltage can be used to control the driving subcircuit 122, so that the output of the driving subcircuit 122 is compensated.

[0057] For example, the first light emitting control subcircuit 123 is connected to the first terminal 132 (second node N2) of the driving subcircuit 122 and the first voltage terminal VDD, and is configured to apply the first power supply voltage of the first voltage terminal VDD to the first terminal 132 of the driving subcircuit 122 in response to the first light emitting control signal. Figure 1B As shown, the first light emitting control sub-circuit 123 is connected to the first light emitting control terminal EM1, the first voltage terminal VDD and the second node N2.

[0058] For example, the second light emitting control subcircuit 124 is connected to the second light emitting control terminal EM2, the first terminal 510 of the light emitting element 120 and the second terminal 132 of the driving subcircuit 122, and is configured to respond to the second light emitting control signal so that the driving current can be applied to the light emitting element 122.

[0059] For example, in the light-emitting stage, the second light-emitting control subcircuit 123 is turned on in response to the second light-emitting control signal provided by the second light-emitting control terminal EM2, so that the driving subcircuit 122 can be electrically connected to the light-emitting element 120 through the second light-emitting control subcircuit 123, thereby driving the light-emitting element 120 to emit light under the control of the driving current; while in the non-light-emitting stage, the second light-emitting control subcircuit 123 is turned off in response to the second light-emitting control signal, thereby preventing current from flowing through the light-emitting element 120 to cause it to emit light, which can improve the contrast of the corresponding display device.

[0060] For another example, during the initialization phase, the second light emitting control sub-circuit 124 may also be turned on in response to the second light emitting control signal, so that the reset circuit may be combined to perform a reset operation on the driving sub-circuit 122 and the light emitting element 120 .

[0061] For example, the second light emitting control signal EM2 may be the same as or different from the first light emitting control signal EM1 , for example, both may be connected to the same or different signal output terminals.

[0062] For example, the reset circuit 129 is connected to the reset voltage terminal Vinit and the first terminal 134 (fourth node N4) of the light emitting element 122, and is configured to apply the reset voltage to the first terminal 134 of the light emitting element 120 in response to the reset signal. Figure 1B As shown, the reset signal can also be applied to the control terminal 131 of the driving sub-circuit, that is, the first node N1. For example, the reset signal is the second scanning signal, and the reset signal can also be other signals synchronized with the second scanning signal, which is not limited in the embodiments of the present disclosure. Figure 1B As shown, the reset circuit 129 is respectively connected to the first terminal 134, the reset voltage terminal Vinit and the reset control terminal Rst (reset control line) of the light emitting element 120. For example, in the initialization stage, the reset circuit 129 can be turned on in response to the reset signal, so that the reset voltage can be applied to the first terminal 134 and the first node N1 of the light emitting element 120, so that the driving sub-circuit 122, the compensation sub-circuit 128 and the light emitting element 120 can be reset to eliminate the influence of the previous light emitting stage.

[0063] For example, the light emitting element 120 includes a first terminal 134 and a second terminal 135, wherein the first terminal 134 of the light emitting element 120 is configured to be coupled to the second terminal 133 of the driving sub-circuit 122, and the second terminal 135 of the light emitting element 120 is configured to be connected to the second voltage terminal VSS. Figure 1B As shown, the first end 134 of the light emitting element 120 can be connected to the third node N3 through the second light emitting control subcircuit 124. The embodiments of the present disclosure include but are not limited to this situation. For example, the light emitting element 120 can be various types of OLEDs, such as top emission, bottom emission, double-side emission, etc., and can emit red light, green light, blue light or white light, etc. The first electrode and the second electrode of the OLED serve as the first end 134 and the second end 135 of the light emitting element, respectively. The embodiments of the present disclosure do not limit the specific structure of the light emitting element.

[0064] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3 and the fourth node N4 do not necessarily represent actual existing components, but represent the junction points of related circuit connections in the circuit diagram.

[0065] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vd can represent both the data signal terminal and the level of the data signal. Similarly, the symbols Ga1 and Ga2 can represent both the first scanning signal and the second scanning signal, and can also represent the first scanning signal terminal and the second scanning signal terminal. Rst can represent both the reset control terminal and the reset signal. The symbol Vinit can represent both the reset voltage terminal and the reset voltage. The symbol VDD can represent both the first voltage terminal and the first power supply voltage. The symbol VSS can represent both the second voltage terminal and the second power supply voltage. The following embodiments are the same as this and will not be described in detail.

[0066] Figure 1C for Figure 1B A circuit diagram of a specific implementation example of a pixel circuit is shown. Figure 1C As shown, the pixel circuit includes: first to seventh transistors T1, T2, T3, T4, T5, T6, T7 and a storage capacitor Cst. For example, the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.

[0067] For example, Figure 1CAs shown, the driving sub-circuit 122 can be implemented as a first transistor T1. The gate of the first transistor T1 serves as a control terminal 131 of the driving sub-circuit 122 and is connected to the first node N1; the first electrode of the first transistor T1 serves as a first terminal 132 of the driving sub-circuit 122 and is connected to the second node N2; the second electrode of the first transistor T1 serves as a second terminal 133 of the driving sub-circuit 122 and is connected to the third node N3.

[0068] For example, Figure 1C As shown, the data writing subcircuit 126 can be implemented as a second transistor T2. The gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, the first electrode of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second electrode of the second transistor T2 is connected to the first terminal 132 (second node N2) of the driving subcircuit 122. For example, the second transistor T2 is a P-type transistor, such as a thin film transistor whose active layer is low-temperature doped polysilicon.

[0069] For example, Figure 1C As shown, the compensation sub-circuit 128 can be implemented as a third transistor T3. The gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal, the first electrode of the third transistor T3 is connected to the control terminal 131 (the first node N1) of the driving sub-circuit 122, and the second electrode of the third transistor T3 is connected to the second terminal 133 (the third node N3) of the driving sub-circuit 122.

[0070] For example, Figure 1C As shown, the storage subcircuit 127 can be implemented as a storage capacitor Cst, which includes a first capacitor electrode Ca and a second capacitor electrode Cb. The first capacitor electrode Ca is coupled to the first voltage terminal VDD, such as electrically connected, and the second capacitor electrode Cb is coupled to the control terminal 131 of the driving subcircuit 122, such as electrically connected.

[0071] For example, Figure 1C As shown, the first light-emitting control subcircuit 123 can be implemented as a fourth transistor T4. The gate of the fourth transistor T4 is connected to the first light-emitting control line (first light-emitting control terminal EM1) to receive the first light-emitting control signal, the first electrode of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply voltage, and the second electrode of the fourth transistor T4 is connected to the first terminal 132 (second node N2) of the driving subcircuit 122.

[0072] For example, the light emitting element 120 may be specifically implemented as an OLED, wherein the first electrode 134 (here, the anode) and the fourth node N4 are connected to receive a driving current from the second terminal 133 of the driving subcircuit 122 through the second light emitting control subcircuit 124, and the second electrode 135 (here, the cathode) of the light emitting element 120 is connected to the second voltage terminal VSS to receive a second power supply voltage. For example, the second voltage terminal may be grounded, that is, VSS may be 0V.

[0073] For example, the second light emitting control subcircuit 124 can be implemented as a fifth transistor T5. The gate of the fifth transistor T5 is connected to the second light emitting control line (the second light emitting control terminal EM2) to receive the second light emitting control signal, the first electrode of the fifth transistor T5 is connected to the second terminal 133 (the third node N3) of the driving subcircuit 122, and the second electrode of the fifth transistor T5 is connected to the first terminal 134 (the fourth node N4) of the light emitting element 120.

[0074] For example, the reset circuit 129 may include a first reset circuit configured to apply a first reset voltage Vini1 to the first node N1 in response to a first reset signal Rst1, and a second reset circuit configured to apply a second reset voltage Vini2 to the fourth node N4 in response to a second reset signal Rst2. Figure 1C As shown, the first reset circuit is implemented as a sixth transistor T6, and the second reset circuit is implemented as a seventh transistor T7. The gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset signal Rst1, the first electrode of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1, and the second electrode of the sixth transistor T6 is configured to be connected to the first node N1. The gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset signal Rst2, the first electrode of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2, and the second electrode of the seventh transistor T7 is configured to be connected to the fourth node N4.

[0075] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are described by taking thin film transistors as examples. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0076] Figure 2A schematic diagram of a display substrate 20 provided for at least one embodiment of the present disclosure. The display substrate 20 includes a base substrate 101, and a plurality of sub-pixels 100 are located on the base substrate 101. The pixel circuits of the plurality of sub-pixels 100 are arranged as a pixel circuit array, the column direction of the pixel circuit array is a first direction D1, the row direction is a second direction D2, and the first direction D1 intersects with the second direction D2, for example, being orthogonal. In some embodiments, the first direction D1 may also be a row direction, and the second direction D2 may also be a column direction. In some embodiments, the pixel circuits of each sub-pixel may have exactly the same structure except for the connection structure with the light-emitting element, that is, the pixel circuits are repeatedly arranged in the row and column directions, and the connection structures of different sub-pixels with the light-emitting element may be different according to the arrangement shape and position of the electrodes of the light-emitting structure of each sub-pixel. In some embodiments, the general framework of the pixel circuits of different color sub-pixels, such as the shapes and positions of each signal line, are basically the same, and the relative positional relationship of each transistor is also basically the same, but the width and shape of some signal lines or connecting lines, or the channel size and shape of some transistors, or the connecting lines or via positions used to connect to the light-emitting elements of different sub-pixels may be different and can be adjusted according to each layout structure and sub-pixel arrangement. Figure 2 2 exemplarily shows four directly adjacent sub-pixels in a row of sub-pixels (ie, a first sub-pixel 100a, a second sub-pixel 100b, a third sub-pixel 100c, and a fourth sub-pixel 100d), but the embodiments of the present disclosure are not limited to this layout.

[0077] Figure 3A Corresponds to Figure 2 The semiconductor layer 102 and the first conductive layer (gate layer) 201 of the transistors T1-T7 in the four sub-pixels 100 are schematically shown. Figure 3B exist Figure 3A A second conductive layer 202 is also shown on the basis of Figure 3C exist Figure 3B A third conductive layer 203 is also shown on the basis of Figure 3D exist Figure 3C The fourth conductive layer 204 is also shown on the basis of FIG. It should be noted that the figure only schematically shows the corresponding structure of four adjacent sub-pixels in a row of sub-pixels, but this should not be used as a limitation of the present disclosure. The semiconductor layer 102, the first conductive layer 201, the second conductive layer 202, the third conductive layer 203, and the fourth conductive layer 204 are sequentially arranged on the base substrate 101 to form a Figure 2 The structure of the display substrate is shown.

[0078] For the convenience of explanation, in the following description, Tng, Tns, Tnd, and Tna are used to represent the gate, the first electrode, the second electrode, and the active layer of the nth transistor Tn, respectively, where n is 1-7.

[0079] It should be noted that the “same-layer arrangement” referred to in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process, and their materials may be the same or different. The “integrated structure” in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process and connected to each other, and their materials may be the same or different.

[0080] For example, Figure 3A As shown, the first conductive layer 201 includes the gate of each transistor and some scan lines and control lines. Figure 3A The area where each sub-pixel 100 is located is shown by a large dotted line frame, and the gates T1g-T7g of the first to seventh transistors T1-T7 in one sub-pixel 100 are shown by a small dotted line frame.

[0081] The semiconductor layer 102 includes active layers T1a-T7a of the first to seventh transistors T1-T7. Figure 3A As shown, the active layers T1a-T7a of the first to seventh transistors T1-T7 are connected to each other as an integrated structure. For example, the semiconductor layers 20 in each column of sub-pixels are connected to each other as an integrated structure, and the semiconductor layers in two adjacent columns of sub-pixels are spaced from each other.

[0082] For example, Figure 3A As shown, the first conductive layer 104 includes gates T1g-T7g of the first to seventh transistors T1-T7. For example, the third transistor T3 and the sixth transistor T6 adopt a double-gate structure, which can improve the gate control capability of the transistors and reduce leakage current.

[0083] For example, the first conductive layer 104 further includes a plurality of mutually insulated scan lines 210, a plurality of reset control lines 220 and a plurality of light emitting control lines 230. For example, each row of sub-pixels is connected to a scan line 210, a reset control line 220 and a light emitting control line 230 respectively.

[0084] The scan line 210 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or is an integrated structure) to provide a first scan signal Ga1, the reset control line 220 is electrically connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels to provide a first reset signal Rst1, and the light-emitting control line 230 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide a first light-emitting control signal EM1.

[0085] For example, Figure 3AAs shown, the scan line 210 is also electrically connected to the gate of the third transistor T3 to provide a second scan signal Ga2, that is, the first scan signal Ga1 and the second scan signal Ga2 can be the same signal; the light-emitting control line 230 is also electrically connected to the gate of the fifth transistor T5 to provide a second light-emitting control signal EM2, that is, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are the same signal.

[0086] For example, Figure 3A As shown, the gate of the seventh transistor T7 of the pixel circuit in this row is electrically connected to the reset control line 220 corresponding to the pixel circuit in the next row (i.e., the pixel circuit row where the scan lines that are sequentially turned on after the scan lines in this row are located according to the scan order of the scan lines) to receive the second reset signal Rst2.

[0087] For example, from Figure 3A It can be seen that the gate line 11 that divides the pixel area in the column direction (first direction D1) can be the reset control line 220 or the light control line 230, and the area of ​​each pixel circuit includes a reset control line 220, a light control line 230 and a part of a scan line 210.

[0088] For example, Figure 3A As shown, the display substrate 20 adopts a self-alignment process and uses the first conductive layer 201 as a mask to perform conductorization treatment (such as doping treatment) on the semiconductor layer 102, so that the portion of the semiconductor layer 102 not covered by the first conductive layer 201 is conductorized, so that the portion of the active layer of each transistor located on both sides of the channel region is conductorized to form the first electrode and the second electrode of the transistor respectively.

[0089] For example, Figure 3B As shown, the second conductive layer 202 includes a first capacitor electrode Ca. The first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in a direction perpendicular to the substrate 101 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the second capacitor electrode Cb of the storage capacitor Cst. For example, the first capacitor electrode Ca includes a via 301, and the via 301 exposes at least a portion of the gate T1g of the first transistor T1, so that the gate T1g is electrically connected to other structures.

[0090] For example, the second conductive layer 202 may further include a plurality of reset voltage lines 240, which are connected one-to-one with a plurality of rows of sub-pixels. The reset voltage line 240 is electrically connected to the first electrode of the sixth transistor T6 in a corresponding row of sub-pixels to provide a first reset voltage Vinit1.

[0091] For example, Figure 3BAs shown, the first electrode of the seventh transistor T7 in the current row of sub-pixels is electrically connected to the reset voltage line 240 corresponding to the next row of sub-pixels to receive the second reset voltage Vinit2.

[0092] For example, Figure 3B As shown, the second conductive layer 202 may further include a shielding electrode 221, which overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101, thereby protecting the signal in the first electrode T2s of the second transistor T2 from interference from other signals. Since the first electrode T2s of the second transistor T2 is configured to receive the data signal Vd, and the data signal Vd determines the display grayscale of the sub-pixel, the shielding electrode 221 improves the stability of the data signal, thereby improving the display performance.

[0093] For example, Figure 3C As shown, the third conductive layer 203 includes a plurality of first power lines 250 extending along the first direction D1. For example, the plurality of first power lines 250 are electrically connected to a plurality of columns of sub-pixels one by one to provide a first power supply voltage VDD. The first power line 250 is electrically connected to the first capacitor electrode Ca in the corresponding column of sub-pixels through the via 302, and is electrically connected to the first electrode of the fourth transistor T4 through the via 303. For example, the first power line 250 is also electrically connected to the shielding electrode 221 through the via 304, so that the shielding electrode 221 has a fixed potential, thereby improving the shielding ability of the shielding electrode.

[0094] For example, the third conductive layer 203 further includes the plurality of data lines 12. The plurality of data lines 12 are electrically connected to the plurality of columns of sub-pixels one by one to provide data signals. For example, the data line 12 is electrically connected to the first electrode T2s of the second transistor T2 in the corresponding column of sub-pixels through the via 305 to provide the data signal.

[0095] Specifically, considering the uniformity and reliability of process margin, the vias are usually arranged in the row and column directions, the via 304 and the via 305 are approximately located on the same straight line in the row direction, and the via 304 is located on the side of the connection via 305 between the data line 12 and the first electrode T2s of the second transistor T2 away from the data line 12. For example, the via 305 is located at the position where the data line overlaps with the first electrode T2s of the second transistor T2 (for example, the end of the first electrode T2s of the second transistor T2, that is, the end of the semiconductor layer 102 on the left side), and the via 304 is located at the position covered by the first power line 250.

[0096] In some embodiments, the data line 12 is located on the left side of the first power line 250, and extends in the column direction with the first power line 250. The first shielding electrode 221 extends downward from the position covering the via 304 and extends to the left side at a position not exceeding the scanning line and covers part of the first electrode T2s of the second transistor T2. The shape of the first shielding electrode 221 is roughly an L-shaped left-right mirror pattern. It should be noted that in this embodiment, the left side refers to the side where the data line is relative to the first power line. For example, the boundary of the area of ​​a pixel circuit in the row direction is roughly the data line of a pixel circuit and the data line of the next pixel circuit in the same row (for example, the right adjacent), that is, the part between two adjacent data lines and the data line of the pixel circuit constitute the range of the pixel circuit in the row direction. In other embodiments, the first power line or the reset signal line, etc., are used as the boundary of the pixel circuit division, and are designed as needed.

[0097] For example, Figure 3C As shown, the third conductive layer 203 further includes a connecting electrode 231, one end of which is electrically connected to the gate T1g of the first transistor T1, i.e., the second capacitor electrode Cb, through the via 301 in the first capacitor electrode Ca and the via 401 in the insulating layer, and the other end is electrically connected to the first electrode of the third transistor T3 through the via 402, thereby electrically connecting the second capacitor electrode Cb to the first electrode T3s of the third transistor T3. For example, the via 401 penetrates the second insulating layer 104 and the second insulating layer 105, and the via 402 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105 (refer to Figure 5 ).

[0098] For example, Figure 3C As shown, the third conductive layer 203 further includes a connecting electrode 232, one end of which is electrically connected to the reset voltage line through a via 403, and the other end of which is electrically connected to the sixth transistor T6 through a via 404, so that the first electrode T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 240. For example, the via 403 penetrates the third insulating layer 105, and the via 404 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105 (refer to Figure 5 ).

[0099] For example, Figure 3C As shown, the third conductive layer 203 further includes a connecting electrode 233, which is electrically connected to the second electrode T5d of the fifth transistor T5 through a via hole 405, and is used to electrically connect the second electrode T5d of the fifth transistor T5 to the first electrode 134 of the light-emitting element. For example, the via hole 405 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105 (refer to Figure 5). This will be explained in detail later.

[0100] For example, Figure 3D As shown, the fourth conductive layer 204 includes a second power line 260, which extends along the second direction D2 and electrically connects the plurality of first power lines 250, thereby forming a meshed power line structure. This structure helps to reduce the resistance on the power line, thereby reducing the voltage drop of the power line, and helps to evenly transmit the first power voltage to each sub-pixel of the display substrate.

[0101] For example, the fourth conductive layer 204 further includes a plurality of third power lines 270, the third power lines 270 extending along the first direction D1 and electrically connected to the plurality of first power lines 250 in a one-to-one correspondence. Figure 3D As shown, the third power line 270 and the corresponding first power line 250 at least partially overlap each other in a direction perpendicular to the base substrate 101, and are electrically connected to each other through the via 306. For example, a via 306 is provided for each sub-pixel, so that each third power line 270 forms a parallel structure with the corresponding first power line 250, which helps to reduce the resistance of the power line. In some embodiments, the first power line 250 located in the third conductive layer can be widened or narrowed at some positions in order to avoid certain structures such as vias or connecting lines, or to make the upper structure flat. In some embodiments, the third power line 270 located in the fourth conductive layer can also be widened or narrowed at some positions in order to avoid certain structures such as vias or connecting lines, or to make the upper structure flat. In this way, the third power line 270 and the corresponding first power line 250 in the direction perpendicular to the base substrate 101 will also have some positions that cannot be completely overlapped.

[0102] For example, the second power line 260 and the third power line 270 are electrically connected to each other or are integrated into one structure, so that the plurality of first power lines 250 , the plurality of second power lines 260 and the plurality of third power lines 270 form a mesh power line structure.

[0103] For example, the fourth conductive layer 204 further includes a connection electrode 234 insulated from the third power line 270, and the connection electrode 234 is electrically connected to the connection electrode 233 (an example of the second connection electrode in the embodiment of the present disclosure) through a via 307 (an example of the second via hole in the embodiment of the present disclosure), so as to electrically connect the second electrode T5d of the fifth transistor T5 to the first electrode 134 of the light-emitting element. For example, the connection electrode 234 at least partially overlaps with the connection electrode 233 in a direction perpendicular to the base substrate 101.

[0104] Figure 4 exist Figure 3DA fifth conductive layer 205 is also shown on the basis of FIG. 1 , and the fifth conductive layer 205 includes the first electrode 134 of the light emitting element 120 . Figure 5 Shows Figure 4 Cross-sectional view along section line AA'.

[0105] like Figure 5 As shown, the semiconductor layer 102, the first insulating layer 103, the first conductive layer 201, the second insulating layer 104, the second conductive layer 202, the third insulating layer 105, the third conductive layer 203, the fourth insulating layer 106, the fourth conductive layer 204, the fifth insulating layer 107, and the fifth conductive layer 205 are sequentially arranged on the base substrate 101, so as to form a Figure 4 The structure of the display substrate is shown.

[0106] Combination Figure 4 and Figure 5 As shown, the first electrode 134 may include a main body 141 and a connecting portion 142. The main body 141 is mainly used to drive the light-emitting layer to emit light. The orthographic projection of the main body 141 on the base substrate 101 covers the orthographic projection of the opening area 600 of the sub-pixel to which the first electrode belongs on the base substrate. The connecting portion 142 is mainly used to connect with the pixel circuit. Figure 4 As shown, the second power line 260 does not overlap with each first electrode 134 in a direction perpendicular to the base substrate 101. This arrangement can prevent the first electrode 134 of the light-emitting element from being uneven due to overlapping with the second power line 260, resulting in display problems such as color deviation. A pixel defining layer is formed on the first electrode 134, and an opening area 600 is formed on the pixel defining layer. The opening area 600 exposes at least a portion of the main body 141 of the first electrode 134 and defines the light-emitting area (opening area) of each corresponding sub-pixel. The light-emitting layer of the light-emitting element 120 is at least formed in the opening area of ​​the pixel defining layer. The flatness of the first electrode 134 will directly affect the uniformity of the light emission of the light-emitting layer, thereby affecting the display effect. For example, the second power line 260 can be a curved structure to adapt to the pattern of the first electrode 134, such as a broken line or a wavy line shape. For example, two adjacent second power lines 260 define a row of sub-pixels 100. For example, as Figure 4 As shown, the second power line 260 includes a first portion 261 and a second portion 262 that are alternately connected, the extension directions of the first portions 261 are parallel to each other and parallel to the second direction D2, and the extension direction of the second portion 262 intersects both the first direction D1 and the second direction D2. For example, the main body 141 of the first electrode 134 is in the shape of a quadrilateral, for example, each first portion 261 is arranged corresponding to a vertex of the main body 141 of a first electrode 134, and the second portion 262 adjacent to the first portion 261 is arranged parallel to one side of the main body 141.

[0107] Figure 3E Shows Figure 3D Section view along section line C-C'. Figure 3E As shown, the first part 261 of the second power line 260 overlaps with the reset control line 220 in a direction perpendicular to the base substrate 101; the second part 262 overlaps with a data line 12 in a direction perpendicular to the base substrate 101, and the data line 12 is electrically connected to a column of pixel circuits corresponding to the second part 262 to provide the data signal.

[0108] Figure 4 The first electrodes 134 a , 134 b , 134 c and 134 d of the four adjacent sub-pixels are shown. For example, the first sub-pixel 100 a , the second sub-pixel 100 b , the third sub-pixel 100 c and the fourth sub-pixel 100 d constitute a repeating unit of the display substrate 20 .

[0109] For example, in each repeating unit, the color of the light emitted by the light-emitting element of the second sub-pixel 100b is the same as the color of the light emitted by the light-emitting element of the fourth sub-pixel 100d, that is, the second sub-pixel 100b and the fourth sub-pixel 100d are sub-pixels of the same color. For example, the second sub-pixel 100b and the fourth sub-pixel 100d are sensitive color sub-pixels. When the display substrate 20 adopts a red, green, and blue (RGB) display mode, the above-mentioned sensitive color is green, that is, the second sub-pixel 100b and the fourth sub-pixel 100d are both green sub-pixels. For example, the first sub-pixel 100a can be a red sub-pixel, and the third sub-pixel 100c can be a blue sub-pixel.

[0110] For example, in each repeating unit, the first sub-pixel 100a and the third sub-pixel 100c are alternately arranged in the row direction, and the second sub-pixel 100b and the fourth sub-pixel 100d are respectively located between the first sub-pixel 100a and the third sub-pixel 100c in adjacent rows, and between the third sub-pixel 100c and the first sub-pixel 100a in the next repeating unit.

[0111] For example, in each repeating unit, the first sub-pixel 100a and the third sub-pixel 100c are alternately arranged in the column direction. In the repeating units of two adjacent rows, the two first sub-pixels 100a and the two third sub-pixels 100c located in two rows and two columns form a 2*2 matrix, in which the two first sub-pixels 100a are located at one diagonal position of the matrix, and the two third sub-pixels 100c are located at another diagonal position of the matrix, and the two first sub-pixels 100a and the two third sub-pixels 100c surround a second sub-pixel 100b or a fourth sub-pixel 100d. The 2*2 matrix is ​​repeated in the row direction and the column direction in a manner of sharing a column or a row of sub-pixels.

[0112] For example, four sub-pixels in each repeating unit may form two virtual pixels, and the first sub-pixel 100a and the third sub-pixel 100c in the repeating unit are shared by the two virtual pixels. Figure 4 As shown, the first sub-pixel 100a and the second sub-pixel 100b located on the right and adjacent to it constitute a virtual pixel, and the third sub-pixel 100c in the adjacent (right) virtual pixel is used to form a light-emitting pixel unit; the third sub-pixel 100c and the fourth sub-pixel 100d located on the right and adjacent to it constitute a virtual pixel, and the adjacent (right side not shown) first sub-pixel 100a is used to form a light-emitting pixel unit. The sub-pixels in the multiple repeating units form a pixel array, and in the row direction of the pixel array, the sub-pixel density is 1.5 times the virtual pixel density, and in the column direction of the pixel array, the sub-pixel density is 1.5 times the virtual pixel density.

[0113] For example, the second sub-pixel 100 b and the fourth sub-pixel 100 d belong to two virtual pixels respectively.

[0114] It should be noted that, first, since the first sub-pixel 100a and the third sub-pixel 100c are shared by two adjacent virtual pixels, the boundary of each virtual pixel is also very fuzzy, and therefore, the embodiment of the present disclosure does not limit the shape of each virtual pixel. Second, the division of virtual pixels is related to the driving mode, and the specific division method of virtual pixels can be determined according to the actual driving mode, and the present disclosure does not make specific restrictions on this.

[0115] For example, the shapes and sizes of the multiple opening areas corresponding to the sub-pixel 100 can be changed according to the luminous efficiency and service life of the luminescent materials emitting light of different colors. For example, the opening area corresponding to the luminescent material with a shorter luminous life can be set larger to improve the stability of luminescence. For example, the size of the opening area of ​​the blue sub-pixel, the red sub-pixel, and the green sub-pixel can be reduced in sequence. Since the opening area is set on the first electrode 134, accordingly, Figure 4 As shown, the areas of the first electrodes 134a, 121b, 121c and 121d of the first subpixel 100a, the second subpixel 100b, the third subpixel 100c and the fourth subpixel 100d decrease sequentially.

[0116] For each row of sub-pixels, the main body of the first electrode of the light-emitting element of the sub-pixel is arranged along the second direction and staggered along the first direction. For example, Figure 4As shown, a first electrode 134b / 134d of a green sub-pixel with the smallest area is arranged between the first electrode 134a of each adjacent red sub-pixel (first sub-pixel 100a) and the first electrode 134c of the blue sub-pixel (third sub-pixel 100c), and the main body of the first electrode 134b / 134d is staggered with the main body of the first electrodes 134a and 134c along the second direction. For example, the main body of the first electrodes 134a and 134c overlaps with the first capacitor electrode Ca in the sub-pixels to which they belong in a direction perpendicular to the base substrate, and the main body of the first electrode 134b / 134d does not overlap with the first capacitor electrode Ca in the sub-pixels to which they belong in a direction perpendicular to the base substrate. This can improve the layout space utilization, thereby improving the pixel density. Figure 4 As shown, the main body 141 of each first electrode extends in a Z-shape along the second direction D2.

[0117] For example, for a repeating unit row, the main portion of the first electrode 134 of the first sub-pixel 100a and the third sub-pixel 100c is, for example, a quadrilateral, and is arranged in the row and column directions with the vertex angles opposite, and the second power line 260 extends along the contour of the first electrode 134 of the first sub-pixel 100a and the third sub-pixel 100c on one side away from the second sub-pixel 100b and the fourth sub-pixel 100d. For example, the second sub-pixel 100b and the fourth sub-pixel 100d are located between two corresponding adjacent sub-pixels in the sub-pixel row formed by the first sub-pixel 100a and the third sub-pixel 100c in the row direction, i.e., the D2 direction, and the main body of the first electrode 134 of the second sub-pixel 100b and the fourth sub-pixel 100d is, for example, a quadrilateral, and the main body of the first electrode 134 of each adjacent sub-pixel has relative and parallel sides, and the second power line 260 extends along the contour of the first electrode 134 of the first sub-pixel 100a and the third sub-pixel 100c on a side away from the second sub-pixel 100b and the fourth sub-pixel 100d, and also extends along the contour of the first electrode 134 of the second sub-pixel 100b and the fourth sub-pixel 100d on a side away from the first sub-pixel 100a and the third sub-pixel 100c. For example, the second power line 260 extends along the gap between the first electrode 134 of the sub-pixel row formed by the first sub-pixel 100a and the third sub-pixel 100c and the first electrode 134 of the sub-pixel row formed by the second sub-pixel 100b and the fourth sub-pixel 100d, forming a wave shape, and forms a crest at the electrode vertex angle position of the main body of the first electrode 134 corresponding to the first sub-pixel 100a and the third sub-pixel 100c, and forms a trough at the electrode vertex angle position of the main body of the first electrode 134 corresponding to the second sub-pixel 100b and the fourth sub-pixel 100d. The direction close to the previous row is the protruding direction of the crest, and the direction close to the next row is the protruding direction of the trough. For example, Figure 4 and Figure 5 As shown, the connection portion 142 of the first electrode 134 of each sub-pixel is electrically connected to the connection electrode 234 (an example of the first connection electrode in the embodiment of the present disclosure) through the via hole 308 (an example of the first via hole in the embodiment of the present disclosure), so that the second electrode T5d of the fifth transistor T5 is electrically connected to the first electrode 134 of the light-emitting element 120. For example, the connection portion 142 of the first electrode 134 at least partially overlaps with the connection electrode 234 in a direction perpendicular to the base substrate 101.

[0118] For example, the opening area 600 does not overlap with the connection portion 142 of the first electrode 134 in a direction perpendicular to the base substrate 101, and the vias 307 and 308 overlap with the connection portion 142 of the first electrode 134 in a direction perpendicular to the base substrate 101, thereby preventing the vias 308 and 307 from affecting the flatness of the light-emitting layer in the opening area and thus affecting the light-emitting quality. In some embodiments, the via 307 may partially overlap with the opening area, because the layer where the via 307 is located and the layer where the first electrode 134 is located are separated by at least the layer where the connecting electrode 234 is located, and the insulating layer where the via 308 is located, so the via 307 has a smaller effect on the flatness of the opening area than the via 308.

[0119] For example, for the first sub-pixel 100a and the third sub-pixel 100c, their corresponding fourth connecting electrodes are located on the side of their first electrodes 134 away from the reset control line 220 in the pixel circuit, and correspondingly, the connecting electrode of the first electrode 134 is also located on the side of the first electrode 134 away from the reset control line 220 in the pixel circuit, and the connecting electrode of the first electrode 134 at least partially overlaps with the corresponding fourth connecting electrode.

[0120] For example, for the second sub-pixel 100b and the fourth sub-pixel 100d, their corresponding fourth connecting electrodes are located on the side of their first electrodes 134 close to the reset control line 220 in the pixel circuit, and correspondingly, the connecting electrode of the first electrode 134 is also located on the side of the first electrode 134 away from the reset control line 220 in the pixel circuit, and the connecting electrode of the first electrode 134 at least partially overlaps with the corresponding fourth connecting electrode.

[0121] For example, Figure 5As shown, the display substrate 20 further includes a pixel defining layer 108 located on the first electrode of the light emitting element. An opening is formed in the pixel defining layer 108 to define an opening area 600 of the display substrate. The light emitting layer 136 is at least formed in the opening (the light emitting layer 136 may also cover part of the pixel defining layer), and the second electrode 135 is formed on the light emitting layer 136 to form the light emitting element 120. For example, the second electrode 135 is a common electrode, which is arranged in the display substrate 20 on its entire surface. For example, the first electrode is an anode of the light emitting element, and the second electrode is a cathode of the light emitting element.

[0122] For example, combined with Figure 4 and Figure 5 As shown, Figure 4 As shown, for each pixel circuit, the orthographic projections of the via hole 307 and the via hole 308 on the substrate 101 are both located within the orthographic projection of the third connection electrode 234 on the substrate. For example, the via hole 307 and the via hole 308 are arranged side by side in the D1 direction, and their center lines along the first direction D1 are roughly coincident. In the direction parallel to the surface of the substrate 101, the via hole 308 is further away from the main body 141 of the first electrode 134 than the via hole 307, that is, the opening area 600 of the sub-pixel (for example, the area of ​​the first electrode 134 is larger than the area of ​​the corresponding opening area 600, and the opening area 600 is roughly located in the middle area of ​​the first electrode 134), that is, the orthographic projection of the via hole 308 on the substrate 101 is further away from the orthographic projection of the opening area 600 on the substrate than the orthographic projection of the via hole 307 on the substrate 101. This is because in the direction perpendicular to the base substrate 101, the insulating layer where the via 308 is located (for example, the second flat layer) is closer to the main body 142 of the first electrode 134 than the insulating layer where the via 307 is located (for example, the first flat layer). Therefore, the via 308 has a greater impact on the flatness of the first electrode 134. Disposing the via 308 farther away from the opening area or the main body of the first electrode 134 (on the surface parallel to the base substrate) can reduce the impact of the via on the flatness of the light-emitting layer 136 in the opening area, thereby improving the performance of the light-emitting element.

[0123] For example, in a row of repeating units, the vias 307 and 308 in the pixel circuits of the first sub-pixel 100a and the third sub-pixel 100c are both located on the side of their corresponding first electrodes 134 away from the reset control line 220 in the pixel circuit, and the corresponding fourth connecting electrodes of the second sub-pixel 100b and the fourth sub-pixel 100d are located on the side of their first electrodes 134 close to the reset control line 220 in the pixel circuit, that is, in a row of repeating units, the vias 307 and 308 in the pixel circuits of each sub-pixel are both located between the row formed by the first sub-pixel 100a and the third sub-pixel 100c, and the row formed by the second sub-pixel 100b and the fourth sub-pixel 100d.

[0124] For example, in a repeating unit, the shapes of the fourth connection electrodes in the pixel circuits of the first sub-pixel 100a, the third sub-pixel 100c, the second sub-pixel 100b, and the fourth sub-pixel 100d are substantially the same, and are substantially arranged on the same straight line parallel to the D2 direction. For example, the vias 307 and the vias 308 located within the projection of the fourth connection electrode are substantially non-overlapping or incompletely overlapping, so as to avoid the vias being stacked in the direction perpendicular to the substrate, resulting in poor connection, disconnection, or unevenness at the positions where the vias are located. For example, the vias 307 of the first sub-pixel 100a and the third sub-pixel 100c are substantially located on the same straight line as the vias 308 of the second sub-pixel 100b and the fourth sub-pixel 100d, and the vias 308 of the first sub-pixel 100a and the third sub-pixel 100c are substantially located on the same straight line as the vias 307 of the second sub-pixel 100b and the fourth sub-pixel 100d.

[0125] For example, Figure 5 As shown, the opening area 600 does not overlap with the orthographic projection of the via hole 308 on the base substrate 101. For example, the opening area 600 does not overlap with the orthographic projection of the connecting electrode 234 on the base substrate 101. This helps to improve the flatness of the light-emitting layer 136 and thus improve the light-emitting efficiency.

[0126] For example, the base substrate 101 can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc.

[0127] For example, the material of the semiconductor layer 102 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.).

[0128] For example, the materials of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by combinations of the above metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0129] For example, the light emitting element 120 is a top emission structure, the first electrode 134 is reflective and the second electrode 135 is transmissive or semi-transmissive. For example, the first electrode 134 is a material with a high work function to act as an anode, such as an ITO / Ag / ITO stacked structure; the second electrode 135 is a material with a low work function to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0130] For example, the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105 are, for example, inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxide, or aluminum oxide, titanium nitride, or other insulating materials including metal nitride oxides. For example, the fourth insulating layer 106, the fifth insulating layer 107, and the pixel defining layer 108 are respectively organic insulating materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), or other organic insulating materials. For example, the fourth insulating layer 106 and the fifth insulating layer 107 are planarization layers.

[0131] like Figure 2 As shown, the pixel circuit of the first sub-pixel 100a is electrically connected to the first data line 12a to receive the data signal Vd, and the pixel circuit of the second sub-pixel 100b is electrically connected to the second data line 12b to receive the data signal Vd. For example, the second data line 12b is located between the pixel circuit of the first sub-pixel 100a and the pixel circuit of the second sub-pixel 100b.

[0132] like Figure 2 As shown in FIG. 1 , the first capacitor electrode Caa in the first sub-pixel 100a and the first capacitor electrode Cab in the second sub-pixel 100b are arranged at intervals from each other, that is, the first capacitor electrodes Ca in the first sub-pixel 100a and the first capacitor electrodes Ca in the second sub-pixel 100b are disconnected from each other in the conductive layer where they are located. This arrangement can reduce the overlap between adjacent first capacitor electrodes Ca and other signal lines caused by connection, thereby reducing parasitic capacitance.

[0133] For example, the first capacitor electrode Ca in each sub-pixel 100 has substantially the same area and shape.

[0134] For example, the relative positions of the first capacitor electrodes Ca in each sub-pixel 100 are the same. For example, the first capacitor electrodes Ca in each row of sub-pixels 100 are arranged in a straight line along the second direction D2.

[0135] For example, the first capacitor electrode Ca in each sub-pixel 100 is an island structure in the conductive layer where it is located, that is, it is not electrically connected to other structures in the conductive layer where it is located.

[0136] For example, Figure 6As shown, there is a junction where the second electrode T3d of the third transistor T3, the second electrode T1d of the first transistor T1, and the first electrode T1s of the fifth transistor T5 in the pixel circuit of the first sub-pixel 100a are connected to each other between adjacent first capacitor electrodes Ca. Disconnecting the first capacitor electrode Caa in the first sub-pixel 100a and the first capacitor electrode Cab in the second sub-pixel 100b from each other can prevent the first capacitor electrode Cab in the second sub-pixel 100b from overlapping with the junction and generating parasitic capacitance, thereby causing adverse effects on the signal at the junction. For example, the orthographic projections of the second electrode T3d of the third transistor T3, the second electrode T1d of the first transistor T1, and the first electrode T1s of the fifth transistor T5 in the first sub-pixel 100a on the direction perpendicular to the substrate do not overlap with the first capacitor electrode Cab in the second sub-pixel 100b in the direction perpendicular to the substrate 101.

[0137] For example, the range of the first capacitor electrode Ca in the sub-pixel 100 does not exceed the pixel area of ​​the sub-pixel (the area where the pixel circuit is located), that is, the first capacitor electrode Cab of the sub-pixel 100 does not extend into the pixel area of ​​the adjacent sub-pixel and overlap with the structure in the sub-pixel to cause crosstalk.

[0138] For example, Figure 6 As shown, there is a second data line 12b between the first capacitor electrodes Ca of the adjacent first sub-pixel 100a and the second sub-pixel 100b, and the projections of the first capacitor electrodes Caa of the first sub-pixel 100a and the first capacitor electrodes Cab of the second sub-pixel 100b on the substrate do not overlap. Disconnecting the first capacitor electrode Caa in the first sub-pixel 100a and the first capacitor electrode Cab in the second sub-pixel 100b from each other can prevent the first capacitor electrode from overlapping with the second data line 12b to generate parasitic capacitance, which will have an adverse effect on the transmission of the data signal on the data line, such as causing a delay in the data signal. On the other hand, since the data signal Vd is usually a high-frequency signal, and the first capacitor electrode Ca transmits the first power supply voltage VDD, due to the existence of parasitic capacitance, the first power supply voltage is prone to sudden changes with the sudden changes of the data signal Vd, and the resistance-capacitance load between the first capacitor electrode Ca and the data line is too large, resulting in the first power supply voltage not being able to recover in a short time after the sudden change. According to the formula of the saturation current in the first transistor T1 during the light-emitting stage, Id=k / 2*(Vd-VDD) 2 It can be known that the fluctuation of the first power supply voltage VDD causes the fluctuation of the driving current, thereby causing unstable luminous brightness. Therefore, disconnecting the first capacitor electrode Caa in the first sub-pixel 100a and the first capacitor electrode Cab in the second sub-pixel 100b from each other can also help improve the stability of the luminous element.

[0139] The inventors of the present disclosure have found that due to the overlap between the signal lines, a parasitic capacitance is generated between the data line 12 and the second capacitor electrode Cb of the storage capacitor Cst, which affects the stability of the storage capacitor Cst. Since the storage capacitor Cst is configured to store the data signal Vd and the information related to the threshold voltage of the driving subcircuit, and is configured to use the stored information to control the driving subcircuit 122 during the light-emitting stage, so that the output of the driving subcircuit 122 is compensated, the stability of the voltage (stored information) across the storage capacitor Cst will affect the stability of the displayed grayscale, thereby affecting the quality of the displayed image.

[0140] Some other embodiments of the present disclosure further provide a display substrate, such as Figure 2 and Fig. 7A As shown, the first capacitor electrode Ca in at least one sub-pixel includes an extension portion 290 , and the extension portion 290 and the data line 12 connected to the sub-pixel overlap each other in a direction perpendicular to the base substrate 101 to provide a first capacitor C1 .

[0141] Due to the existence of the first capacitor C1, the fluctuation of the data signal in the data line 12 is coupled to the second capacitor electrode Cb of the storage capacitor Cst through the parasitic capacitance, and is also coupled to the first capacitor electrode Ca of the storage capacitor Cst through the first capacitor C1. This improves the stability of the information stored in the storage capacitor Cst and improves the display performance.

[0142] Fig. 7A Shows Figure 2 Sectional view along section line BB', Figure 7B The equivalent circuit diagram of the pixel circuit is shown in FIG. Figure 2 and Figure 7A-7B The data line 12 and the scan line 210 overlap in a direction perpendicular to the base substrate 101 to form a second capacitor C2 (an example of a first sub-capacitor in the embodiment of the present disclosure), and the connecting electrode 231 and the scan line 210 overlap in a direction perpendicular to the base substrate 101 to form a third capacitor C3 (an example of a second sub-capacitor in the embodiment of the present disclosure).

[0143] Since the connection electrode 231 is electrically connected to the second capacitor electrode Cb of the storage capacitor Cst, the second capacitor C2 and the third capacitor C3 are connected in series between the data line 12 and the second capacitor electrode Cb of the storage capacitor Cst, and the fluctuation of the data signal in the data line 12 is coupled to the second capacitor electrode Cb of the storage capacitor Cst through the second capacitor C2 and the third capacitor C3. Due to the existence of the first capacitor C1, the fluctuation of the data signal in the data line 12 is also coupled to the first capacitor electrode Ca of the storage capacitor Cst through the first capacitor C1. In this way, the stability of the information stored in the storage capacitor Cst is improved, and the display performance is improved.

[0144] For example, the capacitance of the first capacitor C1 is approximately equal to the capacitance of the second capacitor C2 and the third capacitor C3 connected in series, for example, the two are equal, that is, C1 = (C2*C3) / (C2+C3).

[0145] For example, the extension portion 290 extends (protrudes) from the main body of the first capacitor electrode Ca toward the direction of the overlapping data line 12. For example, the shape of the first capacitor electrode Ca is a convex shape facing the direction of the data line in the pixel circuit where it is located, that is, the first capacitor electrode Ca is a roughly rectangular electrode block, and there is a protrusion protruding toward the data line direction on the side close to the data line in the pixel circuit, and the protrusion is located in the approximate middle of the side, and there is a via hole inside the first capacitor electrode Ca.

[0146] For example, in this case, the first capacitor electrode Ca still does not exceed the pixel area where the sub-pixel is located, that is, the first capacitor electrode Cab of the pixel circuit does not extend into the pixel area of ​​the adjacent sub-pixel and overlap with the structure in the sub-pixel to cause crosstalk.

[0147] Figure 8 FIG. 4 shows a schematic diagram of the first capacitor electrode Ca. Figure 8 As shown, for example, the ratio of the area of ​​the extension portion 290 to the area of ​​the first capacitor electrode Ca is in the range of 1 / 10-1 / 3, for example, 1 / 5.

[0148] For example, in the first direction D1 , the ratio of the maximum dimension D2 of the extension portion 290 to the maximum dimension D1 of the first capacitor electrode is in the range of 1 / 4-1 / 2, for example, 1 / 3.

[0149] At least one embodiment of the present disclosure further provides a display panel, including any of the above display substrates 20. It should be noted that the above display substrate 20 provided in at least one embodiment of the present disclosure may include a light-emitting element 120, or may not include the light-emitting element 120, that is, the light-emitting element 120 may be formed in a panel factory after the display substrate 20 is completed. In the case where the display substrate 20 itself does not include the light-emitting element 120, the display panel provided in the embodiment of the present disclosure further includes the light-emitting element 120 in addition to the display substrate 20.

[0150] For example, the display panel is an OLED display panel, and the display substrate 20 included therein is an OLED display substrate. Fig. 9 As shown, for example, the display panel 30 also includes an encapsulation layer 801 and a cover plate 802 disposed on the display substrate 20, and the encapsulation layer 801 is configured to seal the light-emitting element on the display substrate 20 to prevent external moisture and oxygen from penetrating into the light-emitting element and the driving subcircuit and causing damage to the device. For example, the encapsulation layer 801 includes an organic film or a structure including an organic film and an inorganic film alternately stacked. For example, a water-absorbing layer (not shown) can also be disposed between the encapsulation layer 801 and the display substrate 20, configured to absorb residual water vapor or sol of the light-emitting element in the early production process. The cover plate 802 is, for example, a glass cover plate. For example, the cover plate 802 and the encapsulation layer 801 can be an integrated structure.

[0151] At least one embodiment of the present disclosure further provides a display device 40, such as Fig.10 As shown, the display device 40 includes any of the above-mentioned display substrates 20 or display panels 30. The display device in this embodiment can be: a display, an OLED panel, an OLED TV, an electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0152] The present disclosure also provides a method for manufacturing the display substrate 20. Figure 2 , Figure 3A-3E and Figure 4-Figure 5 The structure and manufacturing method of the display substrate provided in the embodiment of the present disclosure are described by way of example only, however, the embodiment of the present disclosure is not limited thereto.

[0153] In some examples, the manufacturing method includes the following steps S61-S70.

[0154] Step S61: forming a semiconductor material layer on the substrate, and performing a patterning process on the semiconductor material layer to form Figure 3AThe semiconductor layer 102 shown includes active layers T1a-T7a and doping region patterns (i.e., source regions and drain regions corresponding to the first to seventh transistors T1-T7) of the first to seventh transistors T1-T7 in each pixel area, and the active layer patterns and doping region patterns of each transistor in the same pixel area are integrally arranged.

[0155] It should be noted that the active layer may include an integrally formed low-temperature polysilicon layer, wherein the source region and the drain region may be made conductive by doping, etc. to achieve electrical connection of various structures. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel region includes a doping region pattern (i.e., a source region and a drain region) and an active layer pattern, and the active layers of different transistors are separated by doping structures.

[0156] Step S62: forming a first insulating layer 103 (for example, a transparent layer), for example, a gate insulating layer, on the semiconductor layer 102, and forming a plurality of first insulating layer vias on the first insulating layer for connection with the pattern of the subsequently formed third conductive layer 203. For example, corresponding first insulating layer vias are formed in the first insulating layer corresponding to the positions of the source region and the drain region in the semiconductor layer, that is, the first insulating layer vias overlap with the source region and the drain region in the semiconductor layer, respectively, so as to connect the source region and the drain region with the data line 12, the first power line 250, the connecting electrode 231, the connecting electrode 232, and the connecting electrode 233 in the third conductive layer, for example, vias 402, vias 405, vias 303, vias 305, etc., which penetrate the first insulating layer.

[0157] Step S63: forming a first conductive material layer on the first insulating layer, and performing a patterning process on the first conductive material layer to form Figure 3A The first conductive layer 201 shown forms a scan line 210, a reset control line 220 and a light emitting control line 230 that are insulated from each other and extend along the second direction. For example, for a row of pixel circuits, the corresponding reset control lines 220, scan lines 210 and light emitting control lines 230 are arranged in sequence in the first direction D1.

[0158] For example, the first conductive layer 201 further includes the gates T1g-T7g of the first to seventh transistors T1-T7. For example, the gate T6g of the sixth transistor T6 is an integrated structure with the reset control line 220, that is, a part of the reset control line 220 is used as the gate T6g of the sixth transistor T6; the gate T2g of the second transistor T2 is an integrated structure with the scan line 210, that is, a part of the scan line 210 is used as the gate T2g of the second transistor T2; the gate T4g of the fourth transistor T4 and the gate T5g of the fifth transistor T5 are both an integrated structure with the light emitting control line 230, that is, a part of the light emitting control line 230 is used as the gate T4g of the fourth transistor T4 and the gate T5g of the fifth transistor T5; the gate T7g of the seventh transistor T7 is an integrated structure with the reset control line 220 corresponding to the next row of pixel circuits. For example, the sixth transistor T6 and the third transistor T3 are both dual-gate structures, the two gates T6g of the sixth transistor T6 are both part of the reset control line 220, one gate of the third transistor T3 is part of the scan line 210, and the other gate of the third transistor T3 is a part that is integrally connected to the scan line 210 and protrudes toward the reset control line 220.

[0159] For example, the overlapped portion of the semiconductor layer 102 and the first conductive layer 201 in a direction perpendicular to the substrate defines active layers (channel regions) T1a-T7a of the first to seventh transistors T1-T7.

[0160] For example, in the direction D1, the gate of the second transistor (for example, a data writing transistor) T2, the gate of the third transistor (for example, a threshold compensation transistor) T3, the gate of the sixth transistor (for example, a first reset transistor) T6, and the gate of the seventh transistor (for example, a second reset transistor) T7 are all located on the first side of the gate of the first transistor (for example, a driving transistor) T1, and the gate of the fourth transistor (for example, a first light emission control transistor) T4 and the gate of the fifth transistor (for example, a second light emission control transistor) T5 are all located on the second side of the gate of the first transistor T1. In a plane parallel to the substrate, the first side of the gate of the first transistor T1 in the same pixel area can be the side of the gate T1g of the first transistor T1 close to the scan line 230, and the second side of the gate of the first transistor T1 can be the side of the gate of the first transistor T1 away from the scan line 230.

[0161] For example, in the second direction D2, the gate of the second transistor T2 and the gate of the fourth transistor T4 are both located on the third side of the gate of the first transistor T1, and the first gate of the third transistor T3 (the gate integrated with the scan line 210), the gate of the fifth transistor T5, and the gate of the seventh transistor T7 are all located on the fourth side of the gate of the first transistor T1. For example, the third side and the fourth side of the gate of the first transistor T1 in the same pixel area are the two sides of the gate of the first transistor T1 opposite to each other in the D2 direction. For example, the third side of the gate of the first transistor T1 in the same pixel area can be the left side of the gate of the first transistor T1, and the fourth side of the gate of the first transistor T1 can be the right side of the gate of the first transistor T1. The left side and the right side, for example, in the same pixel area, the data line 12 is on the left side of the first power line 250, and the first power line 250 is on the right side of the data line.

[0162] Step S64: Figure 3A As shown, a self-alignment process is adopted to perform conductorization treatment (e.g., doping treatment) on the semiconductor layer 102 using the first conductive layer 201 as a mask, so that the portion of the semiconductor layer 102 not covered by the first conductive layer 201 is conductorized, so that the portion of the semiconductor layer 102 located on both sides of the active layer of each transistor is conductorized to form the source region and the drain region of the first to seventh transistors T1-T7, that is, the first electrode (T1s-T7s) and the second electrode (T1d-T7d) of the first to seventh transistors T1-T7.

[0163] Step S65: forming a second insulating layer 104 (e.g., a transparent layer), e.g., a second gate insulating layer, on the first conductive layer 201. At least a second insulating layer via hole corresponding to the first insulating layer via hole is formed on the second insulating layer. For example, the corresponding via holes penetrating at least the first insulating layer and the second insulating layer include at least via hole 402, via hole 405, via hole 303, via hole 305, etc.

[0164] Step S66: forming a second conductive material layer on the second insulating layer 104 and performing a patterning process on the second conductive material layer to form Figure 3B The second conductive layer 202 shown forms a shielding electrode 221 , a first capacitor electrode Ca and a reset voltage line 240 extending along a first direction which are insulated from each other.

[0165] For example, the shielding electrode 221 overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101 so as to protect the signal in the first electrode T2s of the second transistor T2 from being interfered by other signals.

[0166] For example, the first capacitor electrode Ca at least partially overlaps the gate T1g of the first transistor T1 in a direction perpendicular to the substrate 101. The patterning process also forms a via hole 301 in the first capacitor electrode Ca, and the via hole 301 exposes at least a portion of the gate T1g of the first transistor T1.

[0167] Step S67: forming a third insulating layer 105 on the second conductive layer 202. The third insulating layer may be, for example, an interlayer insulating layer. Vias are formed in the third insulating layer for connecting to a third conductive layer formed subsequently. At least some of the vias correspond to the positions of the first insulating layer vias and the second insulating layer vias, and penetrate the first insulating layer, the second insulating layer, and the third insulating layer at the same time, such as via 402, via 405, via 303, and via 305.

[0168] Step S68: forming a third conductive material layer on the third insulating layer 105, and patterning the third conductive material layer to form Figure 3C The third conductive layer 203 shown forms the data line 12, the first power line 250, the connecting electrode 231, the connecting electrode 232 and the connecting electrode 233 which are insulated from each other. The data line 12 and the first power line 250 extend along the first direction D1.

[0169] For example, Figure 3C As shown, the data line 12 overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the substrate 101 and is electrically connected to the first electrode T2s of the second transistor T2 through a via 305. The via 305, for example, passes through the first insulation 103, the second insulation layer 104 and the third insulation layer 105.

[0170] For example, Figure 3C and Figure 5 As shown, the first power line 250 overlaps with the shielding electrode 221 in a direction perpendicular to the base substrate 101 and is electrically connected to the shielding electrode 221 through a via hole 304 . For example, the via hole 304 penetrates the third insulating layer 105 .

[0171] For example, Figure 3C As shown, the first power line 250 is electrically connected to the first capacitor electrode Ca in the corresponding column of sub-pixels through the via hole 302, and is electrically connected to the first electrode T4s of the fourth transistor T4 through the via hole 303. For example, the via hole 302 passes through the third insulating layer 105, and the via hole 303 passes through the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.

[0172] For example, Figure 3C and Figure 5As shown, one end of the connecting electrode 231 is electrically connected to the gate T1g of the first transistor T1, that is, the second capacitor electrode Cb, through the via hole 301 in the first capacitor electrode Ca and the via hole 401 in the insulating layer, and the other end is electrically connected to the first electrode of the third transistor T3 through the via hole 402, thereby electrically connecting the second capacitor electrode Cb to the first electrode T3s of the third transistor T3. For example, the via hole 401 penetrates the second insulating layer 104 and the third insulating layer 105, and the via hole 402 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.

[0173] For example, Figure 3C As shown, one end of the connection electrode 232 is electrically connected to the reset voltage line through the via 403, and the other end is electrically connected to the sixth transistor T6 through the via 404, so that the first electrode T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 240. For example, the via 403 penetrates the third insulating layer 105, and the via 404 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.

[0174] For example, Figure 3C and Figure 5 As shown, the connecting electrode 233 is electrically connected to the second electrode T5d of the fifth transistor T5 through the via 405, and is used to electrically connect the second electrode T5d of the fifth transistor T5 to the first electrode 134 of the light-emitting element. For example, the via 405 passes through the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.

[0175] Step S69: forming a fourth insulating layer 106 on the third conductive layer 203. A via hole for connecting to the subsequently formed fourth conductive layer is formed in the third insulating layer. In some embodiments, for example, the fourth insulating layer 106 includes a first flat layer. In other embodiments, for example, the fourth insulating layer 106 includes a passivation layer and a first flat layer, and the via hole formed in the fourth insulating layer needs to penetrate the passivation layer and the first flat layer. For example, the first flat layer is located on the side of the passivation layer away from the third conductive layer.

[0176] Step S70: forming a fourth conductive material layer on the fourth insulating layer 106, and performing a patterning process on the fourth conductive material layer to form Figure 3D The fourth conductive layer 204 shown forms a second power line 260 , a third power line 270 and a connecting electrode 234 . The second power line 260 and the third power line 270 are connected to each other and insulated from the connecting electrode 234 .

[0177] For example, Figure 3DAs shown, the plurality of third power lines 270 extend along the first direction D1 and are electrically connected to the plurality of first power lines 250 in a one-to-one correspondence through vias 306. For example, each third power line 270 overlaps with the corresponding first power line 250 in a direction perpendicular to the base substrate 101. For example, the via 306 penetrates the fourth insulating layer 106.

[0178] For example, Figure 3D As shown, the connection electrode 234 overlaps with the connection electrode 233 in a direction perpendicular to the base substrate 101 , and the third connection electrode 234 is electrically connected to the connection electrode 233 through a via hole 307 penetrating the fourth insulating layer 106 .

[0179] For example, refer to Figure 4 and Figure 5 The manufacturing method of the display substrate may further include forming a fifth insulating layer 107 on the fourth conductive layer 204, and forming a via hole in the fifth insulating layer 107 for connecting with a fifth conductive layer formed subsequently. For example, the fifth insulating layer 107 may be a second flat layer. The fifth insulating layer via hole is used, for example, to connect the drain of the first transistor and the first electrode of the light-emitting device. The fifth insulating layer via hole may overlap or may not overlap with the second electrode of the first transistor. In the case of no overlap, a connection line may be additionally provided in the third conductive layer for connection. The specific situation is related to the sub-pixel arrangement structure, such as the position and shape of the first electrode.

[0180] For example, the manufacturing method of the display substrate may further include forming a fifth conductive material layer on the fifth insulating layer 107, and patterning the fifth conductive material layer to form a fifth conductive layer 205, that is, forming a plurality of first electrodes 134 insulated from each other for forming light-emitting elements.

[0181] For example, each first electrode 134 includes a main body portion 141 and a connecting portion 142 , wherein the main body portion 141 is mainly used to drive the light-emitting layer to emit light, and the connecting portion 142 is mainly used to be electrically connected to the pixel circuit.

[0182] For example, Figure 5 As shown, the connecting portion 142 is electrically connected to the connecting electrode 234 through the via hole 308 in the fifth insulating layer 107. For example, in a direction parallel to the surface of the base substrate 101, the via hole 308 is farther away from the main portion 141 of the first electrode 134, that is, the opening area 600 of the sub-pixel, than the via hole 307. That is, the orthographic projection of the via hole 308 on the base substrate 101 is farther away from the orthographic projection of the opening area 600 on the base substrate than the orthographic projection of the via hole 307 on the base substrate 101.

[0183] For example, Figure 5As shown, the method for manufacturing the display substrate may also include sequentially forming a pixel defining layer 108 on the fifth conductive layer 205, and forming an opening area 600 in the pixel defining layer 108 corresponding to the main body 141 of each first electrode 134, and then forming a light-emitting layer 136 at least in the opening area 600, and forming a second electrode 135 on the light-emitting layer.

[0184] For example, the material of the semiconductor material layer includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.).

[0185] For example, the materials of the first conductive material layer, the second conductive material layer, the third conductive material layer, the fourth conductive material layer, the fifth conductive material layer and the second electrode may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by combinations of the above metals; or transparent metal oxide conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0186] For example, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, and the fifth insulating layer 107 are, for example, inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride, and other silicon oxides, silicon nitrides, or silicon oxynitrides, or aluminum oxide, titanium nitride, and other insulating materials including metal nitride oxides. For example, some of these insulating layers may also be organic materials, such as the first planar layer and the second planar layer, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc., which is not limited in the embodiments of the present disclosure. For example, the fourth insulating layer 106 and the fifth insulating layer 107 may include planar layers, respectively.

[0187] For example, the above-mentioned patterning process may adopt a conventional photolithography process, for example, including the steps of photoresist coating, exposure, development, drying, etching, etc.

[0188] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: substrate substrate; A plurality of sub-pixels are located on the substrate; Each of the plurality of sub-pixels comprises a pixel circuit, a first connecting electrode and a pixel electrode, the first connecting electrode is connected to the pixel circuit and is electrically connected to the pixel electrode through a first via hole; the plurality of pixel circuits of the plurality of sub-pixels are distributed in a plurality of rows and columns along a first direction and a second direction; The plurality of sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction, and an orthographic projection of a first via hole of the first sub-pixel on the base substrate and an orthographic projection of a first via hole of the second sub-pixel on the base substrate have different heights in the first direction; Each sub-pixel further includes a second connection electrode, the second connection electrode is located on a side of the first connection electrode close to the substrate, the pixel circuit of each sub-pixel is connected to the first connection electrode through the second connection electrode, and the second connection electrode is electrically connected to the first connection electrode through a second via hole; The display substrate further comprises a plurality of first power lines extending along the first direction, the plurality of first power lines being insulated and arranged in the same layer as the second connection electrode and configured to provide a first power voltage for the plurality of sub-pixels; The display substrate further includes a second power line extending along the second direction and electrically connecting the plurality of first power lines; The display substrate further includes a plurality of third power lines extending along the first direction, the plurality of third power lines are electrically connected to the plurality of first power lines one by one, and each third power line at least partially overlaps with the corresponding first power line in a direction perpendicular to the base substrate; The plurality of third power lines are arranged at the same layer as the second power line and are an integrated structure.

2. The display substrate according to claim 1, wherein: The second via hole of the first sub-pixel is arranged along the first direction with the first via hole.

3. The display substrate according to claim 1, wherein: The pixel electrode of the first sub-pixel comprises a main body portion and a connecting portion, the main body portion is used to drive the light-emitting layer of the light-emitting element to emit light, and the connecting portion is electrically connected to the first connecting electrode through the first via hole; The orthographic projection of the first via hole on the base substrate is farther away from the orthographic projection of the main body of the pixel electrode on the base substrate than the orthographic projection of the second via hole on the base substrate.

4. The display substrate according to claim 1, wherein: The first via hole of the first sub-pixel and the second via hole of the second sub-pixel are arranged along the second direction, The second via hole of the first sub-pixel and the first via hole of the second sub-pixel are arranged along the second direction.

5. The display substrate according to any one of claims 1 to 4, wherein: The pixel circuit includes a driving subcircuit and a storage capacitor; The driving subcircuit includes a control terminal, a first terminal, and a second terminal, and is configured to be coupled to the light emitting element and control a driving current flowing through the light emitting element. The storage capacitor includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is configured to receive a first power supply voltage. The second capacitor electrode is coupled to the control terminal of the driving sub-circuit.

6. The display substrate according to claim 5, wherein: The first capacitor electrode in the first sub-pixel and the first capacitor electrode in the second sub-pixel are arranged in the same layer and are spaced apart from each other.

7. The display substrate according to claim 1, in, The second power line is insulated from the first connection electrode in the same layer and is electrically connected to the plurality of first power lines through a third via hole.

8. The display substrate according to claim 7, wherein: The second power line includes a first portion and a second portion, wherein a width of the first portion in the second direction is greater than a width of the second portion in the second direction; A maximum dimension of the third via in the second direction is greater than a maximum dimension of the second portion in the second direction.

9. The display substrate according to claim 1, wherein: The second power line includes a first portion and a second portion that are alternately connected, An extending direction of the first portion is parallel to the second direction, and an extending direction of the second portion intersects both the first direction and the second direction.

10. The display substrate according to claim 9, wherein: The second portion is parallel to at least one side of the pixel electrode of the first sub-pixel.

11. The display substrate according to claim 5, wherein: The pixel circuit further includes a light emitting control subcircuit, the light emitting control subcircuit being configured to be connected to the first voltage terminal and the driving subcircuit, and configured to apply the first power supply voltage from the first voltage terminal to the first terminal of the driving subcircuit in response to a light emitting control signal; The display substrate further comprises a light emitting control line extending along the second direction, wherein the light emitting control line is connected to the light emitting control subcircuit to provide the light emitting control signal; In a direction perpendicular to the base substrate, the first via hole does not overlap with the light emitting control line, and the second via hole at least partially overlaps with the light emitting control line.

12. The display substrate according to any one of claims 1 to 4, wherein: The pixel circuit includes a driving subcircuit configured to be coupled to a light emitting element and to control a driving current flowing through the light emitting element; The driving sub-circuit comprises a first transistor, wherein a gate, a first electrode and a second electrode of the first transistor respectively serve as a control terminal, a first terminal and a second terminal of the driving sub-circuit.

13. The display substrate according to claim 12, wherein: The pixel electrode of each sub-pixel comprises a main body portion and a connecting portion, wherein the main body portion is used to drive the light-emitting layer to emit light, and the connecting portion is electrically connected to the first connecting electrode through the first via hole; In a direction perpendicular to the base substrate, the main portion of the pixel electrode of the second subpixel does not overlap with the gate of the first transistor of the second subpixel, and the connecting portion of the pixel electrode of the second subpixel at least partially overlaps with the gate of the first transistor of the second subpixel.

14. The display substrate according to claim 12, wherein: The channel region of the first transistor is in an "Ω" shape, The orthographic projection of the “Ω”-shaped channel region on the base substrate protrudes along the first direction toward the orthographic projection of the first via hole on the base substrate.

15. The display substrate according to claim 12, wherein: The orthographic projection of the first via hole of the first sub-pixel on the base substrate is farther away from the orthographic projection of the channel region of the driving transistor on the base substrate than the orthographic projection of the second via hole of the first sub-pixel on the base substrate; The orthographic projection of the first via hole of the second sub-pixel on the base substrate is closer to the orthographic projection of the channel region of the driving transistor on the base substrate than the orthographic projection of the second via hole on the base substrate.

16. A display device, comprising the display substrate according to any one of claims 1 to 15.

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