Devices and methods for suppressing spike currents in memory arrays

Abstract

Systems, methods, and apparatus related to peak current suppression in memory arrays. In one method, a memory device includes a memory array having a crosspoint memory architecture. The memory array has access lines (e.g., word lines and / or bit lines) configured to access memory cells of the memory array. Each access line is divided into a left portion and a right portion. Each portion is electrically connected to a single via, and a driver uses the single via to generate a voltage on the access line. To reduce discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.

Description

Technical Field

[0001] At least some of the embodiments disclosed herein generally relate to memory devices, and more specifically, to spike current suppression in memory arrays. Background Technology

[0002] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of them. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0003] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for a long time even without an external power supply. Volatile memory devices (e.g., DRAM) may lose their stored state when disconnected from an external power supply. Summary of the Invention

[0004] Describe a device. In some instances, the device may include: a memory array including access lines configured to access memory cells of the memory array; at least one via electrically connected at a central region to a first portion and a second portion; a first resistor located between the first portion and the via; a second resistor located between the second portion and the via; and a driver electrically connected to the via. The access lines have a first portion and a second portion on opposite sides of the central region of the access lines, the first portion being configured to access a first memory cell, and the second portion being configured to access a second memory cell. The first resistor is configured to shield against discharge from the first portion when accessing the second memory cell. The second resistor is configured to shield against discharge from the second portion when accessing the first memory cell. The driver is configured to generate a voltage on the first portion to access the first memory cell, and a voltage on the second portion to access the second memory cell.

[0005] Describe a device. In some instances, the device may include: an access line having a first portion and a second portion; a via electrically connected to the first portion and the second portion; and a resistive film having a first segment between the first portion and the via, and a second segment between the second portion and the via. The first portion is configured to access memory cells of a memory array, and the first portion and the second portion are physically separated by a gap.

[0006] A method is described. In some instances, the method may include: forming a via; forming a resistive film over the via; forming an access line over the resistive film; and patterning the access line to provide first and second portions. The patterning physically separates the first portion from the second portion, and the first portion is configured to access memory cells of a memory array. A first segment of the resistive film is located between the first portion and the via, and a second segment of the resistive film is located between the second portion and the via. Attached Figure Description

[0007] The embodiments are illustrated by way of example and not by way of limitation in the figures, in which similar reference numerals indicate similar elements.

[0008] Figure 1 A memory device is shown that implements spike current suppression in a memory array according to some embodiments.

[0009] Figure 2 A resistor is shown according to some embodiments for implementing spike current suppression for access lines of a memory array.

[0010] Figure 3 The diagram illustrates access lines divided into left and right portions for spike current suppression, according to some embodiments.

[0011] Figure 4 The illustration shows a memory array in a cross-point architecture according to some embodiments, the cross-point architecture including various word lines and bit lines providing access to memory cells arranged in multiple stacked layers.

[0012] Figure 5 The image illustrates word lines electrically connected via vias in a memory array according to some embodiments.

[0013] Figure 6 A memory device configured with a driver to generate voltage on the access lines of a memory array, according to some embodiments, is shown.

[0014] Figure 7 A memory cell according to some embodiments is shown, the memory cell having a bit line driver to generate voltage on a bit line and a word line driver to generate voltage on a word line.

[0015] Figure 8 Examples of memory cells including selection devices according to some embodiments are shown.

[0016] Figures 9 to 12 Various steps are shown in manufacturing a memory device that implements spike current suppression, according to some embodiments.

[0017] Figure 13 A method for manufacturing a memory device that implements spike current suppression is shown according to some embodiments. Detailed Implementation

[0018] The following disclosure describes various embodiments for spike current suppression in memory arrays. At least some embodiments herein relate to a memory device having a memory array using a crosspoint architecture. In one example, the memory array is a resistive RAM (RRAM) crosspoint memory array or a ferroelectric RAM (FeRAM) crosspoint memory array. Other memory types may be used.

[0019] In one instance, the memory device stores data used by a host device (e.g., a computing device in an autonomous vehicle, an artificial intelligence (AI) engine, or other computing device that accesses data stored in the memory device). In another instance, the memory device is a solid-state drive installed in an electric vehicle.

[0020] In some memory arrays (e.g., crosspoint memory arrays), current discharge through memory cells can generate current spikes (e.g., relatively high current discharges through memory cells over relatively short periods), which can damage the memory cells. For example, current discharges occurring when a chalcogenide memory cell is turned on can cause the memory cell to become amorphous. Such spikes can be generated by internal discharges within the memory array. In one instance, this is the discharge of parasitic capacitances within the memory array. Current spikes caused by internal discharges can be particularly problematic.

[0021] In one example, a memory cell is selected by generating voltages on the word lines and bit lines of the memory array. When a memory cell is selected, a large current spike can flow through the cell. The spike is caused by parasitic capacitance resulting from charge buildup during operation of the memory device. The charge discharges in the form of current spikes that can potentially damage the memory cell.

[0022] In one example, the memory cell is a chalcogenide-based auto-select memory cell that is activated when selected (e.g., the cell is in a set state). The selection spike is generated by the discharge of parasitic capacitances coupled to the word lines and / or bit lines used to select the memory cell. Memory cells that use both a selection device and a memory storage element (e.g., phase-change memory) may encounter similar problems.

[0023] Such selection spikes can be the root cause of several reliability mechanisms. This is especially true for memory cells located near the decoder, where spike currents are typically larger. For example, selection spikes can cause reliability mechanisms such as read interference and / or decreased durability.

[0024] In one instance, various voltages of the memory array can be varied to perform access operations. These voltage variations can cause charge to accumulate in the memory array, for example, in parasitic capacitances associated with the array (e.g., the parasitic capacitances of the access lines of the memory array). In some cases, the accumulated charge can be discharged through selected memory cells. For example, a memory cell can become conductive based on selection (e.g., during access, such as when the voltage across the memory cell exceeds a threshold voltage of the memory cell), which can allow the accumulated charge on the access lines coupled to the memory cell to discharge through the cell as current spikes (e.g., current spikes with a peak value of at least 100 microamps, such as 200 to 300 microamps). The memory cell can degrade or wear down proportionally to the number and magnitude of the current spikes experienced by the memory cell over time.

[0025] In one example, the memory array uses self-selected chalcogenide memory cells. When a cell is selected, the word lines and bit lines are charged to select the cell. This can result in capacitive coupling with adjacent word lines or bit lines of adjacent cells. Over time, this capacitive coupling causes charge to accumulate in various parasitic capacitances (e.g., as mentioned above). When the memory cell is selected and the memory cell is open (e.g., during a read operation), the accumulated charge flows through the memory cell as a current spike.

[0026] In some cases, current spikes may be higher for memory cells located near or close to access line drivers (e.g., near electrical distance (ED)) compared to memory cells located far from the via / driver (e.g., far ED). For example, discharge through memory cells with near ED may be more severe due to the relatively low resistance path between the memory cell and the charge that accumulates in parasitic capacitance along the entire length of the access line. This can result in a higher current flow through the memory cell when it becomes conductive (e.g., a relatively high magnitude current spike) compared to memory cells with far ED, which may be more separated from the charge that accumulates further along the access line (e.g., the charge that accumulates further along the access line on the other side of the via).

[0027] To address these and other technical issues, one or more resistors are used to shield the portions of the access lines other than those used to access memory cells. The shielding of discharge by one or more resistors reduces the extent of discharge that would occur without resistors (e.g., in existing devices where such resistors are absent).

[0028] For example, the physical configuration of the resistors can be customized depending on the location of the access lines in the memory array. In one example, each resistor is a portion of a resistive film located between the access line and a via electrically connected to a driver used to drive the voltage on the access line when a memory cell is selected.

[0029] In one example, the access lines are word lines of a crosspoint memory array. One or more resistors are configured to increase the resistance of the circuit path through which the parasitic capacitance of the crosspoint memory array can discharge, thereby reducing the magnitude of any current spikes. Compared to existing methods that do not use resistors, the magnitude of current spikes is lower (e.g., resistors increase the resistance of an RC discharge circuit, thereby reducing current spikes). Moreover, the use of one or more resistors has minimal impact on the bias current and the ability to deliver current to the word lines for normal memory cell operations (e.g., read, write, etc.).

[0030] In one embodiment, the access line is divided into a left portion and a right portion (e.g., left and right word line or bit line portions). Each portion is electrically connected to a via, which the driver uses to generate a voltage on the access line. To reduce discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.

[0031] In one embodiment, the memory device includes a memory array having a cross-point memory architecture. The memory array has access lines configured to access memory cells of the memory array. The access lines have a first portion and a second portion on opposite sides of a central region of the access line. The first portion is configured to access a first memory cell, and the second portion is configured to access a second memory cell. In one example, the access line is a word line or a bit line, and the central region is located in the middle of the word line or bit line. In one example, as mentioned above, the access line is divided into a left portion and a right portion.

[0032] One or more through-holes are electrically connected to the first and second portions at the central region. In one example, a single through-hole is used. In other examples, multiple through-holes may be used.

[0033] A first resistor is located between a first portion of the access line and the via. The first resistor is configured to shield against discharge from the first portion when accessing the second memory cell. A second resistor is located between a second portion and the via. The second resistor is configured to shield against discharge from the second portion when accessing the first memory cell.

[0034] The driver is electrically connected to one or more vias. The driver is configured to generate a voltage on a first portion when a first memory cell is accessed. When a second memory cell is accessed, the driver generates a voltage on a second portion. In one example, the driver is a word line or bit line driver. In another example, the driver is electrically connected to a single via located in the middle of a word line and generates a voltage on both the first and second portions when a single memory cell is accessed. The memory cell may be located on either the first or second portion.

[0035] Various advantages are provided by the embodiments described herein. In one advantage, current spikes generated during memory cell selection are suppressed by shielding charges from distant capacitors in the memory array (e.g., charges from distant cells on the left portion of the access lines in the left half-tile for accessing nearby memory cells, and / or charges from the right portion of the access lines in the right half-tile). In another advantage, the aforementioned resistors can be easily added to existing wafer architectures.

[0036] One advantage is that the use of the aforementioned resistors can be varied for different locations within the memory array. The layers used to form the memory cell stacks can be identical for all portions of the memory array. Therefore, the use of spike current suppression as described herein can be transparent to the memory cell structure.

[0037] One advantage is that, for a given level of tolerable current spikes, the tile size can be increased, and thus the memory density can be increased. Another advantage is that various resistor configurations can be combined and varied for different parts of the memory array as needed. Another advantage is that spike current suppression can be commonly used in any cross-point technique.

[0038] Figure 1 A memory device 101 is illustrated according to some embodiments, which implements spike current suppression in a memory array 102. The memory device 101 includes a memory controller 120 that controls a sensing circuitry system 122 and a biasing circuitry system 124. The memory controller 120 includes a processing unit 116 and a memory 118. In one example, the memory 118 stores firmware executed on the processing unit 116 to perform various operations of the memory device 101. In one example, the operations include reading from and writing to various memory cells of the memory array 102.

[0039] The memory array 102 includes memory cells 110 and 112. In one example, memory cell 110 is located in the left half-tile and memory cell 112 is located in the right half-tile of the memory array.

[0040] The access lines 130 of the memory array 102 are used to access memory cells 110, 112. In one example, the access lines 130 are word lines and / or bit lines. In one example, each access line 130 is split in a central region (e.g., in the middle of the access line) to have a left portion for accessing memory cell 110 and a right portion for accessing memory cell 112.

[0041] Bias circuitry 124 is used to generate voltage on access line 130. Via 134 is used to electrically connect access line 130 to bias circuitry 124. In one example, a single via 134 is used to electrically connect the left and right portions of each access line 130 to a word line or bit line driver of bias circuitry 124.

[0042] In one instance, a drive voltage is applied to the left portion of access line 130 to access memory cell 110. In another instance, the drive voltage is part of a read or write operation performed in response to a command received from host device 126.

[0043] The sensing circuitry 122 is used to sense the current flowing through the memory cells 110, 112. In one example, the sensing circuitry 122 senses the current generated by applying a voltage to the memory cell 110 during a read operation.

[0044] In one embodiment, various resistors 132 are located between access lines 130 and vias 134 to suppress spike currents in the memory array 102. The resistors 132 shield against discharges from certain portions of the access lines 130 (e.g., as described above), which may occur when accessing memory cells 110, 112 (e.g., when a chalcogenide memory cell is turned on).

[0045] In one embodiment, memory device 101 selects a write voltage to apply to memory cells 110, 112 when performing a write operation. In one embodiment, bias circuitry system 124 is implemented by one or more voltage drivers. Bias circuitry system 124 may further be used to generate a read voltage for read operations performed on memory array 102 (e.g., in response to a read command from host device 126).

[0046] In one embodiment, the sensing circuitry 122 is used to sense the state of each memory cell in the memory array 102. In one example, the sensing circuitry 122 includes a current sensor (e.g., a sensing amplifier) ​​for detecting the current caused by applying various read voltages to the memory cells in the memory array 102. The sensing circuitry 122 senses the current associated with each of the memory cells 110 caused by the applied voltage.

[0047] In one instance, if the sensing circuitry 122 determines that the corresponding current generated by applying the read voltage to the memory cell is greater than a corresponding fixed threshold (e.g., a predetermined level of current or a threshold current), the memory controller 120 determines that the memory cell is turned on.

[0048] In one embodiment, memory cells 110 and 112 may have different memory types (e.g., single-level cells or three-level cells).

[0049] In one embodiment, memory controller 120 receives a write command from host device 126. The write command is accompanied by data to be written to memory array 102 (e.g., user data of the user of host device 126). In response to receiving the write command, controller 120 initiates a programming operation by applying a voltage to memory cell 110. Controller 120 determines the corresponding current generated by the applied voltage.

[0050] In one embodiment, controller 120 determines whether the existing programming state (e.g., logic state zero) and the target programming state (e.g., logic state zero) for each cell are the same. If the existing target state and the target programming state are the same, no write voltage is applied (e.g., this is normal write mode). If the existing programming state and the target programming state are different, a write voltage is applied to the particular memory cell. In one example, the write voltage is 3 to 8 volts applied across the memory cell by applying a voltage bias to the word line and bit line used to select the cell.

[0051] In one example, controller 120 may write logic state to memory cells, such as memory cells 110 and 112, during a write operation using a write voltage (e.g., a write pulse). The write pulse can be applied by providing a first voltage to a bit line and a second voltage to a word line to select the memory cell. Circuitry coupled to access lines (e.g., access line drivers included in decoder circuitry) may be used to provide the write voltage, to which the memory cells may be coupled. The circuitry may be controlled by internal control signals provided by control logic (e.g., controller 120). The resulting voltage applied to the memory cell is the difference between the first and second voltages.

[0052] In some cases, memory cells (e.g., PCM cells) contain material that varies in its crystalline configuration (e.g., between a crystalline phase and an amorphous phase), which in turn determines the threshold voltage of the memory cell for storing information. In other cases, memory cells contain material that remains in a crystalline configuration (e.g., an amorphous phase), which can exhibit a variable threshold voltage for storing information.

[0053] Figure 2 Resistors 210 and 212 are shown according to some embodiments for implementing spike current suppression for access lines in a memory array. The access line has a first portion 202 and a second portion 204 (e.g., a left portion and a right portion as described above). Figure 2 The access lines are examples of access lines 130 of memory array 102. Part 202 is used to access memory cell 206 and part 204 is used to access memory cell 208. Each part 202, 204 is typically used to access multiple memory cells (e.g., memory cells in the memory array located above and below the respective part).

[0054] Access line portions 202 and 204 are electrically connected to via 214 via resistors 210 and 212. In one example, access line portions 202 and 204 are portions of a conductive layer in a memory array. In one example, resistors 210 and 212 are portions of a resistive film formed covering the conductive layer and the via 214.

[0055] In one example, via 214 is a single via. In another example, via 214 is provided by multiple vias. Via 214 electrically connects driver 216 to access line portions 202, 204. Driver 216 is an example of bias circuitry system 124. In one example, driver 216 generates a read voltage on portion 202 to determine the state of memory cell 206. In one example, driver 216 generates a read voltage on portion 204 to determine the state of memory cell 208.

[0056] Memory cells 206 and 208 can be formed using various memory cell types. In one example, the memory cell contains a chalcogenide. In one example, the memory cell includes a selection device and a phase change material as a memory element. In one example, the memory cell is a self-selecting memory cell containing a chalcogenide. In one example, the memory cell is a resistive memory cell.

[0057] Figure 3 This diagram illustrates access lines divided into a left portion 302 and a right portion 304 for peak current suppression, according to some embodiments. The left portion 302 is used to access memory cell 308, and the right portion 304 is used to access memory cell 310. The access lines provided by portions 302 and 304 are... Figure 1 Access line 130 or Figure 2 An instance of an access line.

[0058] In one embodiment, a slit in the access line is provided in the central region 306 of the access line. In one instance, a split is formed in the middle of the access line such that portions 302 and 304 are patterned to have substantially equal or identical lengths. In one instance, portions 302 and 304 are patterned to have different lengths.

[0059] The left portion 302 and the right portion 304 are electrically connected to the via 312 via a resistive film 318. The resistive film 318 has a section 320 located between the left portion 302 of the access line and the via 312. The resistive film 318 has a section 322 located between the right portion 304 of the access line and the via 312.

[0060] In one example, each of segments 320 and 322 has a thickness of 1 to 20 nanometers. In another example, each of segments 320 and 322 has a width of 10 to 200 nanometers. Figure 3 The width is indicated by arrows corresponding to reference numerals 320 and 322 in the accompanying drawings.

[0061] In one example, the resistive film 318 comprises silicon tungsten nitride. In another example, the resistive film 318 comprises one or more of silicon tungsten nitride, silicon titanium nitride, tungsten nitride, titanium nitride, tungsten silicide, or cobalt silicide. The proportions of the aforementioned materials may vary for different memory arrays.

[0062] In one embodiment, the crack is a gap that physically separates portions 302 and 304. In one example, the crack contains a non-conductive material formed in a central region 306 between portions 302 and 304. In one example, the non-conductive material is an insulating oxide. In one example, the crack is an unfilled space between portions 302 and 304.

[0063] Through-hole 312 is electrically connected to transistor circuit system 316 formed in semiconductor substrate 314. In one example, transistor circuit system 316 includes bias circuit system 124. In one example, transistor circuit system 316 includes one or more voltage drivers to... Figure 3 Voltage is generated on portions 302 and 304 of the access lines shown. In one example, the transistor circuit system 316 is formed using CMOS transistors.

[0064] Figure 4 This illustration depicts a memory array in a cross-point architecture according to some embodiments, the cross-point architecture including various word lines and bit lines providing access to memory cells arranged in multiple stacked layers. The memory array includes various word lines and bit lines arranged orthogonally (e.g., perpendicularly) to each other. For example, word lines 412 and 414 are arranged perpendicular to bit lines 406 and 408. Word lines 412 and 414 are... Figure 1 An example of access line 130. Additionally and / or alternatively, bit lines 406 and 408 are examples of access line 130.

[0065] The memory array comprises various memory cells arranged in various layers (e.g., layers 0 to 3). Each layer contains memory cells. For example, layer 0 contains memory cell 402 and layer 1 contains memory cell 404. Memory cells 402 and 404 are instances of memory cell 110. In one embodiment, each bit line 406 provides access to memory cells 402 and 404 located above and below the corresponding bit line.

[0066] Although not shown for simplicity, each of word lines 412, 414 may incorporate resistors 210, 212 as described above. In one example, similarly as described above, each of word lines 412, 414 is split to have a left portion 302 and a right portion 304. In one example, each word line and / or bit line for any or all of layers 0 to 3 may contain gaps, such as those described above for... Figure 3As discussed above. In one example, various configurations of resistors 210, 212 can be used for different word lines and / or bit lines. In one example, the configuration of resistors 210, 212 is determined based on the degree of discharge associated with a given region of the memory array.

[0067] In one embodiment, word line 412 is electrically connected to word line 414 via through hole 410. Through hole 410 is an example of through holes 134, 214, and 312.

[0068] Although not shown for the sake of simplicity, via 410 is electrically connected to a driver for generating voltage on word lines 412, 414. In one example, the driver is either bias circuitry 124 or driver 216.

[0069] Figure 5 This illustrates word lines electrically connected via vias in a memory array according to some embodiments. In one embodiment, a word line providing access to memory cells in the top layer of the memory array has a left portion 502 and a right portion 504 separated by a crack 506. The left portion 502 and right portion 504 are examples of left portions 302 and right portions 304. Word line 520 provides access to memory cells in the bottom layer of the memory array.

[0070] In one embodiment, a via electrically connects left portion 502 and right portion 504 to word line 520. In one example, the via includes conductive portions 508, 510, and 512 electrically connected to a driver (not shown) via via 514. In one example, each of conductive portions 508, 510, and 512 corresponds to a conductive layer patterned and formed using, for example, a photoresist layer during the fabrication of the memory array. In one example, conductive portion 510 is a landing pad for conductive portion 508.

[0071] In one embodiment, resistive film 530 electrically connects left portion 502 and right portion 504 to conductive portion 508. Resistive film 530 is an example of resistive film 318.

[0072] In one embodiment, a crack (not shown) may be formed above a through-hole 514 in the central region 522 of word line 520. Word line 520 is an example of word line 414.

[0073] Figure 6 A memory device configured with a driver to generate voltage on the access lines of memory array 333 is shown according to some embodiments. For example, Figure 2 The memory cells 206 and 208 described herein can be used in the memory cell array 333.

[0074] Figure 6The memory device includes a controller 331 that operates bit line drivers 337 and word line drivers 335 to access individual memory cells (e.g., 206, 208) in array 333. Controller 331 is an example of memory controller 120. Memory array 333 is an example of memory array 102.

[0075] Bit line driver 337 and / or word line driver 335 may be implemented by bias circuitry system 124. In one example, each memory cell (e.g., 206, 208) in array 333 may be accessed via voltages driven by a pair of bit line drivers and word line drivers, such as Figure 7 As explained in the text.

[0076] Figure 7 A memory cell 401 according to some embodiments is illustrated, the memory cell having a bit line driver 447 to generate a voltage on a bit line (wire 441) and a word line driver 445 to generate a voltage on a word line (wire 443). For example, the bit line driver 447 drives a first voltage applied to a row of memory cells in an array 333; and the word line driver 445 drives a second voltage applied to a column of memory cells in the array 333. The memory cells 401 in the rows and columns of the memory cell array 333 experience a voltage difference between the first voltage driven by the bit line driver 447 and the second voltage driven by the word line driver 445. When the first voltage is higher than the second voltage, the memory cell 401 experiences a voltage polarity (e.g., positive polarity); and when the first voltage is lower than the second voltage, the memory cell 401 experiences the opposite voltage polarity (e.g., negative polarity).

[0077] For example, when memory cell 401 is configured to be read using positive voltage polarity, bit line driver 447 can be configured to drive a positive voltage. For example, when memory cell 401 is configured to be read using negative voltage polarity, word line driver 445 can be configured to drive a positive voltage.

[0078] For example, during a write operation, both bit line driver 447 and word line driver 445 can drive voltages of different magnitudes (e.g., to perform read or write steps). For example, bit line driver 447 can be configured to drive positive voltages of different magnitudes; and word line driver 445 can be configured to drive negative voltages of different magnitudes. The difference between the voltage driven by bit line driver 447 and the voltage driven by word line driver 445 corresponds to the voltage applied to memory cell 401.

[0079] In one example, bit line driver 337 can be used to drive parallel wires (e.g., 441) arranged in one direction and in one layer of the crosspoint memory; and word line driver 435 can be used to drive parallel wires (e.g., 443) arranged in another direction and in another layer of the crosspoint memory. Wires (e.g., 441) connected to bit line driver (e.g., 447) and wires (e.g., 443) connected to word line driver (e.g., 445) extend in the two layers in orthogonal directions. Memory cell array 333 is sandwiched between the two layers of wires; and memory cells (e.g., 401) in array 333 are formed at the intersection of two wires (e.g., 441 and 443) in the integrated circuit die of the crosspoint memory.

[0080] Figure 8 Examples of memory cells including selection device 610 according to some embodiments are shown. In one example, selection device 610 includes a chalcogenide. Memory cell 602 is an example of memory cells 110, 112; or memory cells 206, 208.

[0081] The top electrode 608 electrically connects the selector 610 to the bit line 604, and the bottom electrode 612 electrically connects the selector 610 to the word line 606. In one example, electrodes 608 and 612 are formed of carbon material. The bit line 604 and word line 606 are each examples of access line 130. In one example, word line 606 and / or bit line 604 are divided into a left portion 302 and a right portion 304 as described herein.

[0082] In one example, the selection device 610 includes a chalcogenide (e.g., a chalcogenide material and / or a chalcogenide alloy). The threshold voltage characteristics of the selection device may be based on the voltage polarity applied to the memory cell.

[0083] In one example, a logic state can be written to memory cell 602, which may correspond to one or more bits of data. The logic state can be written to the memory cell by applying voltages of different polarities at different voltage and / or current values. The memory cell can be read by applying a voltage of a single polarity. The write and read protocols can utilize different threshold voltages of the selection device generated by different polarities. The chalcogenide material of the selection device may or may not undergo a phase transition during read and / or write. In some cases, the chalcogenide material may not be a phase-change material.

[0084] In one embodiment, the device includes: a memory array (e.g., 102, 333) including access lines (e.g., 130) configured to access memory cells (e.g., 206, 208; 308, 310) of the memory array, the access lines having a first portion (e.g., 202, 302) and a second portion (e.g., 204, 304) on opposite sides of a central region (e.g., 306) of the access line, wherein the first portion is configured to access a first memory cell and the second portion is configured to access a second memory cell; and at least one through-hole (e.g., 214, 312) in the central region. The device is electrically connected to the first portion and the second portion; a first resistor (e.g., 210) located between the first portion and the via, wherein the first resistor is configured to shield against discharge from the first portion when accessing the second memory cell; a second resistor (e.g., 212) located between the second portion and the via, wherein the second resistor is configured to shield against discharge from the second portion when accessing the first memory cell; and a driver (e.g., 216) electrically connected to the via, wherein the driver is configured to generate a voltage on the first portion to access the first memory cell and to generate a voltage on the second portion to access the second memory cell.

[0085] In one embodiment, at least one via is a single via; the access line is a bit line or a word line; and the driver is a bit line driver or a word line driver.

[0086] In one embodiment, the first resistor is provided by a first segment (e.g., 320) of a resistive film (e.g., 318) covering the via; and the second resistor is provided by a second segment (e.g., 322) of a resistive film covering the via. The central region includes the access line covering the via and the gap between the first and second portions of the access line.

[0087] In one embodiment, the resistive film comprises silicon tungsten nitride.

[0088] In one embodiment, a crack is formed by removing a third portion of the access line to physically separate the first portion from the second portion; and the third portion is located between the first portion and the second portion before the third portion is removed.

[0089] In one embodiment, the crack comprises: a non-conductive material configured to prevent current discharge from flowing directly between the first and second portions of the access line; or an unfilled space between the first and second portions.

[0090] In one embodiment, the memory array is part of a memory device (e.g., 101); access lines are associated with physical addresses within the memory array; and a controller of the memory device (e.g., 120) is used to select both the first and second portions of the access lines for access operations of the first memory cell.

[0091] In one embodiment, the device includes: an access line having a first portion (e.g., 302) and a second portion (e.g., 304), wherein the first portion is configured to access memory cells (e.g., 308) of a memory array, and a gap physically separates the first portion and the second portion; a via (e.g., 312) electrically connected to the first portion and the second portion; and a resistive film (e.g., 318) having a first segment between the first portion and the via, and a second segment between the second portion and the via.

[0092] In one embodiment, the device further includes a driver (e.g., a driver in transistor circuitry 316) electrically connected to a through-hole, wherein the driver is configured to generate a voltage on a first portion to access a memory cell.

[0093] In one embodiment, the gap is a crack formed in the access line by removing a third portion of the access line to physically separate the first and second portions of the access line.

[0094] In one embodiment, the material forming the resistive film has a higher resistivity than the materials forming the first and second portions of the access line.

[0095] In one embodiment, the resistive film comprises at least one of the following: tungsten silicon nitride; titanium silicon nitride; tungsten nitride; titanium nitride; tungsten silicide; or cobalt silicide.

[0096] In one embodiment, each of the first and second portions is configured to access memory cells located above and below the respective portion.

[0097] In one embodiment, the memory array has a cross-point architecture, and the memory cells are: memory cells containing chalcogenides; memory cells containing selection devices and phase change materials as memory elements; self-selecting memory cells containing chalcogenides (e.g., memory cell 602); or resistive memory cells.

[0098] In one embodiment, the gap is covered by a third segment of the resistive film (e.g., the middle segment of the resistive film 318 is located below the central region 306), and the third segment is located between the first segment and the second segment.

[0099] Figures 9 to 12 Various steps are illustrated in manufacturing a memory device that implements spike current suppression according to some embodiments. In one example, the memory device is memory device 101.

[0100] Figure 9A memory array 902 is shown at an intermediate stage of manufacturing. The memory array 902 comprises various memory cells 908. Each memory cell 908 comprises a memory stack containing various material layers (e.g., chalcogenides, phase change materials, etc.) corresponding to the selected memory cell technology. Memory cells 908 are examples of memory cells 110, 112; memory cells 206, 208; or memory cells 308, 310.

[0101] The memory array 902 includes a through-hole 904 formed on the pad 906. For example... Figure 9 The memory array 902 shown can be formed using conventional manufacturing techniques.

[0102] like Figure 10 As shown, a nitride layer 1010 is formed over the top surface of the memory array 902. In one example, the nitride layer 1010 comprises one or more of tungsten silicon nitride, titanium silicon nitride, tungsten nitride, or titanium nitride. In one example, one or more of tungsten silicide or cobalt silicide may be used alternatively or additionally. The proportions of the aforementioned materials may vary for different memory arrays.

[0103] The word line 1012 is formed over a nitride layer 1010. In one example, the word line 1012 is a conductive material. In another example, the word line 1012 is tungsten.

[0104] like Figure 11 As shown, a hard mask 1102 is formed over the word line 1012. Then, a photoresist layer 1104 is formed over the hard mask 1102.

[0105] like Figure 12 As shown, the photoresist layer 1104 is patterned and used to etch the hard mask 1102, word lines 1012, and nitride layer 1010 to provide an opening 1202 overlying the via 904. In one example, tungsten-only etching is used.

[0106] After the above etching, the photoresist layer 1104 and hard mask 1102 are removed. Subsequent fabrication of the memory device can be performed using conventional manufacturing techniques.

[0107] An opening 1202 is provided to divide the word line 1012 into a left portion and a right portion. In one example, these portions correspond to the left portion 302 and the right portion 304.

[0108] In one example, the remainder of the nitride layer 1010 covering the via 904 provides a resistive film 318. In an alternative approach, the nitride layer 1010 is not etched, allowing it to completely cover the via 904 (e.g., similarly as...). Figure 3 (as shown in the image).

[0109] In one embodiment, the memory device discussed herein, including a memory array, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping method.

[0110] In one embodiment, the transistor discussed herein (e.g., the transistor of transistor circuit system 316) may represent a field-effect transistor (FET) and includes a three-terminal device comprising a source, a drain, and a gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). In one example, each transistor is used in a CMOS transistor circuit system formed at the top surface of a semiconductor wafer and beneath a memory array having multiple layers of memory cells. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type, the FET may be called an n-type FET. If the channel is p-type, the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be turned on or activated. When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be turned off or deactivated.

[0111] Figure 13 A method for manufacturing a memory device implementing spike current suppression is illustrated according to some embodiments. For example, Figure 13 The method can be used to form Figure 3 The memory device includes the split access lines and resistive film. In one example, the manufactured memory device is memory device 101.

[0112] Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0113] At frame 1301, a via is formed in the memory array. In one example, the via is via 904. In another example, the memory array is memory array 902.

[0114] At frame 1303, a resistive film is formed over the via. In one example, the resistive film is a nitride layer 1010.

[0115] At frame 1305, a resistive film is overlaid to form an access line. In one example, the access line is word line 1012.

[0116] At frame 1307, a photoresist layer is formed over the access line. In one example, the photoresist layer is photoresist layer 1104. In another example, a photoresist layer is formed over a hard mask (e.g., hard mask 1102).

[0117] At frame 1309, a photoresist layer is patterned. In one example, the photoresist layer is patterned for use in the etching that provides opening 1202.

[0118] At frame 1311, a patterned photoresist layer is used to etch the access line to provide a first and second portion of the access line. In one example, the access line is etched to divide the access line into a left portion 302 and a right portion 304.

[0119] In one embodiment, the method includes: forming a via (e.g., via 312); forming a resistive film overlying the via (e.g., 318); forming access lines overlying the resistive film (e.g., providing access lines for a left portion 302 and a right portion 304); and patterning the access lines to provide first and second portions. The patterning physically separates the first and second portions (e.g., the patterning provides a slit in the access line), and the first portion is configured to access memory cells of a memory array (e.g., 308). A first segment of the resistive film is between the first portion and the via, and a second segment of the resistive film is between the second portion and the via.

[0120] In one embodiment, patterning an access line includes: forming a photoresist layer over the access line; patterning the photoresist layer; and performing etching using the patterned photoresist layer to etch the access line. Performing etching includes etching the access line to provide a crack over the via and between the first and second portions (e.g., a crack located in the central region 306 and over the via 312).

[0121] In one embodiment, performing etching further includes etching the resistive film to physically separate the first and second segments.

[0122] In one embodiment, the first and second segments of the resistive film each have a thickness of 1 to 20 nanometers; the first segment has a width of 10 to 200 nanometers; and the second segment has a width of 10 to 200 nanometers.

[0123] In one embodiment, the memory array is part of a memory device (e.g., 101). The method further includes forming transistor circuitry (e.g., transistor circuitry system 316) located beneath the memory array and electrically connected to vias. The transistor circuitry is configured to generate voltage on a first portion to access memory cells during read or write operations, and to generate voltage in response to commands received from a host device (e.g., 126) by a controller (e.g., 120) of the memory device.

[0124] The descriptions and figures are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in some cases, well-known or conventional details have not been described to avoid obscuring the description. References to one or more embodiments in this disclosure do not necessarily refer to the same embodiment; and such references imply at least one.

[0125] In this specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to all of the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. Furthermore, various features that may be presented by some embodiments but not by others are described. Similarly, various requirements are described that may be requirements of some embodiments but not by others.

[0126] In this specification, various functions and / or operations of the memory device may be described as being executed or caused by software code for the sake of simplicity. However, those skilled in the art will recognize that this expression means that the functions and / or operations are caused by one or more processing devices executing code, such as microprocessors, application-specific integrated circuits (ASICs), graphics processors, and / or field-programmable gate arrays (FPGAs). Alternatively or in combination, functions and operations may be implemented using dedicated circuit systems (e.g., logic circuit systems) with or without software instructions. Functions may be implemented using hardwired circuit systems without software instructions or in combination with software instructions. Therefore, the techniques described are neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a computing device.

[0127] The memory device described above may include one or more processing devices (e.g., processing device 116), such as a microprocessor, which executes a sequence of instructions contained in a memory, such as a ROM, volatile RAM, non-volatile memory, cache, or remote storage device.

[0128] Routines executed to perform memory operations can be implemented as part of an operating system, middleware, business delivery platform, software development kit (SDK) component, network service, or other specific application, component, program, object, module, or sequence of instructions (sometimes called a computer program). The calling interface of these routines can be exposed to the software development community as an application programming interface (API). Computer programs typically include one or more sets of instructions stored in various memories and storage devices within a computer at various times, and these sets of instructions, when read and executed by one or more processors in the computer, cause the computer to perform operations necessary for carrying out elements involving various aspects.

[0129] Computer-readable media can be used to store software and data that, when executed by a computing device, cause the device to perform various methods of memory device operations (e.g., read or write operations). Executable software and data can be stored in various locations including, for example, ROM, volatile RAM, non-volatile memory, and / or cache. A portion of this software and / or data can be stored in any of these storage devices. Furthermore, data and instructions can be obtained from a centralized server or a peer-to-peer network. Different portions of data and instructions can be obtained at different times and in different communication sessions or in the same communication session from different centralized servers and / or peer-to-peer networks. All data and instructions can be obtained before the application is executed. Alternatively, portions of data and instructions can be obtained dynamically and as needed for execution. Therefore, it is not required that all data and instructions be on the computer-readable media at any given time.

[0130] Examples of computer-readable media include, but are not limited to, recordable and non-recordable media, such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, disk storage media, optical storage media (e.g., optical disc read-only memory (CD-ROM), digital versatile disk (DVD), etc.). Computer-readable media can store instructions. Other examples of computer-readable media include, but are not limited to, non-volatile embedded devices using NOR flash or NAND flash memory architectures. Media used in these architectures may include unmanaged NAND devices and / or managed NAND devices, including, for example, eMMC, SD, CF, UFS, and SSD.

[0131] Generally, non-transitory computer-readable media includes any means that provides (e.g., stores) information in a form accessible by computing devices (e.g., computers, mobile devices, network devices, personal digital assistants, manufacturing tools with controllers, any device having a collection of one or more processors, etc.). As used herein, “computer-readable media” may include a single medium or multiple media (e.g., storing one or more sets of instructions).

[0132] In various embodiments, hardwired circuitry systems can be used in combination with software and firmware instructions to implement various functions of the memory device. Therefore, the technology is neither limited to any particular combination of hardware circuitry systems and software, nor to any particular source of instructions executed by the computing device.

[0133] The various embodiments described herein can be implemented for memory devices used in a wide variety of computing devices. As used herein, examples of "computing device" include, but are not limited to, servers, centralized computing platforms, systems with multiple computing processors and / or components, mobile devices, user terminals, vehicles, personal communication devices, wearable digital devices, electronic self-service terminals, general-purpose computers, electronic document readers, tablet computers, laptops, smartphones, digital cameras, home appliances, televisions, or digital music players. Additional examples of computing devices include devices that are part of a network called the "Internet of Things" (IoT). Such "things" may interact incidentally with their owners or administrators who can monitor or modify settings for these things. In some cases, such owners or administrators act as users of the "thing" devices. In some instances, a user's primary mobile device (e.g., an Apple iPhone) may act as an administrator server for paired "thing" devices worn by the user (e.g., an Apple Watch).

[0134] In some embodiments, the computing device may be a computer or a host system, such as a desktop computer, a laptop computer, a web server, a mobile device, or another computing device including memory and processing means. The host system may include or be coupled to a memory subsystem (e.g., memory device 101) such that the host system can read data from or write data to the memory subsystem. The host system may be coupled to the memory subsystem via a physical host interface. Generally, the host system may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0135] In some embodiments, the computing device is a system comprising one or more processing devices. Examples of processing devices may include a microcontroller, a central processing unit (CPU), a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), a system-on-a-chip (SoC), or another suitable processor.

[0136] In one example, the computing device is the controller of the memory system. The controller includes a processing device and a memory containing instructions executed by the processing device to control various operations of the memory system.

[0137] While some of the accompanying figures illustrate multiple operations in a particular order, non-orderly dependent operations can be reordered and other operations can be combined or decomposed. Although some reorderings or other groupings are specifically mentioned, other reorderings or groupings will be obvious to those skilled in the art, and therefore an exhaustive list of alternatives is not provided.

[0138] In the foregoing description, this disclosure has been described with reference to specific exemplary embodiments of the invention. It will be apparent that various modifications may be made without departing from the broader spirit and scope set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. An apparatus comprising: a memory array including an access line configured to access memory cells of the memory array, the access line having a first portion and a second portion on opposite sides of a central region of the access line, wherein the first portion is configured to access first memory cells and the second portion is configured to access second memory cells; at least one via electrically connected to the first portion and the second portion at the central region; a first resistor between the first portion and the via, wherein the first resistor is configured to shield a discharge from the first portion when accessing the second memory cells; a second resistor between the second portion and the via, wherein the second resistor is configured to shield a discharge from the second portion when accessing the first memory cells; and a driver electrically connected to the via, wherein the driver is configured to generate a voltage on the first portion to access the first memory cells and generate a voltage on the second portion to access the second memory cells.

2. The apparatus of claim 1, wherein: the at least one via is a single via; the access line is a bit line or a word line; and the driver is a bit line driver or a word line driver.

3. The apparatus of claim 1, wherein: the first resistor is provided by a first segment of a resistive film overlying the via; and the second resistor is provided by a second segment of the resistive film overlying the via; wherein the central region includes a split in the access line overlying the via and between the first and second portions of the access line.

4. The apparatus of claim 3, wherein the resistive film comprises tungsten silicon nitride.

5. The apparatus of claim 3, wherein: the split is formed by removing a third portion of the access line to physically separate the first portion from the second portion; and prior to removing the third portion, the third portion is between the first portion and the second portion.

6. The apparatus of claim 5, wherein the split includes: a non-conductive material configured to prevent a discharge of current from flowing directly between the first and second portions of the access line; or an unfilled space between the first portion and the second portion.

7. The apparatus of claim 1, wherein: the memory array is part of a memory device; the access line is associated with a physical address within the memory array; and an access operation used by a controller of the memory device to select the first memory cells addresses both the first and second portions of the access line.

8. An apparatus comprising: an access line having a first portion and a second portion, wherein the first portion is configured to access memory cells of a memory array and a gap physically separates the first portion and the second portion; a via electrically connected to the first portion and the second portion; and a driver electrically connected to the via, wherein the driver is configured to generate a voltage on the first portion to access the first memory cells and generate a voltage on the second portion to access the second memory cells. ​ a resistive film having a first segment between the first portion and the via, and a second segment between the second portion and the via.

9. The apparatus of claim 8, further comprising a driver electrically connected to the via, wherein the driver is configured to generate a voltage on the first portion to access the memory cell.

10. The apparatus of claim 8, wherein the gap is a split formed in the access line by removing a third portion of the access line to physically separate the first portion from the second portion of the access line.

11. The apparatus of claim 8, wherein a material forming the resistive film has a higher resistivity than a material forming the first and second portions of the access line.

12. The apparatus of claim 8, wherein the resistive film comprises at least one of: tungsten silicon nitride; titanium silicon nitride; tungsten nitride; titanium nitride; tungsten silicide; or cobalt silicide.

13. The apparatus of claim 8, wherein each of the first and second portions is configured to access memory cells located above and below the respective portion.

14. The apparatus of claim 8, wherein the memory array has a cross-point architecture, and the memory cell is: a memory cell comprising a chalcogenide; a memory cell comprising a selection device and a phase change material as a memory element; a self-selecting memory cell comprising a chalcogenide; or a resistive memory cell.

15. The apparatus of claim 8, wherein the gap overlies a third portion of the resistive film, and the third portion is between the first segment and the second segment.

16. A method comprising: forming a via; forming a resistive film overlying the via; forming an access line overlying the resistive film; and patterning the access line to provide first and second portions, wherein the patterning physically separates the first portion from the second portion, and wherein the first portion is configured to access memory cells of a memory array; wherein a first segment of the resistive film is between the first portion and the via, and a second segment of the resistive film is between the second portion and the via.

17. The method of claim 16, wherein patterning the access line comprises: forming a photoresist layer overlying the access line; patterning the photoresist layer; and performing an etch using the patterned photoresist layer to etch the access line, wherein performing the etch includes etching the access line to provide a split overlying the via and between the first and second portions.

18. The method of claim 17, wherein performing the etch further includes etching the resistive film to physically separate the first and second segments.

19. The method of claim 16, wherein: the first and second segments of the resistive film each have a thickness of 1 to 20 nanometers; the first segment has a width of 10 to 200 nanometers; and the second segment has a width of 10 to 200 nanometers. ​ ​ 20. The method of claim 16, wherein the memory array is part of a memory device, the method further comprising forming a transistor circuit located beneath the memory array and electrically connected to the via, wherein the transistor circuit is configured to generate a voltage on the first portion to access the memory cell during a read or write operation, and to generate the voltage in response to a command received by a controller of the memory device from a host device.

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