Memory device and operating method thereof

Abstract

The present disclosure relates to a memory device and an operating method thereof. A memory device includes a memory block including word lines, a word line located in the middle of the word lines serving as a dummy word line, a control circuit establishing word lines stacked on one side and the other side of the dummy word line as a first sub-block and a second sub-block, respectively, performing an independent erase operation on one of the first sub-block and the second sub-block in an erase operation period, and a control logic differently setting a level of a first transfer voltage for controlling transfer of an erase common voltage to a selected sub-block and a level of a second transfer voltage for controlling transfer of the erase common voltage to an unselected sub-block in the erase operation period, applying an erase enable voltage from the erase common voltage to word lines of the selected sub-block, and floating word lines of the unselected sub-block.

Description

Technical Field

[0001] Various embodiments of the present invention relate to semiconductor design technology, and more specifically, to a memory device and a method of operating the same capable of performing erase operations based on sub-blocks. Background Technology

[0002] Memory systems are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Memory systems are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices that lose the data stored in them when power is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices that retain the data stored in them even when power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is mainly classified into NOR type memory and NAND type memory. Summary of the Invention

[0003] Various embodiments of the present invention relate to a memory device and a method of operating thereof that can perform erase operations based on sub-blocks, thereby improving memory efficiency and enhancing the reliability of erase operations.

[0004] The technical problems addressed in this disclosure are not limited to those mentioned above. Other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0005] According to an embodiment of the present invention, a memory device may include: a memory block comprising a plurality of memory cells stacked in a direction intersecting a substrate; and a plurality of word lines arranged between two or more source select lines and two or more drain select lines, wherein two or more word lines located in the middle of the plurality of word lines serve as dummy word lines; control circuitry adapted to: establish a first sub-block as a word line stacked on one side of the dummy word lines, establish a second sub-block as a word line stacked on the other side of the dummy word lines, select one of the first sub-block and the second sub-block during an erase operation period in which an erase voltage is applied to the substrate, and perform an independent erase operation only on the selected sub-block; and control logic adapted to control the control circuitry to differently set the level of a first transmission voltage for controlling the transmission of the erase common voltage to the selected sub-block and the level of a second transmission voltage for controlling the transmission of the erase common voltage to the unselected sub-block during the erase operation period, apply the erase common voltage as an erase-allowed voltage to the word lines of the selected sub-block, and float the word lines of the unselected sub-block.

[0006] According to an embodiment of the present invention, a memory device may include: a memory block comprising a plurality of memory cells stacked in a direction intersecting a substrate; and a plurality of word lines arranged between two or more source select lines and two or more drain select lines, wherein two or more word lines located in the middle of the plurality of word lines serve as dummy word lines; and control circuitry adapted to: establish a first sub-block as a word line stacked on one side of the dummy word lines, establish a second sub-block as a word line stacked on the other side of the dummy word lines, select one of the first sub-block and the second sub-block during an erase operation period in which an erase voltage is applied to the substrate, and perform an independent erase operation only on the selected sub-block, wherein during the erase operation period, the control circuitry is further adapted to: set different levels of a first transmission voltage for controlling the transmission of an erase common voltage to the selected sub-block and a second transmission voltage for controlling the transmission of the erase common voltage to the unselected sub-block, apply the erase common voltage as an erase-allowed voltage to the word lines of the selected sub-block, and float the word lines of the unselected sub-block.

[0007] According to an embodiment of the present invention, an operation method of a memory device is provided. The memory device includes: a memory block comprising a plurality of memory cells stacked in a direction intersecting a substrate; and a plurality of word lines arranged between two or more source select lines and two or more drain select lines, wherein two or more word lines located in the middle of the plurality of word lines are used as dummy word lines, wherein a word line stacked on one side of the dummy word lines is established as a first sub-block, and a word line stacked on the other side of the dummy word lines is established as a second sub-block. The operation method may include... The method includes: an erase operation, which includes selecting one of a first sub-block and a second sub-block during an erase operation period when an erase voltage is applied to the substrate, and then performing an independent erase operation only on the selected sub-block; and a transfer operation, which includes: during the erase operation period, setting the level of a first transfer voltage for controlling the transfer of the erase common voltage to the sub-block selected between the first and second sub-blocks and the level of a second transfer voltage for controlling the transfer of the erase common voltage to the unselected sub-block, applying the erase common voltage as an erase enable voltage to the word line of the selected sub-block, and floating the word line of the unselected sub-block.

[0008] According to an embodiment of the present invention, a memory device may include: a memory block comprising stacked memory cells respectively coupled to local lines arranged in a stacking direction; and control circuitry adapted to perform an erase operation on the first sub-block by transmitting an erase enable voltage to word lines coupled to a first sub-block while preventing the transmission of an erase enable voltage to word lines coupled to a second sub-block, wherein the local lines include select lines of a first group and a second group and word lines of a third group arranged between the first group and the second group, wherein the memory block is divided into a first sub-block and a second sub-block relative to a cluster of dummy word lines within the third group, and wherein the erase operation is an erase operation based on gate-induced drain leakage (GIDL).

[0009] The control circuit can also be adapted to float each of the first and second groups at the same or different timings.

[0010] The control circuit can float each of the first and second groups sequentially from the outermost line to the innermost line.

[0011] The control circuit can also be adapted to apply erase blocking voltages of different levels to each dummy word line, wherein the level of the erase blocking voltage can be increased as the dummy word lines in the cluster are arranged closer to the second subgroup.

[0012] According to an embodiment of the present invention, a memory device capable of performing an erase operation based on sub-blocks can receive a voltage and drive internal word lines in response to different transmission voltages of each sub-block.

[0013] In addition, two or more dummy word lines can be set between the sub-block selected as the erase target and the sub-block not selected as the erase target, and each can be driven to erase blocking voltage with a different level.

[0014] In addition, two or more drain select lines or source select lines can be floated sequentially in a predetermined order during the erasure operation period, starting at a time later than the time when the erasure voltage is applied to the substrate.

[0015] This technology can improve memory efficiency and enhance the reliability of erase operations. Attached Figure Description

[0016] Figure 1 This is a diagram illustrating an example of a memory system according to an embodiment of the present invention.

[0017] Figure 2 It is used to describe embodiments according to the present invention. Figure 1 A diagram showing an example of a memory device.

[0018] Figure 3 It is used to describe embodiments according to the present invention. Figure 2 A diagram showing an example of a storage block.

[0019] Figure 4 This is a diagram illustrating an example of an erase operation performed by a memory device according to an embodiment of the present invention.

[0020] Figures 5 to 8 This is a diagram illustrating an erasure operation method for a memory device according to an embodiment of the present invention. Detailed Implementation

[0021] Various examples of this disclosure are described in more detail below with reference to the accompanying drawings. However, aspects and features of the invention may be embodied in different ways to form other embodiments, including variations of any of the disclosed embodiments. Therefore, the invention is not limited to the embodiments set forth herein. Rather, the described embodiments are provided to make this disclosure thorough and complete, and to fully convey the disclosure to those skilled in the art to which this invention pertains. Throughout this disclosure, similar reference numerals denote similar portions throughout the various drawings and examples of this disclosure. It should be noted that references to “implementation,” “another embodiment,” etc., do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment.

[0022] It will be understood that although the terms “first,” “second,” “third,” etc., may be used in this document to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. Thus, a first element in one instance may be referred to as a second or third element in another instance without indicating any change in the element itself.

[0023] The accompanying drawings are not necessarily to scale, and in some cases, the scale may be exaggerated to clearly show the features of the embodiments. When an element is referred to as being connected to or coupled to another element, it should be understood that the former may be directly connected to or coupled to the latter, or electrically connected to or coupled to the latter via one or more intermediate elements between them. Additionally, it will be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or there may be one or more intermediate elements present.

[0024] The terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the invention. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. Similarly, the indefinite articles “a” and “an” mean one or more unless it is clear from the language or context that only one is intended.

[0025] It will also be understood that, when used in this specification, the terms “comprising” and “including” specify the presence of the said element and do not exclude the presence or addition of one or more other elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0026] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains in view of this disclosure. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having the meaning consistent with their meaning in the context of this disclosure and related technologies, rather than in an idealized or overly formal sense, unless expressly so defined herein.

[0027] Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. The invention may be practiced without some or all of these specific details. In other instances, well-known process structures and / or processes have not been described in detail so as not to unnecessarily obscure the invention.

[0028] It should also be noted that in some cases, it will be apparent to those skilled in the art that, unless otherwise specifically indicated, the features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment.

[0029] The embodiments of this disclosure are described in detail below with reference to the accompanying drawings, wherein similar reference numerals denote similar elements.

[0030] Figure 1 This is a diagram illustrating an example of a memory system according to an embodiment of the present invention.

[0031] Reference Figure 1 The data processing system 100 may include a host 102 that is coupled to or operatively connected to the memory system 110.

[0032] Host 102 may include any portable electronic device such as a mobile phone, MP3 player, laptop computer, etc., and any electronic device such as a desktop computer, game console, television (TV), projector, etc.

[0033] Host 102 also includes at least one operating system (OS), which typically manages and controls the functions and operations performed within host 102. The OS provides interoperability between host 102, which is coupled to memory system 110, and users of memory system 110. The OS may support functions and operations corresponding to user requests. By way of example and not limitation, OSes may be categorized as general operating systems and mobile operating systems based on the mobility of host 102. General operating systems may be categorized as personal operating systems and enterprise operating systems based on system requirements or user environment. Personal operating systems, including Windows and Chrome, may need to support services for general purposes. However, enterprise operating systems may be dedicated to protection and support for high performance, including Windows Server, Linux, Unix, etc. Furthermore, mobile operating systems may include Android, iOS, Windows Mobile, etc. Mobile operating systems may need to support services or functions for mobility (e.g., power-saving features). Host 102 may include multiple operating systems. Host 102 may execute multiple operating systems coupled to memory system 110 in response to user requests. Host 102 may send multiple commands corresponding to user requests to memory system 110, thereby executing operations corresponding to the commands within memory system 110.

[0034] The storage device for the memory system 110 may be implemented using volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM) and / or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM) and flash memory.

[0035] The memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data that the host 102 needs to access. The controller 130 may control the operation of storing data in the memory device 150.

[0036] The controller 130 and memory device 150 included in memory system 110 may be integrated into a single semiconductor device, which may be included in any of the various types of memory systems discussed above in the examples.

[0037] By way of example and not limitation, controller 130 and memory device 150 may be implemented using an SSD. When memory system 110 is used as an SSD, the operating speed of host 102 connected to memory system 110 can be improved compared to the operating speed of host 102 implemented using a hard disk. Alternatively, controller 130 and memory device 150 may be integrated into a single semiconductor device to form memory cards such as PC cards (PCMCIA), compact flash memory cards (CF), smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), general-purpose flash memory, etc.

[0038] The storage system 110 can be configured as, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet computer, a tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage unit configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a remote information network, a radio frequency identification (RFID) device, or part of one of various components configured for a computing system.

[0039] Figure 2 It is used to describe embodiments according to the present invention. Figure 1 A diagram showing an example of a memory device.

[0040] Reference Figure 2The memory device 150 according to the embodiment may include a memory cell array 151 for storing data. The memory device 150 may include peripheral circuitry 152 to 155, configured to perform programming operations to store data in the memory cell array 151, read operations to output the stored data, and erase operations to erase the stored data. The memory device 150 may include control logic 156, configured to control the memory controller (…). Figure 1 Under the control of 130), the peripheral circuits 152 to 155 are controlled. The peripheral circuits 152 to 155 may include a line decoder 152, a page buffer 153, an I / O buffer 154, and a voltage generator 155.

[0041] The memory cell array 151 may include multiple memory blocks BLK1 to BLKn, where n is a positive integer. Local lines LL and bit lines BL may be connected to memory blocks BLK1 to BLKn. For example, local lines LL may include two or more source select lines SSL, two or more drain select lines DSL, and multiple word lines WL disposed between the source select lines SSL and drain select lines DSL. Local lines LL may also include two or more dummy lines DWL disposed between word lines WL. In addition, local lines LL may include substrate bias lines PWL. Local lines LL may be connected to memory blocks BLK1 to BLKn, and bit lines BL may be collectively connected to memory blocks BLK1 to BLKn. Memory blocks BLK1 to BLKn may be implemented as 2D or 3D structures. For example, in memory blocks BLK1 to BLKn with 2D structures, memory cells may be arranged in a direction parallel to the substrate. For example, in memory blocks BLK1 to BLKn with 3D structures, memory cells may be stacked in a direction intersecting the substrate.

[0042] The line decoder 152 is electrically connected to the memory cell array 151 via the word line WL, select lines DSL and SSL, and dummy line DWL. The page buffer 153 is electrically connected to the memory cell array 151 via the bit line BL. The voltage generator 155 is electrically connected to the memory cell array 151 via the substrate bias line PWL.

[0043] Each of the memory blocks BLK1 to BLKn may include two or more sub-blocks. Each sub-block may correspond to an erase unit. Each of the two or more sub-blocks may include multiple cell strings. Each cell string may include multiple memory cells stacked in a direction intersecting the substrate.

[0044] The row decoder 152 can be configured to operate in response to control of control logic 156. The row decoder 152 can receive a row address RADD from control logic 156. The row decoder 152 can be configured to decode the received row address RADD. The row decoder 152 can select any one of the memory blocks BLK1 to BLKn included in the memory cell array 151 in response to the decoded row address RADD. The row decoder 152 can transmit operating voltages S, SS, EPS, T1, and T2 from voltage generator 155 to the word line WL, select line DSL and SSL, and dummy line DWL of the selected memory block. For example, the operating voltages S, SS, EPS, T1, and T2 may include an erase blocking voltage EPS, an erase common voltage S, a first transfer voltage T1, a second transfer voltage T2, and a select voltage SS.

[0045] Page buffer 153 can operate as a write driver or a sense amplifier depending on the operating mode. During a programming operation, page buffer 153 can transmit a voltage corresponding to the data to be programmed to the bit line BL of memory cell array 151. During a read operation, page buffer 153 can sense the data stored in the selected memory cell via bit line BL and transmit the sensed data to I / O buffer 154. During an erase operation, page buffer 153 can float the bit line BL of memory cell array 151.

[0046] During programming operations, I / O buffer 154 can transfer write data from external input to page buffer 153. During read operations, I / O buffer 154 can output data provided from page buffer 153 to the outside. I / O buffer 154 can transfer address ADD or command CMD from external input to control logic 156.

[0047] Voltage generator 155 can be connected to line decoder 152 and control logic 156. Voltage generator 155 can be configured to generate various voltages required for programming, reading, and erasing operations in response to voltage control signal VCON from control logic 156. The voltage generated by voltage generator 155 can be transmitted via line decoder 152 to multiple lines DWL, DSL, WL, and SSL connected to memory cell array 151.

[0048] A voltage generator 155 can be connected to the substrate of the memory cell array 151. The substrate can be connected to the voltage generator 155 via a substrate bias line PWL. The erase voltage generated by the voltage generator 155 can be transmitted to the substrate of the memory cell array 151.

[0049] Control logic 156 can be connected to row decoder 152, page buffer 153, I / O buffer 154, and voltage generator 155. Control logic 156 can output a voltage control signal VCON in response to a command CMD input through I / O buffer 154 to generate the voltage required for the operation of memory device 150. Control logic 156 can also output a row address signal RADD and a column address signal CADD in response to an address signal ADD input through I / O buffer 154.

[0050] During the erase operation period, control logic 156 can control voltage generator 155 to transmit the erase voltage generated by voltage generator 155 to the substrate of a selected memory block from a plurality of memory blocks BLK1 to BLKn included in memory cell array 151.

[0051] During the erase operation period, control logic 156 can control voltage generator 155 and row decoder 152 to supply the erase common voltage S to the selected memory block. During the erase operation period, control logic 156 can control voltage generator 155 and row decoder 152 to apply a first transmission voltage T1 to control the transmission of the erase common voltage S to the word line of the selected sub-block among two or more sub-blocks included in the selected memory block that is selected as the erase target. During the erase operation period, control logic 156 can control voltage generator 155 and row decoder 152 to apply a second transmission voltage T2 to control the transmission of the erase common voltage S to the sub-blocks among two or more sub-blocks included in the selected memory block that are not selected as the erase target. Through this operation, control logic 156 can control row decoder 152 to transmit the erase common voltage S as an erase-allowed voltage to the word line of the selected erase target sub-block during the erase operation period. In addition, control logic 156 can control line decoder 152 to float word lines of sub-blocks that are not selected as erase targets during the erase operation period.

[0052] During the erase operation period, control logic 156 can float the source select line SSL and drain select line DSL of the selected memory block. During the erase operation period, control logic 156 can apply a selection voltage SS to the source select line SSL and float the drain select line DSL at a first time point when the erase voltage begins to be applied to the substrate of the selected memory block, and then float the source select line SSL for a preset period starting at a second time point later than the first time point. In another embodiment, during the erase operation period, control logic 156 can apply a selection voltage SS to the drain select line DSL and float the source select line SSL at a first time point when the erase voltage begins to be applied to the substrate of the selected memory block, and then float the drain select line DSL for a preset period starting at a second time point later than the first time point. In another embodiment, during the erase operation period, control logic 156 may apply a selection voltage SS to each of the source select line SSL and drain select line DSL at a first time point when the erase voltage begins to be applied to the substrate of the selected memory block, and then float the source select line SSL and drain select line DSL for a preset time starting at a second time point later than the first time point. At this time, control logic 156 may float two or more source select lines SSL sequentially from the source select line closer to the substrate to the source select line farther from the substrate. Furthermore, control logic 156 may float two or more drain select lines DSL sequentially from the drain select line farther from the substrate to the drain select line closer to the substrate.

[0053] During the erase operation period, control logic 156 can control voltage generator 155 to apply erase blocking voltage EPS to dummy lines DWL. Specifically, during the erase operation period, control logic 156 can control voltage generator 155 to apply erase blocking voltage EPS with different levels to two or more dummy lines DWL.

[0054] To improve the integration density of the memory device 150, it is necessary to increase the number of cell strings included in each of the memory blocks BLK1 to BLKn. To improve the efficiency of the memory device 150, it is necessary to reduce the time required to rewrite data after erasing data stored in each of the memory blocks BLK1 to BLKn. However, as the number of cell strings included in each of the memory blocks BLK1 to BLKn increases, existing schemes that perform erase operations based on memory blocks require a significant amount of time during the erase operation period, thus degrading memory efficiency.

[0055] In this embodiment, each of the storage blocks BLK1 to BLKn can be divided into two or more sub-blocks, allowing erase operations to be performed based on these sub-blocks. The sub-block-based erase operation scheme refers to erasing a portion of the storage block's capacity. This scheme can quickly and efficiently erase small amounts of data, thereby improving memory efficiency.

[0056] Figure 3 It is used to describe embodiments according to the present invention. Figure 2 A diagram showing an example of a storage block.

[0057] Reference Figure 3 The storage block BLKi may include multiple cell strings CSTR11 to CSTR14 and CSTR21 to CSTR24 connected between multiple bit lines BL and a common source line CSL. Strings CSTR11 to CSTR14 and CSTR21 to CSTR24 may be configured in the same manner.

[0058] Each of CSTR11 to CSTR14 and CSTR21 to CSTR24 can be connected between the corresponding bit line BL and the common source line CSL.

[0059] Each of strings CSTR11 to CSTR14 and CSTR21 to CSTR24 may include a plurality of drain selection transistors DST<1:2>, a plurality of memory cells MC<1:8>, a plurality of dummy memory cells DMC<1:2>, and a plurality of source selection transistors SST<1:2> connected in series between the corresponding bit line BL and the common source line CSL. Memory cells MC<1:8> indicate memory cells used to store valid data, and dummy memory cells DMC<1:2> indicate memory cells not used to store valid data.

[0060] The source selection transistor SST<1:2>, memory cell MC<1:8>, dummy memory cell DMC<1:2>, and drain selection transistor DST<1:2> can be arranged sequentially on the height direction VD. In this case, the dummy memory cell DMC<1:2> can be located in the middle of the memory cell MC<1:8>. For example, as... Figure 3 As shown, the dummy memory cell DMC<1:2> can be arranged between the first to fourth memory cells MC<1:4> and the fifth to eighth memory cells MC<5:8>.

[0061] The gate of the source select transistor SST<1:2> can be connected to the corresponding source select line SSL<1:2>. The gate of the memory cell MC<1:8> can be connected to the corresponding word line WL<1:8>. The gate of the dummy memory cell DMC<1:2> can be connected to the corresponding dummy word line WL<1:2>. The gate of the drain select transistor DST<1:2> can be connected to the corresponding drain select line DSL<1:2>.

[0062] A common source line (CSL) may be formed in a substrate (not shown). The substrate may have a main surface extending in a first direction (FD) and a second direction (SD). The common source line (CSL) may extend in the second direction (SD). The first direction (FD) and the second direction (SD) may intersect each other at right angles.

[0063] Bit line BL can be extended on the first direction FD and arranged on the second direction SD. Source select line SSL<1:2>, word line WL<1:8>, dummy word line DWL<1:2> and drain select line DSL<1:2> can be extended on the second direction SD.

[0064] Cell strings CSTR11 to CSTR14 and CSTR21 to CSTR24 may extend in a height direction VD perpendicular to the main surface of the substrate and be arranged in a first direction FD and a second direction SD. In each of cell strings CSTR11 to CSTR14 and CSTR21 to CSTR24, the memory cell MC closest to the source selection transistor SST<1:2> <1> The memory cell MC can be located at the minimum height, closest to the drain selection transistor DST<1:2>. <8> It can be located at the maximum height.

[0065] For example, Figure 3 Each of the cell strings CSTR11 to CSTR14 and CSTR21 to CSTR24 is shown to include two drain-select transistors (DST<1:2>) and two source-select transistors (SST<1:2>). However, each of the cell strings CSTR11 to CSTR14 and CSTR21 to CSTR24 may include two or more drain-select transistors or two or more source-select transistors.

[0066] For example, Figure 3 Each of the cell strings CSTR11 to CSTR14 and CSTR21 to CSTR24 is shown to include eight main memory cells MC<1:8>. However, each of the cell strings CSTR11 to CSTR14 and CSTR21 to CSTR24 may include two or more memory cells.

[0067] For example, Figure 3 Each of the cell strings CSTR11 to CSTR14 and CSTR21 to CSTR24 is shown to include two dummy memory cells DMC<1:2> between four main memory cells MC<1:4> and another four main memory cells MC<5:8>. However, each of the cell strings CSTR11 to CSTR14 and CSTR21 to CSTR24 may include two or more dummy memory cells.

[0068] The storage block BLKi may include a first sub-block 1 and a second sub-block 2. The first sub-block 1 may include the first to fourth word lines WL<1:4>, and the second sub-block 2 may include the fifth to eighth word lines WL<5:8>. In this case, the first sub-block 1 and the second sub-block 2 may be positioned on the height direction VD. That is, the first to fourth word lines WL<1:4> superimposed on one side of the two dummy word lines DWL<1:2> can be established as the first sub-block 1, and the fifth to eighth word lines WL<5:8> superimposed on the other side can be established as the second sub-block 2.

[0069] The first sub-block 1 and the second sub-block 2 can be erased independently of each other. That is, any sub-block in the first sub-block 1 and the second sub-block 2 can be selected such that the erase operation is performed only on the selected sub-block and not on the unselected sub-blocks. In this case, an erase blocking voltage can be applied to the two dummy word lines DWL<1:2> located between the first to fourth word lines WL<1:4> and the fifth to eighth word lines WL<5:8> to erase the first sub-block 1 and the second sub-block 2 independently. The erase blocking voltages applied to the two dummy word lines DWL<1:2> can have different levels.

[0070] So far, we have described, as an example, a method for creating a sub-block defined in a storage block BLKi. However, the criteria for creating sub-blocks are not limited to the examples shown. That is, Figure 3 This example shows a physical block BLKi comprising two sub-blocks, Sub-block1 and Sub-block2. However, a physical block BLKi can include three or more sub-blocks. Furthermore, Figure 3 The example shown depicts a sub-block1 or sub-block2 comprising four word lines. However, it will be understood that a sub-block1 or sub-block2 may include three or fewer word lines, or five or more word lines. Furthermore, Figure 3 An example is shown that includes two dummy word lines DWL<1:2> to create two sub-blocks, Sub-block1 and Sub-block2. However, it will be understood that one dummy word line or three or more dummy word lines may be included.

[0071] Figure 4 This is a diagram illustrating an example of an erase operation performed by a memory device according to an embodiment of the present invention.

[0072] Reference Figures 1 to 4The following describes an example of an erase operation performed by a memory device 150 according to an embodiment of the present invention.

[0073] First, as referenced Figure 2 As described, the memory device 150 may include a memory cell array 151, peripheral circuitry 152 to 155, and control logic 156.

[0074] The memory cell array 151 may include a plurality of memory cells stacked in a direction intersecting the substrate, and a plurality of word lines WL<1:8> and DWL<1:2> arranged between two or more source select lines SSL<1:2> and two or more drain select lines DSL<1:2>. The memory cell array 151 may include a plurality of memory blocks BLK1 to BLKn, wherein two or more word lines located in the middle of the plurality of word lines WL<1:8> are used as dummy word lines DWL<1:2>.

[0075] Peripheral circuits 152 to 155 can establish word lines WL<1:4> stacked on one side of the dummy word lines DWL<1:2> as a first sub-block 1, and word lines WL<5:8> stacked on the other side of the dummy word lines DWL<1:2> as a second sub-block 2. The dummy word lines DWL<1:2> are located between multiple word lines WL<1:8> and DWL<1:2> included in each of the memory blocks BLK1 to BLKn. At this time, reference has been made to... Figure 3 An implementation of two or more sub-blocks, Sub-block1 and Sub-block2, including each of the storage blocks BLK1 to BLKn is described.

[0076] Peripheral circuits 152 to 155 can perform an erase operation by applying an erase voltage to the substrate of a selected memory block among a plurality of memory blocks BLK1 to BLKn. That is, peripheral circuits 152 to 155 can perform an erase operation by applying an erase voltage to the common source line CSL of the selected memory block. During the erase operation period when the erase voltage is applied to the substrate of the selected memory block, peripheral circuits 152 to 155 can select either a first sub-block (Sub-block 1) or a second sub-block (Sub-block 2) included in the selected memory block, and then perform an independent erase operation only on the selected sub-block. For example, when the first sub-block (Sub-block 1) is selected as the erase target and the second sub-block (Sub-block 2) is not selected as the erase target, the erase operation can be performed only on the first sub-block (Sub-block 1) and not on the second sub-block (Sub-block 2).

[0077] For reference, the operation of erasing a programmed memory cell by raising the potential level of the channel of the selected memory block through applying an erase voltage to the substrate of the selected memory block can be defined as a gate-induced drain leakage (GIDL) based erase operation. That is, during a GIDL based erase operation, electrons stored in the charge storage layer of a programmed memory cell among a plurality of memory cells in the selected memory block can be de-trapped through the high potential level of the channel and the low potential level of the word line. Therefore, the programmed memory cell can be transitioned to an erased state.

[0078] During the erase operation, peripheral circuits 152 to 155 can set the levels of the first transmission voltage T1 and the second transmission voltage T2 to different levels. The first transmission voltage T1 can be used to control the transmission of the erase common voltage S to the sub-block selected as the erase target between the first sub-block 1 and the second sub-block 2 included in the selected memory block. The second transmission voltage T2 can be used to control the transmission of the erase common voltage S to the sub-blocks not selected as erase targets between the first sub-block 1 and the second sub-block 2 included in the selected memory block. Through this operation, peripheral circuits 152 to 155 can apply the erase common voltage S as the erase enable voltage to the word lines of the selected sub-blocks and float the word lines of the unselected sub-blocks. Peripheral circuits 152 to 155 can set the level of the first transmission voltage T1 to be a predetermined level higher than the level of the erase common voltage S, so that the erase common voltage S is transmitted to the selected sub-blocks as the erase enable voltage. Peripheral circuits 152 to 155 can set the level of the second transmission voltage T2 to be equal to or lower than the level of the erase common voltage S, so as to float the word lines connected to the unselected subblock by preventing the erase common voltage S from being transmitted to the word lines of the unselected subblock. For example, the erase common voltage S can be set to the ground voltage level VSS or a negative level below the ground voltage VSS. Therefore, the erase enable voltage can have the ground voltage level VSS or a negative level below the ground voltage VSS. In addition, the level of the first transmission voltage T1 can be set to be higher than the ground voltage VSS, that is, a level between 3V and 4.5V. In addition, the level of the second transmission voltage T2 can be set to the ground voltage level VSS or a negative level below the ground voltage VSS.

[0079] Peripheral circuits 152 to 155 can apply an erase blocking voltage to a dummy word line DWL<1:2> located between word lines WL<1:4> of the first sub-block 1 and word lines WL<5:8> of the second sub-block 2, thereby minimizing the impact of an erase operation on the selected sub-block on unselected sub-blocks between the first sub-block 1 and the second sub-block 2. Since there are two or more dummy word lines DWL<1:2>, peripheral circuits 152 to 155 can apply an erase blocking voltage with a relatively low potential level to the dummy word lines of DWL<1:2> closer to the selected sub-block, and apply an erase blocking voltage with a relatively high potential level to the dummy word lines of DWL<1:2> further away from the selected sub-block. In this case, the erase blocking voltage can have a potential level higher than the erase allow voltage and lower than the erase voltage. For example, peripheral circuits 152 to 155 can apply an erase blocking voltage of 5V to one of the two dummy word lines DWL<1:2> closer to the sub-block selected as the erase target, and apply an erase blocking voltage of 10V to the other dummy word line further away from the sub-block selected as the erase target.

[0080] During the erase operation period, peripheral circuits 152 to 155 can float the source select line SSL and drain select line DSL of the selected memory block. During the erase operation period, peripheral circuits 152 to 155 can apply a selection voltage SS to the source select line SSL and float the drain select line DSL at a first time point when the erase voltage begins to be applied to the substrate of the selected memory block, and then float the source select line SSL for a preset period starting at a second time point later than the first time point. In another embodiment, during the erase operation period, peripheral circuits 152 to 155 can apply a selection voltage SS to the drain select line DSL and float the source select line SSL at a first time point when the erase voltage begins to be applied to the substrate of the selected memory block, and then float the drain select line DSL for a preset period starting at a second time point later than the first time point. In another embodiment, during the erase operation period, peripheral circuits 152 to 155 may apply a selection voltage SS to each of the source select line SSL and drain select line DSL at a first time point when the erase voltage begins to be applied to the substrate of the selected memory block, and then float the source select line SSL and drain select line DSL for a preset time starting at a second time point later than the first time point. At this time, peripheral circuits 152 to 155 may sequentially float two or more source select lines SSL from the source select line closer to the substrate to the source select line farther from the substrate. Furthermore, peripheral circuits 152 to 155 may sequentially float two or more drain select lines DSL from the drain select line farther from the substrate to the drain select line closer to the substrate.

[0081] More specifically, the line decoder 152 in the peripheral circuits 152 to 155 may include a block decoder 1521, a line driver 1522, a first selection transistor 1523, and a second selection transistor 1524.

[0082] Block decoder 1521 can decode block address BLK_ADD and output block selection signal SEL_BLK, first sub-select signal SEL_SUB1, and second sub-select signal SEL_SUB2. At this time, block address BLK_ADD can be included in row address RADD (see...). Figure 2 In the context of memory selection, for example, in response to the block address BLK_ADD, the block decoder 1521 can divide multiple memory blocks BLK1 to BLKn into memory blocks selected as operation targets (read, program, or erase targets) and unselected memory blocks. For example, in the case of a memory block selected as an operation target among the multiple memory blocks BLK1 to BLKn, the block selection signal SEL_BLK can be set to a logic "high" level. In the case of a memory block not selected as an operation target, the block selection signal SEL_BLK can be set to a logic "low" level.

[0083] The block decoder 1521 can, in response to the block address BLK_ADD, establish a first sub-block (Sub-block1) and a second sub-block (Sub-block2) included in the selected memory block as a sub-block selected as an erase target and a sub-block not selected as an erase target. At this time, the block decoder 1521 can set the level of the sub-selection signal SEL_SUB1 or SEL_SUB2 corresponding to the sub-block selected as an erase target to the level of a first transmission voltage T1, and set the level of the sub-selection signal SEL_SUB1 or SEL_SUB2 corresponding to the sub-block not selected as an erase target to the level of a second transmission voltage T2. For example, when the first sub-block (Sub-block1) is selected as an erase target and the second sub-block (Sub-block2) is not selected as an erase target, the block decoder 1521 can set the level of the first sub-selection signal SEL_SUB1 to the level of the first transmission voltage T1 and set the level of the second sub-selection signal SEL_SUB2 to the level of the second transmission voltage T2.

[0084] For reference, when performing operations other than erasure (read and programming operations) on word lines WL<1:8> of the first sub-block 1 and the second sub-block 2, the levels of the sub-select signals SEL_SUB1 and SEL_SUB2 can be set such that the voltage generated by the line driver 1522 drives the word lines WL<1:8> without any change in voltage level.

[0085] The first selection transistor 1523 may include multiple transistors for applying the voltage generated by the line driver 1522 to the word lines WL<1:4> of the first sub-block 1 in response to the first sub-select signal SEL_SUB1 generated by the block decoder 1521. For example, when the first sub-select signal SEL_SUB1 is set to the level of the first transfer voltage T1 during the erase operation period, the first selection transistor 1523 may output the erase common voltage S generated by the line driver 1522 as the erase enable voltage in response to the first transfer voltage T1, thereby driving the word lines WL<1:4> of the first sub-block 1 to the erase enable voltage. Alternatively, when the first sub-select signal SEL_SUB1 is set to the level of the second transfer voltage T2 during the erase operation period, the first selection transistor 1523 may block the transmission of the erase common voltage S generated by the line driver 1522 in response to the second transfer voltage T2, thereby floating the word lines WL<1:4> of the first sub-block 1.

[0086] The second selection transistor 1524 may include multiple transistors for driving the word lines WL<5:8> of the second sub-block 2 via the voltage generated by the line driver 1522 in response to the second sub-select signal SEL_SUB2 generated by the block decoder 1521. For example, when the second sub-select signal SEL_SUB2 is set to the level of the first transfer voltage T1 during the erase operation period, the second selection transistor 1524 may output the erase common voltage S generated by the line driver 1522 as the erase enable voltage in response to the first transfer voltage T1, thereby driving the word lines WL<5:8> of the second sub-block 2 to the erase enable voltage. Alternatively, when the second sub-select signal SEL_SUB2 is set to the level of the second transfer voltage T2 during the erase operation period, the second selection transistor 1524 may block the transmission of the erase common voltage S generated by the line driver 1522 in response to the second transfer voltage T2, thereby floating the word lines WL<5:8> of the second sub-block 2.

[0087] The line driver 1522 can generate various drive voltages VSSL<1:2>, VWL<1:8>, VDWL<1:2>, and VDSL<1:2> for driving the word lines WL<1:8> and DWL<1:2>, source select line SSL<1:2>, and drain select line DSL<1:2> in response to the block select signal SEL_BLK output from the block decoder 1521. At this time, the various drive voltages VSSL<1:2>, VWL<1:8>, VDWL<1:2>, and VDSL<1:2> generated by the line driver 1522 can have various levels depending on the type of operation performed on the selected memory block (read operation, programming operation, and erase operation).

[0088] Figures 5 to 8 This is a diagram illustrating an erasure operation method of a memory device according to an embodiment of the present disclosure.

[0089] Figures 1 to 5 This illustrates a scenario where the erase operation is performed on the second sub-block 2 but not on the first sub-block 1, and the first sub-block 1 and the second sub-block 2 are included in a storage block selected from a plurality of storage blocks BLK1 to BLKn.

[0090] Specifically, an erase voltage can be applied to the substrate of the selected memory block to perform an erase operation on the second sub-block 2. That is, an erase voltage can be applied to the common source line CSL of the selected memory block to perform an erase operation on the second sub-block 2.

[0091] During the erase operation period when the erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply the erase common voltage S to the first sub-block 1 and the second sub-block 2. At this time, since no erase operation is performed on the first sub-block 1, the block decoder 1521 included in the line decoder 152 can set the level of the first sub-select signal SEL_SUB1 to the level of the second transmission voltage T2. Therefore, the erase common voltage S transmitted from the line driver 1522 to the first sub-block 1 can not be transmitted to the word line WL<1:4> of the first sub-block 1, and the word line WL<1:4> of the first sub-block 1 can be floated. Furthermore, since an erase operation is performed on the second sub-block 2, the block decoder 1521 included in the line decoder 152 can set the level of the second sub-select signal SEL_SUB2 to the level of the first transmission voltage T1. Therefore, the erase common voltage S transmitted from the line driver 1522 to the second sub-block 2 can be transmitted as the erase enable voltage to the word line WL<5:8> of the second sub-block 2.

[0092] During the erase operation period when erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply erase blocking voltages EPS1 and EPS2 to the dummy word line DWL<1:2> located between the word lines WL<1:4> of the first sub-block 1 and the word lines WL<5:8> of the second sub-block 2. At this time, since the second sub-block 2 is the sub-block selected as the erase target and the first sub-block 1 is not selected as the erase target, the first erase blocking voltage EPS1, which has a relatively low level, can be applied to the second dummy word line DWL<1:2> closer to the second sub-block 2. <2> Furthermore, a second erase blocking voltage EPS2 with a relatively high level can be applied to the first dummy word line DWL between the dummy word lines DWL<1:2>, further away from the second sub-block 2. <1> .

[0093] During the erase operation period when the erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can float the drain select line DSL<1:2> and the source select line SSL<1:2>.

[0094] Figures 1 to 4 and Figure 6 This illustrates a scenario where the erase operation is performed on the second sub-block 2 but not on the first sub-block 1, and the first sub-block 1 and the second sub-block 2 are included in a storage block selected from a plurality of storage blocks BLK1 to BLKn.

[0095] Specifically, an erase voltage can be applied to the substrate of the selected memory block to perform an erase operation on the second sub-block 2. That is, an erase voltage can be applied to the common source line CSL of the selected memory block to perform an erase operation on the second sub-block 2.

[0096] During the erase operation period when the erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply the erase common voltage S to the first sub-block 1 and the second sub-block 2. At this time, since no erase operation is performed on the first sub-block 1, the block decoder 1521 included in the line decoder 152 can set the level of the first sub-select signal SEL_SUB1 to the level of the second transmission voltage T2. Therefore, the erase common voltage S transmitted from the line driver 1522 to the first sub-block 1 can not be transmitted to the word line WL<1:4> of the first sub-block 1, and the word line WL<1:4> of the first sub-block 1 can be floated. Furthermore, since an erase operation is performed on the second sub-block 2, the block decoder 1521 included in the line decoder 152 can set the level of the second sub-select signal SEL_SUB2 to the level of the first transmission voltage T1. Therefore, the erase common voltage S transmitted from the line driver 1522 to the second sub-block 2 can be applied as an erase enable voltage to the word line WL<5:8> of the second sub-block 2.

[0097] During the erase operation period when erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply erase blocking voltages EPS1 and EPS2 to the dummy word line DWL<1:2> located between the word lines WL<1:4> of the first sub-block 1 and the word lines WL<5:8> of the second sub-block 2. At this time, since the second sub-block 2 is the sub-block selected as the erase target and the first sub-block 1 is not selected as the erase target, the first erase blocking voltage EPS1, which has a relatively low level, can be applied to the second dummy word line DWL<1:2> closer to the second sub-block 2. <2> Furthermore, a second erase blocking voltage EPS2 with a relatively high level can be applied to the first dummy word line DWL between the dummy word lines DWL<1:2>, further away from the second sub-block 2. <1> .

[0098] During the erase operation period when the erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can float the drain selection line DSL<1:2>.

[0099] During the erase operation period when an erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply a selection voltage SS to the source select lines SSL<1:2> at a first time point during the erase operation period when the erase voltage begins to be applied to the substrate of the selected memory block, and float the source select lines SSL<1:2> for a preset time starting at a second time point later than the first time point. At this time, the line driver 1522 can float two or more source select lines SSL<1:2> sequentially from the source select lines closer to the substrate to the source select lines farther from the substrate. For example, the line driver 1522 can apply the selection voltage SS to the first source select line SSL<1:2> closer to the substrate between two source select lines SSL<1:2> at the first time point. <1> And at the second time point, the first source selection line SSL will be selected. <1> Floating. On the other hand, the line driver 1522 can apply the selection voltage SS to the second source select line SSL, which is further away from the substrate between the two source select lines SSL<1:2>, at a first time point. <2> Furthermore, the second source selection line SSL was selected after the first time point had passed since the second time point. <2> Floating.

[0100] When the target level of the erase voltage is 20V and the third time point is a preset time point elapsed from the second time point, the period between the first and third time points is the period during which the erase voltage level rises from 0V to 20V. The period between the second time point and the time point elapsed from the second time point can be a period during which the erase voltage level rises by 1V. For example, when the erase voltage level is 8V at the second time point, the erase voltage level can be 9V at the time point elapsed from the second time point, and the erase voltage can rise to the target level of 20V. Furthermore, the time point elapsed from the second time point can be earlier than the third time point.

[0101] Figures 1 to 4 and Figure 7 This illustrates a scenario where the erase operation is performed on the first sub-block 1 but not on the second sub-block 2, and the first sub-block 1 and the second sub-block 2 are included in a storage block selected from a plurality of storage blocks BLK1 to BLKn.

[0102] Specifically, an erase voltage can be applied to the substrate of the selected memory block to perform an erase operation on the first sub-block 1. That is, the erase voltage can be applied to the common source line CSL of the selected memory block to perform an erase operation on the first sub-block 1.

[0103] During the erase operation period when the erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply the erase common voltage S to the first sub-block 1 and the second sub-block 2. At this time, since no erase operation is performed on the second sub-block 2, the block decoder 1521 included in the line decoder 152 can set the level of the second sub-select signal SEL_SUB2 to the level of the second transmission voltage T2. Therefore, the erase common voltage S transmitted from the line driver 1522 to the second sub-block 2 can not be transmitted to the word line WL<5:8> of the second sub-block 2, and the word line WL<5:8> of the second sub-block 2 can be floated. Furthermore, since an erase operation is performed on the first sub-block 1, the block decoder 1521 included in the line decoder 152 can set the level of the first sub-select signal SEL_SUB1 to the level of the first transmission voltage T1. Therefore, the erase common voltage S transmitted from the line driver 1522 to the first sub-block 1 can be transmitted as the erase enable voltage to the word line WL<1:4> of the first sub-block 1.

[0104] During the erase operation period when erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply erase blocking voltages EPS1 and EPS2 to the dummy word lines DWL<1:2> located between the word lines WL<1:4> of the first sub-block 1 and the word lines WL<5:8> of the second sub-block 2. At this time, since the first sub-block 1 is the sub-block selected as the erase target and the second sub-block 2 is not selected as the erase target, the first erase blocking voltage EPS1, which has a relatively low level, can be applied to the first dummy word line DWL<1:2> closer to the first sub-block 1. <1> Furthermore, a relatively high level of the second erase blocking voltage EPS2 can be applied to the second dummy word lines DWL<1:2> further away from the first sub-block 1 between the dummy word lines DWL<1:2>. <2> .

[0105] During the erase operation period when the erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can float the source selection line SSL<1:2>.

[0106] During the erase operation period when an erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply a selection voltage SS to the drain selection lines DSL<1:2> at a first time point during the erase operation period when the erase voltage begins to be applied to the substrate of the selected memory block, and float the drain selection lines DSL<1:2> for a preset time starting at a second time point later than the first time point. At this time, the line driver 1522 can float two or more drain selection lines DSL<1:2> sequentially from the drain selection lines farther from the substrate to the drain selection lines closer to the substrate. For example, the line driver 1522 can apply the selection voltage SS to the second drain selection line DSL<1:2> farther from the substrate between the two drain selection lines DSL<1:2> at the first time point. <2> And at the second time point, the second drain selection line DSL <2> Floating. On the other hand, the line driver 1522 can apply the selection voltage SS to the first drain selection line DSL, which is closer to the substrate between the two drain selection lines DSL<1:2>, at a first time point. <1> And at the time point from the second time point to the first time point, the first drain selection line DSL will be selected. <1> Floating.

[0107] When the target level of the erase voltage is 20V and the third time point is a preset time elapsed from the second time point, the period between the first and third time points is the period during which the erase voltage level rises from 0V to 20V. The period between the second time point and the time point from the second time point elapsed after the first time point can be a period during which the erase voltage level rises by 1V. For example, when the erase voltage level is 8V at the second time point, the erase voltage level can be 9V, and the erase voltage can rise to the target level of 20V at the time point from the second time point elapsed after the first time point. Furthermore, the time point from the second time point elapsed after the first time point can be earlier than the third time point.

[0108] Figures 1 to 4 and Figure 8 This illustrates a scenario where the erase operation is performed on the first sub-block 1 but not on the second sub-block 2, and the first sub-block 1 and the second sub-block 2 are included in a storage block selected from a plurality of storage blocks BLK1 to BLKn.

[0109] Specifically, an erase voltage can be applied to the substrate of the selected memory block to perform an erase operation on the first sub-block 1. That is, an erase voltage can be applied to the common source line CSL of the selected memory block to perform an erase operation on the first sub-block 1.

[0110] During the erase operation period when the erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply the erase common voltage S to the first sub-block 1 and the second sub-block 2. At this time, since no erase operation is performed on the second sub-block 2, the block decoder 1521 included in the line decoder 152 can set the level of the second sub-select signal SEL_SUB2 to the level of the second transmission voltage T2. Therefore, the erase common voltage S transmitted from the line driver 1522 to the second sub-block 2 can not be transmitted to the word line WL<5:8> of the second sub-block 2, and the word line WL<5:8> of the second sub-block 2 can be floated. Furthermore, since an erase operation is performed on the first sub-block 1, the block decoder 1521 included in the line decoder 152 can set the level of the first sub-select signal SEL_SUB1 to the level of the first transmission voltage T1. Therefore, the erase common voltage S transmitted from the line driver 1522 to the first sub-block 1 can be transmitted as the erase enable voltage to the word line WL<1:4> of the first sub-block 1.

[0111] During the erase operation period when erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply erase blocking voltages EPS1 and EPS2 to the dummy word lines DWL<1:2> located between the word lines WL<1:4> of the first sub-block 1 and the word lines WL<5:8> of the second sub-block 2. At this time, since the first sub-block 1 is the sub-block selected as the erase target and the second sub-block 2 is not selected as the erase target, the first erase blocking voltage EPS1, which has a relatively low level, can be applied to the first dummy word line DWL<1:2> closer to the first sub-block 1. <1> Furthermore, a relatively high level of the second erase blocking voltage EPS2 can be applied to the second dummy word lines DWL<1:2> further away from the first sub-block 1 between the dummy word lines DWL<1:2>. <2> .

[0112] During the erase operation period when an erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply a selection voltage SS to the source select lines SSL<1:2> at a first time point during the erase operation period when the erase voltage begins to be applied to the substrate of the selected memory block, and float the source select lines SSL<1:2> for a preset time starting at a second time point later than the first time point. At this time, the line driver 1522 can float two or more source select lines SSL<1:2> sequentially from the source select lines closer to the substrate to the source select lines farther from the substrate. For example, the line driver 1522 can apply the selection voltage SS to the first source select line SSL<1:2> closer to the substrate between two source select lines SSL<1:2> at the first time point. <1> And at the second time point, the first source selection line SSL will be selected. <1> Floating. On the other hand, the line driver 1522 can apply the selection voltage SS to the second source select line SSL, which is further away from the substrate between the two source select lines SSL<1:2>, at a first time point. <2> And from the time point where the second time point has passed since the first time point, the second source selection line SSL will be selected. <2> Floating.

[0113] During the erase operation period when an erase voltage is applied to the substrate of the selected memory block, the line driver 1522 included in the line decoder 152 can apply a selection voltage SS to the drain selection lines DSL<1:2> at a first time point during the erase operation period when the erase voltage begins to be applied to the substrate of the selected memory block, and float the drain selection lines DSL<1:2> for a preset time starting at a second time point later than the first time point. At this time, the line driver 1522 can float two or more drain selection lines DSL<1:2> sequentially from the drain selection lines farther from the substrate to the drain selection lines closer to the substrate. For example, the line driver 1522 can apply the selection voltage SS to the second drain selection line DSL<1:2> farther from the substrate between the two drain selection lines DSL<1:2> at the first time point. <2> And at the second time point, the second drain selection line DSL <2> Floating. On the other hand, the line driver 1522 can apply the selection voltage SS to the first drain selection line DSL, which is closer to the substrate between the two drain selection lines DSL<1:2>, at a first time point. <1> And at the time point from the second time point to the first time point, the first drain selection line DSL will be selected. <1> Floating.

[0114] When the target level of the erase voltage is 20V and the third time point is a preset time point elapsed from the second time point, the period between the first and third time points is the period during which the erase voltage level rises from 0V to 20V. The period between the second time point and the time point elapsed from the second time point can be a period during which the erase voltage level rises by 1V. For example, when the erase voltage level is 8V at the second time point, the erase voltage level can be 9V at the time point elapsed from the second time point, and the erase voltage can rise to the target level of 20V. Furthermore, the time point elapsed from the second time point can be earlier than the third time point.

[0115] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. Furthermore, the disclosed embodiments may be combined to form additional embodiments.

[0116] Cross-references to related applications

[0117] This application claims priority to Korean Patent Application No. 10-2021-0042452, filed on April 1, 2021, the entirety of which is incorporated herein by reference.

Claims

1. A memory device comprising: A memory block comprising a plurality of memory cells stacked in a direction intersecting a substrate and a plurality of word lines arranged between two or more source select lines and two or more drain select lines, wherein two or more word lines located in the middle of the plurality of word lines are used as dummy word lines. Control circuit, which is suitable for: The character line that overlaps with one side of the dummy character line among the multiple character lines is established as the first sub-block. Create a second sub-block by layering the character line on the other side of the dummy character line. During the erasure operation period when the erasure voltage is applied to the substrate, one of the first sub-block and the second sub-block is selected, and Perform an independent erase operation only on the selected sub-blocks; and Control logic, adapted to control the control circuit during the erase operation period, to differently set the level of a first transmission voltage for controlling the transmission of the erase common voltage to the selected sub-block and the level of a second transmission voltage for controlling the transmission of the erase common voltage to the unselected sub-block, apply the erase common voltage as an erase enable voltage to the word line of the selected sub-block, and float the word line of the unselected sub-block. During the erase operation period, the control logic further controls the control circuit to set the level of the first transmitted voltage to be higher than the level of the erase common voltage by a predetermined level, thereby applying the erase common voltage as the erase allow voltage.

2. The memory device according to claim 1, wherein, During the erase operation period, the control logic also controls the control circuit to set the level of the second transmission voltage to be equal to or lower than the level of the erase common voltage, thereby floating the word line of the unselected sub-block by preventing the erase common voltage from being transmitted to the unselected sub-block.

3. The memory device according to claim 1, wherein, During the erasure operation period, the control logic also controls the control circuit: At the first point in time when the erase voltage begins to be applied to the substrate, the drain select line is floated and a select voltage is applied to the source select line, and Within a preset time period starting from a second time point later than the first time point, the two or more source selection lines are floated sequentially from the source selection line closer to the substrate to the source selection line farther away from the substrate.

4. The memory device according to claim 1, wherein, During the erasure operation period, the control logic also controls the control circuit: At the first time point when the erase voltage begins to be applied to the substrate, the source select line is floated and a select voltage is applied to the drain select line, and Within a preset time period starting from a second time point later than the first time point, the two or more drain selection lines are floated sequentially from the drain selection line farther away from the substrate to the drain selection line closer to the substrate.

5. The memory device according to claim 1, wherein, During the erasure operation period, the control logic also controls the control circuit: At the first time point when the erase voltage begins to be applied to the substrate, a selection voltage is applied to the source select line and the drain select line, and Within a preset time period starting from a second time point later than the first time point, two or more drain selection lines are floated sequentially from the drain selection line farther from the substrate to the drain selection line closer to the substrate, and two or more source selection lines are floated sequentially from the source selection line closer to the substrate to the source selection line farther from the substrate.

6. The memory device according to claim 1, in, During the erase operation period, the control logic also controls the control circuit to apply an erase blocking voltage with a relatively low potential level to the dummy word line closer to the selected sub-block among the two or more dummy word lines located between the selected sub-block and the unselected sub-block, and to apply the erase blocking voltage with a relatively high potential level to the dummy word line farther away from the selected sub-block among the two or more dummy word lines. The erase blocking voltage has a potential level that is higher than the erase allowing voltage and lower than the erase voltage.

7. The memory device according to claim 1, wherein, The control circuit includes: A voltage generator adapted to generate the erase voltage, the erase common voltage, the first transmission voltage, and the second transmission voltage; A page buffer, coupled to the bit lines of the memory block, and adapted to control the bit lines to float during the erase operation period; and A line decoder adapted to drive the word lines of the selected sub-block to the erase enable voltage in response to the first transmit voltage and to float the word lines of the unselected sub-block in response to the second transmit voltage.

8. A memory device comprising: A memory block comprising a plurality of memory cells stacked in a direction intersecting a substrate and a plurality of word lines arranged between two or more source select lines and two or more drain select lines, wherein two or more word lines located in the middle of the plurality of word lines serve as dummy word lines; and Control circuit, which is suitable for: The character line that overlaps with one side of the dummy character line among the multiple character lines is established as the first sub-block. Create a second sub-block by layering the character line on the other side of the dummy character line. During the erasure operation period when the erasure voltage is applied to the substrate, one of the first sub-block and the second sub-block is selected, and Perform an independent erase operation only on the selected sub-block. During the erasure operation period, the control circuit is further adapted to: The levels of a first transmission voltage used to control the transmission of the erase common voltage to the selected sub-block and a second transmission voltage used to control the transmission of the erase common voltage to the unselected sub-block are set differently. The erase common voltage is applied as the erase allow voltage to the word line of the selected sub-block, and Float the word lines of the unselected sub-blocks. During the erase operation period, the control circuit sets the level of the first transmitted voltage to be higher than the level of the erase common voltage by a predetermined level, thereby applying the erase common voltage as the erase allow voltage.

9. The memory device according to claim 8, wherein, During the erase operation period, the control circuit sets the level of the second transmission voltage to be equal to or lower than the level of the erase common voltage, thereby floating the word line of the unselected sub-block by preventing the erase common voltage from being transmitted to the unselected sub-block.

10. The memory device according to claim 8, wherein, During the erasure operation period, the control circuit is also adapted to: At the first point in time when the erase voltage begins to be applied to the substrate, the drain select line is floated and a select voltage is applied to the source select line, and Within a preset time period starting from a second time point later than the first time point, the two or more source selection lines are floated sequentially from the source selection line closer to the substrate to the source selection line farther away from the substrate.

11. The memory device according to claim 8, wherein, During the erasure operation period, the control circuit is also adapted to: At the first time point when the erase voltage begins to be applied to the substrate, the source select line is floated and a select voltage is applied to the drain select line, and Within a preset time period starting from a second time point later than the first time point, the two or more drain selection lines are floated sequentially from the drain selection line farther away from the substrate to the drain selection line closer to the substrate.

12. The memory device according to claim 8, wherein, During the erasure operation period, the control circuit is also adapted to: At the first time point when the erase voltage begins to be applied to the substrate, a selection voltage is applied to the source select line and the drain select line, and Within a preset time period starting from a second time point later than the first time point, two or more drain selection lines are floated sequentially from the drain selection line farther from the substrate to the drain selection line closer to the substrate, and two or more source selection lines are floated sequentially from the source selection line closer to the substrate to the source selection line farther from the substrate.

13. The memory device according to claim 8, in, During the erase operation period, the control circuit is further adapted to apply an erase blocking voltage with a relatively low potential level to the dummy word line closer to the selected sub-block among two or more dummy word lines located between the selected sub-block and the unselected sub-block, and to apply the erase blocking voltage with a relatively high potential level to the dummy word line farther away from the selected sub-block among the two or more dummy word lines. The erase blocking voltage has a potential level that is higher than the erase allowing voltage and lower than the erase voltage.

14. A method of operating a memory device, the memory device comprising a memory block including a plurality of memory cells stacked in a direction intersecting a substrate and a plurality of word lines arranged between two or more source select lines and two or more drain select lines, wherein, Two or more character lines located in the middle of the plurality of character lines are used as dummy character lines. A character line overlapping one side of the dummy character lines is established as a first sub-block, and a character line overlapping the other side of the dummy character lines is established as a second sub-block. The operation method includes the following operations: An erasing operation comprising selecting one of the first sub-block and the second sub-block during an erasing operation period in which an erasing voltage is applied to the substrate, and then performing an independent erasing operation only on the selected sub-block; and The transmission operation includes: During the erasure operation period, The levels of a first transmission voltage used to control the transmission of the erase common voltage to the selected sub-block between the first sub-block and the second sub-block are set differently, and the levels of a second transmission voltage used to control the transmission of the erase common voltage to the unselected sub-block are also set differently. The erase common voltage is applied as the erase allow voltage to the word line of the selected sub-block, and Float the word lines of the unselected sub-blocks. During the erasure operation period, the transmission operation further includes: The level of the first transmission voltage is set to be higher than the level of the erase common voltage by a predetermined level, thereby applying the erase common voltage as the erase enable voltage.

15. The operating method according to claim 14, wherein, During the erasure operation period, the transfer operation further includes: The level of the second transmission voltage is set to be equal to or lower than the level of the erase common voltage, thereby floating the word line of the unselected subblock by preventing the erase common voltage from being transmitted to the unselected subblock.

16. The method of operation according to claim 14, further comprising one of the following operations during the erasure operation period: At a first time point when the erase voltage is applied to the substrate, the drain selection line is floated and the selection voltage is applied to the source selection line. Then, within a predetermined time period starting at a second time point later than the first time point, the two or more source selection lines are floated sequentially from the source selection line closer to the substrate to the source selection line farther away from the substrate. At the first time point when the erase voltage begins to be applied to the substrate, the source select line is floated and the select voltage is applied to the drain select line, and within the preset time period starting at the second time point later than the first time point, the two or more drain select lines are floated sequentially from the drain select line farther from the substrate to the drain select line closer to the substrate; and At the first time point when the erase voltage is first applied to the substrate, the selection voltage is applied to the source selection line and the drain selection line, and within the preset time period starting at the second time point later than the first time point, the two or more drain selection lines are floated sequentially from the drain selection line farther from the substrate to the drain selection line closer to the substrate, and the two or more source selection lines are floated sequentially from the source selection line closer to the substrate to the source selection line farther from the substrate.

17. The operating method according to claim 14, further comprising: During the erase operation period, an erase blocking voltage with a relatively low potential level is applied to the dummy word line closer to the selected sub-block among two or more dummy word lines located between the selected sub-block and the unselected sub-block, and an erase blocking voltage with a relatively high potential level is applied to the dummy word line farther away from the selected sub-block among the two or more dummy word lines. The erase blocking voltage has a potential level that is higher than the erase allowing voltage and lower than the erase voltage.

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