Method for manufacturing a switching device

Abstract

A method for manufacturing a switching device (10) includes: forming a trench (22) at a top surface (12a) of a semiconductor substrate (12); forming a gate insulating film (24) for covering an inner surface of the trench; forming a gate electrode (26) inside the trench to position the top surface of the gate electrode below the top surface of the semiconductor substrate; forming an oxide film (40) by oxidizing the top surface of the gate electrode; forming an interlayer insulating film (28) at the top surface of the oxide film by vapor phase growth such that the top surface of the interlayer insulating film is below the top surface of the semiconductor substrate; and forming an upper electrode (70) in contact with the semiconductor substrate at the top surface of the semiconductor substrate and the side surface of the trench above the top surface of the interlayer insulating film.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a switching device. Background Technology

[0002] JP 2005-209807 A discloses a switching device comprising a semiconductor substrate, a trench, a gate insulating film, a gate electrode, and an interlayer insulating film. The trench is disposed at the top surface of the semiconductor substrate. The gate insulating film covers the inner surface of the trench. The interlayer insulating film covers the top surface of the gate electrode. In a method for manufacturing the switching device, a gate electrode is formed such that after the gate insulating film is formed at the inner surface of the trench, the top surface of the gate electrode is located below the top surface of the semiconductor substrate. Subsequently, an insulating layer is deposited inside the trench and at the top surface of the semiconductor substrate using chemical vapor deposition (CVD). The insulating layer is then etched to form an interlayer insulating film embedded within the trench. Summary of the Invention

[0003] In the manufacturing method described in JP 2005-209807 A, a relatively thick interlayer insulating film needs to be formed to ensure the withstand voltage of the interlayer insulating film. The object of this disclosure is to provide a technique that ensures the withstand voltage of the insulating film while reducing the thickness of the insulating film covering the gate electrode.

[0004] According to one aspect of this disclosure, a method for manufacturing a switching device includes: forming a trench at a top surface of a semiconductor substrate; forming a gate insulating film for covering an inner surface of the trench; forming a gate electrode inside the trench to position the top surface of the gate electrode below the top surface of the semiconductor substrate; forming an oxide film by oxidizing the top surface of the gate electrode; forming an interlayer insulating film at the top surface of the oxide film by vapor phase growth to position the top surface of the interlayer insulating film below the top surface of the semiconductor substrate; and forming an upper electrode in contact with the semiconductor substrate at the top surface of the semiconductor substrate and at a trench side surface located above the top surface of the interlayer insulating film.

[0005] In a process for forming an interlayer insulating film on the top surface of an oxide film via vapor phase growth, the top surface of the interlayer insulating film can be located below the top surface of the semiconductor substrate by adjusting the vapor phase growth time. In this process, an interlayer insulating film extending above the top surface of the semiconductor substrate is formed by vapor phase growth, and the top surface of the interlayer insulating film can be located below the top surface of the semiconductor substrate by etching the interlayer insulating film. The vapor phase growth described in this disclosure can also be referred to as vapor phase epitaxial growth or vapor phase deposition.

[0006] In the above manufacturing method, an oxide film is formed by oxidizing the gate electrode. As a result, the top surface of the gate electrode is covered by the oxide film. Subsequently, an interlayer insulating film is grown on the top surface of the oxide film by vapor phase growth to form a double-layer insulating film for covering the gate electrode. Compared with the interlayer insulating film formed by vapor phase growth, the oxide film formed by oxidizing the gate electrode has a lower impurity content, such as hydrogen content, and higher density. Therefore, the oxide film has a higher withstand voltage. Since the withstand voltage is ensured by the oxide film, the film thickness of the interlayer insulating film formed by subsequent vapor phase deposition can be reduced. In the above manufacturing method, the overall film thickness of the insulating film can be reduced while ensuring the withstand voltage of the insulating film used to cover the gate electrode. Therefore, the contact area between the upper electrode and the trench side surface of the upper part of the interlayer insulating film can be increased. Attached Figure Description

[0007] Other objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings:

[0008] Figure 1 This is a perspective view of the switching device according to the first embodiment;

[0009] Figure 2 It is along Figure 1 A cross-sectional view taken from plane II in the diagram;

[0010] Figure 3 It is along Figure 1 A cross-sectional view taken from plane III in the diagram;

[0011] Figure 4 The manufacturing process of the switching device according to the first embodiment is shown;

[0012] Figure 5 The manufacturing process of the switching device according to the first embodiment is shown;

[0013] Figure 6 The manufacturing process of the switching device according to the first embodiment is shown;

[0014] Figure 7 The manufacturing process of the switching device according to the first embodiment is shown;

[0015] Figure 8 The manufacturing process of the switching device according to the first embodiment is shown;

[0016] Figure 9 The manufacturing process of the switching device according to the first embodiment is shown;

[0017] Figure 10 The manufacturing process of the switching device according to the first embodiment is shown;

[0018] Figure 11The manufacturing process of the switching device according to the first embodiment is shown;

[0019] Figure 12 The manufacturing process of the switching device according to the first embodiment is shown;

[0020] Figure 13 The manufacturing process of the switching device according to the first embodiment is shown; and

[0021] Figure 14 The manufacturing process of the switching device according to the second embodiment is shown. Detailed Implementation

[0022] The following are the technical elements disclosed herein. Each of these technical elements may be applied independently.

[0023] In the exemplary manufacturing method disclosed in this embodiment, the semiconductor substrate can be made of silicon carbide. The semiconductor substrate can have an n-type drift region, a p-type body region disposed above the drift region, and an n-type source region disposed above the body region. During trench formation, the trench can penetrate the source region and the body region and reach the drift region. The top surface of the gate electrode can be oxidized to satisfy the mathematical relationship L > 2.7 × A, where "L" represents the length along the trench side surface between the oxide film and the body region, and "A" represents the diffusion distance of the oxide material into the gate insulating film during the oxidation of the gate electrode. In other words, "L" is greater than the value obtained by multiplying "A" by 2.7.

[0024] In this manufacturing method, oxidizing agents (e.g., oxygen when the gate electrode is oxidized) are unlikely to reach the body region. When the gate electrode is oxidized, the body region having the area in contact with the gate insulating film (in other words, the area forming the channel) is unlikely to be oxidized, and the interface between the body region and the gate insulating film is unlikely to be defective. According to this manufacturing method, a switching device with a stable gate threshold can be manufactured.

[0025] During the formation of the trench, a curved surface can be formed at the boundary between the side surface of the trench and the top surface of the semiconductor substrate.

[0026] In this manufacturing method, when a metal layer or the like is formed from the side surface of the trench on the upper surface of the semiconductor substrate, the forming performance of the film is enhanced, and the reliability of the manufactured switching device is enhanced.

[0027] (First Embodiment)

[0028] Figures 1 to 3Each of the following illustrates a switching device 10 according to a first embodiment. The switching device 10 is a metal-oxide-semiconductor field-effect transistor (MOSFET). The switching device 10 described in this disclosure may also be referred to as a switching element. The switching device 10 includes a semiconductor substrate 12. The semiconductor substrate 12 is made of silicon carbide (SiC). However, the material used to manufacture the semiconductor substrate 12 is not particularly limited and may be, for example, other semiconductor materials such as silicon (Si) or gallium nitride (GaN). In the following, the direction parallel to the top surface 12a of the semiconductor substrate 12 may also be referred to as the x-direction, the direction parallel to the top surface 12a and perpendicular to the x-direction may also be referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 may also be referred to as the z-direction. Figure 2 It is along Figure 1 The cross-sectional view taken from line II-II in the diagram, and Figure 3 It is along Figure 1 The cross-sectional view taken from line III-III in the diagram. (See diagram below.) Figure 2 and Figure 3 As shown, the source electrode 70 is disposed above the top surface 12a of the semiconductor substrate 12. Figure 1 The source electrode 70 is omitted from the diagram.

[0029] Multiple trenches 22 are disposed on the top surface 12a of the semiconductor substrate 12. For example... Figure 1 As shown, trenches 22 extend at the top surface 12a and are parallel to each other. Each trench 22 extends linearly. The trenches 22 are spaced apart in the x-direction. A gate insulating film 24, a gate electrode 26, an oxide film 40, and an interlayer insulating film 28 are disposed inside each trench 22.

[0030] A gate insulating film 24 covers the inner surface of the trench 22. The top end of the gate insulating film 24 is located below the top surface 12a of the semiconductor substrate 12. In other words, the top end of the gate insulating film 24 is located inside the trench 22. The gate insulating film 24 is made of silicon oxide.

[0031] The gate electrode 26 is disposed inside the trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by a gate insulating film 24. The gate electrode 26 is made of polysilicon.

[0032] An oxide film 40 covers the top surface of the gate electrode 26. The oxide film 40 is made of silicon oxide. The oxide film 40 is formed by thermal oxidation of the gate electrode 26. The oxide film 40 has a relatively low hydrogen content.

[0033] An interlayer insulating film 28 covers the top surface of the oxide film 40. The interlayer insulating film 28 is made of silicon oxide. The interlayer insulating film 28 is formed by vapor-phase growth of, for example, a silane compound at the top surface of the oxide film 40. The interlayer insulating film 28 has a higher hydrogen content than the oxide film 40.

[0034] The drain electrode 80 is disposed on the bottom surface 12b of the semiconductor substrate 12. The drain electrode 80 is in contact with substantially the entire bottom surface 12b of the semiconductor substrate 12.

[0035] like Figure 2 and Figure 3 As shown, a source electrode 70 is disposed at the top surface 12a of the semiconductor substrate 12. The source electrode 70 is arranged to extend across the interior of the trench 22 from a position above the top surface 12a. The source electrode 70 covers the top surface 12a of the semiconductor substrate 12, the side surface of the trench 22 above the interlayer insulating film 28, and the top surface of the interlayer insulating film 28. The source electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28 and the oxide film 40. The source electrode 70 has a nickel silicide layer 72, a barrier metal layer 74, and an aluminum layer 76. The source electrode 70 is one example of an upper electrode.

[0036] A nickel silicide layer 72 extends from a position above the top surface 12a of the semiconductor substrate 12 into the trench 22. The nickel silicide layer 72 extends to a position adjacent to the gate insulating film 24 on the upper side and covers the side surface of the trench 22. The nickel silicide layer 72 is made of a compound of nickel and silicon.

[0037] The barrier metal layer 74 extends from a position above the nickel silicide layer 72 to a position inside the trench 22. The barrier metal layer 74 covers the surface of the nickel silicide layer 72 and the top surface of the interlayer insulating film 28. The barrier metal layer 74 is made of, for example, a titanium-containing metal, such as titanium alone or an alloy of titanium and aluminum.

[0038] The aluminum layer 76 extends from a position above the top surface 12a of the semiconductor substrate 12 into the trench 22. The aluminum layer 76 covers the surface of the barrier metal layer 74.

[0039] like Figures 1 to 3 As shown, multiple source regions 30, body regions 32, drift regions 34 and drain regions 35 are disposed inside the semiconductor substrate 12.

[0040] Each source region is an n-type region. For example... Figure 1 and Figure 2 As shown, each source region 30 is located in the region sandwiched between two adjacent trenches 22 (hereinafter referred to as the inter-trench region). Figure 1 As shown, the source regions 30 are arranged at intervals along the y-direction in the trench region. Figure 2 As shown, each source region 30 is disposed in a region exposed to the top surface 12a of the semiconductor substrate 12 and is in ohmic contact with a source region 70. Each source region 30 is in ohmic contact with a nickel silicide layer 72. Each source region 30 is in contact with a gate insulating film 24 beneath the nickel silicide layer 72.

[0041] The body region 32 is a p-type region. For example... Figure 1 and Figure 3 As shown, the body region 32 has multiple contact regions 32a and main body regions 32b.

[0042] Each contact region 32a is a p-type region with a high impurity concentration. For example... Figure 1 and Figure 3 As shown, each contact region 32a is arranged in the trench region. Each contact region 32a is arranged in the region exposed to the top surface 12a of the semiconductor substrate 12. Figure 1 As shown, in each trench region, contact regions 32a are spaced apart along the y-direction. Source regions 30 and contact regions 32a are arranged alternately in the y-direction. Figure 3 As shown, each contact region 32a has a 70-ohm contact with the source electrode. Each contact region 32a has a 72-ohm contact with the nickel silicide layer. Each contact region 32a has a contact with the gate insulating film 24 beneath the nickel silicide layer 72.

[0043] The main body region 32b is a p-type region with a lower p-type impurity concentration than each contact region 32a. For example... Figures 1 to 3 As shown, the body region 32b is disposed below each source region 30 and each contact region 32a. The body region 32b contacts each source region 30 and each contact region 32a at its lower surface. The body region 32b is distributed over the entire lower region of each source region 30 and each contact region 32a. Figure 2 and Figure 3 As shown, the body region 32b is in contact with the gate insulating film 24 located below each source region 30 and each contact region 32a. The lower end of the body region 32b is disposed above the lower end of the gate electrode 26.

[0044] Drift region 34 is an n-type region, such as Figures 1 to 3 As shown, the drift region 34 is disposed below the body region 32b. When viewed from below, the drift region 34 is in contact with the lower body region 32. The drift region 34 is separated from each source region 30 through the body region 32b. The drift region 34 is distributed from each trench region to the region below each trench 22. The drift region 34 is in contact with the gate insulating film 24 below the body region 32b. The drift region 34 is in contact with the gate insulating film 24 at the bottom surface of the trench 22.

[0045] Drain region 35 is an n-type region with a higher n-type impurity concentration than drift region 34. For example... Figures 1 to 3 As shown, the drain region 35 is disposed below the drift region 34. Viewed from below, the drain region 35 is in contact with the drift region 34. The drain region 35 is exposed on the bottom surface 12b of the semiconductor substrate 12. The drain region 35 is in 80-ohm contact with the drain electrode.

[0046] The operation of switching device 10 is described below. When switching device 10 is used, switching device 10, a power supply, and a load such as a motor are connected in series. A power supply voltage is applied to the series circuit of switching device 10 and the load. The power supply voltage is applied in a direction where the drain electrode 80 has a higher potential than the source electrode 70. When an on-potential is applied to the gate electrode 26, a channel is formed in the body region 32 (in other words, the body region 32b in the region in contact with the gate insulating film 24). The on-potential is a potential higher than the gate threshold. Electrons then flow from the source electrode 70 through the source region 30, the channel, the drift region 34, and the drain region 35 to the drain electrode 80, and switching device 10 is turned on. When the potential of the gate electrode 26 drops to the off-potential, the channel disappears and the flow of electrons stops, turning off switching device 10. The off-potential is a potential lower than the gate threshold.

[0047] In the switching device 10, since the source region 30 contacts not only the top surface 12a of the semiconductor substrate 12, but also the source electrode 70 at the side surface of the trench 22, a wider contact surface between the source region 30 and the source electrode 70 can be ensured. Therefore, the contact resistance between the source region 30 and the source electrode is small, and the on-resistance of the switching device 10 is small.

[0048] The following is for reference. Figures 4 to 13 A method for manufacturing a switching device 10 is described. Figures 4 to 13 Each of them shows the corresponding Figure 2 A cross-sectional view. The switching device 10 is fabricated from a semiconductor substrate 12, in other words, from a pre-processed semiconductor substrate 12 with the drain region 35 configured. Figure 4 As shown, drift region 34 is epitaxially grown on drain region 35. Subsequently, host region 32b and source region 30 are formed inside semiconductor substrate 12. Although not shown, contact region 32a is formed corresponding to... Figure 3 The contact region 32a, the host region 32b, and the source region 30 can be formed, for example, by epitaxial growth or ion implantation.

[0049] like Figure 5 As shown, trenches 22 are formed by selectively etching the top surface 12a of the semiconductor substrate 12. Each trench 22 is formed such that it penetrates the source region 30, the contact region 32A, and the body region 32b and reaches the drift region 34.

[0050] like Figure 6 As shown, an insulating layer 90 made of silicon oxide is deposited using chemical vapor deposition (CVD) to cover the top surface 12a of the semiconductor substrate 12 and the inner surface of the trench 22. The insulating layer 90 covering the inner surface of the trench 22 is a gate insulating film 24. Subsequently, a gate electrode 26 is formed by depositing polysilicon on the surface of the insulating layer 90.

[0051] Gate electrode 26 is etched. As a result, as... Figure 7 As shown, a portion of the gate electrode 26 is removed from the upper part of the top surface 12a of the semiconductor substrate 12. The gate electrode 26 remains inside the trench 22. The gate electrode 26 is etched such that the top surface of the remaining gate electrode 26 is located below the top surface 12a of the semiconductor substrate 12. Additionally, the gate electrode 26 is etched such that the top surface of the remaining gate electrode 26 is located above the lower end of the source region 30. (Refer to...) Figure 8 In the process of oxidizing the top surface of the gate electrode 26, the gate electrode 26 is etched to satisfy the mathematical relationship L > 2.7 × A, where "L" represents the distance along the trench 22 in the body region 32b and in the... Figure 8 The distance between the oxide films 40 formed in the process shown, and "A" indicates the diffusion distance of oxidizing substances such as oxygen into the gate insulating film 24.

[0052] The semiconductor substrate 12 is heated. For example, the semiconductor substrate 12 is heat-treated in an oxygen atmosphere at a temperature ranging from 800 to 900 degrees Celsius. As a result, the top surface of the gate electrode 26 is oxidized, and an oxide film 40 is formed at the top surface of the gate electrode 26, such as... Figure 8 As shown. Oxidation of the gate electrode 26 is performed by heat treatment from the top surface of the gate electrode 26 to the interior (bottom side) of the gate electrode 26. In this embodiment, the gate insulating film 24 is made of silicon oxide, and A is approximately 100 nanometers. Therefore, the etching amount, i.e., the distance between the etched body region 32b and the gate electrode 26, is appropriately designed such that the distance L is longer than approximately 270 nanometers. In this embodiment, heat treatment in an oxygen atmosphere is used as an example. However, an oxide film 40 can be formed on the surface of the gate electrode by, for example, exposure to oxygen plasma or a hydrochloric acid-hydrogen peroxide mixture (HPM).

[0053] like Figure 9 As shown, an insulating layer 92 made of silicon oxide is deposited on the surface of the insulating layer 90 and the top surface of the oxide film 40 using CVD technology. The insulating layer 92 is deposited inside the trench 22 and on the top surface 12a of the semiconductor substrate 12. In this process, the insulating layer 90 and the insulating layer 92 are integrated.

[0054] Etch insulating layers 90 and 92. Insulating layer 92 remains within trench 22. Insulating layer 92 is left so that it covers the top surface of oxide film 40. The insulating layer 92 remaining inside trench 22 is interlayer insulating film 28. Etch insulating layer 92 so that the top surface of interlayer insulating film 28 is below the top surface 12a of semiconductor substrate 12.

[0055] like Figure 11As shown, the nickel layer 42 is deposited, for example by sputtering, on the surface of the semiconductor substrate 12 and the top surface of the interlayer insulating film 28. The nickel layer 42 is formed to cover the top surface 12a of the semiconductor substrate 12 and the inner surface of the trench 22, particularly the inner surface of the trench 22 above the top surface of the interlayer insulating film 28.

[0056] The semiconductor substrate 12 is heated. For example, the semiconductor substrate 12 is heat-treated at a temperature of approximately 700 degrees Celsius under a nitrogen atmosphere. The nickel in the nickel layer 42 reacts with the silicon in the semiconductor substrate 12. As a result, as Figure 12 As shown, a nickel silicide layer 72 is formed in the region where the nickel layer 42 and the semiconductor substrate 12 are in contact with each other. In the region where the nickel layer 42 is not in contact with the semiconductor substrate 12, in other words, in the region where the nickel layer 42 is in contact with the interlayer insulating film 28, the nickel layer 42 is not silicided and remains as is.

[0057] The unsiliconized nickel layer 42 is removed by etching, and a barrier metal layer 74 is deposited to cover the top surface of the interlayer insulating film 28 and the surface of the siliconized nickel layer 72, as follows. Figure 13 As shown.

[0058] An aluminum layer 76 is deposited on the surface of the barrier metal layer 74, and a drain electrode 80 is formed on the bottom surface 12b of the semiconductor substrate 12 to complete the following: Figures 1 to 3 Manufacturing of the switch device 10 shown.

[0059] According to this manufacturing method, a switching device 10 can be manufactured, in which a nickel silicide layer 72 is disposed on the side surface of the trench 22 above the interlayer insulating film 28 and on the top surface 12a of the semiconductor substrate 12. Therefore, the source electrode 70 can contact the source region 30 and the contact region 32a with a lower contact resistance.

[0060] According to this manufacturing method, the top surface of the gate electrode 26 is covered by an oxide film 40 and an interlayer insulating film 28. That is, the gate electrode 26 and the source electrode 70 are insulated by a double-layer insulating film. Since the oxide film 40 is formed by thermally oxidizing the gate electrode 26, the content of impurities such as hydrogen is lower than the impurity content of the interlayer insulating film 28 formed by vapor phase growth, and the oxide film 40 has higher density. Therefore, the withstand voltage between the gate electrode and the source electrode can be ensured by the oxide film 40. As a result, the film thickness of the interlayer insulating film 28 can be reduced. In the above manufacturing method, the withstand voltage of the insulating film used to provide insulation between the gate electrode 26 and the source electrode 70 can be ensured while reducing the overall film thickness of the insulating film. The overall film thickness is the sum of the film thickness of the oxide film 40 and the film thickness of the interlayer insulating film 28. Therefore, the contact area between the source electrode 70 and the trench 22 side surface above the interlayer insulating film 28 can be increased, and the contact resistance between the source electrode 70 and the semiconductor substrate 12 can be reduced. Because the overall thickness of the insulating film is reduced, the design freedom of the structure in which the insulating film is embedded in the trench is increased.

[0061] In this manufacturing method, a gate electrode 26 is formed to satisfy the mathematical relationship L > 2.7 × A, where “L” represents the length along the trench 22 between the body region 32b and the oxide film 40, and “A” represents the diffusion distance of the oxidized material into the gate insulating film 24 when the oxide film 40 is oxidized.

[0062] Therefore, during subsequent heat treatment, oxidizing agents such as oxygen are unlikely to reach the body region 32, in other words, the main body region 32b. When the gate electrode 26 is oxidized, the main body region 32b (in other words, the region forming the channel) within the area in contact with the gate insulating film 24 is unlikely to be oxidized, and the interface between the main body region 32b and the gate insulating film 24 is unlikely to be defective. According to this manufacturing method, a switching device 10 with a stable gate threshold can be manufactured.

[0063] (Second Embodiment)

[0064] In the manufacturing method according to the second embodiment, as... Figure 5 After forming the trench 22 described in the first embodiment, the boundary portion 22a between the side surface of the trench 22 and the top surface 12a of the semiconductor substrate 12 is formed as a curved surface. For example, after forming the trench 22, the boundary portion 22a is bent by reactive ion etching (RIE), thereby forming a curved portion 22b to connect the top surface 12a of the semiconductor substrate 12 and the side surface of the trench 22, as shown. Figure 13As shown. For example, the curved portion 22b can be formed by heat treatment on the semiconductor substrate 12 at a temperature of about 1200 degrees Celsius in an argon atmosphere. By forming the curved portion 22b as described above, the film-forming properties of the metal layer are enhanced when a metal layer such as a nickel layer 42 or a barrier metal layer 74 is formed from the top surface 12a of the semiconductor substrate 12 on the inner surface of the trench 22, and the reliability of the manufactured switching device 10 is also enhanced.

[0065] Although embodiments have been described in detail above, these are merely examples and do not limit the scope of this disclosure. The technology described in the claims includes various modifications and modifications to the specific examples described above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in this disclosure at the time of filing. Furthermore, the technology shown in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A method for manufacturing a switching device, the method comprising: A trench is formed on the top surface of the semiconductor substrate; A gate insulating film is formed to cover the inner surface of the trench; A gate electrode is formed inside the trench to position the top surface of the gate electrode below the top surface of the semiconductor substrate; An oxide film is formed by oxidizing the top surface of the gate electrode; An interlayer insulating film is formed on the top surface of the oxide film by vapor phase growth, such that the top surface of the interlayer insulating film is located below the top surface of the semiconductor substrate; as well as An upper electrode, in contact with the semiconductor substrate, is formed at the top surface of the semiconductor substrate and at the side surface of the trench located above the top surface of the interlayer insulating film. The semiconductor substrate is made of silicon carbide. The semiconductor substrate includes: The drift region of n-type conductivity The p-type conductive body region is disposed above the drift region, and The n-type conductive source region is disposed above the body region. During the formation of the trench, the trench is formed to penetrate the source region and the body region and reach the drift region. During the formation of the oxide film, the top surface of the gate electrode is oxidized to satisfy the mathematical relationship L > 2.7 × A. Where L represents the distance between the oxide film and the body region along the side surface of the trench, and A represents the diffusion length of the oxide material into the gate insulating film when the gate electrode is oxidized.

2. The method according to claim 1, in, During the formation of the trench, the boundary portion between the side surface of the trench and the top surface of the semiconductor substrate is formed to be curved.

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