Semiconductor device including a transistor and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device includes a first stack structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked in a vertical direction, a second stack structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked in the vertical direction and having a first side surface facing a first side surface of the first stack structure, a first channel layer formed on the first side surface of the first stack structure, a second channel layer formed on the first side surface of the second stack structure, a lower electrode layer commonly coupled to a lower end portion of the first channel layer and a lower end portion of the second channel layer between the first stack structure and the second stack structure, a first upper electrode layer coupled to an upper end portion of the first channel layer, and a second upper electrode layer coupled to an upper end portion of the second channel layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0045308, filed on April 7, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention disclose a semiconductor technology, and more specifically, a semiconductor device including a transistor and a method of manufacturing the semiconductor device. Background Technology

[0004] Advances in the electronics industry demand that electronic products become increasingly smaller, more integrated, and exhibit higher performance and operating speeds.

[0005] To meet these needs, new technologies are required to maintain and / or improve the characteristics of unit components (such as transistors, capacitors, etc.) that form electronic products while reducing the size of unit components. Summary of the Invention

[0006] The various embodiments disclosed herein pertain to semiconductor devices with reduced dimensions, exhibiting reduced parasitic capacitance and improved operating characteristics. Other embodiments of the invention disclose pertain to a method of manufacturing a semiconductor device.

[0007] According to one embodiment of the present invention, a semiconductor device includes: a first stacked structure, the first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked in a vertical direction; a second stacked structure, the second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked in a vertical direction, and the second stacked structure having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer, the lower electrode layer being commonly coupled to a lower end of the first channel layer and a lower end of the second channel layer between the first stacked structure and the second stacked structure; a first upper electrode layer, the first upper electrode layer being coupled to an upper end of the first channel layer; and a second upper electrode layer, the second upper electrode layer being coupled to an upper end of the second channel layer.

[0008] According to another embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a first initial stacked structure, the first initial stacked structure including a first lower dielectric layer, a first sacrificial layer, and a first upper dielectric layer stacked on a substrate in a vertical direction; forming a second initial stacked structure, the second initial stacked structure including a second lower dielectric layer, a second sacrificial layer, and a second upper dielectric layer stacked on the substrate in the vertical direction, and the second initial stacked structure having a first side facing a first side of the first initial stacked structure; and forming a lower electrode layer on the substrate, the upper surface of the lower electrode layer being at or below the first lower dielectric layer. At the height of the upper surface of the dielectric layer and the upper surface of the second lower dielectric layer, the lower electrode layer fills the lower space between the first initial stacked structure and the second initial stacked structure; a first channel layer and a second channel layer are formed on the first side surface of the first initial stacked structure and the first side surface of the second initial stacked structure, respectively, and the first channel layer and the second channel layer have lower ends coupled to the lower electrode layer; a first upper electrode layer and a second upper electrode layer are formed and respectively coupled to the upper ends of the first channel layer and the upper ends of the second channel layer; and the first sacrificial layer and the second sacrificial layer are replaced by a first horizontal gate structure and a second horizontal gate structure, respectively.

[0009] These and other features and advantages of the present invention will be better understood by those skilled in the art from the following detailed description of specific embodiments and accompanying drawings. Attached Figure Description

[0010] Figures 1A to 14B A semiconductor device and a method for manufacturing the semiconductor device are shown according to an embodiment of the present invention.

[0011] Figure 15 and Figure 16 This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present invention.

[0012] Figure 17A and Figure 17B This is a view illustrating a semiconductor device and a method of manufacturing the semiconductor device according to another embodiment of the present invention. Detailed Implementation

[0013] Various embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, in the various drawings and embodiments of the present invention, the same reference numerals refer to the same parts.

[0014] It should be understood that when one element is referred to as "connected" or "coupled" to another element, this may mean that the two are directly coupled or electrically connected to each other via another circuit in between. Other expressions explaining the relationship between elements, such as "between," "directly between," "adjacent to," or "directly adjacent to," should also be interpreted in the same way.

[0015] As used herein, the term "upper and lower ends of an element" may include the upper and lower parts or portions of an element.

[0016] In the following, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0017] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate certain features of the embodiments. When the first layer is referred to as "on the second layer" or "on the substrate," it means not only that the first layer is formed directly on the second layer or substrate, but also that the third layer exists between the first layer and the second layer or substrate.

[0018] Figures 1A to 14B A semiconductor device and a method for manufacturing a semiconductor device according to an embodiment of the present invention are illustrated. The figures denoted as 1A, 2A, etc., are cross-sectional views taken along line BB′ of the corresponding figures denoted as 1B, 2B, etc. The figure denoted as B is a plan view shown at the height of line AA′ of the corresponding figures denoted as 1A, 2A, etc. The semiconductor device of this embodiment may include a CMOS transistor having NMOS transistors and / or PMOS transistors.

[0019] First, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described.

[0020] refer to Figure 1A and Figure 1B A substrate 100 may be provided. The substrate 100 may include a semiconductor material, such as, for example, silicon.

[0021] Subsequently, a first initial stacked structure 110A and a second initial stacked structure 110B can be formed on the substrate 100. From a planar perspective, each of the first initial stacked structure 110A and the second initial stacked structure 110B can have a rectangular shape. For example, each of the first initial stacked structure 110A and the second initial stacked structure 110B can have a strip shape, wherein the side length in the first direction is longer than the side length in the second direction.

[0022] The first and second directions can be orthogonal to each other and can define a plane perpendicular to the stacking direction, which is also referred to as the vertical direction or third direction. Furthermore, the first initial stacking structure 110A and the second initial stacking structure 110B can be spaced apart from each other in the second direction, such that, from a plan view perspective, a side 111A of the first initial stacking structure 110A and a side 111B of the second initial stacking structure 110B in the second direction face each other. The side 111A of the first initial stacking structure 110A and the side 111B of the second initial stacking structure 110B facing each other can be inclined.

[0023] The first initial stacked structure 110A may include a first lower dielectric layer 112A, a first sacrificial layer 114A, and a first upper dielectric layer 116A stacked in a vertical direction. The second initial stacked structure 110B may include a second lower dielectric layer 112B, a second sacrificial layer 114B, and a second upper dielectric layer 116B stacked in a vertical direction. Here, the first sacrificial layer 114A and the second sacrificial layer 114B can be used to provide space for forming the first gate electrode layer and the second gate electrode layer therein, as will be described later. The first lower dielectric layer 112A and the second lower dielectric layer 112B can be used to electrically disconnect the first gate electrode layer and the second gate electrode layer from the substrate 100 and the lower electrode layer, as will be described later. The first upper dielectric layer 116A and the second upper dielectric layer 116B can be used to electrically disconnect the first gate electrode layer and the second gate electrode layer from the first upper electrode layer and the second upper electrode layer, as will be described later.

[0024] The first initial stacked structure 110A and the second initial stacked structure 110B can be formed by sequentially depositing dielectric materials for forming the first lower dielectric layer 112A and the second lower dielectric layer 112B, sacrificial materials for forming the first sacrificial layer 114A and the second sacrificial layer 114B, and dielectric materials for forming the first upper dielectric layer 116A and the second upper dielectric layer 116B on a substrate 100, and then selectively etching these materials. Since the first sacrificial layer 114A and the second sacrificial layer 114B are replaced by the first gate electrode layer and the second gate electrode layer in subsequent processes, the first sacrificial layer 114A and the second sacrificial layer 114B can be formed of materials with etching rates different from those of the first lower dielectric layer 112A and the second lower dielectric layer 112B and the first upper dielectric layer 116A and the second upper dielectric layer 116B. For example, the first sacrificial layer 114A and the second sacrificial layer 114B may include SiON (silicon oxynitride) or SiN (silicon nitride), and the first lower dielectric layer 112A and the second lower dielectric layer 112B, as well as the first upper dielectric layer 116A and the second upper dielectric layer 116B, may include SiCN (silicon carbon nitride), SiBCN (silicon boron carbon nitride), or SiCO (silicon carbon oxide).

[0025] Subsequently, a conductive layer 120 can be formed on the substrate 100 to fill the remaining space except for the first initial stacked structure 110A and the second initial stacked structure 110B. The conductive layer 120 can be used to form a common electrode for NMOS transistors and PMOS transistors, for example, as a lower electrode layer serving as a common source electrode. The conductive layer 120 can be formed by depositing a conductive material on the substrate 100 having a thickness sufficient to cover the first initial stacked structure 110A and the second initial stacked structure 110B while filling the space between the first initial stacked structure 110A and the second initial stacked structure 110B; and performing a planarization process, such as a chemical mechanical polishing (CMP) process, until the upper surfaces of the first initial stacked structure 110A and the second initial stacked structure 110B are exposed. The conductive layer 120 may include a variety of conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), metal compounds, or metal alloys.

[0026] refer to Figure 2A and Figure 2B The conductive layer pattern 120' can be formed by removing a portion of the conductive layer 120 through processes such as etching back. In the vertical direction, the upper surface of the conductive layer pattern 120' can be located at a height equal to or lower than the upper surfaces of the first lower dielectric layer 112A and the second lower dielectric layer 112B. For ease of description, in... Figure 2B In the plan view. Shown by dashed lines. Figure 2A The shape of the conductive layer pattern 120′ is not visible at the height of line AA′.

[0027] Subsequently, a material layer 130 can be formed along a lower contour on the conductive layer pattern 120' and the first initial stacked structure 110A and the second initial stacked structure 110B. This lower contour includes the upper surface of the conductive layer pattern 120', the sides of the first initial stacked structure 110A and the second initial stacked structure 110B that protrude above the conductive layer pattern 120', and the upper surfaces of the first initial stacked structure 110A and the second initial stacked structure 110B. The material layer 130 can be provided to form the channels of NMOS and PMOS transistors. The material layer 130 can be conformally formed to have a thin thickness that does not completely fill the space between the first initial stacked structure 110A and the second initial stacked structure 110B. That is, the material layer 130 can be in the form of a thin film. For example, the material layer 130 can include an undoped semiconductor material. In one embodiment, the material layer 130 can be an undoped silicon thin film.

[0028] refer to Figure 3A and Figure 3B The mask pattern M can be formed to extend in a first direction, while in Figure 2A and Figure 2B The mask pattern M overlaps spatially with the first initial stacked structure 110A and the second initial stacked structure 110B above the resulting fabrication. Therefore, the mask pattern M can cover the conductive layer pattern 120' and material layer 130 between the first initial stacked structure 110A and the second initial stacked structure 110B, and can expose the conductive layer pattern 120' and material layer 130 in other areas. Furthermore, although not shown, the mask pattern M can also overlap with at least a portion of the upper surfaces of the first initial stacked structure 110A and the second initial stacked structure 110B.

[0029] refer to Figure 4A and Figure 4B The material layer pattern 130' and the lower electrode layer 120'' can be formed by removing the material layer 130 and the conductive layer pattern 120' exposed by the mask pattern M through etching or other methods.

[0030] The lower electrode layer 120′′ may have a linear shape located below the material layer pattern 130′ between the first initial stacked structure 110A and the second initial stacked structure 110B and extending in a first direction. For ease of description, in Figure 4B In the plan view, it is shown by dashed lines. Figure 4AThe shape of the lower electrode layer 120′′ is not visible in the cross-section taken at the height of line AA′. As described above, the lower electrode layer 120′′ can be used as a common electrode for NMOS transistors and PMOS transistors.

[0031] A material layer pattern 130' can be formed along the lower contour of one side 111A of the first initial stacked structure 110A, one side 111B of the second initial stacked structure 110B, and the upper surface of the lower electrode layer 120''. Furthermore, although not shown, depending on the shape of the mask pattern M described above, the material layer pattern 130' can extend further onto at least a portion of the upper surfaces of the first initial stacked structure 110A and the second initial stacked structure 110B.

[0032] After forming the material layer pattern 130′ and the lower electrode layer 120′′, the mask pattern M can be removed.

[0033] refer to Figure 5A and Figure 5B The first doped layer 132A can be formed by doping a material layer pattern 130' on one side 111A of the first initial stacked structure 110A with an impurity of a first conductivity type. For example, the first doped layer 132A can be used as the channel of an NMOS transistor, and for this purpose, a high concentration of N-type impurities can be doped.

[0034] N-type impurities can be doped using a tilting implantation method, where the implantation is tilted towards one side 111A of the first initial stacked structure 110A (see arrow ①). The tilting implantation angle can be adjusted such that the N-type impurities are doped onto the entire material layer pattern 130′ on one side 111A of the first initial stacked structure 110A. In this case, since the N-type impurities are doped onto the lowest portion of the material layer pattern 130′, the lower end of the first doped layer 132A can contact the lower electrode layer 120′′ for electrical connection.

[0035] refer to Figure 6A and Figure 6B The second doped layer 132B can be formed by doping a material layer pattern 130' on one side 111B of the second initial stacked structure 110B with an impurity of a second conductivity type. For example, the second doped layer 132B can be used as the channel of a PMOS transistor, and for this purpose, a high concentration of P-type impurities can be doped.

[0036] P-type impurities can be doped using a tilt implantation method, where the implantation is tilted towards one side 111B of the second initial stacked structure 110B (see arrow ②). The tilt implantation angle can be adjusted so that the P-type impurities are doped onto the entire material layer pattern 130' on one side 111B of the second initial stacked structure 110B. In this case, since the P-type impurities are doped onto the lowest portion of the material layer pattern 130', the lower end of the second doped layer 132B can contact the lower electrode layer 120'' for electrical connection.

[0037] The embodiments disclosed in this invention illustrate the portion between the lower end of the first doped layer 132A and the lower end of the second doped layer 132B (see [reference]). Figure 6A The first doped layer 132A (130′) is not doped with any impurities and thus remains an undoped semiconductor material. However, the present invention is not limited thereto, and the lower ends of the first doped layer 132A and the second doped layer 132B may be in contact with each other (not shown), or a mixed region of N-type impurities and P-type impurities (not shown) may exist between the lower ends of the first doped layer 132A and the lower ends of the second doped layer 132B.

[0038] Furthermore, the order of the processes for forming the first doped layer 132A and the second doped layer 132B can be reversed. In other words, the second doped layer 132B can be formed first, and then the first doped layer 132A can be formed later. The conductivity type of the impurities doped into the first doped layer 132A and the second doped layer 132B can also be reversed. In other words, the first doped layer 132A can be a P-type doped layer, and the second doped layer 132B can be an N-type doped layer.

[0039] refer to Figure 7A and Figure 7B A structure sufficient to cover is formed on the substrate 100. Figure 6A and Figure 6BAfter the dielectric material of the resulting thickness is obtained, a first initial interlayer dielectric material 140 can be formed by performing a planarization process such as chemical mechanical polishing (CMP) until the upper surfaces of the first initial stacked structure 110A and the second initial stacked structure 110B are exposed. The first initial interlayer dielectric material 140 may include a dielectric material, such as SiO2, having an etching rate different from the etching rates of the first sacrificial layer 114A and the second sacrificial layer 114B, the first lower dielectric layer 112A and the second lower dielectric layer 112B, and the first upper dielectric layer 116A and the second upper dielectric layer 116B. During this process, a portion of the first doped layer 132A and the second doped layer 132B that protrudes above the first initial stacked structure 110A and the second initial stacked structure 110B may be removed. When the first doped layer 132A and the second doped layer 132B further extend to the upper surfaces of the first initial stacked structure 110A and the second initial stacked structure 110B, the portions of the first doped layer 132A and the second doped layer 132B above the upper surfaces of the first initial stacked structure 110A and the second initial stacked structure 110B can be removed in this process.

[0040] Subsequently, a portion of the first initial interlayer dielectric material 140 can be removed by a process such as etch-back to form the first interlayer dielectric layer 140'. In the vertical direction, the upper surface of the first interlayer dielectric layer 140' can be located below the upper surfaces of the first initial stacked structure 110A and the second initial stacked structure 110B, and above the upper surfaces of the first sacrificial layer 114A and the second sacrificial layer 114B. As a result, the upper portions of the first doped layer 132A and the second doped layer 132B can be exposed and not covered by the first interlayer dielectric layer 140'. The process for forming the first interlayer dielectric layer 140' can be performed to reduce the contact resistance (which will be described later) by increasing the contact area between the first and second upper electrode layers and the first and second channel layers, and / or to appropriately control the height of the lower surfaces of the first and second additional doped layers during their formation. This process can be omitted.

[0041] refer to Figure 8A and Figure 8B The first additional doped layer 134A can be formed by additionally doping it with an impurity (e.g., an N-type impurity) whose conductivity type is the same as that of the impurity in the first doped layer 132A. Figure 7A and Figure 7BThe process exposes the upper surface of the first doped layer 132A. Since a first additional doped layer 134A is formed, the first doped layer 132A, located below the first additional doped layer 134A and not additionally doped with impurities, can be represented by reference numeral 132A′. The impurity concentration of the first additional doped layer 134A can be higher than the impurity concentration of the first doped layer 132A′. Since a heat treatment for activation after impurity doping is an essential process, the lower surface of the first additional doped layer 134A can be lowered from the upper surface of the first interlayer dielectric layer 140′ to a predetermined extent. Even in this case, the lower surface of the first additional doped layer 134A can be controlled to be at a height equal to or higher than the upper surface of the first sacrificial layer 114A.

[0042] Doping of the impurities for forming the first additional doped layer 134A can be performed by tilting the implantation method towards one side 111A of the first initial stacked structure 110A (see arrow ③). Based on a horizontal plane (e.g., the surface of substrate 100), the tilting implantation angle can be smaller than [missing information]. Figure 5A and Figure 5B The angle of the inclined injection.

[0043] The first additional doped layer 134A and the first doped layer 132A′ can be referred to hereinafter as the first channel layer 136A. The first channel layer 136A can correspond to the channel of an NMOS transistor. The first additional doped layer 134A can serve to reduce the contact resistance with the first upper electrode layer, which will be described later. In one embodiment, the first additional doped layer 134A can be omitted. When the process for forming the first additional doped layer 134A is omitted, Figure 7A and Figure 7B The first doped layer 132A can be used as the channel of an NMOS transistor.

[0044] refer to Figure 9A and Figure 9B The second additional doped layer 134B can be formed by additionally doping it with an impurity (e.g., a P-type impurity) whose conductivity type is the same as that of the impurity in the second doped layer 132B. Figure 7A and Figure 7BThe process exposes the upper portion of the second doped layer 132B. Since a second additional doped layer 134B is formed, the second doped layer 132B, located below the second additional doped layer 134B and not additionally doped with impurities, can be represented by reference numeral 132B′. The impurity concentration of the second additional doped layer 134B can be higher than that of the second doped layer 132B′. Since a heat treatment for activation after impurity doping is an essential process, the lower surface of the second additional doped layer 134B can be lowered from the upper surface of the first interlayer dielectric layer 140′ to a predetermined extent. Even in this case, the lower surface of the second additional doped layer 134B can be controlled to be at a height equal to or higher than the upper surface of the second sacrificial layer 114B.

[0045] Doping of the impurities for forming the second additional doped layer 134B can be performed by tilting the implantation method towards one side 111B of the second initial stacked structure 110B (see arrow ④). Based on a horizontal plane (e.g., the surface of substrate 100), the tilting implantation angle can be smaller than [the required angle]. Figure 6A and Figure 6B The angle of the inclined injection.

[0046] In the following text, the second additional doped layer 134B and the second doped layer 132B′ will be referred to as the second channel layer 136B. The second channel layer 136B may correspond to the channel of a PMOS transistor. The second additional doped layer 134B can serve to reduce the contact resistance with the second upper electrode layer, which will be described later. In one embodiment, the second additional doped layer 134B may be omitted. When the process for forming the second additional doped layer 134B is omitted, Figure 7A and Figure 7B The second doped layer 132B can be used as the channel of a PMOS transistor.

[0047] Furthermore, the order of processes for forming the first additional doped layer 134A and the second additional doped layer 134B can be reversed. For example, the second additional doped layer 134B can be formed first, and then the first additional doped layer 134A can be formed later.

[0048] refer to Figure 10A and Figure 10B The first upper electrode layer 150A and the second upper electrode layer 150B can be formed on Figure 9A and Figure 9BBased on the process results, the first upper electrode layer 150A and the second upper electrode layer 150B can be formed to contact the first channel layer 136A and the second channel layer 136B, respectively. The first upper electrode layer 150A and the second upper electrode layer 150B can be electrically connected to the first channel layer 136A and the second channel layer 136B. When the lower electrode layer 120′′ is used as the common source of the NMOS transistor and the PMOS transistor, the first upper electrode layer 150A and the second upper electrode layer 150B can be used as the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor, respectively. For ease of description, in Figure 10B In the plan view, dashed lines are used to represent... Figure 10A The shapes of the first upper electrode layer 150A and the second upper electrode layer 150B are not visible at the height of line AA′.

[0049] From a plan view perspective, the first upper electrode layer 150A and the second upper electrode layer 150B can have rectangular shapes that overlap with the first channel layer 136A and the second channel layer 136B, respectively. For example, each of the first upper electrode layer 150A and the second upper electrode layer 150B can have a strip shape, wherein the side length of the strip shape in the first direction is longer than the side length in the second direction. Furthermore, from a plan view perspective, the width of each of the first upper electrode layer 150A and the second upper electrode layer 150B in the second direction can be equal to or greater than the width of the first channel layer 136A and the second channel layer 136B.

[0050] From a cross-sectional perspective, the first upper electrode layer 150A extends from the upper surface of the first channel layer 136A to the portion of the upper surface of the first initial stacked structure 110A adjacent to the upper surface of the first channel layer 136A, and extends to the side surface of the upper part of the first channel layer 136A that protrudes from the first interlayer dielectric layer 140'. Furthermore, from a cross-sectional perspective, the second upper electrode layer 150B extends from the upper surface of the second channel layer 136B to the portion of the upper surface of the second initial stacked structure 110B adjacent to the upper surface of the second channel layer 136B, and extends to the side surface of the upper part of the second channel layer 136B that protrudes from the first interlayer dielectric layer 140'. As a result, since the first upper electrode layer 150A covers the upper surface and part of the side surface of the first channel layer 136A, the contact area between the first upper electrode layer 150A and the first channel layer 136A is increased, which reduces the contact resistance. Furthermore, since the second upper electrode layer 150B covers the upper surface and part of the side surface of the second channel layer 136B, the contact area between the second upper electrode layer 150B and the second channel layer 136B is increased, which reduces the contact resistance. Additionally, since the first upper electrode layer 150A contacts a first additional doped layer 134A having a higher impurity concentration than the first doped layer 132A′ of the first channel layer 136A, and the second upper electrode layer 150B contacts a second additional doped layer 134B having a higher impurity concentration than the second doped layer 132B′ of the second channel layer 136B, the contact resistance between the first upper electrode layer 150A and the first channel layer 136A, and the contact resistance between the second upper electrode layer 150B and the second channel layer 136B, may be further reduced.

[0051] It can be done in Figure 9A and Figure 9B The first upper electrode layer 150A and the second upper electrode layer 150B are formed by depositing and patterning conductive materials on the process results, and they may include different conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), compounds of these metals and / or alloys of these metals.

[0052] refer to Figure 11A and Figure 11B It can form a coverage by Figure 10A and Figure 10B The second interlayer dielectric layer 160 of the structure produced by the process. The second interlayer dielectric layer 160 may include a dielectric material such as SiO2, which has an etching rate different from that of the first sacrificial layer 114A and the second sacrificial layer 114B, the first lower dielectric layer 112A and the second lower dielectric layer 112B, and the first upper dielectric layer 116A and the second upper dielectric layer 116B.

[0053] Subsequently, by selectively etching the second interlayer dielectric layer 160 and the first interlayer dielectric layer 140', a first contact hole CA can be formed, which exposes at least a portion (specifically, the second side of the first sacrificial layer 114A) of the first initial stacked structure 110A and the second side 111A' opposite to the first side 111A. From a vertical perspective, the first contact hole CA can be formed such that the lower surface of the first contact hole CA is at a depth equal to or lower than the height of the lower surface of the first sacrificial layer 114A. For example, as shown, the first contact hole CA can be formed to a depth that exposes the substrate 100. Furthermore, from a planar perspective, the first contact hole CA is illustrated as having a strip shape, in which the length in the first direction is longer than the length in the second direction and slightly shorter than the side length of the first initial stacked structure 110A in the first direction. However, the present invention is not limited thereto, and the shape and / or size of the first contact hole CA on the plane can be modified in various ways, as long as the first contact hole CA exposes the first sacrificial layer 114A in the second side 111A′ of the first initial stacked structure 110A to remove the first sacrificial layer 114A.

[0054] Subsequently, the first sacrificial layer 114A exposed by the first contact hole CA can be removed. Hereinafter, the space formed by removing the first sacrificial layer 114A may be referred to as the first recess portion GA. The first sacrificial layer 114A can be removed by an isotropic etching process. Since the first interlayer dielectric layer 140′, the second interlayer dielectric layer 160, the first lower dielectric layer 112A, and the first upper dielectric layer 116A can be formed from materials having an etching rate different from that of the first sacrificial layer 114A, these layers 140′, 160, 112A, and 116A can be maintained when the first sacrificial layer 114A is removed.

[0055] Subsequently, a first gate dielectric layer 172A can be formed along the inner walls of the first contact hole CA and the first recessed portion GA. The first gate dielectric layer 172A can be conformally formed to have a thin thickness that does not completely fill the first contact hole CA and the first recessed portion GA.

[0056] Subsequently, a first gate electrode layer 174A can be formed along the surface of the first gate dielectric layer 172A in the first recessed portion GA and the first contact hole CA in which the first gate dielectric layer 172A is formed. In an embodiment, the first gate electrode layer 174A can be conformally formed to have a thickness that completely fills the first recessed portion GA but not completely fills the first contact hole CA. However, the present invention is not limited thereto. In another embodiment, the first gate electrode layer 174A can be formed to have a thickness that completely fills the first contact hole CA and the first recessed portion GA. In yet another embodiment, the first gate electrode layer 174A can be formed to have a thickness that fills a portion of the first contact hole CA and a portion of the first recessed portion GA.

[0057] The first gate electrode layer 174A can be used as the gate electrode of an NMOS transistor, and therefore can include a metallic material having an effective work function suitable for an NMOS transistor. The metallic material can include metals, metal compounds, or metal alloys. When the first channel layer 136A is doped with a high concentration of N-type impurities, the first gate electrode layer 174A can include a metallic material with a large work function, such as TaN (tantalum nitride) or TiN (titanium nitride), such that the portion of the first channel layer 136A facing the first gate electrode layer 174A can become a depletion region to reduce the cutoff current of the NMOS transistor.

[0058] Subsequently, a first metal-containing layer 176A can be formed to fill the remaining space of the first contact hole CA in which the first gate electrode layer 174A is formed. The first metal-containing layer 176A can be a metal-containing material with a lower resistance than the first gate electrode layer 174A, such as metals like tungsten (W), molybdenum (Mo), ruthenium (Ru), metal compounds, or metal alloys. The first metal-containing layer 176A can have a lower resistance than the first gate electrode layer 174A and can therefore be used to facilitate the transfer of current / voltage to the first gate electrode layer 174A. In another embodiment where the first gate electrode layer 174A completely fills the first contact hole CA and the first recessed portion GA, the first metal-containing layer 176A can be omitted. In yet another embodiment where the first gate electrode layer 174A does not completely fill the first contact hole CA and the first recessed portion GA, the first metal-containing layer 176A can be formed to completely fill the remaining space of the first recessed portion GA in which the first gate dielectric layer 172A and the first gate electrode layer 174A are formed, as well as the first contact hole CA.

[0059] In the first gate dielectric layer 172A, the first gate electrode layer 174A, and / or the first metal-containing layer 176A, the portion buried in the first recessed portion GA can be referred to as the first horizontal gate structure GPA, and the portion filling the first contact hole CA can be referred to as the first vertical gate structure CPA. The first horizontal gate structure GPA may include the first gate electrode layer 174A and the first gate dielectric layer 172A, wherein the first gate dielectric layer 172A surrounds the upper surface of the first gate electrode layer 174A, the lower surface of the first gate electrode layer 174A, and the side of the first gate electrode layer 174A facing the first side surface 111A. As a result, the first gate dielectric layer 172A may be located between the first gate electrode layer 174A and the first channel layer 136A. The first vertical gate structure CPA may include a first metal-containing layer 176A, a first gate electrode layer 174A, and a first gate dielectric layer 172A. The first metal-containing layer 176A has a columnar shape. The first gate electrode layer 174A surrounds the side and lower surface of the first metal-containing layer 176A and extends from the first horizontal gate structure GPA. The first gate dielectric layer 172A surrounds the side and lower surface of the first gate electrode layer 174A of the first vertical gate structure CPA and extends from the first horizontal gate structure GPA. Since the first horizontal gate structure GPA fills the first recessed portion GA, it can have a planar and cross-sectional shape substantially the same as the planar and cross-sectional shape of the first sacrificial layer 114A described above. Since the first vertical gate structure CPA is buried in the first contact hole CA, it can have a planar and cross-sectional shape substantially the same as the planar and cross-sectional shape of the first contact hole CA described above. Furthermore, in the following text, the stacked structure of the first upper dielectric layer 116A, the first horizontal gate structure GPA, and the first lower dielectric layer 112A formed by replacing the first sacrificial layer 114A with the first horizontal gate structure GPA can be referred to as the first stacked structure 110A′.

[0060] As a result, an NMOS transistor comprising a first horizontal gate structure GPA, a first channel layer 136A, a lower electrode layer 120′′, and a first upper electrode layer 150A can be manufactured.

[0061] refer to Figure 12A and Figure 12BThe second interlayer dielectric layer 160 and the first interlayer dielectric layer 140′ can be selectively etched to form a second contact hole CB, which exposes at least a portion (particularly the second side surface of the second sacrificial layer 114B) of the first side surface 111B and the second side surface 111B′ opposite to the first side surface 111B. In the vertical direction, the second contact hole CB can be formed with a depth such that the lower surface of the second contact hole CB is at a height equal to or lower than the lower surface of the second sacrificial layer 114B. For example, as shown, the second contact hole CB can be formed with a depth that exposes the substrate 100. Furthermore, from a plan view perspective, the second contact hole CB is illustrated as having a strip shape in which the length in the first direction is longer than the length in the second direction and slightly shorter than the side length of the second initial stacked structure 110B in the first direction. However, the present invention is not limited thereto, and the shape or size of the second contact hole CB on the plane can be modified in various ways, as long as the second sacrificial layer 114B can be removed by exposing the second sacrificial layer 114B on the second side 111B′ of the second initial stacked structure 110B.

[0062] Subsequently, the second sacrificial layer 114B exposed by forming the second contact hole CB can be removed. The space formed by removing the second sacrificial layer 114B can be referred to hereinafter as the second recess portion GB.

[0063] Subsequently, a second gate dielectric layer 172B can be formed along the inner wall of the second contact hole CB and the second recess portion GB. The second gate dielectric layer 172B can be conformally formed to have a thin thickness that does not completely fill the second contact hole CB and the second recess portion GB.

[0064] Subsequently, a second gate electrode layer 174B can be formed along the surface of the second gate dielectric layer 172B in the second recessed portion GB and the second contact hole CB where the second gate dielectric layer 172B is formed. For example, the second gate electrode layer 174B can be conformally formed to have a thickness that does not completely fill the second contact hole CB but completely fills the second recessed portion GB. However, the present invention is not limited thereto. In another embodiment of the present invention, the second gate electrode layer 174B can be formed to have a thickness that completely fills the second recessed portion GB and the second contact hole CB. Alternatively, in yet another embodiment, the second gate electrode layer 174B can be formed to have a thickness that fills a portion of the second contact hole CB and a portion of the second recessed portion GB.

[0065] The second gate electrode layer 174B can be used as the gate electrode of a PMOS transistor. The second gate electrode layer 174B may include a metallic material having an effective work function suitable for a PMOS transistor. For example, when the second channel layer 136B is doped with a high concentration of P-type impurities, the second gate electrode layer 174B may include a metallic material with a relatively small work function, such as TiAl or TiC, such that the portion of the second channel layer 136B facing the second gate electrode layer 174B can be depleted, and thus the cutoff current of the PMOS transistor can be reduced.

[0066] Subsequently, a second metal-containing layer 176B can be formed to fill the remaining space of the second contact hole CB in which the second gate electrode layer 174B is formed. The second metal-containing layer 176B may comprise a metal-containing material with a lower resistance than the second gate electrode layer 174B, such as metals like tungsten (W), molybdenum (Mo), and ruthenium (Ru), metal compounds, or metal alloys. Because the second metal-containing layer 176B has a lower resistance than the second gate electrode layer 174B, it can be used to facilitate the transfer of current / voltage to the second gate electrode layer 174B. In another embodiment, the second metal-containing layer 176B may be omitted when the second gate electrode layer 174B completely fills the second contact hole CB and the second groove portion GB. Alternatively, in yet another embodiment, when the second gate electrode layer 174B does not completely fill the second contact hole CB and the second groove portion GB, the second metal-containing layer 176B may be formed to completely fill the remaining space in which the second groove portion GB and the second contact hole CB are formed, wherein the second gate dielectric layer 172B and the second gate electrode layer 174B are formed.

[0067] In the second gate dielectric layer 172B, the second gate electrode layer 174B, and / or the second metal-containing layer 176B, the portion filling the second recess portion GB can be referred to as the second horizontal gate structure GPB, and the portion filling the second contact hole CB will be referred to as the second vertical gate structure CPB. The second horizontal gate structure GPB may include the second gate electrode layer 174B and the second gate dielectric layer 172B, wherein the second gate dielectric layer 172B surrounds the upper surface of the second gate electrode layer 174B, the lower surface of the second gate electrode layer 174B, and the side of the second gate electrode layer 174B facing the first side surface 111B. Therefore, the second gate dielectric layer 172B may be located between the second gate electrode layer 174B and the second channel layer 136B. The second vertical gate structure CPB may include a columnar second metal-containing layer 176B, a second gate electrode layer 174B, and a second gate dielectric layer 172B. The second gate electrode layer 174B extends from the second horizontal gate structure GPB and surrounds the side and bottom surfaces of the second metal-containing layer 176B. The second gate dielectric layer 172B extends from the second horizontal gate structure GPB and surrounds the side and bottom surfaces of the second gate electrode layer 174B of the second vertical gate structure CPB. Since the second horizontal gate structure GPB fills the second recess portion GB, it can have a plane and cross-sectional shape substantially the same as the planar and cross-sectional shape of the second sacrificial layer 114B described above. Since the second vertical gate structure CPB is buried in the second contact hole CB, it can also have a plane and cross-sectional shape substantially the same as the planar and cross-sectional shape of the second contact hole CB described above. Furthermore, in the following text, the stacked structure of the second upper dielectric layer 116B, the second horizontal gate structure GPB, and the second lower dielectric layer 112B formed by replacing the second sacrificial layer 114B with the second horizontal gate structure GPB can be referred to as the second stacked structure 110B′.

[0068] As a result, a PMOS transistor can be formed, comprising a second horizontal gate structure GPB, a second channel layer 136B, a lower electrode layer 120′′, and a second upper electrode layer 150B.

[0069] In addition, CMOS transistors, including NMOS transistors and PMOS transistors sharing a lower electrode layer 120′′, can be formed.

[0070] After formation, the CMOS transistor can be electrically connected to the lower electrode layer 120′′, the first upper electrode layer 150A and the second upper electrode layer 150B, and the first horizontal gate structure GPA and the second horizontal gate structure GPB. Different wiring structures can be formed to control them. This will be referenced below. Figures 13A to 14B Describe it.

[0071] refer to Figure 13A and Figure 13B It can be made by Figure 12A and Figure 12B A third interlayer dielectric layer 180 is formed on top of the structure produced by the process. The third interlayer dielectric layer 180 may include a variety of dielectric materials, such as SiO2.

[0072] Subsequently, the lower electrode contact 182 can be formed to be coupled to the lower electrode layer 120′′ and can pass through the third interlayer dielectric layer 180, the second interlayer dielectric layer 160, and the first interlayer dielectric layer 140′. In the first direction, the lower electrode contact 182 may not be located between the first stacked structure 110A′ and the second stacked structure 110B′, but rather outside the space between the first stacked structure 110A′ and the second stacked structure 110B′. This is because it is difficult to form the lower electrode contact 182 when the space between the first stacked structure 110A′ and the second stacked structure 110B′ is narrow. As an example, two lower electrode contacts 182 may be located in the first direction on the first side surface 111A and the second side surface 111A′ of the first initial stacked structure 110A and the first side surface 111B and the second side surface 111B′ of the second initial stacked structure 110B. However, the present invention is not limited thereto, and the number and arrangement of the lower electrode contacts 182 can be modified in various ways based on the assumption that they can overlap and couple with the lower electrode layer 120′′. For ease of description, in Figure 13A In the cross-sectional view, it is shown by the dashed line. Figure 13B The shape of the lower electrode contact portion 182 is not visible on line BB′. Furthermore, in Figure 13B In the cross-sectional view, the lower electrode contact 182 is shown as a point. The lower electrode contact 182 can be formed by selectively etching the third interlayer dielectric layer 180, the second interlayer dielectric layer 160, and the first interlayer dielectric layer 140′ to form a contact hole that exposes the lower electrode layer 120′′, and then filling the contact hole with a conductive material including but not limited to metal.

[0073] Subsequently, a lower electrode line 184 extending in one direction can be formed on the third interlayer dielectric layer 180, while the lower electrode line 184 overlaps and couples with the lower electrode contact portion 182. When the two lower electrode contacts 182 are arranged in the first direction as shown in this embodiment of the present invention, the lower electrode line 184 can extend in the first direction to overlap and couple with the two lower electrode contacts 182. The lower electrode line 184 can be electrically connected to the lower electrode layer 120′′ through the lower electrode contacts 182, and therefore the lower electrode line 184 can be used as a common source line to drive the lower electrode layer 120′′. For ease of description, in Figure 13B In the plan view, it is shown by solid lines. Figure 13AThe lower electrode line 184 is not visible at the height of line AA′.

[0074] refer to Figure 14A and Figure 14B , can Figure 13A and Figure 13B A fourth interlayer dielectric layer 190 is formed on top of the structure produced by the process. The fourth interlayer dielectric layer 190 can be thick enough to cover the thickness of the lower electrode line 184. For example... Figure 14A As shown, the fourth interlayer dielectric layer 190 can have a thickness greater than that of the lower electrode line 184. The fourth interlayer dielectric layer 190 can be made of any suitable dielectric material, including, for example, SiO2.

[0075] Subsequently, a first upper electrode contact 192A and a second upper electrode contact 192B can be formed through the fourth interlayer dielectric layer 190, the third interlayer dielectric layer 180, and the second interlayer dielectric layer 160. The first upper electrode layer 150A and the second upper electrode layer 150B can be respectively connected to the first upper electrode contact 192A and the second upper electrode contact 192B. According to one embodiment of the present invention, a plurality of first upper electrode contacts 192A can be arranged in a line along a first direction while coupled to the first upper electrode layer 150A, and a plurality of second upper electrode contacts 192B can be arranged in a line along the first direction while coupled to the second upper electrode layer 150B. However, the present invention is not limited to this, and various modifications can be made to the number and arrangement of the first upper electrode contacts 192A and the second upper electrode contacts 192B as long as the first upper electrode contacts 192A and the second upper electrode contacts 192B overlap and are coupled to the first upper electrode layer 150A and the second upper electrode layer 150B, respectively. The first upper electrode contact 192A and the second upper electrode contact 192B can be formed by selectively etching the fourth interlayer dielectric layer 190, the third interlayer dielectric layer 180 and the second interlayer dielectric layer 160 to form contact holes that expose the first upper electrode layer 150A and the second upper electrode layer 150B, and then filling the contact holes with a suitable conductive material (including, for example, a metal).

[0076] Subsequently, a first upper electrode line 194A and a second upper electrode line 194B can be formed on the fourth interlayer dielectric layer 190. The first upper electrode line 194A and the second upper electrode line 194B extend in one direction and overlap with and couple to the first upper electrode contact portion 192A and the second upper electrode contact portion 192B, respectively. In this embodiment of the present invention, when the first upper electrode contact portion 192A is arranged as a line along the first direction, the first upper electrode line 194A can extend in the first direction. Similarly, when the second upper electrode contact portion 192B is arranged as a line along the first direction, the second upper electrode line 194B can extend in the first direction. Since the first upper electrode line 194A is electrically connected to the first upper electrode layer 150A through the first upper electrode contact portion 192A, the first upper electrode line 194A can be used as a first line to drive the first upper electrode layer 150A. Since the second upper electrode line 194B is electrically connected to the second upper electrode layer 150B through the second upper electrode contact portion 192B, the second upper electrode line 194B can be used as a second bit line to drive the second upper electrode layer 150B.

[0077] Furthermore, the first gate contact 196A and the second gate contact 196B can be formed to penetrate the fourth interlayer dielectric layer 190 and the third interlayer dielectric layer 180 to be coupled to the first vertical gate structure CPA and the second vertical gate structure CPB, respectively. In the embodiments disclosed in this invention, a plurality of first gate contacts 196A can be arranged in a line along a first direction while being coupled to the first vertical gate structure CPA, and a plurality of second gate contacts 196B can be arranged in a line along the first direction while being coupled to the second vertical gate structure CPB. As long as the first gate contacts 196A and the second gate contacts 196B overlap and are coupled to the first vertical gate structure CPA and the second vertical gate structure CPB, various modifications can be made to the number and arrangement of the first gate contacts 196A and the second gate contacts 196B. The first gate contact 196A and the second gate contact 196B can be formed by selectively etching the fourth interlayer dielectric layer 190 and the third interlayer dielectric layer 180 to form contact holes that expose the first vertical gate structure CPA and the second vertical gate structure CPB, and then filling the contact holes with a suitable conductive material (including, for example, a metal). The processes for forming the first gate contact 196A and the second gate contact 196B and the processes for forming the first upper electrode contact 192A and the second upper electrode contact 192B can be performed simultaneously.

[0078] Subsequently, a first gate line 198A and a second gate line 198B extending in one direction and overlapping and coupling with the first gate contact 196A and the second gate contact 196B, respectively, can be formed on the fourth interlayer dielectric layer 190. According to one embodiment of the present invention, when the first gate contact 196A is arranged as a line along a first direction, the first gate line 198A can extend in the first direction. Similarly, when the second gate contact 196B is arranged as a line along the first direction, the second gate line 198B can extend in the first direction. Since the first gate line 198A is electrically connected to the first horizontal gate structure GPA through the first gate contact 196A and the first vertical gate structure CPA, the first gate line 198A can be used as a first word line to drive the first horizontal gate structure GPA. Since the second gate line 198B is electrically connected to the second horizontal gate structure GPB through the second gate contact 196B and the second vertical gate structure CPB, the second gate line 198B can be used as a second word line to drive the second horizontal gate structure GPB. The processes for forming the first gate line 198A and the second gate line 198B, as well as the processes for forming the first upper electrode line 194A and the second upper electrode line 194B, can be performed simultaneously.

[0079] For ease of description, Figure 14B In the plan view, points and solid lines are used to indicate the position of the points. Figure 14A The first upper electrode contact 192A and the second upper electrode contact 192B, the first upper electrode line 194A and the second upper electrode line 194B, the first gate contact 196A and the second gate contact 196B, and the first gate line 198A and the second gate line 198B are not visible at the height of line AA′.

[0080] In this embodiment of the present invention, the lower electrode line 184 is shown to be located vertically below the first upper electrode line 194A, the second upper electrode line 194B, and the first gate line 198A and the second gate line 198B. ​​This is because when the lower electrode line 184 is at the same level as the first upper electrode line 194A and the second upper electrode line 194B, a short circuit may occur due to the narrow gap between them. Furthermore, in this embodiment of the present invention, the first upper electrode line 194A, the second upper electrode line 194B, and the first gate line 198A and the second gate line 198B are shown to be at the same level vertically. This is because sufficient gap can be ensured between them. However, the present invention is not limited to this. Various modifications can be made to the vertical positions of the lower electrode line 184, the first upper electrode line 194A, the second upper electrode line 194B, and the first gate line 198A and the second gate line 198B.

[0081] The semiconductor device of this embodiment can be manufactured using the manufacturing method described above.

[0082] Return to reference Figure 14A and Figure 14B The semiconductor device according to various embodiments of the present invention may include: a substrate 100; a first stacked structure 110A′ disposed on the substrate 100 and including a first lower dielectric layer 112A, a first horizontal gate structure GPA, and a first upper dielectric layer 116A stacked in a vertical direction; a second stacked structure 110B′ disposed on the substrate 100 to have a first side 111B facing the first side 111A of the first stacked structure 110A′ and including a second lower dielectric layer 112B, a second horizontal gate structure GPB, and a second upper dielectric layer 116B stacked in a vertical direction; and a first channel layer 136A formed to... The system comprises: a first horizontal gate structure GPA facing at least on the first side 111A of the first stacked structure 110A′; a second channel layer 136B, which is formed as a second horizontal gate structure GPB facing at least on the first side 111B of the second stacked structure 110B′; a lower electrode layer 120′′ disposed between the first stacked structure 110A′ and the second stacked structure 110B′ and coupled together to the lower ends of the first channel layer 136A and the second channel layer 136B; a first upper electrode layer 150A coupled to the upper end of the first channel layer 136A; and a second upper electrode layer 150B coupled to the upper end of the second channel layer 136B.

[0083] Furthermore, a first vertical gate structure CPA and a second vertical gate structure CPB can be formed on the substrate 100. The first vertical gate structure CPA extends in the vertical direction and is coupled to a first horizontal gate structure GPA located in a second side 111A' opposite to the first side 111A of the first stacked structure 110A'. The second vertical gate structure CPB extends in the vertical direction and is coupled to a second horizontal gate structure GPB disposed on a second side 111B' opposite to the first side 111B of the second stacked structure 110B'.

[0084] The lower electrode layer 120′′, the first vertical gate structure CPA and the second vertical gate structure CPB, as well as the first upper electrode layer 150A and the second upper electrode layer 150B, can be driven by wiring structures of various shapes. For example, the wiring structures shown in the figure include the lower electrode contact 182, the lower electrode line 184, the first gate contact 196A and the second gate contact 196B, the first gate line 198A and the second gate line 198B, the first upper electrode contact 192A and the second upper electrode contact 192B, and the first upper electrode line 194A and the second upper electrode line 194B.

[0085] Since the details of the constituent elements of the semiconductor device according to the embodiments of the present invention have already been described in the process of describing the manufacturing method, their description will be omitted.

[0086] The following effects can be obtained based on the above-mentioned semiconductor device and its manufacturing method.

[0087] First, since the first channel layer 136A and the second channel layer 136B, which serve as the channels for NMOS and PMOS transistors, extend vertically, the distance between the first channel layer 136A and the second channel layer 136B in the horizontal direction can be reduced. As a result, the planar area of ​​the semiconductor device and the parasitic capacitance originating from the first channel layer 136A and the second channel layer 136B can also be reduced.

[0088] Furthermore, by doping impurities on the thin film material layer 130 to form the first channel layer 136A and the second channel layer 136B, the thickness of the first channel layer 136A and the second channel layer 136B can be reduced, improving the controllability of the transistor. However, in this case, the drive current may be reduced, but this can be compensated for by increasing the width and / or length of the first channel layer 136A and the second channel layer 136B in the first direction.

[0089] Furthermore, unlike typical planar transistors where the gate electrode faces the source / drain contacts, thus generating a large amount of parasitic capacitance, there may be a small number of contacts facing the first horizontal gate structure GPA and the second horizontal gate structure GPB, as well as the first vertical gate structure CPA and the second vertical gate structure CPB, or no contacts at all. For example, in the embodiments disclosed in this invention, the lower electrode contact 182 and the first upper electrode contact 192A and the second upper electrode contact 192B may not face the first horizontal gate structure GPA and the second horizontal gate structure GPB, as well as the first vertical gate structure CPA and the second vertical gate structure CPB, or they may face a portion of the first horizontal gate structure GPA and the second horizontal gate structure GPB, as well as the first vertical gate structure CPA and the second vertical gate structure CPB. As a result, the parasitic capacitance can be further reduced compared to planar transistors.

[0090] Figure 15 and Figure 16 This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present invention. Specifically, Figure 15 It shows that it can be used Figure 5A and Figure 5B The process and Figure 7A and Figure 7B The intermediate process steps performed between processes, and Figure 16 It shows that it can be used Figure 6A and Figure 6B The process and Figure 7A and Figure 7B Intermediate process steps performed between processes.

[0091] refer to Figure 15 After forming the first doped layer 132A, a different type of impurity, such as a P-type impurity, can be de-doped in region L1 of the first doped layer 132A facing the first sacrificial layer 114A. For example, region L1 can be a region of the first doped layer 132A that is substantially at the same or similar level to the first sacrificial layer 114A. The concentration of the de-doped P-type impurity can be lower than the concentration of the N-type impurity in the first doped layer 132A. In this case, the concentration of the N-type impurity can be reduced in region L1 while maintaining the N-type, thereby reducing the cutoff current of the NMOS transistor. When the first sacrificial layer 114A is replaced with a gate electrode layer in a subsequent process, a metal-containing material with a relatively small work function (such as TiAl (titanium aluminide) or TiC (titanium carbide)) can be used as the gate electrode layer. This is because, unlike the embodiments disclosed above, since the N-type impurity concentration in region L1 of the first doped layer 132A is relatively low, a separate process for forming a depletion region is not required.

[0092] Doping of impurities for forming region L1 can be performed using a tilt implantation method that tilts towards the first side 111A of the first initial stacked structure 110A (see arrow ⑤). Based on a horizontal plane (e.g., the surface of substrate 100), the tilt implantation angle can be smaller than [the required angle]. Figure 5A and Figure 5B The angle of the inclined injection can be greater than that of the angle of the inclined injection. Figure 8A and Figure 8B The angle of the inclined injection. The angle of inclined injection used here is the angle formed between the injection direction and the horizontal plane.

[0093] refer to Figure 16After forming the second doped layer 132B, an impurity of a different conductivity type than the impurities in the second doped layer 132B, such as an N-type impurity, can be de-doped in region L2 of the second doped layer 132B facing the second sacrificial layer 114B. For example, region L2 can be a region of the second doped layer 132B that is substantially at the same or similar level to the second sacrificial layer 114B. The concentration of the de-doped N-type impurity can be lower than the concentration of the P-type impurities in the second doped layer 132B. In this case, the concentration of the P-type impurities in region L2 can be reduced while maintaining the P-type, thereby reducing the cutoff current of the PMOS transistor. When the second sacrificial layer 114B is replaced with a gate electrode layer in a subsequent process, a metal-containing material with a large work function (such as TaN or TiN) can be used as the gate electrode layer. Unlike the embodiments disclosed above, since the concentration of the P-type impurities in region L2 of the second doped layer 132B is relatively low, a separate process for forming the depletion region is not required.

[0094] Doping of impurities for forming region L2 can be performed using a tilt implantation method that tilts towards the first side 111B of the second initial stacked structure 110B (see arrow ⑥). Based on a horizontal plane (e.g., the surface of substrate 100), the tilt implantation angle can be smaller than [the required angle]. Figure 6A and Figure 6B The angle of the inclined injection can be greater than that of the angle of the inclined injection. Figure 9A and Figure 9B The angle of the inclined injection.

[0095] Since the subsequent processes are substantially the same as those described in the above embodiments of the present invention, detailed descriptions thereof will be omitted.

[0096] Furthermore, although the above embodiments pertain to semiconductor devices including CMOS transistors and methods for manufacturing the same, the disclosure of this invention is not limited thereto. According to embodiments of the present invention, semiconductor devices including NMOS transistors or semiconductor devices including PMOS transistors can be manufactured. This will be referred to below. Figure 17A and Figure 17B Describe it.

[0097] Figure 17A and Figure 17B This is a view illustrating a semiconductor device and a method of manufacturing the semiconductor device according to another embodiment of the present invention. Figure 17A It is along Figure 17B The cross-sectional view of line BB′, and Figure 17B This is a plan view shown at the height of line AA′. However, in Figure 17A Some components that are not visible at the height of line AA′ can be found at... Figure 17B The line is represented by a dashed line, a solid line, or a dot, or in... Figure 17B The components that are not visible at the height of line BB′ can be Figure 17A The diagram is shown as a dashed line. The differences from the above-described embodiments disclosed in this invention will be highlighted.

[0098] refer to Figure 17A and Figure 17B A first stacked structure 210A and a second stacked structure 210B can be formed on the substrate 200. The first stacked structure 210A may include a first lower dielectric layer 212A, a first horizontal gate structure GPA, and a first upper dielectric layer 216A stacked on the substrate 200 in the vertical direction. The second stacked structure 210B may include a second lower dielectric layer 212B, a second horizontal gate structure GPB, and a second upper dielectric layer 216B stacked on the substrate 200 in the vertical direction. The first side surface 211B of the second stacked structure 210B faces the first side surface 211A of the first stacked structure 210A. The first horizontal gate structure GPA may include a first gate electrode layer 274A and a first gate dielectric layer 272A, with the first gate dielectric layer 272A surrounding the upper and lower surfaces of the first gate electrode layer 274A and the side surface facing the first side surface 211A. In addition, the second horizontal gate structure GPB may include a second gate electrode layer 274B and a second gate dielectric layer 272B, wherein the second gate dielectric layer 272B surrounds the upper and lower surfaces of the second gate electrode layer 274B and the side facing the first side 211B.

[0099] The lower electrode layer 220′′ can be disposed on the substrate 200 between the first stacked structure 210A and the second stacked structure 210B. The lower electrode layer 220′′ can have an upper surface disposed at a height equal to or lower than the upper surfaces of the first lower dielectric layer 212A and the second lower dielectric layer 212B, to be spaced apart from the first horizontal gate structure GPA and the second horizontal gate structure GPB, and in particular from the first gate electrode layer 274A and the second gate electrode layer 274B.

[0100] The first channel layer 236A and the second channel layer 236B can be formed on the first side surface 211A of the first stacked structure 210A and the first side surface 211B of the second stacked structure 210B, respectively. In addition, the lower end of the first channel layer 236A and the lower end of the second channel layer 236B can be connected together to the lower electrode layer 220′′.

[0101] Here, both the first channel layer 236A and the second channel layer 236B can be doped with impurities of the same conductivity type. For example, when the first channel layer 236A and the second channel layer 236B are doped with N-type impurities, the first channel layer 236A and the second channel layer 236B can be used as the channel of an NMOS transistor. When the first channel layer 236A includes a first doped layer 232A′ and a first additional doped layer 234A, and the second channel layer 236B includes a second doped layer 232B′ and a second additional doped layer 234B, all of the first doped layer 232A′, the first additional doped layer 234A, the second doped layer 232B′, and the second additional doped layer 234B can include N-type impurities. Alternatively, as another example, when the first channel layer 236A and the second channel layer 236B are doped with P-type impurities, the first channel layer 236A and the second channel layer 236B can be used as the channel of a PMOS transistor. When the first channel layer 236A includes a first doped layer 232A′ and a first additional doped layer 234A, and the second channel layer 236B includes a second doped layer 232B′ and a second additional doped layer 234B, all of the first doped layer 232A′, the first additional doped layer 234A, the second doped layer 232B′, and the second additional doped layer 234B may include P-type impurities. In this case, the first gate electrode layer 274A and the second gate electrode layer 274B may be formed of materials having the same work function. An undoped material layer pattern 230′ may exist between the lower end of the first channel layer 236A and the lower end of the second channel layer 236B.

[0102] A first upper electrode layer 250A and a second upper electrode layer 250B can be formed on the first channel layer 236A and the second channel layer 236B to contact and electrically connect with the first channel layer 236A and the second channel layer 236B. When there is a first interlayer dielectric layer 240' between the first channel layer 236A and the second channel layer 236B, the upper surface of which is lower than the upper surfaces of the first channel layer 236A and the second channel layer 236B, the first upper electrode layer 250A can surround a portion of the side surface of the first channel layer 236A that protrudes above the first interlayer dielectric layer 240' and its upper surface, and the second upper electrode layer 250B can surround a portion of the side surface of the second channel layer 236B that protrudes above the first interlayer dielectric layer 240' and its upper surface.

[0103] Furthermore, a first vertical gate structure CPA can be formed, extending vertically and coupled to a first horizontal gate structure GPA located on a second side 211A′ opposite to the first side 211A of the first stacked structure 210A. Additionally, a second vertical gate structure CPB can be formed on the substrate 200, extending vertically and coupled to a second horizontal gate structure GPB located on a second side 211B′ opposite to the first side 211B of the second stacked structure 210B. The first vertical gate structure CPA may include a columnar first metal-containing layer 276A, a first gate electrode layer 274A, and a first gate dielectric layer 272A, wherein the first gate electrode layer 274A extends from the first horizontal gate structure GPA and surrounds the side and lower surface of the first metal-containing layer 276A, and the first gate dielectric layer 272A extends from the first horizontal gate structure GPA and surrounds the side and lower surface of the first gate electrode layer 274A of the first vertical gate structure CPA. The second vertical gate structure CPB may include a columnar second metal-containing layer 276B, a second gate electrode layer 274B, and a second gate dielectric layer 272B, wherein the second gate electrode layer 274B extends from the second horizontal gate structure GPB and surrounds the side and lower surface of the second metal-containing layer 276B, and the second gate dielectric layer 272B extends from the second horizontal gate structure GPB and surrounds the side and lower surface of the second gate electrode layer 274B of the second vertical gate structure CPB.

[0104] The lower electrode contact 282 can be formed to pass through the third interlayer dielectric layer 280, the second interlayer dielectric layer 260, and the first interlayer dielectric layer 240′ to couple to the lower electrode layer 220′′. The lower electrode line 284 can be formed to extend in a first direction, while overlapping and coupling with the lower electrode contact 282 on the third interlayer dielectric layer 280.

[0105] The first upper electrode contact 292A and the second upper electrode contact 292B can be formed to pass through the fourth interlayer dielectric layer 290, the third interlayer dielectric layer 280, and the second interlayer dielectric layer 260 to be coupled to the first upper electrode layer 250A and the second upper electrode layer 250B, respectively. The first upper electrode line 294A and the second upper electrode line 294B can be formed to extend in a first direction, overlapping and coupling with the first upper electrode contact 292A and the second upper electrode contact 292B on the fourth interlayer dielectric layer 290, respectively. In this case, the first upper electrode line 294A and the second upper electrode line 294B can be coupled to each other through a first coupling pattern 295. The first coupling pattern 295 can be at the same height as the first upper electrode line 294A and the second upper electrode line 294B, and extends in a second direction between the first upper electrode line 294A and the second upper electrode line 294B. Various modifications can be made to the number of the first coupling pattern 295, as long as the number is one or more.

[0106] The first gate contact 296A and the second gate contact 296B can be formed to pass through the fourth interlayer dielectric layer 290 and the third interlayer dielectric layer 280, respectively, to be coupled to the first vertical gate structure CPA and the second vertical gate structure CPB. The first gate line 298A and the second gate line 298B can be formed to extend in a first direction, overlapping and coupling with the first gate contact 296A and the second gate contact 296B on the fourth interlayer dielectric layer 290. In this case, the first gate line 298A and the second gate line 298B can be coupled to each other through a second coupling pattern 299. The second coupling pattern 299 can be at the same level as the first gate line 298A and the second gate line 298B, and extends in a second direction between the first gate line 298A and the second gate line 298B. Various modifications can be made to the number of second coupling patterns 299, as long as the number is one or more. Furthermore, the second coupling pattern 299 can be formed at a position that does not overlap with the first coupling pattern 295.

[0107] Even in this embodiment, substantially the same effects as those in the embodiments described above can be achieved. In other words, the size of the semiconductor device can be reduced, parasitic capacitance can be reduced, and operating characteristics can be improved.

[0108] The above embodiments are applicable to all semiconductor devices and their manufacturing methods, including NMOS transistors, PMOS transistors, or CMOS transistors. For example, the above embodiments can also be applied to a variety of semiconductor devices, including: non-volatile memories such as flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), and magnetoresistive random access memory (MRAM); volatile memories such as dynamic random access memory (DRAM) and static random access memory (SRAM); non-memory devices such as logic circuits; and CIS (CMOS image sensors).

[0109] According to one embodiment of the present invention, a semiconductor device is disclosed that has reduced parasitic capacitance and improved operating characteristics while having a reduced semiconductor device size, as well as a method for manufacturing the semiconductor device.

[0110] While the disclosure of this invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined in the appended claims.

Claims

1. A semiconductor device, comprising: A first stacked structure, the first stacked structure including a first lower dielectric layer, a first horizontal gate structure and a first upper dielectric layer stacked in the vertical direction; The second stacked structure includes a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked in a vertical direction, and the second stacked structure has a first side facing the first side of the first stacked structure. A first trench layer is formed on the upper part of the first side surface of the first stacked structure; A second trench layer is formed on the upper part of the first side surface of the second stacked structure; The lower electrode layer is commonly coupled to the lower end of the first channel layer and the lower end of the second channel layer between the first stacked structure and the second stacked structure. The lower electrode layer has a first sidewall that contacts the lower part of the first side surface of the first stacked structure and a second sidewall that contacts the lower part of the first side surface of the second stacked structure. A first upper electrode layer is coupled to the upper end of the first channel layer; as well as The second upper electrode layer is coupled to the upper end of the second channel layer.

2. The semiconductor device as claimed in claim 1, wherein, The first channel layer includes impurities of a first conductivity type, and The second channel layer includes impurities of a second conductivity type that are different from the first conductivity type.

3. The semiconductor device of claim 1, wherein, The first channel layer and the second channel layer contain impurities of the same conductivity type.

4. The semiconductor device as claimed in claim 1, wherein, The first channel layer includes a first doped layer and a first additional doped layer above the first doped layer, wherein the impurity concentration of the first additional doped layer is greater than the impurity concentration of the first doped layer. The second channel layer includes a second doped layer and a second additional doped layer on top of the second doped layer, wherein the concentration of impurities in the second additional doped layer is greater than the concentration of impurities in the second doped layer.

5. The semiconductor device as claimed in claim 4, wherein, The first upper electrode layer is in contact with the first additional doped layer, and The second upper electrode layer is in contact with the second additional doped layer.

6. The semiconductor device of claim 1, further comprising: A dielectric layer having an upper surface at a height lower than the upper surfaces of the first channel layer and the second channel layer, and filling the space between the first channel layer and the second channel layer. Wherein, the first upper electrode layer surrounds a portion of the side surface of the first channel layer that protrudes from the dielectric layer and its upper surface, and The second upper electrode layer surrounds a portion of the side surface of the second channel layer that protrudes from the dielectric layer and its upper surface.

7. The semiconductor device of claim 1, wherein, The upper surface of the lower electrode layer is located at a height equal to or lower than the upper surface of the first lower dielectric layer and the upper surface of the second lower dielectric layer.

8. The semiconductor device of claim 1, further comprising: A first vertical gate structure extends in the vertical direction and is coupled to a first horizontal gate structure on a second side of the first stacked structure; as well as A second vertical gate structure extends in the vertical direction and is coupled to a second horizontal gate structure on a second side of the second stacked structure.

9. The semiconductor device of claim 1, wherein, The first horizontal gate structure includes: a first gate electrode layer; and a first gate dielectric layer, the first gate dielectric layer surrounding the upper surface, lower surface, and side surface of the first gate electrode layer, the side surface of the first gate electrode layer facing the first side surface of the first stacked structure. The second horizontal gate structure includes: a second gate electrode layer; and a second gate dielectric layer, the second gate dielectric layer surrounding the upper surface, lower surface and side surface of the second gate electrode layer, the side surface of the second gate electrode layer facing the first side surface of the second stacked structure.

10. The semiconductor device of claim 9, further comprising: A first vertical gate structure, the first vertical gate structure including a first metal layer, the first vertical gate structure extending in the vertical direction and coupled to a first horizontal gate structure on a second side of the first stacked structure; as well as A second vertical gate structure, comprising a second metal layer, extends in the vertical direction and is coupled to a second horizontal gate structure on a second side surface of the second stacked structure. Wherein, the first gate electrode layer further extends to surround the side surface and the lower surface of the first metal-containing layer, and The first gate dielectric layer further extends to surround the side surface and lower surface of the further extended first gate electrode layer, and The second gate electrode layer further extends to surround the side surface and lower surface of the second metal-containing layer, and The second gate dielectric layer extends further to surround the side surface and the bottom surface of the further extended second gate electrode layer.

11. The semiconductor device of claim 10, wherein, The first metal-containing layer has a lower resistance than the first gate electrode layer, and The second metal-containing layer has a lower resistance than the second gate electrode layer.

12. The semiconductor device of claim 8, further comprising: The lower electrode contact portion and the lower electrode line are above the lower electrode layer and are coupled to the lower electrode layer. A first upper electrode contact portion and a first upper electrode line are located on the first upper electrode layer, and the first upper electrode contact portion and the first upper electrode line are coupled to the first upper electrode layer. A second upper electrode contact portion and a second upper electrode line are on the second upper electrode layer, and the second upper electrode contact portion and the second upper electrode line are coupled to the second upper electrode layer. A first gate contact and a first gate line are disposed on the first vertical gate structure, and the first gate contact and the first gate line are coupled to the first vertical gate structure; and A second gate contact and a second gate line are coupled to the second vertical gate structure.

13. The semiconductor device of claim 12, wherein, The first side surface of the first stacked structure and the first side surface of the second stacked structure extend in a first direction, and The lower electrode layer extends in the first direction, and The lower electrode contact portion is located outside the space between the first stacked structure and the second stacked structure in the first direction.

14. The semiconductor device of claim 12, wherein, The first side surface of the first stacked structure and the first side surface of the second stacked structure extend in a first direction, and The lower electrode line, the first upper electrode line and the second upper electrode line, as well as the first gate line and the second gate line extend in the first direction.

15. The semiconductor device of claim 12, wherein, The lower electrode line is located at a lower height than the first upper electrode line and the second upper electrode line, as well as the first gate line and the second gate line.

16. The semiconductor device of claim 12, wherein, The first upper electrode line and the second upper electrode line, as well as the first gate line and the second gate line, are located at the same height.

17. The semiconductor device of claim 12, wherein, When the first channel layer and the second channel layer contain impurities of the same conductivity type The first upper electrode line and the second upper electrode line are electrically connected to each other, and the first gate line and the second gate line are electrically connected to each other.

18. The semiconductor device of claim 17, wherein, The first side of the first stacked structure and the first side of the second stacked structure extend in a first direction, and The first upper electrode line and the second upper electrode line, as well as the first gate line and the second gate line, extend in the first direction, and Further includes: A first coupling pattern extends between the first upper electrode line and the second upper electrode line in a second direction intersecting the first direction, and couples the first upper electrode line and the second upper electrode line to each other; and A second coupling pattern extends between the first gate line and the second gate line in the second direction, and couples the first gate line and the second gate line to each other.

19. The semiconductor device of claim 1, wherein, The first side of the first stacked structure and the first side of the second stacked structure extend in a first direction, and The length of each of the first and second trench layers in the first direction is longer than its length in the second direction intersecting the first direction.

20. The semiconductor device of claim 2, wherein, The work function of the first horizontal gate structure and the work function of the second horizontal gate structure are different from each other.

21. A method for manufacturing a semiconductor device, comprising: A first initial stacked structure is formed, the first initial stacked structure including a first lower dielectric layer, a first sacrificial layer and a first upper dielectric layer stacked on the substrate in the vertical direction; A second initial stacked structure is formed, the second initial stacked structure including a second lower dielectric layer, a second sacrificial layer and a second upper dielectric layer stacked on the substrate in the vertical direction, and the second initial stacked structure having a first side facing the first side of the first initial stacked structure; A lower electrode layer is formed on the substrate, the upper surface of the lower electrode layer is located at a height equal to or lower than the upper surface of the first lower dielectric layer and the upper surface of the second lower dielectric layer, and the lower electrode layer fills the lower space between the first initial stacked structure and the second initial stacked structure. The lower electrode layer has a first sidewall that contacts the lower part of a first side of the first initial stacked structure and a second sidewall that contacts the lower part of the first side of the second initial stacked structure. A first channel layer and a second channel layer are formed on the upper part of the first side surface of the first initial stacked structure and the upper part of the first side surface of the second initial stacked structure, respectively, and the first channel layer and the second channel layer have lower ends coupled to the lower electrode layer. A first upper electrode layer and a second upper electrode layer are formed, respectively coupled to the upper end of the first channel layer and the upper end of the second channel layer; as well as The first sacrificial layer and the second sacrificial layer are replaced by a first horizontal gate structure and a second horizontal gate structure, respectively.

22. The method of claim 21, wherein, The formation of the first trench layer and the second trench layer includes: A material layer pattern is formed along the first side surface of the first initial stacked structure, the upper surface of the lower electrode layer, and the first side surface of the second initial stacked structure; A first doped layer is formed by performing a tilting implantation process into the first side of the first initial stacked structure using impurities of a first conductivity type; and The second doped layer is formed by performing a tilting implantation process into the first side of the second initial stacked structure using impurities of the second conductivity type.

23. The method of claim 22, further comprising: After the first doped layer is formed, an additional doped layer is formed by performing an additional tilting implantation process on top of the first doped layer using impurities of the first conductivity type. as well as After the second doped layer is formed, an additional doped layer is formed by performing an additional tilt implantation process on top of the second doped layer using impurities of the second conductivity type.

24. The method of claim 22, further comprising: After the first doped layer is formed, an additional tilting implantation process is performed in at least one region of the first doped layer facing the first sacrificial layer using impurities of a different conductivity type than the first conductivity type. as well as After the second doped layer is formed, an additional tilt implantation process is performed in at least one region of the second doped layer facing the second sacrificial layer using impurities of a different conductivity type than the second conductivity type.

25. The method of claim 22, wherein, The first conductivity type and the second conductivity type are different from each other.

26. The method of claim 22, wherein, The first conductivity type and the second conductivity type are the same.

27. The method of claim 23, wherein, The formation of the first additional doped layer and the second additional doped layer is performed while the dielectric layer is formed and the space between the first channel layer and the second channel layer is filled, wherein the upper surface of the dielectric layer is located at a height lower than the upper surface of the first channel layer and the upper surface of the second channel layer.

28. The method of claim 21, further comprising: Before forming the first upper electrode layer and the second upper electrode layer, a dielectric layer is formed, the upper surface of which is located at a lower height than the upper surface of the first channel layer and the upper surface of the second channel layer, and fills the space between the first channel layer and the second channel layer. Wherein, the first upper electrode layer is formed to surround a portion of the side surface of the first channel layer protruding from the dielectric layer and its upper surface, and The second upper electrode layer is formed to surround a portion of the side surface of the second channel layer that protrudes from the dielectric layer and its upper surface.

29. The method of claim 21, wherein, The step of replacing the first sacrificial layer and the second sacrificial layer with the first horizontal gate structure and the second horizontal gate structure, respectively, includes: A dielectric layer is formed, the dielectric layer covering the first initial stacked structure and the second initial stacked structure, as well as the first upper electrode layer and the second upper electrode layer; By selectively etching the dielectric layer, a first contact hole and a second contact hole are formed on the second side of the first initial stacked structure and the second side of the second initial stacked structure, exposing the first sacrificial layer and the second sacrificial layer; The first groove portion and the second groove portion are formed by removing the first sacrificial layer and the second sacrificial layer exposed by the first contact hole and the second contact hole; Forming a first horizontal gate structure that fills the first recess portion and a first vertical gate structure that fills the first contact hole and has a side surface coupled to the first horizontal gate structure; and A second horizontal gate structure is formed that fills the second groove portion and a second vertical gate structure is formed that fills the second contact hole and has a side coupled to the second horizontal gate structure.

30. The method of claim 29, wherein, The steps of forming the first horizontal gate structure and the first vertical gate structure include: A first gate dielectric layer is formed along the inner wall of the first contact hole and the inner wall of the first groove; and A first gate electrode layer is formed on top of the first gate dielectric layer, and The steps of forming the second horizontal gate structure and the second vertical gate structure include: A second gate dielectric layer is formed along the inner wall of the second contact hole and the inner wall of the second groove; and A second gate electrode layer is formed on top of the second gate dielectric layer.

31. The method of claim 30, further comprising: After the first gate electrode layer is formed, if there is remaining space at least in the first contact hole, a first metal-containing layer is formed, the first metal-containing layer filling the remaining space of the first contact hole; and After the second gate electrode layer is formed, if there is remaining space in at least the second contact hole, a second metal-containing layer is formed, which fills the remaining space in the second contact hole.

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