Bitcell structure for one-time programming

Abstract

A bit cell structure for one-time programming includes a substrate, a first doped region in the substrate and electrically connected to a source line, a second doped region in the substrate and having a source and a drain, the drain being electrically connected to a bit line, a heavily doped channel region in the substrate and connecting the first doped region and the source of the second doped region, and a word line across the second doped region and between the source and the drain.

Description

Technical Field

[0001] The present invention relates to a one-time programmable bit cell (bit lattice) structure, and more specifically, to a bit cell structure having a heavily doped channel region for one-time programming. Background Technology

[0002] One-time programmable memory (EPM) elements are used in integrated circuits as non-volatile memory, meaning that data stored in EPM is not lost when the integrated circuit is turned off. EPM allows integrated circuit manufacturers to store batch numbers or security data on the chip for use in other applications. Fuses or antifuses are common examples of EPM elements.

[0003] Other types of components, such as flash memory, can also serve as non-volatile memory in integrated circuits. However, incorporating such components into CMOS integrated circuits can significantly increase costs due to the additional fabrication process steps required. Currently, various types of fuses are available on the market, such as polysilicon fuses, metal fuses, contact fuses, and via fuses, all of which are compatible with standard CMOS logic fabrication processes.

[0004] However, high-density one-time programmable memories generally have low reliability, with a lower programming yield than flash memories of the same size. Therefore, the industry hopes to develop a one-time programmable memory structure with higher reliability and yield. Summary of the Invention

[0005] In view of the poor reliability and yield of existing one-time programmable memories, this invention proposes a novel bit cell structure for one-time programming, characterized by heavily doped channel regions and / or special channel shapes to improve programming reliability and device performance.

[0006] One objective of this invention is to provide a bit cell structure for one-time programming, comprising a substrate, a first doped region located in the substrate and electrically connected to a source line, a second doped region located in the substrate, the second doped region having a source and a drain, the drain being electrically connected to a bit line, a heavily doped channel region located in the substrate and connecting the source of the first doped region and the second doped region, and a character line crossing the second doped region and between the source and the drain.

[0007] Another object of the present invention is to provide a bit cell structure for one-time programming, comprising a substrate, a first doped region located in the substrate and electrically connected to a source line, a second doped region located in the substrate, the second doped region having a source and a drain, the drain being electrically connected to a bit line, and a doped channel region located in the substrate, the doped channel region having a first portion and a second portion, the first portion and the second portion being respectively connected to the source of the first doped region and the second doped region in a first direction, wherein the width of the first portion in a second direction perpendicular to the first direction is smaller than the width of the second portion in the second direction and smaller than the width of the first doped region in the second direction and a character line, spanning the second doped region and located between the source and the drain.

[0008] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0009] This specification includes accompanying drawings, which form part of the document, to provide the reader with a further understanding of embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0010] Figure 1 This is a circuit diagram of a 2×2 bit cell structure in a preferred embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram of the layout of the 2×2 bit unit structure in a preferred embodiment of the present invention;

[0012] Figure 3 This is a cross-sectional schematic diagram of the 2×2 unit structure in a preferred embodiment of the present invention;

[0013] Figure 4 This is an actual layout diagram of the intermediate unit structure in a preferred embodiment of the present invention;

[0014] Figure 5 This is an actual layout diagram of the intermediate unit structure in another embodiment of the present invention; and

[0015] Figure 6 This is an actual layout diagram of the intermediate unit structure in another embodiment of the present invention.

[0016] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0017] Explanation of main component symbols

[0018] 100 base

[0019] 101 Active (Active) Region

[0020] 102 Shallow trench isolation structure

[0021] 103 transistors

[0022] 104 First Doped Region

[0023] 106 Second Doped Region

[0024] 108 heavily doped channel region (fuse)

[0025] 109 lightly doped channel region

[0026] 110 Short circuit

[0027] 112 Programming

[0028] BC unit

[0029] BL1, BL2 bit lines

[0030] CT contact components

[0031] D drain

[0032] D1 First Direction

[0033] D2 Second Direction

[0034] G gate

[0035] HDC heavily doped patterns

[0036] M1 First Metal Layer

[0037] RPO mask

[0038] S source pole

[0039] V1 guide hole component

[0040] WL1~WL4 character lines

[0041] Width of W1, W2 Detailed Implementation

[0042] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various features in the embodiments that do not conflict with each other can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0043] Readers should easily understand that the meanings of "on," "above," and "above" in this case should be interpreted broadly, so that "on" not only means "directly on" something but also includes the meaning of being "on" something with an intermediary feature or layer, and "above" or "above" not only means "above" or "above" something but can also include the meaning of being "above" or "above" something without an intermediary feature or layer (i.e., directly on something).

[0044] In addition, spatial terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein for convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0045] As used herein, the term "substrate" refers to the material on which subsequent material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0046] Please refer to now. Figure 1This is a circuit diagram of a 2×2 bit cell structure according to a preferred embodiment of the present invention. As shown in the figure, in this embodiment, a bit cell structure is composed of a transistor 103 and a fuse 108 (1T1R). The gate G of transistor 103 is electrically connected to one of the character lines WL1, WL2, so that the character line controls the switching of transistor 103. Each character line is electrically connected to the gate G of all bit cells in the same row and controls their switching. The source S of transistor 103 is electrically connected to fuse 108, and fuse 108 is electrically connected to one of the source lines SL1, SL2, to receive electronic signals from the source lines and transmit them to transistor 103. Each source line is electrically connected to the fuse 108 of some or all bit cells in the same column and sends signals to them. The drain D of transistor 103 is electrically connected to one of the bit lines BL1, BL2, and transmits electronic signals from the source lines to the connected bit lines to complete the read or write operation. Note that... Figure 1 In the illustrated embodiment, although bit lines BL1, BL2 and source lines SL1, SL2 are designed to extend in the first direction D1 and alternately spaced in the second direction D2, which is orthogonal to the first direction D1, in other embodiments, source lines SL1, SL2 can also be designed to extend in the second direction D2 parallel to character lines WL1, WL2 and alternately spaced with character lines WL1, WL2 in the first direction D1. Furthermore, it should be noted that this invention uses antifuse programming, meaning that the fuse portion of the programmed bit cell will form a permanent short circuit, making its resistance close to 0, thus achieving a one-time programming effect.

[0047] When performing programming 112, the selected bit unit (e.g. Figure 1 The lower right bit cell receives the programming voltage VDD via the connected source line SL2, while the connected bit line BL2 is grounded (GND). If voltage is applied to the connected character line WL2 to activate the transistor 103 of that bit cell, the fuse 108 of that bit cell will undergo junction breakdown due to the excessive voltage difference. This creates a permanent short circuit 110 at the fuse 108, meaning the resistance of the fuse 108 approaches zero, thus achieving a one-time programming effect. During reading, the programmed bit cell, due to the near-zero resistance at the fuse 108, will experience a near-zero voltage difference, i.e., the L state (low state). Unprogrammed bit cells, because the fuse 108 has not undergone permanent junction breakdown and retains its inherent resistance, will experience a voltage difference during reading, i.e., the H state (high state). This permanent difference between the L and H states during bit cell reading achieves the desired one-time programming effect.

[0048] Now please refer to the following: Figure 2 and Figure 3 These figures are a layout schematic diagram of the 2×2 bit cell structure according to a preferred embodiment of the present invention, and a cross-sectional schematic diagram taken along the line A-A' in the layout schematic diagram. This allows the reader to understand the general planar layout of the bit cell structure of the present invention and its structural connections in the direction perpendicular to the substrate. As shown, the bit cell structure of the present invention is constructed on a substrate 100. The substrate 100 may be a silicon substrate, and well regions, such as p-type well regions, may be pre-formed using a doping process. A plurality of active regions 101 are defined on the substrate 100, such as... Figure 2 The active regions 101 extend in the first direction D1, and shallow trench isolation structures 102 are formed between the active regions 101 to electrically isolate them from each other. The character lines WL1 and WL2 extend in the second direction D2, crossing multiple active regions 101.

[0049] An active region 101 may contain multiple bit cells and multiple doped regions. Taking a preferred embodiment of the present invention as an example, two bit cells share an active region 101 and a common source line (not shown). Each bit cell includes a first doped region 104 and a second doped region 106. The first doped region 104 and the second doped region 106 are electrically connected through a heavily doped channel region 108. This heavily doped channel region 108 and the second doped region 106 are respectively the antifuse 108 portion and the transistor 103 portion used for one-time programming in the present invention (see...). Figure 1 Furthermore, the second doped region 106 has a source S and a drain D, and its conduction is controlled by the character line WL1 or WL2 between the source S and the drain D. The first doped region 104 serves as the common source region for the left and right bit cells, and it is electrically connected to the upper source line (not shown) via the contact CT to receive electronic signals. When the transistors are turned on at the character lines WL1 and WL2, the received electronic signals are transmitted from the first doped region 104 sequentially through the heavily doped channel region 108 and the source S of the second doped region 106 to the drain D of the second doped region 106, where they are electrically connected to the upper bit line (not shown) via the contact CT.

[0050] In this embodiment of the invention, the first doped region 104, the source S, and the drain D can be lightly doped conductive regions, for example, formed by doping an n-type dopant such as phosphorus or arsenic on a p-type well region of the substrate 100 using an ion implantation process. In contrast, the heavily doped channel region 108 is a heavily doped conductive region, such as a heavily n-type doped region, meaning that its doping concentration is much greater than that of the aforementioned lightly doped region. Due to the heavy doping, the junction breakdown voltage of the heavily doped channel region 108 will be lower than that of other doped regions. Thus, by applying a suitable programming voltage, the heavily doped channel region 108 can be caused to undergo junction breakdown, forming a permanent short circuit 110 (resistance value close to 0), while the unprogrammed heavily doped channel region 108 remains unaffected (having its inherent resistance value). In this embodiment of the invention, the advantage of using the heavily doped channel region 108 as an antifuse component to achieve a one-time programming effect is that it is compatible with CMOS logic fabrication processes and can fabricate the antifuse portion without adding additional fabrication process steps and costs. Furthermore, the antifuse region can be easily programmed by adjusting the doping concentration of the heavily doped channel region 108, thus solving the problem of poor reliability and programming yield of high-density one-time programmable memory in the prior art.

[0051] Please refer to now. Figure 4 This is an actual layout diagram of the bit cell structure according to a preferred embodiment of the present invention. This layout diagram shows only one active region extending in the first direction D1, which has a common first doped region 104, and is connected on both sides to the source S in the second doped region 106 of the two bit cells BC via heavily doped channel regions 108. The two bit cells BC are symmetrical about the first doped region 104.

[0052] The shared first doped region 104 is first connected to the upper first metal layer M1 via contact CT, and then connected to the source line SL1 located at the upper second metal layer level via via V1. In this embodiment, the width W2 of the heavily doped channel region 108 in the second direction D2 is smaller than the width W1 of the first doped region 104 and the source S in the second direction D2. The heavily doped pattern HDC defines the area on the substrate surface that will be heavily ion doped, and the portion that overlaps with the active region 101 forms the heavily doped channel region 108. The doping concentration of the source S adjacent to the heavily doped channel region 108 is smaller than the doping concentration of the heavily doped channel region 108. Both the source S and the heavily doped channel region 108 are covered by the mask RPO to prevent the formation of metal silicides on them in subsequent fabrication processes. The selectively programmed heavily doped channel region 108 will form a short circuit, as described in the previous embodiment, and will not be repeated here.

[0053] Rereference Figure 4The source S and drain D of the second doped region 106 are separated by character lines WL1 to WL4 serving as gates. In this embodiment, the drain D can serve as the common drain D for the two bit cells BC, which is first electrically connected to the upper first metal layer M1 via contact CT, and then electrically connected to the bit line BL1 located in the second metal layer level above via via via V1. It should be noted that although the source line SL1 is designed to be parallel to the bit line BL1 in this embodiment, in other embodiments, the source line SL1 may be parallel to the character lines WL1 to WL4.

[0054] Please refer to now. Figure 5 This is an actual layout diagram of the intermediate unit structure according to another embodiment of the present invention. This embodiment is similar to... Figure 4 The difference in the embodiments lies in the fact that the heavily doped channel region 108 has a different width. For example... Figure 5 As shown, the heavily doped channel region 108 has a smaller width W2 in the second direction D2 near the portion connected to the first doped region 104 (the first portion), and a larger width W1 in the second direction D2 near the portion connected to the source S (the second portion). Designing the channel near the source doped region (i.e., the first doped region 104) to have a smaller width compared to the drain end will help improve the electrical properties of the device.

[0055] Please refer to now. Figure 6 This is an actual layout diagram of the intermediate unit structure according to another embodiment of the present invention. This embodiment is similar to... Figure 5 The difference in the embodiments lies in the different doping concentrations in the channel regions. For example... Figure 6 As shown, in this embodiment, the heavily doped channel region 108 is limited to the portion with a larger width W1 near the source S, while the portion with a smaller width W2 near the first doped region 104 is the lightly doped channel region 109. The doping concentration of the lightly doped channel region 109 is less than that of the heavily doped channel region 108, and preferably equal to the doping concentration of the first doped region 104 and / or the source S. The heavily doped pattern HDC only overlaps with the heavily doped channel region 108. The lightly doped channel region 109, the heavily doped channel region 108, and the source S are all covered by the mask RPO to prevent the formation of metal silicides on them during subsequent fabrication processes. This design of two different doping concentrations and widths for the channel regions facilitates programming and improves reliability and yield.

[0056] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A bit cell structure for one-time programming, characterized in that, include: Base; The first doped region is located in the substrate and electrically connected to the source line; A second doped region is located in the substrate, the second doped region having a source and a drain, the drain being electrically connected to a bit line; The source of the heavily doped channel region is located in the substrate and connects the first doped region and the second doped region. The source line is electrically connected to the source of the second doped region via the first doped region and the heavily doped channel region. The doping concentration of the heavily doped channel region is greater than that of the first doped region and the second doped region. The heavily doped channel region acts as an antifuse, and its doping concentration is set such that junction breakdown and short circuit will occur during one-time programming. as well as The character line crosses the second doped region and lies between the source and the drain.

2. The bit cell structure for one-time programming as claimed in claim 1, wherein the heavily doped channel region has the same doping type as the first doped region and the second doped region, and the breakdown voltage of the heavily doped channel region is lower than the breakdown voltage of the first doped region and the second doped region.

3. The bit cell structure for one-time programming as described in claim 1, wherein the heavily doped channel region extends in a first direction and its two ends are respectively connected to the source of the first doped region and the second doped region, and the width of the heavily doped channel region in a second direction orthogonal to the first direction is smaller than the width of the first doped region in the second direction and smaller than the width of the second doped region in the second direction.

4. The bit cell structure for one-time programming as described in claim 3, wherein the source line and the bit line extend in the first direction, and the plurality of source lines and the bit line are interactively arranged in the second direction.

5. The bit cell structure for one-time programming as described in claim 3, wherein the source line and the character line extend in the second direction, and a plurality of the source lines and the character lines are interactively arranged in the first direction.

6. The bit cell structure for one-time programming as claimed in claim 1, wherein the first doped region is first electrically connected to the upper first metal layer via a contact, and then electrically connected to the source line located at the upper second metal layer level via a via.

7. The bit cell structure for one-time programming as claimed in claim 1, wherein the drain of the second doped region is first electrically connected to the upper first metal layer via a contact, and then electrically connected to the bit line located at the upper second metal layer level via a via.

8. The bit cell structure for one-time programming as claimed in claim 1, wherein the first doped region is shared by two bit cell structures, and the two bit cell structures are symmetrical about the first doped region as a center line.

9. A bit cell structure for one-time programming, characterized in that, include: Base; The first doped region is located in the substrate and electrically connected to the source line; A second doped region is located in the substrate, the second doped region having a source and a drain, the drain being electrically connected to a bit line; A doped channel region is located in the substrate. The doped channel region has a first portion and a second portion. The first portion and the second portion are respectively connected to the source of the first doped region and the second doped region in a first direction. The width of the first portion in a second direction orthogonal to the first direction is smaller than the width of the second portion in the second direction and smaller than the width of the first doped region in the second direction. The source line is electrically connected to the source of the second doped region via the first doped region and the doped channel region. The doping concentration of the doped channel region is greater than the doping concentration of the first doped region and the second doped region. The doped channel region acts as an antifuse, and its doping concentration is set such that junction breakdown and short circuit will occur during one-time programming. as well as The character line crosses the second doped region and lies between the source and the drain.

10. The bit cell structure for one-time programming as claimed in claim 9, wherein the source line and the bit line extend in the first direction, and the plurality of source lines and the bit line are alternately arranged in the second direction.

11. The bit cell structure for one-time programming as claimed in claim 9, wherein the source line and the character line extend in the second direction, and a plurality of the source lines and the character line are alternately arranged in the first direction.

12. The bit cell structure for one-time programming as claimed in claim 9, wherein the doped channel region is a heavily doped channel region and has the same doping type as the first doped region and the second doped region.

13. The bit cell structure for one-time programming as claimed in claim 9, wherein the second portion of the doped channel region is a heavily doped channel region and the first portion is a lightly doped channel region, the doped channel region has the same doping type as the first doped region and the second doped region, the doping concentration of the heavily doped channel region is higher than the doping concentration of the lightly doped channel region, the first doped region and the second doped region, and the heavily doped channel region serves as an antifuse and the doping concentration is set such that junction breakdown and short circuit will occur during one-time programming.

14. The bit cell structure for one-time programming as claimed in claim 9, wherein the first doped region is first electrically connected to the upper first metal layer via a contact, and then electrically connected to the source line located at the upper second metal layer level via a via.

15. The bit cell structure for one-time programming as claimed in claim 9, wherein the drain of the second doped region is first electrically connected to the upper first metal layer via a contact, and then electrically connected to the bit line located at the upper second metal layer level via a via.

16. The bit cell structure for one-time programming as claimed in claim 9, wherein the first doped region is shared by two bit cell structures, and the two bit cell structures are symmetrical about the first doped region as a center line.

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