Display device

Abstract

A display device is provided that can suppress characteristic variations of an oxide semiconductor transistor while providing high-definition display. The display device includes: a substrate; a first transistor including an oxide semiconductor layer, a first gate insulating layer, and a first gate electrode, and is disposed in a display area; and a light shielding layer disposed between the substrate and the oxide semiconductor layer, the light shielding layer including: a first light shielding metal layer disposed between the substrate and the oxide semiconductor layer; and a second light shielding metal layer covering the upper surface and side surfaces of the first light shielding metal layer, and being opposite to the oxide semiconductor layer. The above-mentioned display device may also include a second transistor, the second transistor including a second semiconductor layer including silicon, a second gate insulating layer, and a second gate electrode, and is disposed in a peripheral area located around the display area, the second light shielding metal layer and the second gate electrode being disposed on the same layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. In particular, one embodiment of the present invention relates to a display device using a transistor including an oxide semiconductor. Background Art

[0002] Recently, the development of transistors using oxide semiconductors in the channel instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been advancing (for example, Patent Document 1). Transistors using oxide semiconductors in the channel are formed by simple structures and low-temperature processes in the same way as transistors using amorphous silicon in the channel. It is known that transistors using oxide semiconductors in the channel have higher mobility and very low cut-off current than transistors using amorphous silicon in the channel.

[0003] In recent years, the pixel size reduction of display devices has been continuously promoted. As the pixel size is reduced, the reduction of wiring width and transistor size is being studied. However, these reductions have limits. Due to the configuration of the metal layer and semiconductor layer that constitute the pixel circuit, the aperture ratio of the pixel becomes smaller. Therefore, the development of transistors for pixel circuits using transistors whose channels use oxide semiconductor layers that have characteristics sufficient to drive the pixel circuit even if the transistor size is small is continuously promoted.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2020-076950

[0005] When a transistor using an oxide semiconductor as a channel is exposed to light, its characteristics may change (e.g., a change in threshold). When the characteristics change, normal display may not be possible. For this reason, a structure is provided as follows: a light shielding layer is provided under the transistor using an oxide semiconductor as a channel (Patent Document 1).

[0006] On the other hand, a transistor whose channel uses low-temperature polysilicon (LTPS) is sometimes set in a peripheral circuit. In this case, the light shielding layer of the transistor whose channel uses an oxide semiconductor and the gate electrode of the transistor whose channel uses an LTPS are sometimes on the same layer. In this case, the thickness of the gate electrode of the LTPS transistor needs to be less than a certain film thickness in terms of polycrystallization. Therefore, the gate electrode and the light shielding layer with thickness are not sufficient to block exposure, and the characteristics of the oxide semiconductor may change. Summary of the invention

[0007] In view of such technical problems, one object of the present invention is to provide a display device capable of performing high-definition display while suppressing characteristic variation of an oxide semiconductor transistor.

[0008] A display device involved in one embodiment of the present invention comprises: a substrate; a first transistor, including an oxide semiconductor layer, a first gate insulating layer and a first gate electrode, and arranged in a display area; and a light-shielding layer, arranged between the substrate and the oxide semiconductor layer, the light-shielding layer comprising: a first light-shielding metal layer, arranged between the substrate and the oxide semiconductor layer; and a second light-shielding metal layer, covering the upper surface and side surfaces of the first light-shielding metal layer and opposite to the oxide semiconductor layer.

[0009] A display device involved in one embodiment of the present invention includes: a substrate; a first transistor, including an oxide semiconductor layer, a first gate insulating layer and a first gate electrode, and is arranged in a display area; a light shielding layer, which is arranged between the substrate and the oxide semiconductor layer and overlaps with the oxide semiconductor layer; and a second transistor, including a second semiconductor layer including silicon, a second gate insulating layer and a second gate electrode, and is arranged in a peripheral area located around the display area, and the thickness of the light shielding layer is greater than the thickness of the second gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0011] Figure 2 It is a plan view schematically showing a display device according to an embodiment of the present invention.

[0012] Figure 3 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0013] Figure 4 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0014] Figure 5 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0015] Figure 6 It is a plan view schematically showing a display device according to an embodiment of the present invention.

[0016] Figure 7 This is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention.

[0017] Figure 8 : is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.

[0018] Description of Reference Numerals

[0019] 10: display device, 20: display device, 22: liquid crystal region, 24: sealing region, 26: terminal region, 300: array substrate, 310: pixel circuit, 320: source driving circuit, 321: source wiring, 330: gate driving circuit, 331: gate wiring, 333: terminal portion, 341: connection wiring, 400: sealing portion, 410: liquid crystal element, 500: counter substrate, 600: flexible printed circuit substrate, 700: chip, 800: transistor, 810: first gate electrode, 830: first source electrode, 840: first drain electrode, 890 : Holding capacitor, CMTL: common auxiliary electrode, CON1: first contact region, CON2: second contact region, CTCO: common electrode, GI1, GI2: gate insulating layer, GL1, GL2: gate electrodes, IL1~IL5: insulating layer, LS: shielding layer, OP: opening, OS: oxide semiconductor layer, PCON, WCON, ZCON: opening, PJT: protrusion, PTCO: pixel electrode, S: semiconductor layer, SL: slit, SP: spacer, SUB: substrate, Tr1, Tr2: transistors, W: wiring, ZTCO: connecting electrode. DETAILED DESCRIPTION

[0020] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. A person skilled in the art can easily think of a configuration that appropriately changes the configuration of the embodiment while maintaining the gist of the invention, and of course it is also included in the scope of the present invention. In order to make the description clearer, the accompanying drawings sometimes schematically show the width, thickness, shape, etc. of each part compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and the accompanying drawings, for the same elements as those described in the figures that have appeared, the detailed description is sometimes appropriately omitted.

[0021] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. In this way, the term above or below is used for convenience of explanation, but for example, the up-down relationship between the substrate and the oxide semiconductor layer can also be configured to be opposite to that shown in the figure. In the following description, for example, the expression of the oxide semiconductor layer on the substrate is just to illustrate the up-down relationship between the substrate and the oxide semiconductor layer as described above, and other components can also be configured between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure with multiple layers stacked, for example, in the case of a pixel electrode described as "above" a transistor, it can also mean only a vertical positional relationship, and there is no need to be a mutually overlapping relationship in a top view. It can also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode described as "vertically above" a transistor, it is necessary to have a positional relationship in which the transistor and the pixel electrode overlap each other when viewed from above.

[0022] A “display device” refers to a structure that uses an electro-optical layer to display an image. For example, the term display device sometimes refers to a display panel that includes an electro-optical layer, or sometimes refers to a structure in which a display unit is equipped with other optical components (for example, a polarization component, a backlight source, a touch panel, etc.). As long as there is no technical contradiction, the “electro-optical layer” may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described below, a liquid crystal display device including a liquid crystal layer is illustrated as an example for explanation as a display device, but the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0023] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C. Furthermore, these expressions do not exclude the case where α includes other elements.

[0024] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0025] [1. First embodiment]

[0026] [1-1. Configuration of Display Device 10]

[0027] use Figure 1 to Figure 5 The configuration of a display device 10 according to one embodiment of the present invention will be described. Figure 1 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention. Figure 2It is a plan view schematically showing a display device according to an embodiment of the present invention. Figure 3 to Figure 5 is with Figure 2 The top view shown corresponds to the cross-sectional views of the various parts.

[0028] like Figure 1 As shown, the display device 10 has a substrate SUB. In addition, the display device 10 has a transistor Tr1, a transistor Tr2, a wiring W, a connecting electrode ZTCO, a pixel electrode PTCO, a common auxiliary electrode CMTL and a common electrode CTCO on the substrate SUB. It should be noted that TCO is an abbreviation for transparent conductive oxide (Transparent Conductive Oxide). Transistor Tr1 is arranged in the display area. Specifically, transistor Tr1 is a transistor included in the pixel circuit of the display device 10. Transistor Tr2 is arranged in a peripheral area located around the display area. Specifically, transistor Tr2 is a transistor included in the peripheral circuit. It should be noted that the peripheral circuit is a circuit that drives the pixel circuit, and the details will be described later.

[0029] [1-2. Configuration of transistor Tr1]

[0030] The transistor Tr1 (also referred to as the first transistor) includes an oxide semiconductor layer OS, a gate insulating layer GI1, and a gate electrode GL1. The gate electrode GL1 is opposite to the oxide semiconductor layer OS. The gate insulating layer GI1 is provided between the oxide semiconductor layer OS and the gate electrode GL1. In this embodiment, a top-gate transistor in which the oxide semiconductor layer OS is provided closer to the substrate SUB than the gate electrode GL1 is shown as an example, but a bottom-gate transistor in which the positional relationship between the gate electrode GL1 and the oxide semiconductor layer OS is opposite may also be used.

[0031] The oxide semiconductor layer OS includes oxide semiconductor layers OS1 and OS2. The oxide semiconductor layer OS1 overlaps with the gate electrode GL1 when viewed from above. The oxide semiconductor layer OS1 functions as a semiconductor layer, and switches between a conductive state and a non-conductive state according to a voltage supplied to the gate electrode GL1. That is, the oxide semiconductor layer OS1 functions as a channel of the transistor Tr1. The oxide semiconductor layer OS2 functions as a conductive layer. The oxide semiconductor layers OS1 and OS2 are layers formed of the same oxide semiconductor layer. For example, the oxide semiconductor layer OS2 is a region whose resistance is reduced by doping a layer having the same physical properties as the oxide semiconductor layer OS1 with impurities.

[0032] An insulating layer IL2 is provided on the gate electrode GL1. A wiring W1 is provided on the insulating layer IL2. The wiring W1 is connected to the oxide semiconductor layer OS2 via an opening WCON provided in the insulating layer IL2 and the gate insulating layer GI1. The wiring W1 is transmitted with a data signal associated with the grayscale of the pixel. An insulating layer IL3 is provided on the insulating layer IL2 and the wiring W1. A connecting electrode ZTCO is provided on the insulating layer IL3. The connecting electrode ZTCO is connected to the oxide semiconductor layer OS2 via an opening ZCON provided in the insulating layers IL3, IL2 and the gate insulating layer GI1. The connecting electrode ZTCO is connected to the oxide semiconductor layer OS2 at the bottom of the opening ZCON. The connecting electrode ZTCO is a transparent conductive layer.

[0033] The area where the connection electrode ZTCO is in contact with the oxide semiconductor layer OS2 is called the first contact area CON1. ​​The connection electrode ZTCO is sometimes referred to as the "first transparent conductive layer". The details will be described later. The first transparent conductive layer is in contact with the oxide semiconductor layer OS2 in the first contact area CON1 that does not overlap with the gate electrode GL1 and the wiring W1 when viewed from above. In addition, the first contact area CON1 is included in the display area of ​​the pixel when viewed from above.

[0034] Here, for example, when a transparent conductive layer such as an ITO layer is formed to be in contact with a semiconductor layer such as a silicon layer, the surface of the semiconductor layer is oxidized due to the process gas and oxygen ions during the ITO film formation. The oxide layer formed on the surface of the semiconductor layer is high in resistance, so the contact resistance between the semiconductor layer and the transparent conductive layer becomes high, and the electrical contact between the two is poor. On the other hand, even if the above-mentioned transparent conductive layer is formed to be in contact with the oxide semiconductor layer, the above-mentioned high-resistance oxide layer will not be formed on the surface of the oxide semiconductor layer, so the electrical contact between the oxide semiconductor layer and the transparent conductive layer will not be poor.

[0035] An insulating layer IL4 is provided on the connecting electrode ZTCO. The insulating layer IL4 mitigates the height difference formed by the structure provided at a lower layer than the insulating layer IL4. The insulating layer IL4 is sometimes referred to as a planarization film. A pixel electrode PTCO is provided on the insulating layer IL4. The pixel electrode PTCO is connected to the connecting electrode ZTCO via an opening PCON provided in the insulating layer IL4. The area where the connecting electrode ZTCO and the pixel electrode PTCO are in contact is referred to as a second contact area CON2. The second contact area CON2 overlaps with the gate electrode GL1 when viewed from above. The pixel electrode PTCO is a transparent conductive layer.

[0036] An insulating layer IL5 is provided on the pixel electrode PTCO. A common auxiliary electrode CMTL and a common electrode CTCO are provided on the insulating layer IL5. The common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The resistance of the common auxiliary electrode CMTL is a resistance lower than the resistance of the common electrode CTCO. In addition, the common auxiliary electrode CMTL also functions as a light shielding layer, for example, by shielding light from adjacent pixels, thereby suppressing color mixing. A spacer SP is provided on the common electrode CTCO.

[0037] A spacer SP is provided for a part of the pixels. For example, a spacer SP may be provided for any one of the blue pixel, the red pixel, and the green pixel. However, a spacer SP may be provided for all the pixels. In addition, the height of the spacer SP may be half the height of the cell gap. It should be noted that another spacer may be provided on the opposing substrate, and the spacer on the opposing substrate overlaps with the above-mentioned spacer SP when viewed from above.

[0038] A light shielding layer LS is provided between the transistor Tr1 and the substrate SUB. In this example, the light shielding layer LS is provided between the oxide semiconductor layer OS and the substrate SUB. In this embodiment, light shielding layers LS1 and LS2 are provided as the light shielding layer LS.

[0039] It is desirable that the light shielding layer LS has a thickness sufficient to shield the oxide semiconductor layer from light. In this example, it is preferred that the entire thickness of the light shielding layer LS is 100 nm or more.

[0040] The light shielding layer LS2 covers the upper surface and side surfaces of the light shielding layer LS1. In this case, the light shielding layer LS may be provided in a step shape. Thus, the coverage of the light shielding layer LS by the insulating layer (gate insulating layer GI2 and insulating layer IL1 described later) can be improved.

[0041] In a plan view, the light shielding layer LS overlaps the gate electrode GL1 and the oxide semiconductor layer OS. At this time, the width DLS of the light shielding layer LS is larger than the width DGL1 of the gate electrode GL1 and the width DOS1 of the oxide semiconductor layer OS1. Thus, the light shielding layer LS can prevent light incident from the substrate SUB side from reaching the oxide semiconductor layer OS1.

[0042] [1-3. Configuration of transistor Tr2]

[0043] The transistor Tr2 includes a p-type transistor Tr2-1 and an n-type transistor Tr2-2. The transistor Tr2-1 and the transistor Tr2-2 are provided in a peripheral region located at the periphery of the display region.

[0044] The p-type transistor Tr2-1 and the n-type transistor Tr2-2 each have a gate electrode GL2, a gate insulating layer GI2, and a semiconductor layer S. The gate electrode GL2 is opposite to the semiconductor layer S. The gate insulating layer GI2 is provided between the semiconductor layer S and the gate electrode GL2. In the present embodiment, the p-type transistor Tr2-1 and the n-type transistor Tr2-2 use bottom-gate transistors in which the gate electrode GL2 is provided at a position closer to the substrate SUB side than the semiconductor layer S.

[0045] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. The semiconductor layer S1 is a region overlapping with the gate electrode GL2 when viewed from above. The semiconductor layer S1 functions as a channel of the transistor Tr2-1. The semiconductor layer S2 functions as a conductive layer. The semiconductor layer S3 functions as a conductive layer having a higher resistance than the semiconductor layer S2. The semiconductor layer S3 suppresses hot carrier degradation by attenuating hot carriers invading the semiconductor layer S1.

[0046] An insulating layer IL1 and a gate insulating layer GI1 are provided on the semiconductor layer S. In the transistor Tr2, the gate insulating layer GI1 functions only as an interlayer film. A wiring W2 is provided on these insulating layers. The wiring W2 is connected to the semiconductor layer S via openings provided in the insulating layer IL1 and the gate insulating layer GI1. An insulating layer IL2 is provided on the wiring W2. A wiring W1 is provided on the insulating layer IL2. The wiring W1 is connected to the wiring W2 via an opening provided in the insulating layer IL2.

[0047] In this embodiment, the gate electrode GL2 and the light shielding layer LS2 are arranged on the same layer on the substrate. In addition, the wiring W2 and the gate electrode GL1 are arranged on the same layer. "Arranged on the same layer" means that the components are formed simultaneously by patterning one layer. In addition, as described above, the light shielding layer LS includes the light shielding layer LS1 and the light shielding layer LS2. Therefore, the overall thickness TLS of the light shielding layer LS is greater than the thickness TGL2 of the gate electrode GL2.

[0048] In this embodiment, the semiconductor layer S in the p-type transistor Tr2-1 and the n-type transistor Tr2-2 is formed of silicon. The semiconductor layer S is polycrystallized by laser irradiation. At this time, when the gate electrode GL2 is set thick, the heat during laser irradiation is absorbed by the gate electrode GL2. Therefore, it is desirable to control the thickness of the second gate electrode layer. Specifically, it is desirable that the thickness of the gate electrode GL2 is less than 50nm. On the other hand, as described above, the overall thickness of the light shielding layer LS in the transistor Tr1 preferably has a thickness of more than 100nm. That is, the thickness of the light shielding layer LS in this embodiment is more than twice that of the light shielding layer LS2.

[0049] Here, in the related art, when the light shielding property of the channel portion of the transistor Tr1 is low, characteristic fluctuations (eg, fluctuations in threshold) may occur in reliability tests (eg, NBTS (Negative Bias Temperature Stress) tests).

[0050] However, in this embodiment, the light shielding layer LS provided on the lower side of the oxide semiconductor layer OS (particularly the oxide semiconductor layer OS1) is formed of two layers, and the gate electrode of the transistor (p-type transistor Tr2-1 and n-type transistor Tr2-2) of the peripheral circuit is formed of one of the two layers. Thus, it is possible to stably perform polycrystallization of silicon of the semiconductor layer S constituting the transistor Tr2 of the peripheral circuit while having sufficient light shielding properties for the transistor Tr1. In other words, it is possible to provide a display device that can suppress characteristic variations of the oxide semiconductor transistor while performing high-definition display.

[0051] [1-4. Configuration of Boundary Region Between Display Region DR and Peripheral Region PR in Display Device]

[0052] Figure 2 1 is a planar layout showing a portion of a boundary region (an end portion of the display region) between the display region DR and the peripheral region PR. Figure 3 yes Figure 2 Schematic cross-sectional view between A1-A2 in FIG. Figure 4 yes Figure 2 Schematic cross-sectional view between B1-B2 in FIG. Figure 5 yes Figure 2 Schematic cross-sectional view between C1-C2 in FIG.

[0053] exist Figure 2 to Figure 4 In the embodiment, a display region (pixel) DR is arranged in a first direction D1. A peripheral region PR is arranged toward a third direction D3. Figure 2 As shown, in this example, in the display region DR, the gate electrode GL1, the light shielding layer LS1, and the light shielding layer LS2 extend in a first direction D1 from the display region DR toward the peripheral region PR. The gate electrode GL1 can be referred to as a "first gate wiring". In addition, the light shielding layer LS1 and the gate electrode GL2 extend in a third direction D3 toward the peripheral region PR. The gate electrode GL2 can be referred to as a "second gate wiring". The wiring connecting the first gate wiring and the second gate wiring corresponds to the gate wiring 331 described later.

[0054] like Figure 2 to Figure 4As shown, a shading layer LS1 may also be provided under the gate electrode GL2. The gate electrode GL2 and the shading layer LS1 are conductive. As a result, the film thickness of the second gate wiring becomes larger. As a result, the resistance in the second gate wiring can be reduced. It should be noted that, when the resistance of the gate electrode GL2 is low, the shading layer LS1 may not be provided. In addition, the gate electrode GL2 constituting the second gate wiring is the gate electrode GL2 of the transistor Tr2. The shading layer LS1 of the second gate wiring extends to a position almost reaching the transistor Tr2.

[0055] The end GL1a of the gate electrode GL1 of the display region DR is provided in a boundary region which is the periphery of the display region DR. The end GL1a protrudes in a second direction D2 which intersects (orthogonally in this example) the first direction. The end GL1a can be referred to as a "protrusion". The end GL1a of the gate electrode GL1 is connected to the light shielding layer LS2 at the end of the display region DR via a first opening GCON1 provided in the gate insulating layer GI1, the insulating layer IL1, and the gate insulating layer GI2, and is connected to the gate electrode GL2 via a second opening GCON2 (see Figure 4 ).

[0056] In this embodiment, the light shielding layer LS uses a conductive layer. In this case, a voltage may be applied to the light shielding layer LS to control the oxide semiconductor layer OS1. As described above, the end GL1a of the gate electrode GL1 is connected to the light shielding layer LS2. As a result, the gate electrode GL1 and the light shielding layer LS2 have the same potential. As a result, the transistor Tr1 including the oxide semiconductor layer OS1 is driven by the gate electrode GL1 and the light shielding layer LS.

[0057] In addition, if Figure 2 to Figure 4 As shown, the light shielding layer LS2 of the display area DP and the gate electrode GL2 of the peripheral area RP are separated in the second direction D2 and connected via the end GL1a of the gate electrode GL1. More specifically, as described above, the light shielding layer LS2 of the display area DR and the gate electrode GL2 of the peripheral area PR formed on the same layer are electrically connected to the gate electrode GL1 located on the upper layer thereof via the first opening GCON1 and the second opening GCON2 provided in the gate insulating layer GI1, the insulating layer IL1 and the gate insulating layer GI2 at the end (boundary area) of the display area DR.

[0058] Here, the structure of the conventional gate wiring is described. Conventionally, the gate wiring is arranged in a straight line from the display area DR (pixel circuit) to the peripheral area PR (peripheral circuit) to be relatively long. When stripping charging is generated in the process of stripping the substrate from the manufacturing device when forming the gate wiring, charge is sometimes accumulated locally (specifically at the end of the gate wiring). When the display area (pixel circuit) and the peripheral area (peripheral circuit) are connected by the gate wiring as described above, the charge generated by the stripping charging moves along the wiring and accumulates at the end of the gate wiring, which may, for example, involve the insulation breakdown of the transistor (specifically the gate insulation layer GI2) provided in the peripheral circuit.

[0059] On the other hand, in the case of the present embodiment, the gate electrode GL1 (first gate wiring) of the display area DR and the gate electrode GL2 (second gate wiring) of the peripheral area are formed by different processes, and they are separately arranged in the second direction D2 and connected at the end (boundary area) of the display area DR. In addition, the gate electrode GL2 of the peripheral area PR and the light shielding layer LS of the display area DR are separately arranged in the second direction D2, and are connected via the gate electrode GL1 at the end (boundary area) of the display area DR. Thus, even if the charge is locally accumulated due to the above-mentioned stripping electrification, since the ends of the light shielding layer LS and the gate electrode GL1 are arranged around the ends of the display area DR, even if the charge caused by the above-mentioned stripping electrification is locally generated in the light shielding layer LS and the gate electrode GL1, such charge is concentrated on the ends of these gate electrodes GL1 and the light shielding layer LS, but stops at the periphery of the boundary of the display area DR. Therefore, the above-mentioned charge is suppressed from directly affecting the transistors arranged in the peripheral area PR. As a result, the peripheral circuit (in this example, the gate drive circuit) can be operated stably.

[0060] In addition, if Figure 2 and Figure 5 As shown, at the end of the display region DR, at least one dummy transistor DTr is provided for one gate electrode GL1. The dummy transistor DTr includes a light shielding layer LS (light shielding layer LS1 and light shielding layer LS2), a gate insulating layer GI2, an insulating layer IL1, an oxide semiconductor layer OS (oxide semiconductor layer OS1, oxide semiconductor layer OS2), an insulating layer GI1, a gate electrode GL1, an insulating layer IL2, and a wiring W1. It should be noted that the oxide semiconductor layer OS may also be formed only of the oxide semiconductor layer OS2.

[0061] The dummy transistor DTr is not connected to the transistor in the pixel circuit. The wiring W1 is arranged to overlap with the oxide semiconductor layer OS. More specifically, the wiring W1 has the same width as the oxide semiconductor layer in the first direction D1 and the second direction D2. The wiring W1 is connected to both ends of the oxide semiconductor layer OS via the opening WCON provided in the insulating layer IL2 and the gate insulating layer GI1. By providing the dummy transistor DTr at the end of the display region DR, it is possible to absorb unnecessary charges existing in the display region. Thus, the transistor in the pixel circuit can be protected.

[0062] [1-5. Materials of Components of Display Device 10]

[0063] As the substrate SUB, a glass substrate, a quartz substrate, a sapphire substrate, or other rigid substrate having light transmittance and no flexibility can be used. On the other hand, when the substrate SUB needs to be flexible, a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate or other flexible substrate containing resin and having flexibility can be used as the substrate SUB. In order to improve the heat resistance of the substrate SUB, impurities may be introduced into the above resin.

[0064] General metal materials can be used as gate electrodes GL1, GL2, wirings W1, W2, shading layers LS1, shading layers LS2, and common auxiliary electrodes CMTL. For example, as these components, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and alloys or compounds thereof can be used. As the above-mentioned components, the above-mentioned materials can be used as a single layer, or they can be used in a stacked manner. In this embodiment, the shading layer LS1 can be used as a "first shading metal layer". The shading layer LS2 can be used as a "second shading metal layer".

[0065] For example, a stacked structure of Ti / Al / Ti is used as the gate electrode GL1. In the present embodiment, the cross-sectional shape of the pattern end of the gate electrode GL1 having the stacked structure is a forward tapered shape.

[0066] As the gate insulating layers GI1, GI2 and the insulating layers IL1 to IL5, general insulating layer materials can be used. For example, as the insulating layers IL1 to IL3 and IL5, inorganic insulating layers such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), and aluminum nitride (AlNx) can be used. As these insulating layers, insulating layers with few defects can be used. As the insulating layer IL4, organic insulating materials such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used. It should be noted that the above-mentioned organic insulating materials can also be used as the gate insulating layers GI1, GI2 and the insulating layers IL1 to IL3 and IL5. As the above-mentioned components, the above-mentioned materials can be used as a single layer, or they can be used in a stacked manner.

[0067] It should be noted that, as an example of the above-mentioned insulating layer, SiOx with a thickness of 100nm is used as the gate insulating layer GI1. In addition, as the insulating layer IL1, SiOx / SiNx / SiOx with a total thickness of 600nm to 700nm is used. As the gate insulating layer GI2, SiOx / SiNx with a total thickness of 60 to 100nm is used. As the insulating layer IL2, SiOx / SiNx / SiOx with a total thickness of 300nm to 500nm is used. As the insulating layer IL3, SiOx (single layer), SiNx (single layer), or a stacked layer thereof with a total thickness of 200nm to 500nm is used. As the insulating layer IL4, an organic layer with a thickness of 2μm to 4μm is used. As the insulating layer IL5, SiNx (single layer) with a thickness of 50nm to 150nm is used.

[0068] The above-mentioned SiOxNy and AlOxNy are silicon compounds and aluminum compounds containing nitrogen (N) at a ratio (x>y) less than oxygen (O). In addition, SiNxOy and AlNxOy are silicon compounds and aluminum compounds containing oxygen at a ratio (x>y) less than nitrogen.

[0069] As the oxide semiconductor layer OS, an oxide metal having semiconductor properties can be used. The oxide semiconductor layer OS is light-transmitting. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn and O used in this embodiment is not limited to the above composition, and an oxide semiconductor with a composition different from the above can also be used. For example, in order to improve the mobility, the ratio of In can also be made larger than the above. In addition, in order to increase the band gap and reduce the influence of light irradiation, the ratio of Ga can also be made larger than the above.

[0070] Other elements may also be added to the oxide semiconductor containing In, Ga, Zn and O. For example, metal elements such as Al and Sn may also be added to the oxide semiconductor. In addition to the above-mentioned oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn and Zn (ITZO), and an oxide semiconductor containing In and W may also be used as the oxide semiconductor layer OS. The oxide semiconductor layer OS may be amorphous or crystalline. The oxide semiconductor layer OS may also be a mixed phase of amorphous and crystalline.

[0071] A transparent conductive layer is used as the connecting electrode ZTCO, the pixel electrode PTCO and the common electrode CTCO. As the transparent conductive layer, a mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can be used. As the transparent conductive layer, materials other than the above can also be used.

[0072] According to this embodiment, by making the oxide semiconductor layer OS of the transistor Tr1 directly contact the connection electrode ZTCO, the conduction between the two can be ensured. Therefore, there is no need to set a metal layer between the oxide semiconductor layer OS and the connection electrode ZTCO. Therefore, since the opening ZCON (first contact area CON1) is not shielded from light, the decrease in the aperture ratio can be suppressed.

[0073] In addition, since the oxide semiconductor layer is light-transmitting, in this embodiment, although the oxide semiconductor layer is exposed in the opening area in the pixel area, the light from the backlight passes through the oxide semiconductor layer. Therefore, the decrease in transmittance of the opening area caused by the oxide semiconductor layer being exposed in the opening area is minimized. In addition, the layer exposed in the display area is an oxide semiconductor layer OS that is light-transmitting and does not easily produce uneven transmission light such as a silicon layer, so it is possible to suppress the generation of display unevenness.

[0074] [Second embodiment]

[0075] use Figure 6 to Figure 8 The overall configuration of the display device described in the first embodiment will be described.

[0076] [Overview of Display Device 20]

[0077] Figure 6 1 is a top view showing an overview of a display device according to an embodiment of the present invention. Figure 6 As shown, the display device 20 includes an array substrate 300, a sealing portion 400, an opposing substrate 500, a flexible printed circuit substrate 600 (FPC 600), and an IC chip 700. The array substrate 300 and the opposing substrate 500 are bonded together by the sealing portion 400. A plurality of pixel circuits 310 are arranged in a matrix in a liquid crystal region 22 surrounded by the sealing portion 400. The liquid crystal region 22 is a region overlapping with a liquid crystal element 410 described later when viewed from above.

[0078] The sealing area 24 provided with the sealing portion 400 is an area around the liquid crystal area 22. The FPC 600 is provided in the terminal area 26. The terminal area 26 is an area where the array substrate 300 is exposed from the counter substrate 500, and is provided outside the sealing area 24. It should be noted that the outside of the sealing area 24 means the outside of the area provided with the sealing portion 400 and the area surrounded by the sealing portion 400. The IC chip 700 is provided on the FPC 600. The IC chip 700 provides a signal for driving each pixel circuit 310.

[0079] [Circuit Configuration of Display Device 20]

[0080] Figure 7 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. Figure 7 As shown, a source driving circuit 320 is provided at a position adjacent to the liquid crystal region 22 where the pixel circuit 310 is configured in the second direction D2 (column direction), and a gate driving circuit 330 is provided at a position adjacent to the liquid crystal region 22 in the first direction D1 (row direction). The source driving circuit 320 and the gate driving circuit 330 are provided in the above-mentioned sealing region 24. However, the region where the source driving circuit 320 and the gate driving circuit 330 are provided is not limited to the sealing region 24, and can be any region as long as it is outside the region where the pixel circuit 310 is provided. The source driving circuit 320 and the gate driving circuit 330 can also be used as peripheral circuits.

[0081] It should be noted that the liquid crystal region 22 and the sealing region 24 may be consistent with or inconsistent with the display region DR and the peripheral region PR in the first embodiment. Specifically, a configuration may be adopted in which a part or all of the peripheral region PR is included in the liquid crystal region 22. Figure 2 Although there is a region where no pixel electrode PTCO exists around the edge of the display region DR shown, this region can also serve as the liquid crystal region 22 .

[0082] The source wiring 321 extends from the source driving circuit 320 in the second direction D2 and is connected to the plurality of pixel circuits 310 arranged in the second direction D2. The gate wiring 331 extends from the gate driving circuit 330 in the first direction D1 and is connected to the plurality of pixel circuits 310 arranged in the first direction D1.

[0083] The terminal region 26 is provided with a terminal portion 333. The terminal portion 333 is connected to the source driving circuit 320 via a connection wiring 341. Similarly, the terminal portion 333 is connected to the gate driving circuit 330 via a connection wiring 341. The FPC 600 is connected to the terminal portion 333, so that an external device connected to the FPC 600 is connected to the display device 20, and each pixel circuit 310 provided in the display device 20 is driven by a signal from the external device.

[0084] The transistor Tr1 described in the first embodiment and the second embodiment is used in the pixel circuit 310. The transistor Tr2 described in the first embodiment and the second embodiment is applied to transistors included in the source driving circuit 320 and the gate driving circuit 330.

[0085] [Pixel Circuit 310 of Display Device 20]

[0086] Figure 8 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. Figure 8 As shown, the pixel circuit 310 includes components such as a transistor 800, a holding capacitor 890, and a liquid crystal element 410. One electrode of the holding capacitor 890 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. Similarly, one electrode of the liquid crystal element 410 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. The transistor 800 has a first gate electrode 810, a first source electrode 830, and a first drain electrode 840. The first gate electrode 810 is connected to the gate wiring 331. The first source electrode 830 is connected to the source wiring 321. The first drain electrode 840 is connected to the holding capacitor 890 and the liquid crystal element 410. The transistor Tr1 shown in the first embodiment and the second embodiment is applied to Figure 8Transistor 800 is shown. It should be noted that in this embodiment, for the sake of convenience of description, 830 is called a source electrode and 840 is called a drain electrode, but the function of each electrode as a source and a drain may be reversed.

[0087] (Variation Example)

[0088] As embodiments of the present invention, the embodiments described above can be appropriately combined and implemented as long as they do not contradict each other. In addition, aspects obtained by adding, deleting or changing the design of components or by adding, omitting or changing the conditions of processes based on the display device of each embodiment by a person skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0089] Even if there are other effects different from the effects brought about by the aspects of the above-mentioned embodiments, if they are obvious effects based on the description of this specification or effects that can be easily predicted by those skilled in the art, they should of course be understood to be brought about by the present invention.

[0090] In the first embodiment of the present invention, the light shielding layer LS1 is made of a metal material, but the present invention is not limited thereto. For example, the light shielding layer LS1 may be made of a resin material having light shielding properties. Specifically, the light shielding layer LS1 may be made of a black resin.

Claims

1. A display device comprising: substrate; A first transistor includes an oxide semiconductor layer, a first gate insulating layer and a first gate electrode, and is disposed in a display area; as well as a light shielding layer disposed between the substrate and the oxide semiconductor layer, The light shielding layer comprises: A first light-shielding metal layer is disposed between the substrate and the oxide semiconductor layer; as well as a second light-shielding metal layer, covering the upper surface and side surfaces of the first light-shielding metal layer and facing the oxide semiconductor layer; The display device includes a second transistor, which includes a second semiconductor layer including silicon, a second gate insulating layer, and a second gate electrode, and is disposed in a peripheral area located around the display area. The second light-shielding metal layer and the second gate electrode are arranged on the same layer, The first gate electrode extends in a first direction from the display region toward the peripheral region, and has a protrusion protruding in a second direction intersecting the first direction at a peripheral portion of the display region. The main line portion of the first gate electrode and the second gate electrode are spaced apart from each other in a direction intersecting the extending direction, and are connected to each other via a protruding portion of the first gate electrode.

2. The display device according to claim 1, wherein: The first gate electrode extends from the display area toward the peripheral area, The second gate electrode is connected to the first gate electrode at an end portion of the display region.

3. The display device according to claim 1, wherein: The thickness of the light shielding layer is greater than 100 nm.

4. The display device according to claim 1, wherein: The light shielding layer has a width greater than that of the first gate electrode.

5. The display device according to claim 1, wherein: The first gate electrode is electrically connected to the light shielding layer.

6. The display device according to claim 1, wherein: The first gate electrode extends in a first direction from the display area toward the peripheral area, One or more dummy transistors are provided between the oxide semiconductor layer and an end portion of the first gate electrode, the dummy transistors being provided with an oxide semiconductor layer and a wiring overlapping the oxide semiconductor layer, These oxide semiconductors and wirings intersect the first gate electrode and are connected to each other at both ends.

7. The display device according to claim 6, wherein: The oxide semiconductor layer of the dummy transistor is formed in the same layer as the oxide semiconductor layer of the transistor, and the wiring is formed in a layer above the first gate electrode.

8. A display device comprising: substrate; A first transistor includes an oxide semiconductor layer, a first gate insulating layer and a first gate electrode, and is disposed in a display area; as well as a light shielding layer disposed between the substrate and the oxide semiconductor layer, The light shielding layer comprises: A first light-shielding metal layer is disposed between the substrate and the oxide semiconductor layer; as well as a second light-shielding metal layer, covering the upper surface and side surfaces of the first light-shielding metal layer and facing the oxide semiconductor layer; The display device includes a second transistor, which includes a second semiconductor layer including silicon, a second gate insulating layer, and a second gate electrode, and is disposed in a peripheral area located around the display area. The second light-shielding metal layer and the second gate electrode are arranged on the same layer, The first gate electrode extends in a first direction from the display area toward the peripheral area, One or more dummy transistors are provided between the oxide semiconductor layer and an end portion of the first gate electrode, the dummy transistors being provided with an oxide semiconductor layer and a wiring overlapping the oxide semiconductor layer, These oxide semiconductors and wirings intersect the first gate electrode and are connected to each other at both ends.

9. The display device according to claim 8, wherein: The oxide semiconductor layer of the dummy transistor is formed in the same layer as the oxide semiconductor layer of the transistor, and the wiring is formed in a layer above the first gate electrode.

10. A display device, comprising: substrate; A first transistor includes an oxide semiconductor layer, a first gate insulating layer and a first gate electrode, and is disposed in a display area; a light shielding layer, disposed between the substrate and the oxide semiconductor layer and overlapping the oxide semiconductor layer; as well as The second transistor includes a second semiconductor layer including silicon, a second gate insulating layer and a second gate electrode, and is disposed in a peripheral area located around the display area. The thickness of the light shielding layer is greater than the thickness of the second gate electrode, The first gate electrode extends in a first direction from the display area toward the peripheral area, and has a main line portion and a protruding portion, wherein the protruding portion is located at an end of the main line portion in the peripheral portion of the display area in the first direction and protrudes in a second direction intersecting the extending direction of the main line portion. The main line portion of the first gate electrode and the second gate electrode are spaced apart from each other in a direction intersecting the extending direction, and are connected to each other via a protruding portion of the first gate electrode.

11. The display device according to claim 10, wherein: The thickness of the light shielding layer is more than twice the thickness of the second gate electrode.

12. The display device according to claim 10 or 11, wherein: The light shielding layer includes a first light shielding metal layer and a second light shielding metal layer covering the upper surface and side surfaces of the first light shielding metal layer.

13. The display device according to claim 10, wherein: The first gate electrode extends in a first direction from the display area toward the peripheral area, The second gate electrode is connected to the first gate electrode at an end portion of the display region.

14. The display device according to claim 10, wherein: The thickness of the light shielding layer is greater than 100 nm.

15. The display device according to claim 10, wherein: The light shielding layer has a width greater than that of the first gate electrode.

16. The display device according to claim 10, wherein: The first gate electrode is electrically connected to the light shielding layer.

17. The display device according to claim 10, wherein: The first gate electrode extends in a first direction from the display area toward the peripheral area, One or more dummy transistors are provided between the oxide semiconductor layer and an end portion of the first gate electrode, the dummy transistors being provided with an oxide semiconductor layer and a wiring overlapping the oxide semiconductor layer, These oxide semiconductor layers and wirings intersect the first gate electrode and are connected to each other at both ends.

18. The display device according to claim 17, wherein: The oxide semiconductor layer of the dummy transistor is formed in the same layer as the oxide semiconductor layer of the transistor, and the wiring is formed in a layer above the first gate electrode.

19. A display device comprising: substrate; A first transistor includes an oxide semiconductor layer, a first gate insulating layer and a first gate electrode, and is disposed in a display area; a light shielding layer, disposed between the substrate and the oxide semiconductor layer and overlapping the oxide semiconductor layer; as well as The second transistor includes a second semiconductor layer including silicon, a second gate insulating layer and a second gate electrode, and is disposed in a peripheral area located around the display area. The thickness of the light shielding layer is greater than the thickness of the second gate electrode, The first gate electrode extends in a first direction from the display area toward the peripheral area, One or more dummy transistors are provided between the oxide semiconductor layer and an end portion of the first gate electrode, the dummy transistors being provided with an oxide semiconductor layer and a wiring overlapping the oxide semiconductor layer, These oxide semiconductor layers and wirings intersect the first gate electrode and are connected to each other at both ends.

20. The display device according to claim 19, wherein: The oxide semiconductor layer of the dummy transistor is formed in the same layer as the oxide semiconductor layer of the transistor, and the wiring is formed in a layer above the first gate electrode.

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