Display panel and electronic device

Abstract

The embodiments of the present disclosure provide a display panel and an electronic device, wherein the display panel comprises: a substrate, the substrate comprises a display area and a non-display area; the non-display area is located outside the display area, and a plurality of virtual sub-pixels are arranged on the non-display area; a plurality of display sub-pixels, a plurality of power supply voltage lines and a plurality of data signal lines are arranged on the display area, and the display sub-pixels comprise: a display pixel driving circuit, and a light-emitting unit driven to emit light by the display pixel driving circuit; the power supply voltage line and the data signal line are connected to the display pixel driving circuit; the display pixel driving circuit comprises at least a first transistor group and a second transistor connected to the first transistor group, and the first transistor group and the second transistor both comprise an active layer; the first transistor group comprises at least two first transistors connected in series, and the active layers of the two first transistors are connected via a channel connection region; and the data signal line is connected to the second transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display, and in particular to a display panel and an electronic device. Background Art

[0002] Panel (display panel) routing design must comprehensively consider the impact of loading (coupling capacitance) and power consumption on product display effects. However, the routing of existing display panels has many overlapping areas, which makes the overall coupling capacitance larger, the product power consumption higher, and the performance worse. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure propose a display panel and an electronic device to solve the following problems in the prior art: the wiring of the existing display panel has many overlapping areas, resulting in a large overall coupling capacitance, high product power consumption and poor performance.

[0004] On the one hand, an embodiment of the present disclosure proposes a display panel, comprising: a substrate, the substrate comprising a display area and a non-display area; the non-display area is located outside the display area, and a plurality of virtual sub-pixels are arranged on the non-display area; a plurality of display sub-pixels, a plurality of power supply voltage lines and a plurality of data signal lines are arranged on the display area, and the display sub-pixels comprise: a display pixel driving circuit, and a light-emitting unit driven to emit light by the display pixel driving circuit; the power supply voltage line and the data signal line are connected to the display pixel driving circuit; the display pixel driving circuit comprises at least a first transistor group and a second transistor connected to the first transistor group, and the first transistor group and the second transistor both comprise an active layer; the first transistor group comprises at least two first transistors connected in series, and the active layers of the two first transistors are connected through a channel connection region; the data signal line is connected to the second transistor.

[0005] In some embodiments, it also includes: a pixel driving circuit layer, which is arranged on one side of the base substrate, and at least includes: a first semiconductor layer, a first gate layer, a second gate layer, and a first conductive layer arranged in sequence; the first semiconductor layer includes the active layer of the first transistor group and the second transistor and the channel connection area.

[0006] In some embodiments, the pixel driving circuit layer also includes a shielding member, which is connected to the power supply voltage line, and the orthographic projection of the shielding member on the substrate at least partially overlaps with the orthographic projection of the channel connection area on the substrate, and the shielding member does not overlap with the orthographic projection of the data signal line and the active layer of the second transistor on the substrate.

[0007] In some embodiments, the second gate layer includes the shielding member, and the first conductive layer includes a power supply voltage line and a data signal line connected to a display pixel driving circuit.

[0008] In some embodiments, it also includes: the virtual sub-pixel includes a virtual pixel driving circuit and a virtual light-emitting unit; the setting boundary of the virtual pixel driving circuit in the row direction is the same as the boundary of the display sub-pixel driving circuit in the row direction, and the setting boundary of the virtual sub-pixel driving circuit in the column direction is the same as the boundary of the display pixel driving circuit in the column direction.

[0009] In some embodiments, the pixel driving circuit layer also includes an anode layer located on a side of the first conductive layer away from the base substrate and a cathode layer located on a side of the anode layer away from the base substrate, the anode layer includes an anode of a light-emitting unit located in a display area and an anode of a virtual light-emitting unit located in a non-display area, and the anode of the virtual light-emitting unit is laid as a whole layer.

[0010] In some embodiments, the anode layer on the non-display area is connected to a low power voltage line to transmit the low power voltage signal through the anode layer to the cathode layer of the display area, and the cathode layer includes a cathode of a light-emitting unit located on the display area.

[0011] In some embodiments, the dummy pixel driving circuit is not connected to the anode layer on the non-display area.

[0012] In some embodiments, the first transistor group further includes: a source, a drain, and a double gate; the source and the drain are located in the first conductive layer, and the double gate is located in the first gate layer.

[0013] In some embodiments, the source and drain of the first transistor group are connected through an active layer of the first transistor group, and the active layer connecting the source and drain has at least an L-shaped structure; the dual gate has a T-shaped structure, and an L-shaped structure in the T-shaped structure is inversely superimposed on the L-shaped structure of the active layer to enclose a square area.

[0014] On the other hand, an embodiment of the present disclosure provides an electronic device, which at least includes the display panel provided by any embodiment of the present disclosure.

[0015] The display panel of the disclosed embodiment includes a display area and a non-display area outside the display area. The power supply voltage line and the data signal line of the display sub-pixel are connected to the display pixel driving circuit of the display sub-pixel. This method of optimizing the routing has less routing overlap, reduces the overall coupling capacitance, reduces product power consumption, and improves product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 A circuit diagram of a 7T1C display pixel driving circuit provided in the related art;

[0018] Figure 2 A wiring diagram of a portion of a display pixel driving circuit for a display sub-pixel provided in the related art;

[0019] Figure 3 A wiring diagram of a portion of a display pixel driving circuit of a display panel provided by an embodiment of the present disclosure;

[0020] Figure 4 A wiring diagram of a first semiconductor layer provided in an embodiment of the present disclosure;

[0021] Figure 5 A wiring diagram of a first gate layer provided in an embodiment of the present disclosure;

[0022] Figure 6 A wiring diagram of a second gate layer provided in an embodiment of the present disclosure;

[0023] Figure 7 A schematic diagram of a layout for forming via holes on a first insulating layer provided in an embodiment of the present disclosure;

[0024] Figure 8 A wiring diagram of a first conductive layer provided in an embodiment of the present disclosure;

[0025] Fig. 9 A schematic diagram of a virtual sub-pixel filling range provided in an embodiment of the present disclosure.

[0026] Reference numerals:

[0027] 1-shielding member, 2-power supply voltage line, 3-data signal line, 4-gate of the first transistor group, 5-gate of the second transistor. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0029] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0030] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0031] For existing display panels, for example, when the display sub-pixel adopts a 7T1C display pixel driving circuit, the poly (first semiconductor layer) shielding of the T2 (first transistor group) double gate adopts a Gate2 (second gate layer) shielding layer connected to the VDD signal (power supply voltage signal) design. Usually, Gate2 is connected to the VDD signal of the previous column to shield the poly layer between the T2 double gates of the current display sub-pixel. This will cause the poly layer and SD layer connected to the data signal (data signal) to overlap with Gate2, forming an overlapping capacitor, increasing data loading, and such a design will make the T2 of the display sub-pixel in the leftmost column of the display panel unable to be shielded. Figure 1 FIG. 1 is a circuit diagram of a display pixel driving circuit of 7T1C. Figure 2 It is a wiring diagram of the pixel driving circuit (T2 double gate related area) for the display sub-pixel.

[0032] Based on the above considerations, the embodiment of the present disclosure optimizes the wiring design for the display panel, which can not only reduce loading and optimize the display, but also reduce power consumption and improve product competitiveness.

[0033] The present disclosure provides a display panel, a portion of the display panel (with Figure 2 The wiring of the display pixel driving circuit is as follows Figure 3 As shown, including:

[0034] A substrate, the substrate comprising a display area and a non-display area; the non-display area is located outside the display area, and a plurality of virtual sub-pixels are arranged on the non-display area; a plurality of display sub-pixels, a plurality of power supply voltage lines and a plurality of data signal lines are arranged on the display area, and the display sub-pixels comprise: a display pixel driving circuit, and a light-emitting unit driven to emit light by the display pixel driving circuit; a power supply voltage line 2 (VDD signal line) and a data signal line 3 (Data signal line) are connected to the display pixel driving circuit; the display pixel driving circuit comprises at least a first transistor group (the reference numeral 4 in the figure is a gate of the first transistor group) and a second transistor connected to the first transistor group (the reference numeral 5 in the figure is a gate of the second transistor), and both the first transistor group and the second transistor comprise an active layer; the first transistor group comprises at least two first transistors connected in series, and the active layers of the two first transistors are connected via a channel connection region; and the data signal line is connected to the second transistor.

[0035] The display panel of the disclosed embodiment includes a display area and a non-display area outside the display area. The power supply voltage line and the data signal line of the display sub-pixel are connected to the display pixel driving circuit of the display sub-pixel. This method of optimizing the routing has less routing overlap, reduces the overall coupling capacitance, reduces product power consumption, and improves product performance.

[0036] Figure 3 Based only on Figure 2 An example, those skilled in the art can make adaptive adjustments based on the above ideas according to the actual display pixel driving circuit, which are all within the protection scope of the embodiments of the present disclosure.

[0037] Whether it is a display area or a non-display area, it includes a pixel driving circuit. Therefore, the display panel of the embodiment of the present disclosure also includes a pixel driving circuit layer, which is arranged on one side of the base substrate and at least includes: a first semiconductor layer, a first gate layer, a second gate layer, and a first conductive layer arranged in sequence; the first semiconductor layer includes an active layer and a channel connection area of ​​a first transistor group and a second transistor. Under the first conductive layer, a first insulating layer is also provided, and a via is formed on the first insulating layer, and the first conductive layer is connected to the first semiconductor layer, the first conductive layer is connected to the first gate layer, and the first conductive layer is connected to the second gate layer through the via.

[0038] against Figure 3 In terms of Figure 4 The wiring diagram of the first semiconductor layer (Poly) is shown in FIG. Figure 5The wiring diagram of the first gate layer (Gate1) is shown below. Figure 6 This is the wiring diagram for the second gate layer (Gate2). Figure 7 The layout diagram of the via holes on the first insulating layer (ILD) is shown below. Figure 8 The pixel driving circuit layer is a wiring diagram of the first conductive layer (SD). Figures 4 to 8 The layers of stacking eventually formed Figure 3 Part of the display pixel drive circuit wiring diagram.

[0039] The pixel driving circuit layer further includes a shielding member 1, the shielding member is connected to a power supply voltage line 2, an orthographic projection of the shielding member on the substrate substrate overlaps at least partially with an orthographic projection of the channel connection region on the substrate substrate, and the orthographic projection of the shielding member on the substrate substrate does not overlap with an orthographic projection of the data signal line and an active layer of the second transistor. The second gate layer includes the shielding member, and the first conductive layer includes a power supply voltage line and a data signal line connected to the display pixel driving circuit.

[0040] For the first transistor group, it includes a source, a drain and a double gate ( Figure 3 4), wherein the first transistor group includes two first transistors connected in series, the active layers of the two first transistors are connected through a channel connection region, the active layer of the first first transistor includes a source and a channel portion, the active layer of the second first transistor includes a channel portion and a drain, the channel portions of the two first transistors are connected through the channel connection region, and the positive projection of the channel portions of the two first transistors on the substrate overlaps with the positive projection of the double gate on the substrate. The source, drain, channel portion and channel connection region are located in the first conductive layer, and the double gate is located in the first gate layer; the source and drain of the first transistor group are connected through the active layer of the first transistor group, the active layer connecting the source and drain has at least one L-shaped structure, the double gate has a T-shaped structure, and an L-shaped structure in the T-shaped structure is reversely superimposed on the L-shaped structure of the active layer to enclose a square area. As can be seen from Figure 3, the first conductive layer in the square area in the figure except the double gate is the channel connection region.

[0041] For the second transistor, Figure 3 It can be seen that the gate of the second transistor ( Figure 3 The wiring connection of the double gate of the first transistor group (marked 5) is located in the first gate layer, and the two ends of the active layer of the second transistor are respectively connected to the power supply voltage line 2 (VDD signal line) and the data signal line 3 (Data signal line), and the orthographic projection of the channel part of the second transistor on the substrate overlaps with the orthographic projection of the gate on the substrate to form a cross-shaped area.

[0042] The disclosed embodiment optimizes the routing design and utilizes the VDD signal line of the pixel in this column to connect the Gate2 shielding member to shield the poly between the double gates of T2 (first transistor group). This not only avoids the overlap with signal lines such as Data and reduces Data loading, but also shields T2 of a column of display sub-pixels at the leftmost edge of the display panel, thereby improving the display effect.

[0043] The disclosed embodiments not only optimize the routing of the display area, but also optimize the non-display area outside the display area. For products such as square frames and arc displays, designs such as filling Dummy pixels (virtual sub-pixels) at the four corners to compensate for Data capacitors and reducing the four-corner anode coverage to reduce loading are proposed.

[0044] For the non-display area, the virtual sub-pixel includes a virtual pixel driving circuit and a virtual light-emitting unit; the setting boundary of the virtual pixel driving circuit in the row direction is the same as the boundary of the display sub-pixel driving circuit in the row direction, and the setting boundary of the virtual sub-pixel driving circuit in the column direction is the same as the boundary of the display pixel driving circuit in the column direction.

[0045] For example Fig. 9 As shown in the figure, it is a schematic diagram of setting the virtual sub-pixel filling range of a corner outside the display area of ​​the display panel. The filling boundaries of the virtual pixel driving circuit are respectively based on the boundary rows and boundary columns where the display sub-pixels are located. Virtual sub-pixels are placed outside the arc display to replace the capacitance compensation of Data, which not only makes the compensation more accurate, but also makes the routing environment of the compensation area consistent with the display area, and the connection from GOA to the display area is more uniform, which reduces the parasitic capacitance of the routing and improves the display effect.

[0046] During wiring, the pixel driving circuit and the anode layer can be connected through the flat layer vias, that is, the flat layer vias are prepared on the first conductive layer, and then the anode layer is prepared, and then the pixel driving circuit is connected to the anode layer through the flat layer vias.

[0047] When the cathode layer of the display panel is laid on the entire surface, its coupling capacitance is also large. Therefore, the embodiment of the present disclosure redesigns the virtual light-emitting unit of the virtual sub-pixel, and the pixel driving circuit layer also includes an anode layer located on the side of the first conductive layer away from the substrate and a cathode layer located on the side of the anode layer away from the substrate. The anode layer includes an anode of the light-emitting unit located in the display area and an anode of the virtual light-emitting unit located in the non-display area. The anode of the virtual light-emitting unit is laid in an entire layer; the anode layer on the non-display area is connected to a low power supply voltage line (VSS signal line, cathode signal) to transmit the low power supply voltage signal to the cathode layer of the display area through the anode layer, and the cathode layer includes the cathode of the light-emitting unit located in the display area; the virtual pixel driving circuit is not connected to the anode layer on the non-display area.

[0048] The embodiment of the present disclosure is to lay the cathode layer which is originally laid on the whole surface only in the display area, and to lay the anode layer ( Fig. 9 The VSS signal is introduced into the triangular area shown in the figure. The increase of the anode area increases the VSS area and reduces the panel power consumption. Under the condition of a certain cathode overlap, the cathode area can be reduced, which also reduces the cathode loading.

[0049] In summary, the disclosed embodiments propose a design scheme for products with a square frame on four corners and an arc-shaped display, including optimizing routing to reduce data loading, filling dummy pixels at four corners with compensating data capacitors, and covering anodes at four corners to reduce loading, so as to achieve the purpose of optimizing display, reducing loading, and reducing power consumption.

[0050] The embodiments of the present disclosure further provide an electronic device, which at least includes the display panel provided by the above embodiments of the present disclosure. The wiring design of the display panel will not be described in detail here.

[0051] In addition, although exemplary embodiments have been described herein, the scope includes any and all embodiments based on the present disclosure with equivalent elements, modifications, omissions, combinations (e.g., various embodiments intersecting schemes), adaptations or changes. The elements in the claims will be interpreted broadly based on the language adopted in the claims, and are not limited to the examples described in this specification or during the implementation of this application, and the examples will be interpreted as non-exclusive. Therefore, this specification and examples are intended to be considered as examples only, and the true scope and spirit are indicated by the following claims and the full scope of their equivalents.

[0052] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more of them) can be used in combination with each other. For example, a person of ordinary skill in the art can use other embodiments when reading the above description. In addition, in the above-mentioned specific embodiments, various features can be grouped together to simplify the present disclosure. This should not be interpreted as an intention that a disclosed feature that is not required to be protected is necessary for any claim. On the contrary, the subject matter of the present disclosure may be less than all the features of a specific disclosed embodiment. Thus, the following claims are incorporated into the specific embodiments as examples or embodiments, wherein each claim is independently used as a separate embodiment, and it is considered that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present disclosure should be determined with reference to the attached claims and the full scope of equivalent forms granted by these claims.

[0053] Multiple embodiments of the present disclosure are described in detail above, but the present disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concepts of the present disclosure, and these variations and modifications should all fall within the scope of protection required by the present disclosure.

Claims

1. A display panel, characterized in that: include: A base substrate, the base substrate comprising a display area and a non-display area; The non-display area is located outside the display area, and a plurality of virtual sub-pixels are arranged on the non-display area; The display area is provided with a plurality of display sub-pixels, a plurality of power supply voltage lines and a plurality of data signal lines, wherein the display sub-pixels include: a display pixel driving circuit, and a light-emitting unit driven to emit light by the display pixel driving circuit; the power supply voltage lines and the data signal lines are connected to the display pixel driving circuit; The display pixel driving circuit comprises at least a first transistor group and a second transistor connected to the first transistor group, wherein the first transistor group and the second transistor both comprise an active layer; the first transistor group comprises at least two first transistors connected in series, and the active layers of the two first transistors are connected via a channel connection region; the data signal line is connected to the second transistor; It also includes: the virtual sub-pixel includes a virtual pixel driving circuit and a virtual light-emitting unit; the setting boundary of the virtual pixel driving circuit in the row direction is the same as the boundary of the display pixel driving circuit in the row direction, and the setting boundary of the virtual sub-pixel driving circuit in the column direction is the same as the boundary of the display pixel driving circuit in the column direction.

2. The display panel according to claim 1, wherein: Also includes: The pixel driving circuit layer is arranged on one side of the base substrate, and at least comprises: a first semiconductor layer, a first gate layer, a second gate layer, and a first conductive layer arranged in sequence; The first semiconductor layer includes active layers of the first transistor group and the second transistor and the channel connection region.

3. The display panel according to claim 2, wherein: The pixel driving circuit layer also includes a shielding member, which is connected to the power supply voltage line. The orthographic projection of the shielding member on the substrate at least partially overlaps with the orthographic projection of the channel connection area on the substrate, and the shielding member does not overlap with the orthographic projection of the data signal line and the active layer of the second transistor on the substrate.

4. The display panel according to claim 3, wherein: The second gate layer includes the shielding member, and the first conductive layer includes a power supply voltage line and a data signal line connected to a display pixel driving circuit.

5. The display panel according to claim 2, wherein: The pixel driving circuit layer also includes an anode layer located on the side of the first conductive layer away from the base substrate and a cathode layer located on the side of the anode layer away from the base substrate, the anode layer includes an anode of a light-emitting unit located in a display area and an anode of a virtual light-emitting unit located in a non-display area, and the anode of the virtual light-emitting unit is laid out as a whole layer.

6. The display panel according to claim 5, wherein: The anode layer on the non-display area is connected to a low power voltage line to transmit the low power voltage signal to the cathode layer of the display area through the anode layer, and the cathode layer includes a cathode of a light emitting unit located on the display area.

7. The display panel according to claim 6, wherein: The dummy pixel driving circuit is not connected to the anode layer on the non-display area.

8. The display panel according to claim 2, wherein: The first transistor group further includes: a source, a drain and a double gate; The source electrode and the drain electrode are located in the first conductive layer, and the double gate electrode is located in the first gate layer.

9. The display panel according to claim 8, wherein: The source and the drain of the first transistor group are connected through an active layer of the first transistor group, and the active layer connecting the source and the drain has at least an L-shaped structure; The double gate has a T-shaped structure, and an L-shaped structure in the T-shaped structure and the L-shaped structure of the active layer are inversely superimposed on each other to enclose a square area.

10. An electronic device, characterized in that: At least: The display panel according to any one of claims 1 to 9.

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