Transistor structure and method of manufacturing the same

Abstract

A transistor structure includes a semiconductor substrate, a channel layer, a gate structure, and a first conductive region. The semiconductor substrate includes a semiconductor surface. The channel layer is separate from the semiconductor substrate and covers the semiconductor surface. The gate structure covers the channel layer. The first conductive region is coupled to the channel layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly, to a transistor structure and a method of fabricating the same. BACKGROUND

[0002] Conventional metal oxide semiconductor field effect transistors (MOSFETs) use a planar silicon surface (so-called original silicon surface (OSS)) with a thin dielectric layer (e.g., silicon oxide or high-k material) and a gate structure (e.g., poly-silicon, poly-metal silicide or metal material) on the planar silicon surface. Below the thin dielectric layer are some channel doping layers (e.g., a layer of boron dopants for NMOS and some n-type dopants for PMOS, respectively, by ion implantation) to form a well-controlled so-called channel region under the gate. This planar channel region for MOSFETs has been used for many technology generations, e.g., from several micrometers (mm) downscaling to 20 nanometers (nm) technology processing nodes.

[0003] As a result, there is an increasing demand to reduce device leakage and enhance device performance by increasing the width-to-length ratio (W / L) of the transistor channel. Therefore, the current design trend for the gate and channel has been changed to a three-dimensional (3D) structure, such as a tri-gate Fin-FET and other 3D shaped structures for 22 nm and below processing nodes. The most popular gate-channel structure is based on a Fin or tri-gate 3D shape as shown in Figure 1

[0004] Figure 1 is a structure perspective view of a tri-gate 3D channel structure 100 according to the prior art FinFET 10. The critical voltage (hreshold voltage VT) for controlling the on or off of the transistor channel is dependent on the channel doping, concentration and the selection of the appropriate work function design in the gate 11, dielectric (not shown) and channel. The work function design is achieved by using appropriate metal materials to match the required potential from the gate to the channel. The channel doping profile must be properly controlled, but this is not easy because the angle of the 3D Fin structure 12 must be precisely aligned with the angles of the different ion implantation processes that provide the channel doping.

[0005] ​Furthermore, high temperature thermal annealing processes are required to minimize the unavoidable defects caused by ion implantation bombardment during the formation of the channel doping regions. The channel doping profiles along the surfaces of the three-dimensional fin structure 12 must also be properly controlled. However, this is not easy because the angles of the three-dimensional fin structure 12 must be precisely aligned with each individual channel doping ion implantation process performed from different angles.

[0006] Another difficult factor to control is that the plurality of channel doping profiles must be as uniform as possible, but the three-dimensional channel structure 10 makes it very difficult to maintain uniformity of the doping profiles around the different process windows of the three-dimensional fin structure 12. As the minimum feature size on the wafer is further scaled down, the gate length and the corresponding channel length CL (both along the X-axis) must be reduced to achieve transistor size scaling. The transistor width, which is critical to transistor performance, is also affected by the device width-to-length ratio (W / L), where W is the sum of the width of the top surface of the fin of the three-dimensional fin structure 12, Wt (measured along the Y-axis), and twice the vertical width of the device, Wv (measured along the Z-axis, which is almost equal to the height of the fin), and can be expressed as W = Wt + 2 x Wv.

[0007] As the three-dimensional transistor size is scaled down, the current design trend requires not only reducing the width of the three-dimensional fin structure 12, but also increasing the height of the three-dimensional fin structure 12 to maintain the transistor width W. This results in a more pointed and difficult-to-control shape of the three-dimensional fin structure 12, which in turn degrades the chip's process yield. Another challenge is that as the fin width 12a (along the Y-axis) is reduced, the transistor body within the three-dimensional fin structure 12 can enter a fully-depleted region, which is connected to a fixed voltage source through either the p-type substrate for NMOS or the n-type well for PMOS. This fully-depleted state of the transistor body is not the best operating state for the transistor because the floating potential of the body can cause a reduction in the ability to resist various noise disturbances. In addition, it can make the device's leakage and short-channel effect (SCE) worse.

[0008] Therefore, there is a need to provide an advanced transistor structure and a method of fabricating the same to solve the problems faced by the prior art. SUMMARY

[0009] One of the objects of the present application is to provide a transistor structure comprising a semiconductor substrate, a channel layer, a gate structure, and a first conductive region. The semiconductor substrate comprises a semiconductor surface. The channel layer is independent of the semiconductor substrate and covers the semiconductor surface. The gate structure covers the channel layer. The first conductive region is coupled to the channel layer.

[0010] In one embodiment of the present application, the semiconductor substrate includes a fin structure and a channel layer covering the fin structure. The channel layer includes a top portion and a side portion. The top portion of the channel layer covers a top surface of the fin structure. The side portion of the channel layer covers a first sidewall and a second sidewall of the fin structure.

[0011] In one embodiment of the present application, the material constituting the top portion is the same as the material constituting the side portion.

[0012] In one embodiment of the present application, the material constituting the top portion or the side portion includes doped silicon (Si) or doped silicon-germanium (SiGe).

[0013] In one embodiment of the present application, the material constituting the top portion or the side portion includes a semiconductor material that allows a conductive inversion of a channel in response to an electric potential applied to the gate structure.

[0014] In one embodiment of the present application, the material constituting the top portion or the side portion is formed by a selective epitaxial growth (SEG) process, an atomic level deposition (ALD) process, a molecular beam epitaxy (MBE) process, or a metal-organic chemical vapor deposition (MOCVD) process.

[0015] In one embodiment of the present application, the material constituting the top portion is different from the material constituting the side portion.

[0016] In one embodiment of the present application, the material constituting the top portion is formed by a first deposition process, the material constituting the side portion is formed by a second deposition process, and the first deposition process and the second deposition process are different from each other.

[0017] In one embodiment of the present application, the first deposition process is a selective epitaxial growth process, an atomic level deposition process, a molecular beam epitaxy process, or a metal-organic chemical vapor deposition process.

[0018] In one embodiment of the present application, the gate structure includes a gate dielectric layer above the channel layer and a gate conductive layer above the gate dielectric layer.

[0019] In one embodiment of the present invention, the transistor structure further comprises a trench containing the first conductive region, wherein the first conductive region is independent of the semiconductor substrate and abuts the first surface of the channel layer and the first surface of the fin structure, and the first surface of the channel layer and the first surface of the fin structure both face the trench.

[0020] In one embodiment of the present invention, the first conductive region comprises a lightly doped drain (LDD) region in the trench; and the LDD region abuts the first surface of the channel layer and the first surface of the fin structure.

[0021] In one embodiment of the present invention, the first conductive region further comprises a heavily doped region in the trench and abutting the LDD region.

[0022] In one embodiment of the present invention, the transistor structure further comprises a local isolation region in the trench and only under the first conductive region.

[0023] In one embodiment of the present invention, the local isolation region comprises a silicon oxide layer and a local insulating plug. The silicon oxide layer covers the sidewalls and the bottom wall of the trench. The local insulating plug is in the trench and covers a portion of the silicon oxide layer that covers the bottom wall of the trench.

[0024] Another object of the present invention is to provide a transistor structure comprising a semiconductor substrate, a channel layer, a gate structure, and a first conductive region. The semiconductor substrate comprises a semiconductor surface. The channel layer is independent of the semiconductor substrate, wherein the material constituting the channel layer comprises a doped semiconductor material formed without ion implantation process. The gate structure covers the channel layer, wherein the gate structure comprises a gate dielectric layer over the channel layer and a gate conductive layer over the gate dielectric layer. The first conductive region is coupled to the channel layer.

[0025] In one embodiment of the present invention, the channel layer covers a predetermined shape structure in the semiconductor substrate.

[0026] In one embodiment of the present invention, the predetermined shape structure is a fin structure, and the transistor structure further comprises a trench containing the first conductive region, wherein the first conductive region abuts the first surface of the channel layer and the first surface of the fin structure, and the first conductive region comprises a LDD region formed without ion implantation process.

[0027] In one embodiment of the present invention, the LDD region is formed by a selective epitaxy growth process or an atomic layer deposition process; and the LDD region contacts the first surface of the channel layer and the first surface of the fin structure.

[0028] In one embodiment of the present invention, the first conductive region further comprises a heavily doped region located in the trench and against the lightly doped drain region.

[0029] In one embodiment of the present invention, the first conductive region has a dopant concentration profile extending laterally from the lightly doped drain region to the heavily doped region; and the dopant concentration profile is controllable.

[0030] In one embodiment of the present invention, an interface between the lightly doped drain region and the first surface of the channel layer is substantially aligned with an edge of the gate structure.

[0031] In one embodiment of the present invention, the transistor structure further comprises a local isolation region located in the trench. The local isolation region comprises a silicon oxide layer and a local insulating plug. The silicon oxide layer covers the sidewalls and the bottom wall of the trench; the local insulating plug is located in the trench and surrounded by the silicon oxide layer; and the first conductive region is surrounded by the silicon oxide layer and the local insulating plug.

[0032] Yet another object of the present invention is to provide a transistor structure comprising a semiconductor substrate, a channel layer, a gate structure, a first conductive region, and a second conductive region. The semiconductor substrate comprises a semiconductor surface and a predetermined shaped structure. The channel layer covers the predetermined shaped structure. The gate structure covers the channel layer. The first conductive region is coupled to the channel layer. The second conductive region is coupled to the channel layer.

[0033] In one embodiment of the present invention, the predetermined shaped structure is a fin structure; and the channel layer comprises a top portion and a side portion. The top portion of the channel layer is located above the semiconductor surface, and the side portion of the channel layer covers the first sidewall and the second sidewall of the fin structure. The transistor structure further comprises a first trench containing the first conductive region and a second trench containing the second conductive region. The first conductive region is independent of the semiconductor substrate and against the first surface of the channel layer and the first surface of the fin structure. The second conductive region is independent of the semiconductor substrate and against the second surface of the channel layer and the second surface of the fin structure.

[0034] In one embodiment of the present invention, the channel layer is capable of preventing the fin structure from being fully depleted.

[0035] In one embodiment of the present invention, the first conductive region comprises a first lightly doped drain region located in the first trench and against the first surface of the channel layer and the first surface of the fin structure. The second conductive region comprises a second lightly doped drain region located in the second trench and against the second surface of the channel layer and the second surface of the fin structure.

[0036] In one embodiment of the present invention, the first conductive region further comprises a first heavily doped region located in the first trench and abutting the first lightly doped drain region; and the second conductive region further comprises a second heavily doped region located in the second trench and abutting the second lightly doped drain region.

[0037] In one embodiment of the present invention, the channel layer, the first lightly doped drain region, and the second lightly doped drain region are formed without ion implantation processes.

[0038] In one embodiment of the present invention, the predetermined shaped structure is a U-shaped recessed structure; the channel layer covers a bottom wall and sidewalls of the U-shaped recessed structure; and at least a portion of the gate structure is located inside the U-shaped recessed structure.

[0039] Another object of the present invention is to provide a transistor structure comprising a semiconductor substrate, a channel layer, a gate structure, and a first conductive region. The semiconductor substrate comprises a semiconductor surface and a fin structure. The channel layer is independent of the semiconductor substrate and covers the fin structure. The gate structure covers the channel layer. The first conductive region is coupled to the channel layer. The channel layer comprises a top portion and a side portion. The top portion of the channel layer covers a top surface of the fin structure. The side portion of the channel layer covers first and second sidewalls of the fin structure. The top portion and the side portion of the channel layer are not formed simultaneously.

[0040] In one embodiment of the present invention, the material forming the top portion is the same as the material forming the side portion.

[0041] In one embodiment of the present invention, the material forming the top portion or the side portion comprises doped silicon or doped silicon germanium.

[0042] In one embodiment of the present invention, the material forming the top portion or the side portion comprises a semiconductor material that allows the channel to be electrically inverted by an electric potential applied to the gate structure.

[0043] In one embodiment of the present invention, the material forming the top portion or the side portion is formed by a selective epitaxial growth process, an atomic layer deposition process, a molecular beam epitaxy process, or a metal organic chemical vapor deposition process.

[0044] In one embodiment of the present invention, the material forming the top portion is different from the material forming the side portion.

[0045] In one embodiment of the present invention, the gate structure comprises a gate dielectric layer located above the channel layer and a gate conductive layer located above the gate dielectric layer.

[0046] In one embodiment of the present invention, the transistor structure further comprises a trench containing the first conductive region, wherein the first conductive region is independent of the semiconductor substrate and abuts the first surface of the channel layer and the first surface of the fin structure, and the first surface of the channel layer and the first surface of the fin structure both face the trench.

[0047] In one embodiment of the present invention, the first conductive region comprises a lightly doped drain region in the trench; and the lightly doped drain region abuts the first surface of the channel layer and the first surface of the fin structure.

[0048] In one embodiment of the present invention, the first conductive region further comprises a heavily doped region in the trench and abutting the lightly doped drain region.

[0049] In one embodiment of the present invention, the first conductive region further comprises a metal-containing region in the trench and abutting the heavily doped region.

[0050] In one embodiment of the present invention, the transistor structure comprises a local isolation region in the trench and under the first conductive region.

[0051] In one embodiment of the present invention, the local isolation region comprises an oxide layer and a local insulating plug. The oxide layer covers the sidewalls and the bottom wall of the trench. The local insulating plug is in the trench and covers a portion of the silicon oxide layer on the bottom wall of the trench.

[0052] Yet another object of the present invention is to provide a transistor structure comprising a semiconductor substrate, a channel layer, a gate structure, and a first conductive region. The semiconductor substrate comprises a semiconductor surface and a fin structure. The channel layer is independent of the semiconductor substrate and covers the fin structure. The gate structure covers the channel layer. The first conductive region is coupled to the channel layer. The channel layer covers first and second sidewalls of the fin structure and does not cover a top surface of the fin structure.

[0053] In one embodiment of the present invention, the transistor structure comprises a trench containing the first conductive region. The first conductive region abuts the first surface of the channel layer and the first surface of the fin structure. The first conductive region comprises a lightly doped drain region formed without an ion implantation process.

[0054] In one embodiment of the present invention, the lightly doped drain region is formed by a selective epitaxy growth process or an atomic layer deposition process; and the lightly doped drain region contacts the first surface of the channel layer and the first surface of the fin structure.

[0055] In one embodiment of the present invention, the first conductive region further comprises a heavily doped region in the trench and abutting the lightly doped drain region.

[0056] In one embodiment of the present invention, the dopant concentration profile of the first conductive region extends laterally from the lightly doped drain region to the heavily doped region, and the dopant concentration profile is controllable.

[0057] In one embodiment of the present invention, the interface between the lightly doped drain region and the first surface of the channel layer is substantially aligned with the edge of the gate structure.

[0058] In one embodiment of the present invention, the transistor structure further comprises a local isolation region in the trench. The local isolation region comprises a silicon oxide layer and a local insulating plug. The silicon oxide layer covers the sidewalls and the bottom wall of the trench; the local insulating plug is in the trench and is surrounded by the silicon oxide layer; and the first conductive region is surrounded by the silicon oxide layer and the local insulating plug.

[0059] In one embodiment of the present invention, the channel layer is capable of preventing the fin structure from being fully depleted.

[0060] Yet another object of the present invention is to provide a transistor structure comprising a semiconductor substrate, a channel layer, a gate structure, and a first conductive region. The semiconductor substrate comprises a semiconductor surface and a fin structure. The channel layer is independent of the semiconductor substrate and covers the fin structure. The gate structure covers the channel layer. The first conductive region is coupled to the channel layer. The channel layer is a doped layer formed without ion implantation process.

[0061] In one embodiment of the present invention, the channel layer has a dopant concentration between 1 x 1018 16 and 9 x 1019 18 .

[0062] In one embodiment of the present invention, the channel layer comprises a top portion and a side portion. The top portion of the channel layer covers the top surface of the fin structure. The side portion of the channel layer covers the first sidewall and the second sidewall of the fin structure.

[0063] In one embodiment of the present invention, the channel layer comprises a side portion that covers the first sidewall and the second sidewall of the fin structure.

[0064] According to the above embodiments, the present invention discloses a three-dimensional transistor structure, particularly a novel structure and method for constructing channel regions on tri-gate or fin field-effect transistor devices. Compared with the conventional method of constructing channel regions within the pristine silicon surface and the sidewall surfaces of the fins, the effective channel region in this novel structure is formed above the pristine silicon surface and outside the sidewall surfaces of the fins. Another feature is that an effective channel region can be formed below the dielectric layer of the MOSFET without the need for an ion implantation process, thereby avoiding unnecessary high-temperature thermal annealing steps, reducing damage caused by the ion implantation process, and thus improving channel conductivity and / or reducing leakage current. Attached Figure Description

[0065] To make the above-described embodiments and other objects, features and advantages of the present invention more apparent and understandable, several preferred embodiments are provided below in conjunction with the accompanying drawings:

[0066] Figure 1 This is a perspective view of a three-gate three-channel structure of a fin field-effect transistor as shown in the prior art.

[0067] Figure 2 According to an embodiment of the present invention, a flowchart of the method steps for forming a transistor structure is shown.

[0068] Figures 2A(1) to 2E(3) The execution is shown separately. Figure 2 The steps shown to form the transistor structure are a top view and a cross-sectional view of the process structure.

[0069] Figure 3A According to another embodiment of the invention, the execution is shown. Figure 2 The top view of the process structure obtained in step S24 is shown.

[0070] Figure 3B It is along Figure 3A The structural cross-section shown is illustrated by tangent C3.

[0071] Figure 4 This is a flowchart illustrating another method for forming a transistor structure according to another embodiment of the present invention.

[0072] Figures 4A(1) to 4F(2) The execution is shown separately. Figure 4 The steps shown to form the transistor structure are a top view and a cross-sectional view of the process structure.

[0073] Figure 5 This is a flowchart illustrating another method for forming a transistor structure according to yet another embodiment of the present invention.

[0074] Figure 5 A(1) indicates the execution Figure 5The top view of the process structure obtained in step S534 is shown.

[0075] Figure 5 A(2) is along Figure 5 The structural cross-section shown by the tangent C51 of A(1).

[0076] Figure 5 B(1) is the execution Figure 5 A top view of the transistor structure formed by the process steps shown.

[0077] Figure 5 B(2) is along Figure 5 The structural cross-section shown by the tangent C52 of B(1).

[0078] Figure 6 This illustrates the doped channel regions formed using conventional methods such as ion implantation and thermal processes, as well as those formed using... Figures 2A(1) to 2E(3) The diagram shows the doping concentration distribution of the effective channel region formed by the in-situ doping growth mechanism.

[0079] Figure 7 This is a cross-sectional view of a three-gate three-channel structure of a fin field-effect transistor as shown in the prior art. Detailed Implementation

[0080] Embodiments of the present invention provide a transistor structure and a method for fabricating the same. To make the above embodiments and other objects, features, and advantages of the present invention more apparent and understandable, several embodiments are described below in detail with reference to the accompanying drawings.

[0081] However, it must be noted that these specific embodiments and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The proposed preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the patent scope of the present invention. Those skilled in the art will be able to make equivalent modifications and variations based on the description in the following specification without departing from the spirit and scope of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0082] The following describes several process steps for forming the main parts of a transistor structure having a transistor channel region, a gate, and source / drain regions as examples, and illustrates the technical features of the present invention with accompanying drawings. It is worth noting that although the transistor structure illustrated in the examples is an NMOS transistor, PMOS transistor structures, except for having the opposite doping or constituent materials to NMOS transistors, can also be analogously applied to the technical features and fabrication methods described in this invention.

[0083] Example 1

[0084] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating the steps of a method for forming a transistor structure 20 according to an embodiment of the present invention. The method for forming the transistor structure 20 includes the following steps:

[0085] Step S21: Using patterned pad-nitride layer and patterned pad-oxide layer as etching mask, form at least one fin structure.

[0086] Step S22: Form a shallow trench isolation (STI) region in the semiconductor substrate to define at least one active island region.

[0087] (active island region).

[0088] Step S23: Remove the patterned pad silicon nitride layer and the patterned pad silicon oxide layer.

[0089] This exposes the semiconductor (silicon) surface of the active island area to the outside.

[0090] Step S24: Form a channel layer independent of the semiconductor substrate and cover the semiconductor surface.

[0091] Step S25: Form a gate dielectric layer on the active island region.

[0092] Step S26: Form the gate structure and the source / drain structure.

[0093] Step S27: Perform back-end processes to form the transistor structure.

[0094] Figure 2 A(1) is a top view of an embodiment according to this description, showing a structure having a patterned pad silicon nitride layer 204 and a patterned pad silicon oxide layer 205 located on top of an active island region 203. The active island region 203 is defined by forming a shallow trench isolation region 202. Figure 2 A(2) is along Figure 2The structural cross-section shown by tangent C21 of A(1) (refer to steps S21 and S22). In this embodiment, the steps for defining the active island region 203 are as follows: a pad silicon nitride layer 204 and a pad silicon oxide layer 205 are formed sequentially to cover the surface of the semiconductor substrate 200. The pad silicon nitride layer 204 and the pad silicon oxide layer 205 are then patterned using a photoresist etching process. Using the patterned pad silicon nitride layer 204 and the patterned pad silicon oxide layer 205 as an etching mask, anisotropic etching (not shown) is performed to remove a portion of the semiconductor substrate 200 to form at least one fin structure 201 with a predetermined shape (e.g., a U-shaped recessed structure). Subsequently, a dielectric deposition process is performed to form a shallow trench isolation region 202 surrounding the fin structure 201 to define the active island region 203.

[0095] like Figure 2 As shown in A(2), since the top surface 202a of the shallow trench isolation region 202 is positioned below the top surface 203t (i.e., the original silicon surface (SOS)) of the fin structure 201 (active island region 203), the four silicon sidewalls 203v of the active island region 203 located above the top surface 202a of the shallow trench isolation region 202 are exposed.

[0096] Referring to step S23: the patterned pad silicon nitride layer 204 and the patterned pad silicon oxide layer 205 are removed to expose the semiconductor (silicon) surface of the active island region 203. In this embodiment, the pad silicon nitride layer 204 and the pad silicon oxide layer 205 can be removed by at least one etching process, so that five silicon surfaces in the active island region 203, including four silicon sidewalls 203v and a top surface 203t (the original silicon surface (SOS)), are exposed (e.g., Figure 2 B(1) and Figure 2 (as shown in B(2)).

[0097] Referring to step S24: forming a channel layer 206 independent of the semiconductor substrate 200, so that it covers the semiconductor surface. Figure 2 C(1) is a top view showing the structure after a channel layer 206 is formed on a semiconductor substrate 200 to cover the semiconductor surface. Figure 2 C(2) is along Figure 2 The structural cross-section shown by the tangent C23 of C(1). Figure 2 C(3) is along Figure 2 The structural cross-section shown by the cutting line C24 of C(1).

[0098] In some embodiments of the present invention, the formation of the channel layer 206 includes a process step of forming an additional semiconductor material layer with a predetermined channel doping concentration (p-type dopant for NMOS or n-type dopant for PMOS) on the active island region 203 using selective epitaxial growth technology. This allows for an efficient channel region method (ECRM) that offers greater controllability and flexibility in the thickness of the efficient channel region (ECR) designed in the channel layer 206 and its conductivity characteristics (i.e., the inverted channel region generated by the gate potential relative to the source / drain potential) compared to conventional methods using channel ion implantation. This efficient channel region not only avoids channel crystal structure damage caused by the ion implantation process but also allows for an abrupt profile between the channel doping concentration and the original substrate doping concentration, thereby enabling better control of the inverted channel region when the transistor 200 is in the on state. Furthermore, since this embodiment features a tri-gate structure or a fin field-effect transistor structure, the width of the fin structure 201 is reduced proportionally, whereas conventional ion implantation techniques would only further reduce the vertical channel. Therefore, this outward-growing effective channel region method can provide another dimension for controlling the fin structure 201.

[0099] In this embodiment, the channel layer 206 is an additional silicon layer with a pre-defined channel doping concentration (p-type dopant for NMOS or n-type dopant for PMOS) formed on five exposed silicon surfaces using selective epitaxial growth technology. These silicon surfaces include the four silicon sidewalls 203v and the top surface 203t (original silicon surface (SOS)) of the active island region 203. Specifically, the channel layer 206 includes a top 206a and a side 206b. The top 206a of the channel layer 206 covers the top surface 203t (i.e., the original silicon surface (SOS)) of the fin structure 201; the side 206b of the channel layer 206 covers the first and second sidewalls of the fin structure 201 (e.g., the two opposing silicon sidewalls 203v of the active island region 203). The material constituting the top 206a can be the same as the material constituting the side portion 206b; and the material constituting the top 206a or the side portion 206b can include doped silicon or doped silicon germanium.

[0100] However, the methods and materials used to form the channel layer 206 are not limited thereto. For example, please refer to... Figure 3A . Figure 3AThis is a top view of the structure after a channel layer 306 is formed on a semiconductor substrate 200 and covers the semiconductor surface, according to another embodiment of the present invention. Figure 3B This is a cross-sectional view of the structure shown along tangent C3 in Figure 3.

[0101] In this embodiment, instead of using selective epitaxial growth to form the doped silicon layer, atomic level deposition (ALD), molecular beam epitaxy (MBE), or metal-organic chemical vapor deposition (MOCVD) is used to form a channel layer 306 on the top surface and four sidewalls of the active island region 203. This channel layer 306 is a suitable heterogeneous efficient channel region (HECR), such as a doped silicon-germanium layer, graphene-like material, or compound semiconductor layer (any material layer whose gate-substrate potential can be reversed). The heterogeneous efficient channel region of the channel layer 306 can be considered as (equivalent to) a... Figures 2C(1) to 2C(3) The effective channel area of ​​channel layer 206 is shown.

[0102] Referring to step S25: A gate dielectric layer 207 is formed on the active island region 203. After defining an effective channel region on the active island region 203 using any of the four methods described above (selective epitaxial growth process, atomic layer deposition process, molecular beam epitaxial growth process, or metal-organic chemical vapor deposition process), the dielectric material 207 is formed on top of the newly grown surface material on the surface of the active island region 203. Figure 2 D(1) is a top view showing the structure after the gate dielectric layer 207 is formed above the active island region 203 and covers the channel layer 206 and the shallow trench isolation region 202. Figure 2 D(2) is along Figure 2 The structural cross-section shown by the tangent C25 of D(1).

[0103] Referring to step S26: forming the gate structure 28 and the source / drain structure 29. The gate structure 28 and the source / drain structure 29 can be formed according to the method of the published invention patent application (U.S. Patent Application No. 17 / 314,233, filed May 7, 2021, entitled "MOSFETSTRUCTURE WITH CONTROLLABLE CHANNEL LENGTH BY FORMING LIGHTLY DOPED DRAINSWITHOUT USING ION IMPLANTATION", which claims priority to U.S. Provisional Patent Application No. 63 / 171,133, filed April 6, 2021, entitled "Complementary MOSFET Structure Using Novel Source / Channel / DrainJunction Structures with Buried Isolations to Reduce Leakages and Planar Areas Reserved for Preventing Latch-Up"). The entire contents of the aforementioned U.S. patent applications and provisional applications are incorporated into the disclosure of this invention by reference. Figure 2 E(1) is a top view showing the structure after the gate structure 28 and the source / drain structure 29 are formed above the active island region 203. Figure 2 E(2) is along Figure 2 The structural cross-section shown is given by the tangent C26 of E(1). Figure 2 E(3) is along Figure 2 The structural cross-section shown is given by the tangent C27 of E(1).

[0104] In this embodiment, the gate structure 28 includes a gate dielectric layer 207 located above the channel layer 206 and a gate conductive layer 208 located above the gate dielectric layer 207. The formation of the gate structure 28 includes the following steps: after forming the gate dielectric layer 207 above the active island region 203, a gate conductive layer 208 is deposited above the gate dielectric layer 207. Then, a silicon nitride layer 209 (silicon nitride capping layer) and a silicon oxide layer 210 (silicon oxide capping layer) with a predetermined thickness are deposited above the gate conductive layer 208. A portion of the gate dielectric layer 207, gate conductive layer 208, silicon nitride layer 209, and silicon oxide layer 210 are then removed using photolithography masking techniques to define the gate structure 28. The gate structure 28 includes the gate dielectric layer 207 and the gate conductive layer 208 to ensure that the gate structure 28 has a suitable metal gate material. The metal gate material is used to provide the work function required for the metal insulator-to-substrate (MIS) structure to achieve a threshold voltage suitable for the transistor structure 20 (e.g., mMOSFET). Furthermore, since the top surface 202a of the shallow trench isolation region 202 is located below the top surface 203t (i.e., the original silicon surface (SOS)) of the fin structure 201 (active island region 203), the channel layer 206 covers the bottom and sidewalls of the U-shaped recessed structure of the fin structure 201. At least a portion of the gate structure 28 is located within the U-shaped recessed structure.

[0105] The formation of the source / drain structure 29 includes the following steps: forming silicon nitride spacers 212 and silicon oxide spacers 213, respectively covering the four silicon sidewalls 203v and the sidewalls of the gate structure 28. A second shallow trench isolation structure 214 is formed above the top surface 202a of the shallow trench isolation region 202 to define the source / drain region on the active island region 203. Then, an anisotropic etching process is performed on the source / drain region to remove a portion of the silicon material, thereby forming at least one trench (e.g., a first trench 215a and a second trench 215b) in the active island region 203. Then, a thermally oxidized silicon layer 216 is formed in the first trench 215a and the second trench 215b, covering the sidewalls and bottom walls of the first trench 215a and the second trench 215b, and silicon nitride blocks 217 (also called local insulating plugs) are formed in the first trench 215a and the second trench 215b to expose the top of the thermally oxidized silicon layer 216. After etching back the top of the thermally oxidized silicon layer 21, a source / drain structure 29 (including a first conductive region 218 and a second conductive region 219) is formed by selective epitaxial growth, atomic layer deposition, molecular beam epitaxy, or metal-organic chemical vapor deposition, without using an ion implantation process.

[0106] After clearly defining the positional relationship between the effective channel region and the source / drain structure 29, a uniform and seamless three-dimensional interface can be formed between the fin structure 201 and the source / drain structure 29 by precisely controlling the defined channel region on the three surfaces of the fin structure 201 (below the gate dielectric layer 207 below the gate metal).

[0107] It is worth noting that the isolation region (including the thermally oxidized silicon layer 216, the silicon nitride block 217, and the silicon nitride spacer 212) is located directly below the source or drain region (which may include a lightly doped drain region), and the isolation region of the present invention does not extend laterally below the channel region of the transistor. Therefore, this isolation region is locally formed, which is completely different from the isolation layer in conventional silicon-on-insulator (SOI). A conventional isolation layer is a complete or generalized isolation region located between the device substrate (the silicon portion is located above the complete or generalized isolation region) and the wafer substrate (the wafer substrate is a bulk wafer located below the complete or generalized isolation region).

[0108] In this embodiment, two local isolation regions 220, including a silicon nitride block 217 (partial insulating plug) and a thermally heated silicon oxide layer 216, can be defined in the first trench 215a and the second trench 215b to surround the first conductive region 218 and the second conductive region 219. Specifically, the first conductive region 218 is composed of a first heavily doped region 218a and a first lightly doped drain region 218b, which is located in the trench 215a and is independent of the semiconductor substrate 200, and abuts against the first surface 206c of the channel layer 206 and the first surface of the fin structure 201 (one of the sidewalls 203v of the active island region 203). The second conductive region 219 is composed of a second heavily doped region 219a and a second LDD region 219b. It is located in the trench 215b and is independent of the semiconductor substrate 200. It abuts against the second surface 206d of the channel layer 206 and the first surface of the fin structure 201 (another sidewall 203v of the active island region 203).

[0109] The first heavily doped region 218a abuts against the first lightly doped drain region 218b, while the first lightly doped drain region 218b abuts against the first edge (surface) 206c of the channel layer 206 and the first surface of the fin structure 201 (one sidewall 203v of the active island region 203). The second heavily doped region 219a abuts against the second lightly doped drain region 219b, while the second lightly doped drain region 219b abuts against the second edge (surface) 206d of the channel layer 206 and the second surface of the fin structure 201 (the other sidewall 203v of the active island region 203). The interface 211a between the first lightly doped drain region 218b and the first surface 206c of the channel layer 206 is substantially aligned with one edge of the gate structure 28; the interface 211b between the second lightly doped drain region 219b and the second surface 206d of the channel layer 206 is substantially aligned with the other edge of the gate structure 28.

[0110] Referring to step S27: Perform back-end processes to form transistor structure 20. After forming the aforementioned gate structure 28 and source / drain structure 29, continue with a series of back-end processes (e.g., fabrication of metal interconnect structure 220) to complete as follows. Figure 2 E(1) and Figure 2 E(2) shows the fabrication of transistor structure 20.

[0111] Example 2

[0112] Figure 4 This is a flowchart illustrating another method for forming a transistor structure 40 according to another embodiment of the present invention. The method for forming the transistor structure 40 includes the following steps:

[0113] Step S41: Using patterned pad silicon nitride layer and patterned pad silicon oxide layer as etching mask, form at least one fin structure.

[0114] Step S42: Form a shallow trench isolation region in the semiconductor substrate to define at least one active island region.

[0115] Step S43: Form a channel layer independent of the semiconductor substrate and cover the semiconductor surface.

[0116] Step S431: Form the side portion of the channel layer outside the sidewall of the active island area.

[0117] Step S432: Form a gap wall on the side of the channel layer.

[0118] Step S433: Remove the patterned pad silicon nitride layer and the patterned pad silicon oxide layer to expose the semiconductor surface of the active island region.

[0119] Step S434: Form the top of the channel layer on the top surface of the active island area.

[0120] Step S435: Remove the gap wall from the side of the channel layer.

[0121] Step S44: Form a gate dielectric layer on the active island region.

[0122] Step S45: Form the gate structure and the source / drain structure.

[0123] Step S46: Perform back-end processes to form the transistor structure.

[0124] Because, apart from the process steps for forming the channel layer 406, the method for forming the transistor structure 40 is the same as the method for forming the transistor structure 20 (e.g., ...). Figures 2 to 2E(2) (As shown) Similar to the steps S41 to S42 in forming transistor structure 40, and the steps S21 to S22 in forming transistor structure 20 are the same, therefore the detailed process steps and materials used will not be described here. The method for forming transistor structure 40 is described starting from step S43.

[0125] Referring to step S43: A channel layer 406, independent of the semiconductor substrate 200, is formed to cover the semiconductor surface. An effective channel region (i.e., the top 406a of the channel layer 406) is formed above the top surface of the fin structure 201, and multiple other effective channel regions (i.e., the side portions 406b of the channel layer 406) are formed outside the four sidewalls of the fin structure 201 (the silicon sidewalls 203v of the active island region 203). This provides greater and more diverse freedom in the design of the device's critical voltage and / or the control of device characteristics. The formation of the channel layer 406 may include the following sub-steps S431 to S435.

[0126] Referring to step S431: a side portion 406b of a channel layer 406 is formed on the outside of the sidewall of the active island area 203. Figure 4 A(1) shows a top view of the structure after the side portion 406b of the channel layer 406 is formed on the outer side of the sidewall of the active island region 203. Figure 4 A(2) is along Figure 4 The structural cross-section shown by tangent C41 in A(1) is as follows. Since this step is performed without removing the pad silicon nitride layer 204 and the pad silicon oxide layer 205, only the four silicon surfaces (silicon sidewalls 203v) of the active island region 203 are exposed, and the top surface 203t of the fin structure 201 is not exposed. An additional silicon layer with a pre-defined channel doping concentration is formed using selective epitaxial growth technology to form the effective channel region (also referred to as the sidewall 406b of the channel layer 406). It should be noted that the effective channel region is formed only on the four sidewalls of the active island region 203.

[0127] Referring to step S432: a gap wall is formed on the side portion 406b of the channel layer 406. Figure 4 B(1) is a top view showing the structure after a spacer wall is formed on the side portion 406b of the channel layer 406. Figure 4 B(2) is along Figure 4 The structural cross-section shown by tangent C42 of A(1) is then grown over the effective channel region (also known as the side portion 406b of the channel layer 406), and then a silicon nitride spacer 422 is defined using a spacer formation technique to cover the four sidewalls that already have the effective channel region.

[0128] Referring to step S433: Remove the patterned pad silicon nitride layer 204 and the patterned pad silicon oxide layer 205 to expose the semiconductor surface of the active island region 203. Figure 4 C(1) is a top view showing the structure after the patterned pad silicon nitride layer 204 and the patterned pad silicon oxide layer 205 have been removed. Figure 4 C(2) is along Figure 4 The structural cross-section shown by tangent C43 of C(1) is then removed using anisotropic etching, thereby exposing the original silicon surface (OSS) above the top surface 203t of the active island region 203, while the effective channel regions above the four sidewalls of the active island region 203 are well protected.

[0129] Referring to step S434: the top 406a of the channel layer 406 is formed on the top surface 203t of the active island area 203. Figure 4 D(1) is a top view showing the structure after the top 406a of the channel layer 406 is formed on the top surface 203t of the active island region 203. Figure 4 D(2) is along Figure 4 The structural cross-section shown is tangent C44 of D(1). Selective epitaxial growth techniques are used to form additional silicon layers with pre-defined channel doping concentrations or to form heterogeneous effective channel regions (such as...). Figure 3A and Figure 3B (As shown) serves as the top 406a of the channel layer 406. It is noteworthy that the effective channel region (the top 406a of the channel layer 406) is formed only on the top surface 203t of the active island region 203, and not on the four sidewalls 203v of the active island region 203. In this embodiment, the material constituting the top 406a of the channel layer 406 is doped silicon-germanium. In another embodiment, the top 406a of the channel layer 406 is optional and can be omitted, with the effective channel region located on the sidewalls of the active island region 203 instead.

[0130] Refer to step S435: Remove the gap wall from the side portion 406b of the channel layer 406. Figure 4 E(1) is a top view showing the structure after the spacer wall has been removed from the side portion 406b of the channel layer 406. Figure 4 E(2) is along Figure 4 The structural cross-section shown by tangent C45 of D(1) is illustrated. Anisotropic etching is used to remove the silicon nitride spacer wall 422 and the thin thermal silicon oxide layer 421 located below the silicon nitride spacer wall 422. These two are located on the four sidewalls 203v above the active island region 203 (and above the side portion 406b of the channel layer 406).

[0131] Subsequently, a gate dielectric layer 207 is formed on the active island region 203 (see step S44); then, a gate structure 28 and a source / drain structure 29 are formed (see step S45); and a series of back-end processes are performed (see step S46) to complete the process as follows. Figure 4 F(1) and Figure 4 The fabrication of transistor structure 40 shown in F(2) can be implemented (along...). Figure 4 (The cross-sectional view taken by cutting line C46 as shown in F(1)). Because steps S44 to S46 are related to... Figure 2 Steps S425 to S27 are the same, so the detailed process steps and materials used will not be described again here.

[0132] Example 3

[0133] Figure 5 This invention, according to yet another embodiment, illustrates a flowchart of another method for forming a transistor structure 50. The method for forming the transistor structure 50 includes the following steps:

[0134] Step S51: Using patterned pad silicon nitride layer and patterned pad silicon oxide layer as etching mask, form at least one fin structure.

[0135] Step S52: Form a shallow trench isolation region in the semiconductor substrate to define at least one active island region.

[0136] Step S53: Form a channel layer independent of the semiconductor substrate and cover the semiconductor surface.

[0137] Step S531: Form a channel layer on the sidewall of the active island area.

[0138] Step S532: Form a spacer wall on the channel layer.

[0139] Step S533: Remove the patterned pad silicon nitride layer and the patterned pad silicon oxide layer to expose the semiconductor surface of the active island region.

[0140] Step S534: Remove a portion of the active island region to form a recess on the semiconductor surface, and fill the recess with insulating material.

[0141] Step S535: Remove the gap wall from the side of the channel layer.

[0142] Step S54: Form a gate dielectric layer on the active island region.

[0143] Step S55: Form the gate structure and the source / drain structure.

[0144] Step S56: Perform back-end processes to form the transistor structure.

[0145] Because, apart from the process steps for forming the channel layer 506, the method for forming the transistor structure 50 is the same as the method for forming the transistor structure 40 (e.g., ...). Figures 4 to 4F(2) (As shown) Similar to the steps S51 to S533 for forming transistor structure 50. Furthermore, steps S41 to S433 for forming transistor structure 40 are identical; therefore, detailed process steps and materials used will not be elaborated here. The method for forming transistor structure 50 is described starting from step S534.

[0146] Referring to step S534: a portion of the active island region 203 is removed to form a recess 523 on the semiconductor surface, and an insulating material 522 is filled into the recess 523. Figure 5 A is a top view showing the structure after the recess 523 is formed on the semiconductor surface. Figure 5 B is along Figure 5 The structural cross-section shown by tangent C51 of A is illustrated. A portion of the original silicon surface (OSS) (top surface 203t of the active island region 203) exposed below a specific height is removed using selective etching to form a recess 523. Then, an insulating material 522, such as thick silicon oxide, is formed using selective epitaxial growth to fill the exposed hollow portion of the silicon recess 523, completely isolating the two effective channel regions (channel layers 506) located on the two sidewalls 203v of the active island region 203. This method does not use a three-gate structure to avoid the problem of uneven conductivity at the two top corners due to the sharp angle at the top.

[0147] Subsequently, the spacer wall is removed from the side portion of the channel layer 506 (see step S535); a gate dielectric layer 207 is formed on the active island region 203 (see step S54); then, the gate structure 28 and the source / drain structure 29 are formed (see step S55); followed by a series of back-end processes (see step S56) to complete the process as described above. Figure 5B(1) and 5B(2)The fabrication process of the transistor structure 50 shown is as follows. Because steps S535 to S56 are... Figure 4 The steps S435 to S46 described herein are the same, so their detailed process steps and the materials used will not be described in detail here.

[0148] A key feature of these embodiments is that by using selective epitaxial growth techniques with doped silicon or other doped heteromaterials, additional layers (e.g., channel layers 206, 306, 406, and 506) with the desired doping concentration are constructed as effective channel layers for the actual channels of transistors, which can enhance channel performance and eliminate the drawbacks of forming channel regions using conventional ion implantation methods.

[0149] Figure 6 The diagrams show the doping concentration distributions of the doped channel regions formed using conventional methods (ion implantation and thermal processes) and the effective channel regions formed using the in-situ doping growth mechanism disclosed in the aforementioned embodiments. The p-type channel dopant (boron) of the NMOS formed using conventional methods exhibits a Poisson distribution 601, with the tail of the distribution located within the silicon substrate. This may result in the critical voltage of the NMOS formed using conventional methods being more difficult to control than that of the transistor structure of Embodiment 1 described herein. The transistor structure of Embodiment 1 has a doping concentration distribution 602 that changes abruptly from the effective channel region (around channel layer 206) to the p-type substrate 200. From these two different doping concentration distributions, it can be seen that Embodiment 1, by modulating the gate voltage, can achieve a better characteristic in the effective channel region, from the non-conductive region to the conductive region between the source and drain regions, compared to conventional diffused channel dopant, providing a better channel. In one embodiment, the doping concentration of the effective channel region can be between 1 × 10⁻⁶. 16 Up to 9×10 18 Between these two states, when no voltage is applied to the gate of the transistor, the effective channel region becomes the depletion region, while when an operating voltage is applied to the gate of the transistor, the effective channel region becomes the inversion region.

[0150] Please refer to this again. Figure 2 E(3) shows a cross-section of this novel fin field-effect transistor structure (transistor structure 200) along the Y direction. This structure uses an effective channel region (around channel layer 206) as a channel connecting the source and drain regions, thus avoiding the need for lightly doped drains (first lightly doped drain region 218b and second lightly doped drain region) and n+ source / drain regions (source / drain structure 29) formed using ion implantation. In contrast, the cross-section of the n+ source / drain region of a conventionally formed fin field-effect transistor structure 70 (see...) Figure 7The channel doping concentration distribution 706 is located inside the semiconductor substrate 700, which not only makes the critical voltage more difficult to control, but also results in a thinner effective area of ​​the substrate 700 in the fin structure 701, further reducing the controllability of the active performance of the transistor 70.

[0151] In the aforementioned embodiments, the effective channel region (ECR) acts like a channel layer 206 (306, 406, or 506) beneath the gate structure 28. When a suitable potential is applied to the gate of transistor 20 (40 or 50), a conduction reversal is induced within the effective channel region or channel layer (i.e., the number of minority carriers accumulated within the channel layer becomes large enough to conduct current), electrically connecting the drain and source terminals together through the effective channel region or channel layer. Therefore, the effective channel region or channel layer can be a selectively conductive layer. Furthermore, with the help of the effective channel region, complete depletion (depletion) of the original fin structure can be prevented.

[0152] It is worth noting that the aforementioned effective channel region can be applied not only to fin-type transistors but also to other transistors, such as planar transistors (in this embodiment, the effective channel region can be formed on the original silicon surface) or transistors with a recessed gate structure deposited in a U-shaped recess (in this embodiment, the effective channel region can be formed along the surface of the U-shaped recess). The key feature is the additional formation of an effective channel region (or heterogeneous effective channel region) covering the original surface of the substrate, or covering any surface with a predetermined shape that can be formed by etching the substrate. Embodiments of the present invention can utilize the effective channel region as the primary conductive channel to connect the source and drain, instead of using channels formed within the silicon of the transistor using conventional methods.

[0153] This invention pioneers a technique that uses a unique material as a three-dimensional conductive channel layer to achieve a more controllable critical voltage for field-effect transistors. Furthermore, by minimizing the depletion of the silicon fins and instead ensuring they have a neutral bulk connected to the substrate voltage, the lifetime of the fin field-effect transistor is extended by maintaining a larger fin width and a lower height. Simultaneously, increasing the width of the fins and the source / drain does not require a drastic reduction in fin height. The use of ion implantation techniques to create effective channel regions within the fins can be completely avoided, thus eliminating the need for high-temperature thermal annealing. High-temperature thermal annealing is not the most necessary process for continuously miniaturized devices.

[0154] In summary, using the embodiments described above, an effective channel region is formed outwardly on the fin structure. Combined with the use of laterally grown lightly doped drains and heavily doped source / drains, the use of ion implantation techniques to drive the dopants of the effective channel region into the fins is completely avoided. This eliminates the need for thermal annealing processes to repair and eliminate crystal damage. This technique, first proposed in this invention, is a novel method for manufacturing high-quality, low-leakage, and high-performance fin field-effect transistors or tri-gate transistors. The features and advantages of the embodiments of this invention are summarized as follows:

[0155] 1. For three-dimensional transistors such as fin field-effect transistors or tri-gate transistors, an effective channel region can be created outside the fin transistor body region, located below the gate and gate dielectric layer, to control the on or off state.

[0156] 2. The effective channel layer can be composed of pre-defined doped silicon materials or non-silicon materials;

[0157] 3. The effective channel area located at the top of the fin can be fabricated separately from the effective channel areas located on the outer sidewalls of the fin;

[0158] 4. Effective channel regions can be generated by various chemical vapor deposition growth mechanisms. These multiple chemical vapor deposition growth mechanisms can be, for example, a selective epitaxial growth technique for forming a pre-doped silicon layer, or an atomic layer deposition process for using various materials to form suitable channel structures;

[0159] 5. It does not require the use of ion implantation technology to form channel regions in the fin surface, thus eliminating the need for a thermal annealing process to activate the implanted ions.

[0160] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A transistor structure, characterized in that, The transistor structure includes: A semiconductor substrate, including a semiconductor surface and a fin structure; A shallow groove isolation zone surrounds the fin structure; A channel layer, independent of the semiconductor substrate, covers the fin structure; A gate structure is used to cover the channel layer; A first conductive region includes a lightly doped drain (LDD) coupled to the channel layer and extending outward from one sidewall of the semiconductor substrate; The channel layer includes a top and a side edge; the top covers a top surface of the fin structure, and the side edge covers a first sidewall and a second sidewall of the fin structure, and the top and the side edge are not formed simultaneously; and A local isolation region is located in a semiconductor substrate for isolating the bottom of the first conductive region from the semiconductor substrate; the sidewall of the semiconductor substrate is located between the local isolation region and the gate structure, and the lightly doped drain region extends from the sidewall toward the shallow trench isolation region.

2. The transistor structure according to claim 1, characterized in that, The material constituting the top is the same as that constituting the side.

3. The transistor structure according to claim 2, characterized in that, The material constituting the top or the side portion includes doped silicon (Si) or doped silicon-germanium (SiGe).

4. The transistor structure according to claim 2, characterized in that, The material constituting the top or side portion includes a semiconductor material; the semiconductor material can cause a channel inversion by a potential applied to the gate structure.

5. The transistor structure according to claim 2, characterized in that, The material constituting the top or side portion is formed by a selective epitaxial growth (SEG) process, an atomic level deposition (ALD) process, a molecular beam epitaxy (MBE) process, or a metal-organic chemical vapor deposition (MOCVD) process.

6. The transistor structure according to claim 1, characterized in that, The material that makes up the top is different from the material that makes up the side.

7. The transistor structure according to claim 1, characterized in that, The gate structure includes: A gate dielectric layer is located above the channel layer; and A gate conductive layer is located above the gate dielectric layer.

8. The transistor structure according to claim 1, characterized in that, The transistor structure further includes: A trench is provided to accommodate the first conductive region, wherein, The first conductive region abuts against a first surface of the channel layer and a first surface of the fin structure; and The first surface of the channel layer and the first surface of the fin structure both face the trench.

9. The transistor structure according to claim 8, characterized in that, The lightly doped drain region abuts against the first surface of the channel layer and the first surface of the fin structure.

10. The transistor structure according to claim 9, characterized in that, The first conductive region further includes a heavily doped region located within the trench and abutting the outermost edge of the lightly doped drain region.

11. The transistor structure according to claim 10, characterized in that, The first conductive region further includes a metal-containing region located in the trench and adjacent to the heavily doped region.

12. The transistor structure according to claim 8, characterized in that, The local isolation area is located in the trench and below the first conductive area.

13. The transistor structure according to claim 12, characterized in that, This localized isolation zone includes: A silicon oxide layer covers one side wall and one bottom wall of the trench; A partially insulating plug is located in the trench and covers a portion of the silicon oxide layer, which covers the bottom wall of the trench.

14. A transistor structure, characterized in that, The transistor structure includes: A semiconductor substrate, including a semiconductor surface and a fin structure; A channel layer, independent of the semiconductor substrate, covers the fin structure; A gate structure is used to cover the channel layer; A first conductive region is coupled to the channel layer; The channel layer covers a first sidewall and a second sidewall of the fin structure, but does not cover a top surface of the fin structure; and A local isolation region is located in the semiconductor substrate to isolate the first conductive region from the semiconductor substrate; and an interface between the channel layer and the first conductive region is substantially aligned with one edge of the gate structure.

15. The transistor structure according to claim 14, characterized in that, The transistor structure further includes: A trench is provided to accommodate the first conductive region, wherein, The first conductive region is independent of the semiconductor substrate and abuts against a first surface of the channel layer and the first sidewall of the fin structure; The first conductive region includes a lightly doped drain region that is not formed using an ion implantation process.

16. The transistor structure according to claim 15, characterized in that, The lightly doped drain region is formed by a selective epitaxial growth process or an atomic layer deposition process, and the lightly doped drain region is in contact with the first surface of the channel layer and the first surface of the fin structure.

17. The transistor structure according to claim 15, characterized in that, The first conductive region further includes a heavily doped region located within the trench and adjacent to the lightly doped drain region.

18. The transistor structure according to claim 17, characterized in that, The first conductive region has a doping concentration profile that extends laterally from the lightly doped drain region to the heavily doped region, and the doping concentration profile is controllable.

19. The transistor structure according to claim 15, characterized in that, The interface is located between the lightly doped drain region and the first surface of the channel layer.

20. The transistor structure according to claim 15, characterized in that, The local isolation zone is located within the trench, and includes: A silicon oxide layer covers one sidewall and one bottomwall of the trench; and A partially insulating plug is located in the trench and surrounded by the silicon oxide layer; and the first conductive region is surrounded by the silicon oxide layer and the partially insulating plug.

21. The transistor structure according to claim 15, characterized in that, This channel layer prevents the fin structure from being completely depleted.

22. A transistor structure, characterized in that, The transistor structure includes: A semiconductor substrate, including a semiconductor surface and a fin structure; A channel layer, independent of the semiconductor substrate, covers the fin structure; A gate structure is used to cover the channel layer; A first conductive region, coupled to the channel layer; and A local isolation region, located within the semiconductor substrate, is used to isolate the first conductive region from the semiconductor substrate therein. The local isolation region includes: An L-shaped isolation region is located in the semiconductor substrate; and An insulating block is located above the L-shaped isolation area, wherein the L-shaped isolation area and the insulating block are made of different materials, and the top of the L-shaped isolation area is aligned with the top of the insulating block.

23. The transistor structure according to claim 22, characterized in that, The doping concentration of the channel layer is between 1×10⁻⁶. 16 Up to 9×10 18 between.

24. The transistor structure according to claim 22, characterized in that, The channel layer includes a top and a side edge; the top covers a top surface of the fin structure, and the side edge covers a first sidewall and a second sidewall of the fin structure.

25. The transistor structure according to claim 22, characterized in that, The channel layer includes a side portion that covers a first sidewall and a second sidewall of the fin structure.

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