Method of manufacturing a semiconductor structure, semiconductor structure and memory

Abstract

The method comprises the following steps: providing a substrate; forming a plurality of first electrode structures and a plurality of bit lines in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and the bit lines are arranged at intervals along a second direction, and the plurality of first electrode structures are arranged in an array; forming an MTJ structure above the first electrode structures; forming an insulating layer above the substrate, wherein the insulating layer covers the substrate and the MTJ structure; forming a plurality of electrode trenches in the insulating layer, wherein the electrode trenches expose the top surface of the MTJ structure and the top surface of the bit lines; and forming a plurality of second electrode structures in the plurality of electrode trenches. The method can reduce the alignment accuracy requirement when preparing the electrode, reduce the process difficulty, and improve the bit line density.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] Magneto-resistive random access memory (MRAM) is a non-volatile memory that offers faster storage speeds and better durability compared to current non-volatile memories (such as flash memory); and lower power consumption compared to current volatile memories (such as dynamic random access memory and static random access memory).

[0003] MRAM stores data using magnetic tunnel junctions (MTJs). Unlike the bottom bit line (BL) design of Dynamic Random Access Memory (DRAM), the bit lines of the MTJs in MRAM are located at the top. This makes it easy for the top electrodes of the MTJ array to misalign in high-density MRAM arrays. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory.

[0005] In a first aspect, embodiments of this disclosure provide a method for fabricating a semiconductor structure, comprising:

[0006] Provide substrate;

[0007] A plurality of first electrode structures and a plurality of bit lines are formed in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and the bit lines are arranged at intervals along a second direction, and the plurality of first electrode structures are arranged in an array.

[0008] An MTJ structure is formed above the first electrode structure;

[0009] An insulating layer is formed over the substrate, and the insulating layer covers the substrate and the MTJ structure;

[0010] Multiple electrode trenches are formed in the insulating layer, and the electrode trenches expose the top surface of the MTJ structure and the top surface of the bit line;

[0011] Multiple second electrode structures are formed in the multiple electrode trenches.

[0012] In some embodiments, forming a plurality of first electrode structures and a plurality of bit lines in the substrate includes:

[0013] A first mask layer is formed above the substrate, the first mask layer exposing a plurality of first electrode regions and a plurality of bit line regions in the substrate, wherein the plurality of bit line regions all extend along the first direction, the first electrode regions and the bit line regions are arranged at intervals along the second direction, and the plurality of first electrode regions are arranged in an array.

[0014] Using the first mask layer as a mask, the substrate is patterned to form a plurality of first electrode trenches in the substrate corresponding to the plurality of first electrode regions, and a plurality of bit line trenches in the substrate corresponding to the plurality of bit line regions.

[0015] The plurality of first electrode structures are formed in the plurality of first electrode trenches, and the plurality of bit lines are formed in the plurality of bit line trenches.

[0016] In some embodiments, forming an MTJ structure above the first electrode structure includes:

[0017] An MTJ layer is formed above the substrate;

[0018] A cover layer is formed above the MTJ layer;

[0019] The cover layer and the MTJ layer are patterned to form a plurality of MTJ pillars; wherein each MTJ pillar is formed above each of the first electrode structures.

[0020] A sidewall protective layer is formed on the side of the MTJ column;

[0021] The MTJ structure is composed of the MTJ column and the sidewall protective layer.

[0022] In some embodiments, the MTJ layer includes a pinned layer, a barrier layer, and a free layer, and forming the MTJ layer over the substrate includes:

[0023] A pinning layer is formed above the substrate;

[0024] A barrier layer is formed above the pinned layer;

[0025] A free layer is formed above the barrier layer;

[0026] The formation of a cover layer above the MTJ layer includes:

[0027] The covering layer is formed above the free layer.

[0028] In some embodiments, the patterning of the overlay layer and the MTJ layer to form a plurality of MTJ pillars includes:

[0029] An MTJ mask layer is formed above the cover layer, the MTJ mask layer comprising an array of MTJ patterns;

[0030] Using the MTJ mask layer as a mask, the MTJ pattern is transferred to the cover layer and the MTJ layer to form the plurality of MTJ pillars.

[0031] In some embodiments, forming a sidewall protective layer on the side of the MTJ column includes:

[0032] An initial sidewall protective layer is formed on the surface of the substrate and the MTJ structure;

[0033] The initial sidewall protective layer located on the substrate surface and the top surface of the MTJ structure is removed, while the initial sidewall protective layer located on the side of the MTJ structure is retained to form the sidewall protective layer.

[0034] In some embodiments, forming a plurality of electrode trenches in the insulating layer includes:

[0035] A plurality of first trenches are formed in the insulating layer, the first trenches exposing the top surfaces of the cover layer and the sidewall protective layer;

[0036] A plurality of second trenches are formed in the insulating layer, the second trenches exposing the top surface of the bit line;

[0037] The first trench and the second trench are connected to form the electrode trench, and the second trench is not connected to the MTJ structure.

[0038] In some embodiments, forming a plurality of second trenches in the insulating layer includes:

[0039] A mask structure is formed in the first trench;

[0040] Using the mask structure as the MTJ protection structure, the insulating layer located above the bit line and connected to the mask structure is removed to form the plurality of second trenches;

[0041] Remove the mask structure.

[0042] In some embodiments, a plurality of transistors are formed in the substrate, and the plurality of transistors correspond to the plurality of first electrode structures, wherein,

[0043] The first electrode structure is connected to the source or drain of the corresponding transistor.

[0044] Secondly, embodiments of this disclosure provide a semiconductor structure, including:

[0045] Substrate;

[0046] A plurality of first electrode structures and a plurality of bit lines are formed in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and the bit lines are arranged at intervals along a second direction, and the plurality of first electrode structures are arranged in an array.

[0047] An MTJ structure formed above the first electrode structure;

[0048] An insulating layer formed above the substrate;

[0049] Multiple electrode trenches, the multiple electrode trenches exposing the top surface of the MTJ structure and the top surface of the bit line;

[0050] Multiple second electrode structures formed in the plurality of electrode trenches.

[0051] In some embodiments, the MTJ structure includes:

[0052] MTJ pillars formed above the first electrode structure;

[0053] A covering layer formed above the MTJ pillar;

[0054] A sidewall protective layer formed on the side of the MTJ column;

[0055] The MTJ structure is composed of the MTJ column and the sidewall protective layer.

[0056] In some embodiments, the MTJ column includes:

[0057] A pinning layer formed above the first electrode structure;

[0058] A barrier layer formed above the pinned layer;

[0059] A free layer formed above the barrier layer;

[0060] A covering layer formed above the free layer.

[0061] In some embodiments, the semiconductor structure further includes a first trench and a second trench; wherein,

[0062] The first trench exposes the top surface of the cover layer and the sidewall protective layer;

[0063] The second trench exposes the top surface of the bit line;

[0064] The first trench and the second trench are connected to form the electrode trench, and the second trench is not connected to the MTJ structure.

[0065] In some embodiments, a plurality of transistors are formed in the substrate, and the plurality of transistors correspond to the plurality of first electrode structures, wherein,

[0066] The first electrode structure is connected to the source or drain of the corresponding transistor.

[0067] Thirdly, embodiments of this disclosure provide a memory including a semiconductor structure as described in any of the second aspects.

[0068] In some embodiments, the memory includes MRAM.

[0069] This disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory. The method includes: providing a substrate; forming a plurality of first electrode structures and a plurality of bit lines in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and bit lines are spaced apart along a second direction, and the plurality of first electrode structures are arranged in an array; forming an MTJ structure above the first electrode structures; forming an insulating layer above the substrate, and the insulating layer covers the substrate and the MTJ structure; forming a plurality of electrode trenches in the insulating layer, the electrode trenches exposing the top surface of the MTJ structure and the top surface of the bit lines; and forming a plurality of second electrode structures in the plurality of electrode trenches. In this way, on the one hand, since the bit line structure is located at the bottom of the semiconductor structure, when forming the second electrode structure, only the insulating layer needs to be partially removed to obtain the electrode trenches exposing the MTJ structure and bit lines, and then the second electrode structure is formed in the electrode trenches, reducing the alignment accuracy requirements when fabricating the second electrode structure, thereby reducing the process difficulty; on the other hand, by fabricating the first electrode structure and the bit lines in the same layer of the substrate, a higher storage density can be ensured by appropriately reducing the linewidth of the bit lines. Attached Figure Description

[0070] Figure 1 This is a schematic diagram of the connection of storage cells in an MRAM;

[0071] Figure 2 This is a schematic diagram of the connection of the top electrode of an MRAM.

[0072] Figure 3 A schematic diagram showing the connection of the top electrode of another type of MRAM;

[0073] Figure 4 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0074] Figure 5This is a schematic diagram of the structure of a substrate provided in an embodiment of the present disclosure;

[0075] Figure 6 This is a schematic diagram of the structure obtained after forming the first mask layer according to an embodiment of the present disclosure;

[0076] Figure 7 This is a schematic diagram of the structure obtained after forming a bit line trench and a first electrode trench, provided by an embodiment of the present disclosure;

[0077] Figure 8 This is a schematic diagram of the structure obtained after forming the bit line and the first electrode structure according to an embodiment of the present disclosure;

[0078] Figure 9 This is a schematic diagram of the structure obtained after forming a bit line mask layer according to an embodiment of the present disclosure;

[0079] Figure 10 This is a schematic diagram of the structure obtained after forming a bit line trench according to an embodiment of the present disclosure;

[0080] Figure 11 This is a schematic diagram of the structure obtained after forming a bit line, provided by an embodiment of the present disclosure;

[0081] Figure 12 This is a schematic diagram of the structure obtained after forming an electrode mask layer according to an embodiment of the present disclosure;

[0082] Figure 13 This is a schematic diagram of the structure obtained after forming the first electrode trench according to an embodiment of the present disclosure;

[0083] Figure 14 This is a schematic diagram of the structure obtained after forming an MTJ layer and a capping layer, as provided in an embodiment of the present disclosure;

[0084] Figure 15 This is a schematic diagram of the structure obtained after forming an MTJ mask layer according to an embodiment of the present disclosure;

[0085] Figure 16 This is a schematic diagram of the structure obtained after forming an MTJ column, as provided in an embodiment of the present disclosure;

[0086] Figure 17 This is a schematic diagram of the structure obtained after forming the third mask layer according to an embodiment of the present disclosure;

[0087] Figure 18 This is a schematic diagram of a structure obtained after transferring a first pattern, as provided in an embodiment of the present disclosure;

[0088] Figure 19 This is a schematic diagram of the structure obtained after forming the first photoresist layer, provided by an embodiment of the present disclosure;

[0089] Figure 20 A cross-sectional schematic diagram of the structure obtained after forming the first photoresist layer is provided in an embodiment of this disclosure;

[0090] Figure 21 This is a schematic diagram of the structure obtained after forming a sidewall protective layer according to an embodiment of the present disclosure;

[0091] Figure 22 This is a schematic diagram of the structure obtained after forming an initial sidewall protective layer, provided by an embodiment of the present disclosure;

[0092] Figure 23 This is a schematic diagram of a structure obtained after forming an insulating layer, provided by an embodiment of the present disclosure;

[0093] Figure 24 This is a schematic diagram of the structure obtained after forming the first trench, provided by an embodiment of the present disclosure;

[0094] Figure 25 This is a schematic diagram of another structure obtained after forming the first trench, provided by an embodiment of the present disclosure;

[0095] Figure 26 This is a schematic diagram of the structure obtained after forming a second photoresist layer, provided by an embodiment of the present disclosure;

[0096] Figure 27 This is a schematic diagram of a structure obtained after forming a mask structure according to an embodiment of the present disclosure;

[0097] Figure 28 This is a schematic diagram of the structure obtained after forming the second trench according to an embodiment of the present disclosure;

[0098] Figure 29 This is a schematic diagram of another structure obtained after forming the second trench according to an embodiment of the present disclosure;

[0099] Figure 30 This is a schematic diagram of the structure obtained after forming a third photoresist layer, provided by an embodiment of the present disclosure;

[0100] Figure 31 This is a schematic diagram of the structure obtained after removing the mask structure according to an embodiment of the present disclosure;

[0101] Figure 32 This is a schematic diagram of another structure obtained after removing the mask structure according to an embodiment of the present disclosure;

[0102] Figure 33 This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of the present disclosure;

[0103] Figure 34 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0104] Figure 35 This is a schematic diagram of the composition of another semiconductor structure provided in an embodiment of the present disclosure;

[0105] Figure 36 This is a comparative structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0106] Figure 37 This is a schematic diagram comparing the connections of a semiconductor structure according to an embodiment of the present disclosure;

[0107] Figure 38 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0108] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0109] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0110] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0111] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0112] Figure 1 This is a schematic diagram of the connection of storage cells in an MRAM, such as... Figure 1As shown, in MRAM, a magnetic tunnel junction (MTJ) 204 serves as a data storage unit. The MTJ 204 may include a pinned layer 2041 (Pinned Layer, also known as a "fixed layer"), a barrier layer 2042 (also known as a "tunnel layer" or "tunneling barrier layer"), and a free layer 2043 (F). In the MTJ 204, the barrier layer 2042 is located between the pinned layer 2041 and the free layer 2043. The free layer 2043 is connected to the bit line 201. The pinned layer 2041 is connected to the drain of the transistor 203. The word line (WL) 202 is connected to the gate of the transistor 203, and the source line (SL) 205 is connected to the source of the transistor 203.

[0113] Figure 2 and Figure 3 This diagram illustrates the connection of two self-aligned MRAMs based on hexagonal array structures, each based on a different process flow. Figure 2 This is a schematic diagram of the connection of the top electrode of an MRAM, wherein (a) shows the connection between the top electrode (TEC) 207 and the MTJ in a normally aligned state, and (b) shows the connection between the top electrode 207 and the MTJ in a misaligned state. Figure 2 As shown in (a) or (b), from bottom to top, the structure sequentially includes a bottom electrode (BE) 206, an MTJ, and a top electrode 207. The top electrode 207 can be connected to the MTJ via a contact plug (CT). The MTJ includes a pinning layer 2041, a barrier layer 2042, a free layer 2043, a capping layer 2044, and a sidewall protective layer 2045. Figure 3 As shown in (b), in a high-density MTJ array, the alignment of the top of the MTJ and the top electrode 207 is prone to misalignment, as shown in the dotted circle in (b). This may cause the top electrode 207 to come into direct contact with the free layer 2043 of the MTJ, which will have an adverse effect on the performance of the MRAM and may even lead to memory failure.

[0114] Figure 3 This is a schematic diagram of the connection of the top electrode of another MRAM, where (a) shows a schematic diagram of the top electrode 207, and (b) shows the connection method between the top electrode 207 and the MTJ, as shown. Figure 3 As shown in (a), in this structure, forming the top electrode 207 requires the fabrication of a relatively deep through-hole, the support layer 208 can be used as a support for the top electrode 207, and the metal layer 209 is connected to the top electrode 207. Figure 3As shown in (b), from bottom to top, the structure includes a bottom electrode 206, an MTJ, and a top electrode 207. The top electrode 207 can be connected to the MTJ via a contact plug. The MTJ includes a pinning layer 2041, a barrier layer 2042, a free layer 2043, a capping layer 2044, and a sidewall protection layer 2045. H represents the depth of the via that needs to be prepared when forming the top electrode 207. As shown in the figure, a very deep via needs to be made to connect the MTJ and the top electrode 207, while maintaining alignment. The process of opening the via is very difficult.

[0115] Based on this, the present disclosure provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate; forming a plurality of first electrode structures and a plurality of bit lines in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and bit lines are arranged at intervals along a second direction, and the plurality of first electrode structures are arranged in an array; forming an MTJ structure above the first electrode structures; forming an insulating layer above the substrate, and the insulating layer covering the substrate and the MTJ structure; forming a plurality of electrode trenches in the insulating layer, the electrode trenches exposing the top surface of the MTJ structure and the top surface of the bit lines; and forming a plurality of second electrode structures in the plurality of electrode trenches. Thus, on the one hand, since the bit line structure is located at the bottom of the semiconductor structure, when forming the second electrode structure, only the insulating layer portion needs to be removed to obtain the electrode trenches exposing the MTJ structure and the bit lines, and then the second electrode structure is formed in the electrode trenches, reducing the alignment accuracy requirements when fabricating the second electrode structure, thereby reducing the process difficulty; on the other hand, by fabricating the first electrode structure and the bit lines in the same layer of the substrate, the linewidth of the bit lines can be appropriately reduced, thereby ensuring a higher storage density.

[0116] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0117] In one embodiment of this disclosure, see [link to embodiment]. Figure 4 It illustrates a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this disclosure, such as... Figure 4 As shown, the method may include:

[0118] S1001, Provide substrate.

[0119] It should be noted that the method provided in this disclosure is applied to the fabrication of semiconductor structures, which can be used in memories such as MRAM. In fabricating the semiconductor structure, a substrate is first provided. Figure 5 This is a schematic diagram of the structure of a substrate 501 provided in an embodiment of this disclosure. Figure 5 In the diagram, (b) is a top view and (a) is a cross-sectional view in the AA' direction of (b).

[0120] The substrate 501 can be a silicon substrate or other suitable substrate materials such as silicon, germanium, or silicon-germanium compounds, such as doped or undoped single-crystal silicon substrates, polycrystalline silicon substrates, etc. The embodiments disclosed herein do not specifically limit this.

[0121] S1002, Multiple first electrode structures and multiple bit lines are formed in the substrate.

[0122] It should be noted that the substrate is processed to form multiple first electrode structures and multiple bit lines. The bit lines extend along a first direction, and the first electrode structures and bit lines are arranged at intervals along a second direction, with the multiple first electrode structures arranged in an array. In other words, several first electrode structures are arranged at intervals along both the first and second directions. Here, the first direction refers to the direction along which the first electrode structures are arranged. Figure 5 The direction perpendicular to AA' in the middle, and the second direction is perpendicular to... Figure 5 The direction parallel to AA' in the middle.

[0123] In some embodiments, a plurality of transistors are formed in the substrate, and the plurality of transistors correspond to a plurality of first electrode structures, wherein,

[0124] The first electrode structure is connected to the source or drain of the corresponding transistor.

[0125] It should be noted that, in the embodiments of this disclosure, a plurality of transistors are formed in the substrate, and there is a one-to-one correspondence between these plurality of transistors and a plurality of first electrode structures, with each first electrode structure connected to the source or drain of the corresponding transistor. Here, the plurality of transistors can be formed in the substrate after the substrate is provided, or they can be formed in the substrate during the provision of the substrate; no specific limitation is made in this regard. The types of transistors can include N-type metal-oxide-semiconductor field-effect transistors (NMOS transistors) or P-type metal-oxide-semiconductor field-effect transistors (PMOS transistors), etc.

[0126] Furthermore, multiple first electrode structures and multiple bit lines can be formed simultaneously. In some embodiments, forming multiple first electrode structures and multiple bit lines in a substrate may include:

[0127] A first mask layer is formed above a substrate, the first mask layer exposes a plurality of first electrode regions and a plurality of bit line regions in the substrate, wherein the plurality of bit line regions extend along a first direction, the first electrode regions and bit line regions are arranged at intervals along a second direction, and the plurality of first electrode regions are arranged in an array.

[0128] Using the first mask layer as a mask, the substrate is patterned to form multiple first electrode trenches in the substrate corresponding to multiple first electrode regions and multiple bit line trenches in the substrate corresponding to multiple bit line regions.

[0129] Multiple first electrode structures are formed in multiple first electrode trenches, and multiple bit lines are formed in multiple bit line trenches.

[0130] It should be noted that, Figure 6 To illustrate the structure obtained after forming the first mask layer 502, in Figure 6 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 6 As shown, a first mask layer 502 is formed above the substrate 501. The first mask layer 502 exposes multiple first electrode regions 503 and multiple bit line regions 504 in the substrate. That is, the portion of the substrate 501 not covered by the first mask layer 502 consists of multiple first electrode regions 503 and multiple bit line regions 504. Along the second direction, the first electrode regions 503 and bit line regions 504 are arranged at intervals, and the bit line regions 504 all extend along the first direction. The multiple first electrode regions 503 are arranged in an array, that is, several first electrode regions 503 are arranged at intervals along both the first and second directions. Among them, the first electrode regions 503 expose the positions subsequently used to form the first electrode structure, and the bit line regions 504 expose the positions subsequently used to form bit lines.

[0131] Using the first mask layer 502 as a mask, the substrate 501 is patterned, and the pattern of the first mask layer 502 is transferred to the substrate 501 to form multiple bit line trenches 506 and first electrode trenches 505 in the substrate 501, resulting in... Figure 7 The structure shown is in Figure 7 In the diagram, (b) is a top view and (a) is a cross-sectional view in the AA' direction of (b). To facilitate the showing of the positions of the multiple bit line trenches 506 and the first electrode trench 505, the positions of the bit line trenches 506 and the first electrode trench 505 are shown in (b) with a pattern without fill.

[0132] The patterning process can be performed by etching the substrate 501 (i.e., multiple first electrode regions 503 and multiple bit line regions 504) exposed by the first mask layer 502, removing a certain depth from the exposed substrate 501, thereby forming multiple first electrode trenches 505 and multiple bit line trenches 506 in the substrate 501. Figure 7As shown, a bit line trench 506 is formed at a position corresponding to the bit line region 504, and a first electrode trench 505 is formed at a position corresponding to the first electrode region 503. Here, the depth of the bit line trench 506 can be slightly deeper than the depth of the first electrode trench 505 to ensure that the bit line formed subsequently has a lower resistance.

[0133] A bit line is formed in the bit line trench 506, and a first electrode structure is formed in the first electrode trench 505. The bit line and the first electrode structure can be formed using the same material, such as titanium nitride or conductive materials like metals, or they can be formed using different materials; no specific limitation is made here.

[0134] When the bit lines and the first electrode structures are made of the same material, the same material can be deposited simultaneously in the first electrode trench 505 and the bit line trench 506, thereby forming multiple first electrode structures 507 and multiple bit lines 508 in the substrate 501, resulting in... Figure 8 The structure shown is in Figure 8 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 8 As shown, corresponding to the arrangement of the first electrode region 503 and the bit line region 504, multiple bit lines 508 extend along the first direction, and the first electrode structure 507 and the bit lines 508 are arranged at intervals along the second direction, with multiple first electrode structures 507 arranged in an array.

[0135] It should also be noted that the multiple first electrode structures and multiple bit line structures can also be formed separately. In some embodiments, forming multiple first electrode structures and multiple bit lines in the substrate may include:

[0136] A bit line mask layer is formed above the substrate, the bit line mask layer exposes multiple bit line regions in the substrate, the multiple bit line regions extend along a first direction and are spaced apart along a second direction;

[0137] Using a bit line mask layer as a mask, the substrate is patterned to form multiple bit line trenches in the substrate corresponding to multiple bit line regions.

[0138] Multiple bit lines are formed in multiple bit line trenches, and the bit line mask layer is removed;

[0139] An electrode mask layer is formed above the substrate and bit lines, the electrode mask layer exposes multiple first electrode regions in the substrate, and the multiple first electrode regions are arranged in an array;

[0140] Using the electrode mask layer as a mask, the substrate is patterned to form multiple first electrode trenches in the substrate corresponding to multiple first electrode regions.

[0141] Multiple first electrode structures are formed in multiple first electrode trenches, and the electrode mask layer is removed.

[0142] It should be noted that when forming the first electrode structure and the bit line respectively, the bit line can be formed first and then the first electrode structure, or the first electrode structure can be formed first and then the bit line. Here, we will describe the process by taking the example of forming the bit line first and then the first electrode structure.

[0143] Figure 9 This is a schematic diagram of the structure obtained after forming the bit line mask layer 509. Figure 9 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 9 As shown, a bit line mask layer 509 is formed above a substrate 501. The bit line mask layer 509 exposes a plurality of bit line regions 504. The plurality of bit line regions 504 extend along a first direction and are spaced apart along a second direction. The bit line regions 504 correspond to the positions subsequently used to form bit lines.

[0144] Using the bit line mask layer 509 as a mask, the substrate 501 is patterned to form multiple bit line trenches 506 in the substrate 501, resulting in... Figure 10 The structure shown is in Figure 10 In the diagram, (b) is a top view and (a) is a cross-sectional view along the AA' direction in (b). The patterning process can be performed by etching the substrate 501 (i.e., the bit line region 504) exposed by the bit line mask layer 509 to remove a certain depth from the exposed substrate 501, thereby forming multiple bit line trenches 506 in the substrate 501 corresponding to the bit line region 504.

[0145] Bit lines 508 are formed in bit line trenches 506, and bit line mask layers 509 are removed to obtain the following: Figure 11 The structure shown is in Figure 11 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). The bit line 508 can be formed by deposition. For example... Figure 11 As shown, multiple bit lines 508 extend along the first direction and are spaced apart along the second direction.

[0146] Next, the first electrode structure 507 is formed. First, an electrode mask layer 510 is formed above the substrate 501 and bit line 508, resulting in... Figure 12 The structure shown is in Figure 12 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 12As shown, the electrode mask layer 510 exposes multiple first electrode regions 503 in the substrate 501. These multiple first electrode regions 503 are arranged in an array, meaning they are spaced apart along a first direction and a second direction. It should be noted that the first electrode regions 503 and the aforementioned bit line regions 504 do not overlap. Furthermore, in the accompanying drawings of this embodiment, an example is provided where the angle between the first and second directions is 90 degrees. In practice, to improve the storage density of the semiconductor structure, the angle between the first and second directions can be set to 60 degrees, resulting in a hexagonal (or honeycomb) array arrangement of the multiple first electrode regions 503. Correspondingly, the subsequently formed MTJ structure also exhibits a hexagonal array arrangement, thereby increasing storage density and improving the storage performance of the semiconductor structure. The angle between the first and second directions can also be set to other angles depending on the actual process and requirements, and is not specifically limited thereto.

[0147] Using the electrode mask layer 510 as a mask, the substrate 501 is patterned to form a plurality of first electrode trenches 505 in the substrate 501, resulting in... Figure 13 The structure described above, in Figure 13 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). The patterning process can be achieved by etching the substrate 501 (i.e., the first electrode region 503) exposed by the electrode mask layer 510, removing a certain depth of the exposed substrate 501, thereby forming multiple first electrode trenches 505 in the substrate 501 corresponding to the multiple first electrode regions 503. The depth of the bit line trench 506 can be slightly deeper than the depth of the first electrode trench 505.

[0148] A first electrode structure 507 is formed in the first electrode trench 505, and the electrode mask layer 510 is removed to obtain the following: Figure 8 The structure shown is such that the first electrode structure 507 can be formed by deposition.

[0149] Furthermore, if the first electrode structure is formed first and then the bit line is formed, only the order of the above process needs to be adjusted. That is, first, an electrode mask layer 510 is formed, and the substrate 501 is patterned using the electrode mask layer 510 as a mask to form the first electrode trench 505. The first electrode structure 507 is formed in the first electrode trench 505, and the electrode mask layer 510 is removed. Then, a bit line mask layer 509 is formed, and the substrate 501 is patterned using the bit line mask layer 509 as a mask to form the bit line trench 506. The bit line 508 is formed in the bit line trench 506, and the bit line mask layer 509 is removed, finally obtaining the following... Figure 8 The structure shown.

[0150] It should also be noted that, in the embodiments disclosed herein, the materials of the first mask layer 502, the bit line mask layer 509 and the electrode mask layer 510 may include photoresist or other suitable single-layer or multi-layer mask materials, and the formation method may be deposition, and the removal method may be etching.

[0151] Thus, in this embodiment of the present disclosure, a first electrode structure and a bit line are first formed in the substrate. The first electrode structure can serve as the bottom electrode in the MRAM. By designing the first electrode structure and the bit line in the same layer, the linewidth of the bit line can be reduced and the density of the bit line can be increased.

[0152] S1003, An MTJ structure is formed above the first electrode structure.

[0153] It should be noted that, in the embodiments of this disclosure, when forming the MTJ structure, an MTJ structure is formed above each first electrode structure, that is, multiple MTJ structures are formed, and the number of MTJ structures corresponds to the number of first electrode structures.

[0154] In some embodiments, forming an MTJ structure above the first electrode structure may include:

[0155] An MTJ layer is formed above the substrate;

[0156] A capping layer is formed above the MTJ layer;

[0157] The capping layer and MTJ layer are patterned to form multiple MTJ pillars; each MTJ pillar is formed above each first electrode structure.

[0158] A sidewall protective layer is formed on the side of the MTJ column;

[0159] The MTJ structure consists of MTJ columns and sidewall protective layers.

[0160] It should be noted that when forming the MTJ structure, an MTJ layer and a capping layer are first formed on the substrate, and the MTJ layer and capping layer are patterned to form multiple MTJ pillars. Each MTJ pillar is formed on top of each first electrode structure, that is, one MTJ pillar and one first electrode structure are connected accordingly. Finally, a sidewall protective layer is formed on the side of the MTJ pillar. One MTJ pillar and the sidewall protective layer formed on its surface constitute an MTJ structure, thus obtaining multiple MTJ structures.

[0161] For an MTJ layer, in some embodiments, the MTJ layer includes a pinned layer, a barrier layer, and a free layer. The MTJ layer formed over the substrate may include:

[0162] A pinning layer is formed above the substrate;

[0163] A barrier layer is formed above the pinned layer;

[0164] A free layer is formed above the barrier layer;

[0165] A cover layer formed above the MTJ layer may include:

[0166] A covering layer forms above the free layer.

[0167] It should be noted that the MTJ layer can consist of a pinned layer, a barrier layer, and a free layer. When forming the pinned layer, the pinned layer, the barrier layer, and the free layer are formed sequentially on the substrate where the potential lines and the first electrode structure have already been formed. Correspondingly, the capping layer is formed on top of the free layer. Figure 14 This is a schematic diagram of the structure obtained after forming the MTJ layer 515 and the capping layer 514. Figure 14 In the diagram, (b) is a top view and (a) is a cross-sectional view in the AA' direction of (b).

[0168] like Figure 14 As shown, a pinned layer 511 is formed above a substrate 501 containing a first electrode structure 507 and a bit line 508, a barrier layer 512 is formed above the pinned layer 511, a free layer 513 is formed above the barrier layer 512, and a capping layer 514 is formed above the free layer 513. The pinned layer 511, the barrier layer 512, and the free layer 513 constitute an MTJ layer 515, and each layer can be formed by deposition.

[0169] The pinning layer 511 may be made of one or more of the following materials: cobalt (Co), nickel (Ni), iron (Fe), cobalt iron (CoFe), cobalt nickel (CoNi), nickel iron (NiFe), cobalt iron nickel (CoFeNi), cobalt boride (CoB), iron boride (FeB), cobalt iron boride (CoFeB), nickel iron boride (NiFeB), platinum (Pt), palladium (Pd), platinum palladium (PtPd), iridium (Ir), rhenium (Re), rhodium (Rh), boron (B), zirconium (Zr), vanadium (V), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), and hafnium (Hf). In addition, the pinning layer 511 is usually a multilayer film structure, and the type and thickness of each thin film need to be adjusted so that its magnetization direction is perpendicular to its interface. The material of the barrier layer 512 may include one or more of magnesium oxide (MgO), aluminum oxide (AlOx), magnesium aluminum oxide (MgAlOx), titanium oxide (TiOx), tantalum oxide (TaOx), gallium oxide (GaOx), and iron oxide (FeOx). Since the oxygen content of these oxides fluctuates during the actual process, x is used to represent the ratio of the number of oxygen atoms to the number of other atoms in a molecule. The material of the free layer 513 may include one or more of the following: Co, Fe, Ni, CoB, FeB, nickel boride (NiB), CoFe, NiFe, CoNi, CoFeNi, CoFeB, NiFeB, expanded cobalt nickel (CoNiB), expanded cobalt iron nickel (CoFeNiB), iron platinum (FePt), iron palladium (FePd), cobalt platinum (CoPt), cobalt palladium (CoPd), cobalt iron platinum (CoFePt), cobalt iron palladium (CoFePd), iron platinum palladium (FePtPd), cobalt platinum palladium (CoPtPd), and cobalt iron platinum palladium (CoFePtPd). The material of the capping layer 514 may include Ta, which can protect the MTJ layer from oxidation.

[0170] In some embodiments, patterning the cover layer and MTJ layer to form multiple MTJ pillars may include:

[0171] An MTJ mask layer is formed above the cover layer, the MTJ mask layer comprising an array of MTJ patterns;

[0172] Using the MTJ mask layer as a mask, the MTJ pattern is transferred to the capping layer and the MTJ layer to form multiple MTJ pillars.

[0173] It should be noted that when forming MTJ pillars, an MTJ mask layer can first be formed above the capping layer, resulting in a structure as shown below. Figure 15 As shown, in Figure 15 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 15As shown, the MTJ mask layer includes MTJ patterns 521 arranged in an array, and the positions of the MTJ patterns 521 correspond to the positions of the first electrode structure 507 to ensure that the MTJ pillars are connected to the first electrode structure 507 during pattern transfer to form MTJ pillars. Here, the cover layer 514 and MTJ layer 515 located below the MTJ patterns 521 are the parts that need to be retained to form MTJ pillars, while the cover layer 514 and MTJ layer 515 not located below the MTJ patterns 521 will be removed during the pattern transfer process.

[0174] Using the MTJ mask layer as a mask, pattern transfer is performed, transferring the MTJ pattern to the capping layer 514 and MTJ layer 515. The portions of the capping layer 514 and MTJ layer 515 not covered by the MTJ pattern 521 are removed, while the portions of the capping layer 514 and MTJ layer 515 located below the MTJ pattern 521 are retained. Finally, the MTJ mask layer is removed, resulting in the following... Figure 16 The structure described above, in Figure 16 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 16 As shown, multiple MTJ pillars are arranged in an array, corresponding to and connected to the first electrode structure 507 above it. The material of the MTJ mask layer can include a single-layer mask, a multi-layer composite mask, or photoresist, depending on the specific process conditions and requirements. The method for removing the capping layer 514, the MTJ layer 515, and the MTJ mask layer can be etching.

[0175] Furthermore, embodiments of this disclosure can form MTJ patterns in stages. Therefore, in some embodiments, patterning of the cover layer and MTJ layer to form multiple MTJ pillars may include...

[0176] An initial second mask layer is formed above the cover layer;

[0177] A third mask layer is formed above the initial second mask layer, the third mask layer having a first pattern extending along a first direction;

[0178] Using the third mask layer as a mask, the first pattern is transferred to the initial second mask layer to obtain the second mask layer;

[0179] A first photoresist layer is formed above the second mask layer, and the first photoresist layer has a second pattern extending along a second direction;

[0180] Using the first photoresist layer as a mask, the second pattern is transferred to the second mask layer to obtain the MTJ mask layer, which has MTJ patterns arranged in an array.

[0181] The MTJ pattern is transferred to the capping layer and the MTJ layer to form multiple MTJ pillars.

[0182] It should be noted that, Figure 17 This is a schematic diagram of the structure obtained after forming the third mask layer. Figure 17 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 17 As shown, an initial second mask layer 516 is formed above a capping layer 514, and a third mask layer 517 is formed above the initial second mask layer 516, with the third mask layer 517 having a first pattern extending along a first direction. The materials of the third mask layer 517 and the initial second mask layer 516 can be single-layer masks, multi-layer masks, or photoresists, and they can be formed by deposition.

[0183] Using the third mask layer 517 as a mask, the first pattern is transferred to the initial second mask layer 516, and the third mask layer 517 is removed to obtain the following: Figure 18 The structure shown is in Figure 18 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 18 As shown, the initial second mask layer 516 retained after pattern transfer is referred to as the second mask layer 518. The second mask layer 518 has a first pattern and is strip-shaped, extending along a first direction. The method of transferring the first pattern can be: etching away the second mask layer 516 that is not covered by the third mask layer 517.

[0184] When forming the second pattern in the second mask layer, a mask protection layer 519 can be formed first. The mask protection layer 519 covers the second mask layer 518 and the capping layer 514. The mask protection layer 519 can be formed by deposition, and the material of the mask protection layer 519 can be a hard mask material (HM). Then, a first photoresist layer 520 with the second pattern is formed on top of the mask protection layer 519, resulting in... Figure 19 The structure shown is in Figure 19 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the BB' direction in (b). Additionally, Figure 20 It shows Figure 19 A schematic diagram of the cross-section along the AA' direction in (b) of the diagram. Figure 19 and Figure 20As shown, the first photoresist layer 520 has a second pattern extending along a second direction. The second pattern is strip-shaped and extends along the second direction. At this time, the second mask layer 519 already has a first pattern. The first pattern extends along the first direction, and the second pattern extends along the second direction. The intersection of the first pattern and the second pattern is the MTJ pattern. Therefore, by transferring the second pattern to the second mask layer 518, a second mask layer 519 with an MTJ pattern is obtained (i.e., the aforementioned MTJ mask layer 521). Then, the first photoresist layer 520 and the mask protective layer 519 are removed to obtain the following... Figure 15 The structure shown is as follows: Figure 15 As shown, at this point, the retained second mask layer forms multiple columnar sub-masks 521, and the multiple sub-masks 521 are arranged in an array. Depending on the actual process implementation, the top view of the sub-masks 521 can be circular.

[0185] It is understood that when transferring the second pattern, the second pattern is simultaneously transferred to the second mask layer 518 and the mask protection layer 519. The method of transferring the second pattern can be: etching away the second mask layer 518 and the mask protection layer 519 that will expose the second pattern, and the mask protection layer 519 can protect the second mask layer 518 from being over-etched.

[0186] It should also be noted that the intersection of the first and second patterns is the MTJ pattern, which corresponds to the position where the MTJ pillars are formed. By transferring the MTJ pattern to the capping layer 514 and the MTJ layer 515, multiple MTJ pillars are obtained. When the angle between the first direction and the second direction is 60 degrees, multiple MTJ pillars arranged in a hexagonal array can be obtained.

[0187] Pattern transfer is performed using the MTJ mask layer as a mask. The capping layer 514 and MTJ layer 515 located below the MTJ pattern 521 are retained, while the remaining capping layer 514 and MTJ layer 515 are removed. The removal method can be etching. This process transforms the capping layer 514 and MTJ layer 515 into multiple MTJ pillars, resulting in... Figure 16 The structure shown. (As illustrated) Figure 16 As shown, multiple MTJ pillars are arranged in an array. Figure 16 In this implementation, the angle between the first direction and the second direction is 90 degrees. In other implementations, the angle between the first direction and the second direction can also be 60 degrees or other angles. When the angle is 60 degrees, a honeycomb MTJ array can be formed, which is beneficial to increasing the storage density of the semiconductor structure.

[0188] In addition, the second pattern can be formed first and then the first pattern in the embodiments of this disclosure. No specific limitation is made here. The method of forming MTJ pillars described here is only exemplary. Multiple MTJ pillars can also be formed in other ways in the embodiments of this disclosure. No specific limitation is made here.

[0189] A sidewall protective layer 522 is formed on the side of the MTJ column, resulting in the following structure: Figure 21 As shown. (a) is a cross-sectional view along the aforementioned AA' direction, where an MTJ pillar and a sidewall protective layer 522 formed on the side of the MTJ pillar constitute an MTJ structure. Multiple MTJ structures are arranged in an array to form an MTJ array. (b) and (c) show top views of two different MTJ structures. As shown in (b) and (c), the sidewall protective layer 522 is formed on the side of the MTJ structure, surrounding the side of the MTJ structure. In (b), the location of the sidewall protective layer 522 does not exceed the range of the first electrode structure 507; in (c), the location of the sidewall protective layer 522 exceeds the range of the first electrode structure 507. No specific limitation is made here. The material of the sidewall protective layer 522 may include insulating materials, such as oxide insulating materials like silicon dioxide (SiO2) or insulating materials like silicon nitride (SiN).

[0190] Additionally, it should be noted that the sidewall protective layer 522 is not shown in the top views of the following figures.

[0191] Furthermore, in some embodiments, a sidewall protective layer is formed on the side of the MTJ column, which may include:

[0192] An initial sidewall protective layer is formed on the surface of the substrate and the MTJ structure;

[0193] The initial sidewall protective layer located on the substrate surface and the top surface of the MTJ structure is removed, while the initial sidewall protective layer located on the side of the MTJ structure is retained to form a sidewall protective layer.

[0194] It should be noted that when forming the sidewall protective layer 522, an initial sidewall protective layer can be formed first, and then part of the initial sidewall protective layer can be removed to obtain the sidewall protective layer 522. Figure 22 This is a schematic diagram of the structure obtained after forming the initial sidewall protective layer 5221. Figure 22 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 12 As shown, an initial sidewall protective layer 5221 is formed on the surface of the MTJ structure (including the top and side surfaces), the surface of the substrate 501, the surface of the first electrode structure 507, and the surface of the bit line 508. The initial sidewall protective layer 5221 can be formed by deposition.

[0195] Then, the initial sidewall protective layer 5221 is partially removed, leaving only the sidewall protective layer 5221 located on the side of the MTJ structure, forming the sidewall protective layer 522, resulting in... Figure 21 The structure shown. The initial sidewall protective layer 5221 can be removed by etching.

[0196] S1004. An insulating layer is formed on the substrate, and the insulating layer covers the substrate and the MTJ structure.

[0197] S1005. Multiple electrode trenches are formed in the insulating layer, and the electrode trenches expose the top surface of the MTJ structure and the top surface of the bit line.

[0198] It should be noted that, Figure 23 This is a schematic diagram of the structure obtained after forming insulating layer 523. Figure 23 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 23 As shown, the insulating layer 523 is formed above the substrate and covers the substrate 501 and each MTJ structure.

[0199] Then, a portion of the insulating layer 523 is removed to form electrode trenches, which expose the top surface of the MTJ structure and the top surface of the bit line. This allows the second electrode structure to be simultaneously connected to both the top surface of the MTJ structure and the top surface of the bit line when it is subsequently formed in the electrode trenches.

[0200] In some embodiments, forming a plurality of electrode trenches in the insulating layer may include:

[0201] Multiple first trenches are formed in the insulating layer, and the first trenches expose the top surface of the cover layer and the sidewall protective layer;

[0202] Multiple second trenches are formed in the insulating layer, and the top surface of the bit line is exposed in the second trenches;

[0203] The first trench and the second trench are connected to form an electrode trench, and the second trench is not connected to the MTJ structure.

[0204] It should be noted that the electrode trench can be formed in two steps in the embodiments of this disclosure. First, a portion of the insulating layer is removed to form a first trench, and then a portion of the insulating layer is removed to form a second trench. The first trench and the second trench together form the electrode trench.

[0205] Figure 24 This is a schematic diagram of the structure obtained after forming the first groove 524. Figure 24 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). To show the relative positions of the bit line 508, the first electrode structure 507, and the first trench 524, all of these are shown in the top view. Figure 24 As shown, a first trench 524 is formed above the MTJ structure, and is formed above the substrate between the first side of the MTJ structure and the bit line adjacent to the first side of the MTJ structure. Figure 24The first side (the right side of the MTJ structure) should be noted. The first trench 524 is a portion of the area used for the subsequent formation of the second electrode structure. A portion of the insulating layer 523 is retained below the first trench 524 to insulate the MTJ layer in the MTJ structure from the subsequently formed second electrode structure, preventing contact and interference that could adversely affect device performance. Therefore, a portion of the insulating layer 523 is retained above the substrate between the first side of the MTJ structure and the bit line for insulation. To facilitate process implementation, when removing the insulating layer 523 to form the first trench 524, the insulating layer 523 above the MTJ structure and the substrate 501 is removed simultaneously, stopping when the top surface of the MTJ structure is reached. Therefore, the top surface of the insulating layer 523 retained below the first trench 524 is flush with the top surface of the MTJ structure. In the first direction, the size of the removed insulating layer 523 can be the same as or slightly larger than the size of the first electrode structure in the first direction. In the second direction, the specific amount of insulating layer 523 retained can be determined based on the actual process and requirements. For example, in... Figure 24 In the top view (b), the first groove 524 is not formed in the area above the bit line 508. In the top view (b), the right side of the first groove 524 coincides with the left side of the bit line 508. In addition, the right side of the first groove 524 may not reach the left side of the bit line 508, but maintain a certain distance. Furthermore, the right side of the first groove 524 may also extend beyond the left side of the bit line 508, resulting in a certain degree of overlap in the top view.

[0206] Furthermore, the first trench 524 may expose part or all of the top surface of the MTJ structure, without specific limitation. When the top surface of the MTJ structure is fully exposed (mainly referring to the tantalum capping layer 514), the contact resistance between the second electrode structure formed in the first trench 524 and the MTJ structure can be reduced.

[0207] See Figure 25 , Figure 25 This is a schematic diagram of another structure obtained after forming the first groove 524. Figure 25 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 25 The diagram shows the right side of the first trench 524 extending beyond the left side of the bit line 508. In this embodiment of the disclosure, [the following is used]... Figure 24 The structure shown will be described in detail using an example.

[0208] Furthermore, the method for forming the first trench 524 can be specifically as follows: firstly, a second photoresist layer 525 is formed above the insulating layer, resulting in... Figure 26 The structure shown is in Figure 26 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 26 As shown, the second photoresist layer 525 exposes the first trench region 526 in the insulating layer 523. The first trench region 526 is the location in the insulating layer 523 used for subsequent formation of the first trench. The insulating layer 523 is patterned using the second photoresist layer 525 as a mask. The patterning process can be as follows: etching is performed on the insulating layer 523 exposed by the second photoresist layer 525 (i.e., the first trench region 526), ​​and etching is stopped when the upper surface of the MTJ structure is reached. The second photoresist layer 525 is then removed, thus completing the first etching and forming multiple first trenches 524, resulting in the desired structure. Figure 24 The structure shown.

[0209] Furthermore, the insulating layer 523 located above the bit line 508 and connected to the first trench 524 is removed to obtain a second trench. The second trench exposes part of the bit line, and the first trench and the second trench together form an electrode trench. Alternatively, the insulating layer 523 located above the bit line 508 is completely removed to obtain a second trench that fully exposes the bit line. In this case, the multiple second trenches located above the same bit line and the multiple first trenches connected to the second trenches form a multi-electrode trench that is interconnected.

[0210] In some embodiments, forming a plurality of second trenches in the insulating layer may include:

[0211] A mask structure is formed in the first trench;

[0212] Using a mask structure as the MTJ protection structure, the insulating layer located above the bit line is removed to form multiple second trenches;

[0213] Remove the mask structure.

[0214] It should be noted that, Figure 27 To illustrate the structure obtained after forming the mask structure, in Figure 27 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 27 As shown, a mask structure 527 is formed in the first trench 524 and completely fills the first trench 524. The material of the mask structure 527 may include a hard mask material, and the mask structure 527 may be formed by deposition.

[0215] Using mask structure 527 as a protective structure for the MTJ, the MTJ structure is protected, and part of the insulating layer 523 is removed to form second trenches. In one implementation, the insulating layer 523 located above the bit line 508 and connected to the first trench (i.e., connected to the mask structure 527) is removed, thereby forming multiple second trenches 528, resulting in... Figure 28 The structure shown is as follows: Figure 28As shown, the second trench 528 exposes part of the bit line 508, and the second trench 528 and the MTJ structure are not connected. The second trench 528 and the MTJ structure (in this embodiment, mainly referring to the first side of the MTJ structure, i.e.) Figure 28 Between the right side of the middle, there is still an insulating layer 523.

[0216] In another implementation, the insulating layer 523 above bit line 508 is removed, resulting in the following: Figure 29 The structure shown is in Figure 29 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 29 As shown, in this implementation, the insulating layer 523 above the bit line 508 is removed, and the entire top surface of the bit line 508 is exposed by the second trench 528. This reduces the contact resistance between the second electrode structure formed in the second trench 528 and the bit line 508. In practice, either of these two implementations can be chosen, or a combination of both can be used; no specific limitation is made here.

[0217] The insulating layer 523 can be removed by etching. The mask structure 527 serves as a protective structure for the MTJ, which can protect the MTJ structure during the etching process and prevent damage to the MTJ structure.

[0218] Furthermore, when forming the second trench 528, a third photoresist layer 529 can be formed first above the insulating layer 523 and the mask structure 527 to obtain the following: Figure 30 The structure shown is in Figure 30 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 30 As shown, the insulating layer 523 exposed by the third photoresist layer 529 (which can be referred to as the second trench region) is the location subsequently used to form the second trench. Using the third photoresist layer 529 as a mask, the insulating layer 523 is patterned. The patterning process can be as follows: the insulating layer 523 exposed by the third photoresist layer 529 is etched until the bit line 508 is exposed, and the third photoresist layer 529 is removed, thereby completing the second etching and forming multiple second trenches 528, resulting in... Figure 28 The structure shown.

[0219] In addition, if you want to obtain such Figure 29 The structure shown only requires changing the pattern of the third photoresist layer 529. That is, the third photoresist layer 529 exposes the insulating layer 523 above the bit line 508, and then the insulating layer 523 is patterned to obtain the second trench 528 extending along the first direction.

[0220] After removing the mask structure 527, the result is as follows: Figure 31 The structure shown is in Figure 31 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 31 As shown, the first trench and the second trench are connected to form the electrode trench 530. The electrode trench 530 exposes the top surface of the MTJ structure and part of the bit line 508, and the electrode trench 530 is the location used to form the second electrode structure.

[0221] In addition, corresponding Figure 29 The implementation method, the second trench obtained after removing the mask structure is as follows: Figure 32 As shown, in Figure 32 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 32 As shown, the first trench and the second trench are connected to form the electrode trench 530, and the multiple electrode trenches 530 formed above the same bit line 508 are connected. The electrode trenches 530 expose the top surface of the MTJ structure and the top surface of the bit line 508.

[0222] In this way, the embodiments of this disclosure can form multiple electrode trenches 530 by two etching processes. A portion of the insulating layer is retained between the second trench and the MTJ structure to serve as insulation between the subsequent second electrode structure and the MTJ structure. The alignment accuracy requirement is low, no complex alignment process is required, and there is no need to etch electrode vias, thus reducing the process difficulty.

[0223] S1006. Multiple second electrode structures are formed in multiple electrode trenches.

[0224] It should be noted that after forming the electrode trench 530, a second electrode structure 531 is formed in each electrode trench. Based on Figure 31 The electrode trenches shown in the figure Figure 33 This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of the present disclosure. Figure 33 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Additionally, for a clearer illustration of the location of the components in the semiconductor structure, please refer to [link to relevant documentation]. Figure 34 This diagram shows a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 34 The image shows all parts of the semiconductor structure (except for the sidewall protective layer).

[0225] like Figure 33 and Figure 34As shown, the second electrode structure 531 completely fills the electrode trench 530, and each second electrode structure 531 is connected to a portion of the bit line 508 located below it. The second electrode structure 534 is formed by deposition, and the material of the second electrode structure 531 may include conductive materials such as titanium nitride or metals.

[0226] In addition, based on Figure 32 The electrode trenches shown in the figure Figure 35 This is a schematic diagram of the composition of another semiconductor structure provided in an embodiment of the present disclosure. Figure 35 In the diagram, (b) is a top view, and (a) is a cross-sectional view along the AA' direction in (b). Figure 35 As shown, in this implementation, the second electrode structure 531 connected to the same bit line 508 is a whole, which helps to reduce the contact resistance between the second electrode structure 531 and the bit line 508.

[0227] It should also be noted that the deposition used in the process steps involved in the embodiments of this disclosure may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., and specific limitations are not made here in combination with actual conditions.

[0228] It should also be noted that, in this embodiment of the disclosure, the semiconductor structure can be applied to MRAM, with the first electrode structure 507 forming the bottom electrode in the MRAM and the second electrode structure 531 forming the top electrode in the MRAM.

[0229] Thus, on the one hand, when forming the top electrode based on the method provided in the embodiments of this disclosure, the complex process of the top electrode is eliminated, the alignment accuracy requirements are reduced, and the process difficulty is effectively reduced; on the other hand, the embodiments of this disclosure form both the bit line and the bottom electrode in the substrate, and the bit line and the bottom electrode are located in the same layer of the substrate, which can reduce the linewidth of the bit line and increase the unit density of the bit line.

[0230] Figure 36 This is a schematic diagram comparing the structures of a semiconductor structure, such as... Figure 36As shown, in (a), the MTJ is formed above the bottom electrode, the top electrode is formed above the MTJ, and the bit line is formed above the top electrode. In this structure, the alignment of the top electrode and the top of the MTJ has high precision requirements, and misalignment is easy to occur, which may cause the top electrode to contact the free layer in the MTJ, thus affecting the performance. In (b), the bottom electrode and the bit line are located in the same layer, the MTJ is formed above the bottom electrode, and the top electrode is connected to the MTJ and the bit line respectively. In this structure, the bit line is located at the bottom, the alignment precision requirement of the top electrode is low, the top electrode and the MTJ are less likely to misalign, the process difficulty is reduced, and the quality of the product can be increased in actual production.

[0231] Furthermore, Figure 37 This is a schematic diagram comparing the connections of a semiconductor structure, such as... Figure 37 As shown, in (a), the gate of the transistor is connected to the word line WL, the source of the transistor is connected to the source line SL, and the drain of the transistor is connected to the bottom electrode (or contact electrode). The MTJ, top electrode, and bit line are formed sequentially above the bottom electrode. In (b), the connection method of the transistor is the same as in (a), but the bit line is no longer located above the top electrode, but is in the same layer as the bottom electrode. The bottom of the top electrode is in contact with the bit line, thereby increasing the bit line density and reducing the process difficulty.

[0232] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a plurality of first electrode structures and a plurality of bit lines in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and bit lines are spaced apart along a second direction, and the plurality of first electrode structures are arranged in an array; forming an MTJ structure above the first electrode structures; forming an insulating layer above the MTJ structure and between the MTJ structures; forming a plurality of electrode trenches in the insulating layer, the electrode trenches exposing the top surface of the MTJ structure and a portion of the top surface of the bit lines; and forming a plurality of second electrode structures in the plurality of electrode trenches. In this way, on the one hand, since the bit line structure is located at the bottom of the semiconductor structure, when forming the second electrode structure, only a portion of the insulating layer needs to be removed to obtain the electrode trenches exposing the MTJ structure and bit lines, and then the second electrode structure is formed in the electrode trenches, reducing the alignment accuracy requirements when fabricating the second electrode structure, thereby reducing the process difficulty; on the other hand, by fabricating the first electrode structure and the bit lines in the same layer of the substrate, the linewidth of the bit lines can be appropriately reduced, thereby ensuring a higher storage density.

[0233] In another embodiment of this disclosure, a semiconductor structure is provided, see [link to relevant documentation]. Figure 33 (or Figure 35 The semiconductor structure may include:

[0234] Substrate 501;

[0235] A plurality of first electrode structures 507 and a plurality of bit lines 508 are formed in a substrate 501; wherein, the plurality of bit lines 508 extend along a first direction, the first electrode structures 507 and bit lines 508 are arranged at intervals along a second direction, and the plurality of first electrode structures 507 are arranged in an array.

[0236] An MTJ structure formed above the first electrode structure 507;

[0237] An insulating layer 523 is formed above the substrate 501;

[0238] Multiple electrode trenches expose the top surface of the MTJ structure and the top surface of bit line 508;

[0239] Multiple second electrode structures 531 are formed in multiple electrode trenches.

[0240] It should be noted that the semiconductor structure provided in this disclosure embodiment can be prepared according to the method provided in the foregoing embodiment.

[0241] In some embodiments, such as Figure 33 As shown, the MTJ structure may include:

[0242] MTJ pillars formed above the first electrode structure 507;

[0243] The capping layer 514 formed above the MTJ column;

[0244] Sidewall protective layer 522 formed on the side of the MTJ column;

[0245] The MTJ structure consists of the MTJ column and the sidewall protective layer 522.

[0246] In some embodiments, the MTJ column may include:

[0247] Pinning layer 511 formed above first electrode structure 507;

[0248] A barrier layer 512 is formed above the pinned layer 511;

[0249] A free layer 513 is formed above the barrier layer 512;

[0250] A covering layer 514 is formed above the free layer 513.

[0251] In some embodiments, the semiconductor structure may further include a first trench and a second trench; wherein,

[0252] The first trench exposes the top surface of the cover layer 514 and the sidewall protective layer 522;

[0253] The top surface of the second trench exposure line 508;

[0254] The first trench and the second trench are connected to form an electrode trench, and the second trench is not connected to the MTJ structure.

[0255] It should be noted that, in cases such as Figure 33 In the implementation shown, the second trench is formed above the bit line 508, but not completely above it. Instead, it is formed above the bit line 508 and connected to the first trench, meaning the second trench exposes the top surface of the bit line 508 adjacent to the first electrode structure 507. Figure 35 In the implementation shown, the second trench 508 is completely formed above the bit line 508.

[0256] In some embodiments, a plurality of transistors are formed in the substrate, and the plurality of transistors correspond to a plurality of first electrode structures, wherein,

[0257] The first electrode structure is connected to the source or drain of the corresponding transistor.

[0258] In some embodiments, the material of the cover layer may include tantalum, and the material of the sidewall protective layer may include an insulating material.

[0259] In some embodiments, a first electrode structure forms the bottom electrode in the MRAM; and a second electrode structure forms the top electrode in the MRAM.

[0260] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0261] This disclosure provides a semiconductor structure, including: a substrate; a plurality of first electrode structures and a plurality of bit lines formed in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and bit lines are spaced apart along a second direction, and the plurality of first electrode structures are arranged in an array; an MTJ structure formed above the first electrode structures; an insulating layer formed above the substrate; a plurality of electrode trenches, the plurality of electrode trenches exposing the top surface of the MTJ structure and the top surface of the bit lines; and a plurality of second electrode structures formed in the plurality of electrode trenches. Thus, on the one hand, this structure can reduce the alignment accuracy requirements when fabricating the second electrode structures, reducing the process difficulty; on the other hand, by fabricating the first electrode structures and bit lines in the same layer of the substrate, the linewidth of the bit lines can be appropriately reduced, thereby ensuring a higher storage density.

[0262] In another embodiment of this disclosure, see [reference needed]. Figure 38 It shows a schematic diagram of the composition structure of a memory 600 provided in an embodiment of this disclosure, such as... Figure 38 As shown, the memory 600 includes the semiconductor structure 500 described in any of the foregoing embodiments.

[0263] In some embodiments, the memory 600 may include MRAM.

[0264] Since the memory 600 includes the semiconductor structure 500 described in the foregoing embodiments, it can improve bit line density, reduce process difficulty, and improve memory performance.

[0265] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0266] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0267] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0268] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0269] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0270] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0271] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A plurality of first electrode structures and a plurality of bit lines are formed in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and the bit lines are arranged at intervals along a second direction, and the plurality of first electrode structures are arranged in an array. An MTJ structure is formed above the first electrode structure; An insulating layer is formed over the substrate, and the insulating layer covers the substrate and the MTJ structure; Multiple electrode trenches are formed in the insulating layer, and the electrode trenches expose the top surface of the MTJ structure and the top surface of the bit line; Multiple second electrode structures are formed in the multiple electrode trenches; The formation of the MTJ structure above the first electrode structure includes: An MTJ layer is formed above the substrate; A cover layer is formed above the MTJ layer; The cover layer and the MTJ layer are patterned to form a plurality of MTJ pillars; wherein each MTJ pillar is formed above each of the first electrode structures. A sidewall protective layer is formed on the side of the MTJ column; The MTJ column and the sidewall protective layer together constitute the MTJ structure. The formation of multiple electrode trenches in the insulating layer includes: A plurality of first trenches are formed in the insulating layer, the first trenches exposing the top surfaces of the cover layer and the sidewall protective layer; A plurality of second trenches are formed in the insulating layer, the second trenches exposing the top surface of the bit line; The first trench and the second trench are connected to form the electrode trench, and the second trench is not connected to the MTJ structure. The formation of a plurality of second trenches in the insulating layer includes: A mask structure is formed in the first trench; Using the mask structure as the MTJ protection structure, the insulating layer located above the bit line is removed to form the plurality of second trenches; Remove the mask structure.

2. The method according to claim 1, characterized in that, The formation of a plurality of first electrode structures and a plurality of bit lines in the substrate includes: A first mask layer is formed above the substrate, the first mask layer exposing a plurality of first electrode regions and a plurality of bit line regions in the substrate, wherein the plurality of bit line regions all extend along the first direction, the first electrode regions and the bit line regions are arranged at intervals along the second direction, and the plurality of first electrode regions are arranged in an array. Using the first mask layer as a mask, the substrate is patterned to form a plurality of first electrode trenches in the substrate corresponding to the plurality of first electrode regions, and a plurality of bit line trenches in the substrate corresponding to the plurality of bit line regions. The plurality of first electrode structures are formed in the plurality of first electrode trenches, and the plurality of bit lines are formed in the plurality of bit line trenches.

3. The method according to claim 1, characterized in that, The MTJ layer includes a pinned layer, a barrier layer, and a free layer. The formation of the MTJ layer over the substrate includes: A pinning layer is formed above the substrate; A barrier layer is formed above the pinned layer; A free layer is formed above the barrier layer; The formation of a cover layer above the MTJ layer includes: The covering layer is formed above the free layer.

4. The method according to claim 1, characterized in that, The process of patterning the cover layer and the MTJ layer to form multiple MTJ pillars includes: An MTJ mask layer is formed above the cover layer, the MTJ mask layer comprising an array of MTJ patterns; Using the MTJ mask layer as a mask, the MTJ pattern is transferred to the cover layer and the MTJ layer to form the plurality of MTJ pillars.

5. The method according to claim 1, characterized in that, The sidewall protective layer formed on the side of the MTJ column includes: An initial sidewall protective layer is formed on the surface of the substrate and the MTJ structure; The initial sidewall protective layer located on the substrate surface and the top surface of the MTJ structure is removed, while the initial sidewall protective layer located on the side of the MTJ structure is retained to form the sidewall protective layer.

6. The method according to any one of claims 1 to 5, characterized in that, A plurality of transistors are formed in the substrate, and the plurality of transistors correspond to the plurality of first electrode structures, wherein, The first electrode structure is connected to the source or drain of the corresponding transistor.

7. A semiconductor structure, characterized in that, include: Substrate; A plurality of first electrode structures and a plurality of bit lines are formed in the substrate; wherein the plurality of bit lines extend along a first direction, the first electrode structures and the bit lines are arranged at intervals along a second direction, and the plurality of first electrode structures are arranged in an array. An MTJ structure formed above the first electrode structure; An insulating layer formed above the substrate; Multiple electrode trenches, the multiple electrode trenches exposing the top surface of the MTJ structure and the top surface of the bit line; Multiple second electrode structures formed in the plurality of electrode trenches; The semiconductor structure is prepared by the method according to any one of claims 1-6.

8. The semiconductor structure according to claim 7, characterized in that, The MTJ structure includes: MTJ pillars formed above the first electrode structure; A covering layer formed above the MTJ pillar; A sidewall protective layer formed on the side of the MTJ column; The MTJ structure is composed of the MTJ column and the sidewall protective layer.

9. The semiconductor structure according to claim 8, characterized in that, The MTJ column includes: A pinning layer formed above the first electrode structure; A barrier layer formed above the pinned layer; A free layer formed above the barrier layer; A covering layer formed above the free layer.

10. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure further includes a first trench and a second trench; wherein... The first trench exposes the top surface of the cover layer and the sidewall protective layer; The second trench exposes the top surface of the bit line; The first trench and the second trench are connected to form the electrode trench, and the second trench is not connected to the MTJ structure.

11. The semiconductor structure according to any one of claims 7 to 10, characterized in that, A plurality of transistors are formed in the substrate, and the plurality of transistors correspond to the plurality of first electrode structures, wherein, The first electrode structure is connected to the source or drain of the corresponding transistor.

12. A memory, characterized in that, Includes the semiconductor structure as described in any one of claims 7 to 11.

13. The memory according to claim 12, characterized in that, The memory includes MRAM.

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