Semiconductor device and method for manufacturing the same

Abstract

Provided are a semiconductor device and a method for manufacturing the same. The method comprises: providing a semiconductor substrate; forming a dielectric layer and at least one connecting through hole in the dielectric layer on a surface of the semiconductor substrate, wherein the top surface of each of the at least one connecting through hole is flush with the top surface of the dielectric layer; patterning the dielectric layer to form at least one boss in the dielectric layer, wherein each of the at least one boss includes at least one of the at least one connecting through hole; and forming at least one covering layer, wherein each of the at least one covering layer covers one of the at least one connecting through hole and extends to cover at least one side wall of the boss where the connecting through hole is located.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In electronic devices, memory is needed to read and store data. Therefore, as the demand for electronic devices continues to grow, the requirements for memory technology are also getting higher and higher.

[0003] Resistive random access memory (RRAM) is a non-volatile memory based on the reversible conversion of the resistance of non-conductive materials between high-resistance and low-resistance states under the action of an external electric field. It has the advantages of simple structure, good miniaturization, high storage density, and compatibility with CMOS technology. Therefore, it has attracted widespread attention. Summary of the invention

[0004] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor substrate; forming a dielectric layer and at least one connecting through hole in the dielectric layer on a surface of the semiconductor substrate, wherein a top surface of each of the at least one connecting through hole is flush with a top surface of the dielectric layer; patterning the dielectric layer to form at least one boss in the dielectric layer, wherein each of the at least one boss includes one or more of the at least one connecting through hole; and forming at least one covering layer, wherein each of the at least one covering layer covers one of the at least one connecting through hole and extends to cover at least one side wall of the boss where the connecting through hole is located.

[0005] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor substrate; forming a dielectric layer and at least one connecting through hole in the dielectric layer on a surface of the semiconductor substrate, wherein a top surface of each of the at least one connecting through hole is flush with a top surface of the dielectric layer; forming at least one bottom electrode layer, wherein each of the at least one bottom electrode layer covers one or more of the at least one connecting through hole; and forming at least one covering layer, wherein each of the at least one covering layer covers a portion of each of the one or more bottom electrode layers in the at least one bottom electrode layer and extends to cover at least one side wall of the bottom electrode layer, wherein the portion is located on one of the at least one connecting through hole covered by the bottom electrode layer.

[0006] According to some embodiments of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a dielectric layer located on a surface of the semiconductor substrate and at least one connecting through hole located in the dielectric layer, wherein the dielectric layer further comprises at least one boss, each of the at least one boss comprising one or more connecting through holes in the at least one connecting through hole; and at least one covering layer, each of the at least one covering layer covering one of the at least one connecting through holes and extending to cover at least one side wall of the boss where the connecting through hole is located.

[0007] According to some embodiments of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a dielectric layer located on the surface of the semiconductor substrate and at least one connecting through hole located in the dielectric layer, the top surface of each of the at least one connecting through hole being flush with the top surface of the dielectric layer; at least one bottom electrode, each of the at least one bottom electrode covering one of the at least one connecting through hole; and at least one covering layer, wherein each of the at least one covering layer covers each of one or more of the at least one bottom electrode and extends to cover at least one side wall of the bottom electrode.

[0008] According to one or more embodiments of the present disclosure, the operating voltage of the manufactured semiconductor device can be reduced, and the stability of the manufacturing process and the yield of the manufactured product can be improved.

[0009] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0012] Figure 2A is a schematic structural diagram of a semiconductor substrate in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0013] Figure 2B is a schematic structural diagram of an exemplary structure formed after a dielectric layer and at least one connecting through hole in the dielectric layer are formed on the surface of the semiconductor substrate in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 2C is based on Figure 2B A schematic plan view of an exemplary structure of;

[0015] Figure 2D is a plan view of an exemplary structure formed after patterning the dielectric layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 2E is based on Figure 2D A schematic cross-sectional view of an exemplary structure of ;

[0017] Figure 2F is a plan view of an exemplary structure formed after patterning the dielectric layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0018] Figure 2G is based on Figure 2F A schematic cross-sectional view of an exemplary structure of ;

[0019] Figure 2H is a schematic plan view of an exemplary structure formed after forming at least one capping layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0020] Fig.2I is based on Figure 2H A schematic cross-sectional view of an exemplary structure of ;

[0021] Figure 2J is a schematic plan view of an exemplary structure formed after forming at least one capping layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0022] Figure 2K is based on Figure 2J A schematic cross-sectional view of an exemplary structure of ;

[0023] Figure 3 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0024] Figure 4A is a schematic structural diagram of a semiconductor substrate in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0025] Figure 4B is a schematic structural diagram of an exemplary structure formed after a dielectric layer and at least one connecting through hole in the dielectric layer are formed on the surface of the semiconductor substrate in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0026] Figure 4C is based on Figure 4B A schematic plan view of an exemplary structure of;

[0027] Figure 4D is a schematic plan view of an exemplary structure formed after forming at least one bottom electrode layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0028] Figure 4E is based on Figure 4D A schematic cross-sectional view of an exemplary structure of ;

[0029] Figure 4F is a schematic plan view of an exemplary structure formed after forming at least one bottom electrode layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0030] Figure 4G is based on Figure 4F A schematic cross-sectional view of an exemplary structure of ;

[0031] Figure 4H is a schematic plan view of an exemplary structure formed after forming at least one capping layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0032] Fig. 4I is based on Figure 4H A schematic cross-sectional view of an exemplary structure of ;

[0033] Figure 4J is a schematic plan view of an exemplary structure formed after forming at least one capping layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0034] Figure 4K is based on Figure 4J A schematic cross-sectional view of an exemplary structure of ;

[0035] Figure 4L is a schematic plan view of an exemplary structure formed after forming at least one capping layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0036] Figure 4M is based on Figure 4L A schematic cross-sectional view of an exemplary structure of ;

[0037] Figure 4N is a schematic plan view of an exemplary structure formed after patterning at least one bottom electrode layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0038] Fig.4O is based on Figure 4N A schematic cross-sectional view of an exemplary structure of ;

[0039] Figure 4Pis a schematic plan view of an exemplary structure formed after patterning at least one bottom electrode layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0040] Figure 4Q is based on Figure 4P A schematic cross-sectional view of an exemplary structure of ;

[0041] Figure 4R is a schematic plan view of an exemplary structure formed after patterning at least one bottom electrode layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure; and

[0042] Figure 4S is based on Figure 4R A schematic cross-sectional view of an exemplary structure of FIG. DETAILED DESCRIPTION

[0043] It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part without departing from the teaching of the present disclosure.

[0044] Spatially relative terms such as "below," "beneath," "lower," "below," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figure. It will be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as "below other elements or features" or "below other elements or features" or "below other elements or features" will be oriented to "above other elements or features." Therefore, the exemplary terms "below" and "below" can cover both orientations above and below. Terms such as "before" or "before" and "after" or "followed by" can be similarly used, for example, to indicate the order in which light passes through the elements. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used in this article are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between two layers,” it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0045] The terms used herein are only for the purpose of describing a specific embodiment and are not intended to limit the present disclosure. As used herein, the singular forms "one", "one" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the existence of the features, integral bodies, steps, operations, elements and / or parts when used in this specification, but do not exclude the existence of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups or add one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" refers to only A, only B, or both A and B.

[0046] It will be understood that when an element or layer is referred to as being "on another element or layer," "connected to another element or layer," "coupled to another element or layer," or "adjacent to another element or layer," it may be directly on another element or layer, directly connected to another element or layer, directly coupled to another element or layer, or directly adjacent to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on another element or layer," "directly connected to another element or layer," "directly coupled to another element or layer," or "directly adjacent to another element or layer," there are no intermediate elements or layers. However, in no case should "on..." or "directly on..." be interpreted as requiring that one layer completely cover the layer below.

[0047] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the zones of the device and are not intended to limit the scope of the present disclosure.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0049] As used herein, the term "substrate" may refer to a substrate of a cut wafer, or may refer to a substrate of an uncut wafer. Similarly, the terms chip and die may be used interchangeably unless such interchange would cause a conflict.

[0050] In the related art, after the manufacture of RRAM is completed, an initial voltage is applied between the top electrode and the bottom electrode of RRAM, and the initial voltage is higher than the "forming voltage" to make the conductive filaments (or conductive fibers) in the dielectric layer between the bottom electrode and the top electrode, and the RRAM is transformed from a high impedance state (HRS) to a low impedance state (LRS). During the writing process, the RESET voltage is applied between the top electrode and the bottom electrode of RRAM to make the RRAM enter a high impedance state from a low impedance state, thereby setting the RRAM to "0" (reset); the SET voltage is applied between the top electrode and the bottom electrode of RRAM to make the RRAM enter a high impedance state from a high impedance state, thereby setting the RRAM to "1" (set). In the above process, the size of the "forming voltage" is often determined by the area and thickness of the dielectric layer between the top electrode and the bottom electrode. How to reduce the size of the operating voltage applied between the top electrode and the bottom electrode of RRAM and during the writing process, and improve the stability and yield of RRAM devices during the manufacturing process, is a problem that people always pay attention to.

[0051] According to one aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate;

[0052] A dielectric layer and at least one connecting through hole in the dielectric layer are formed on the surface of the semiconductor substrate, wherein the top surface of each of the at least one connecting through hole is flush with the top surface of the dielectric layer; the dielectric layer is patterned to form at least one boss in the dielectric layer, wherein each of the at least one boss includes one or more of the at least one connecting through hole; and at least one covering layer is formed, wherein each of the at least one covering layer covers one of the at least one connecting through hole and extends to cover at least one side wall of the boss where the connecting through hole is located.

[0053] A dielectric layer package including at least one boss is formed on the surface of a semiconductor substrate, each of the at least one boss includes a connection through hole in at least one connection through hole in the dielectric layer, so that the covering layer covering each of the at least one connection through hole can extend to cover the side wall of the boss corresponding to the connection through hole, that is, the structure formed by the covering layer has a corner. Since there is a sharp corner at the corner, after the RRAM device is formed, and when the initial voltage is applied, the electric field strength at the sharp corner at the corner is enhanced compared to the planar structure, and it is easier to form a conductive filament, so that the conductive filament in the dielectric layer between the bottom electrode and the top electrode of the covering layer can be formed at a lower voltage, thereby reducing the initial voltage of the RRAM. At the same time, since the conductive filament is easy to form, in the storage process, a smaller SET voltage is applied to achieve the RRAM setting "1" (set), and the write SET voltage is also reduced.

[0054] Furthermore, according to the manufacturing method of the semiconductor device disclosed in the present invention, a boss is formed by patterning a dielectric layer, and a covering layer is formed to cover the side wall of at least one side of the boss, so as to form an RRAM device, so that the process of forming the RRAM device is compatible with the CMOS process, and each step can adopt a mature CMOS process step, so that the process of manufacturing the RRAM device is highly stable and the yield of the manufactured RRAM is high.

[0055] Figure 1 is a schematic flowchart of a method 100 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0056] In step S101 , a semiconductor substrate is provided.

[0057] According to some embodiments, the semiconductor substrate may include a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, or the like, in which a field effect transistor (MOSFET) is formed.

[0058] In some embodiments, the semiconductor substrate also includes a first substrate on which a field effect transistor is formed and a dielectric layer located above the first substrate, wherein the first substrate may be a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator substrate, etc.; a connecting through hole filled with a conductive metal material and a metal layer located above the connecting through hole may be formed in the dielectric layer.

[0059] In some embodiments, a word line metal layer connected to the gate of the field effect transistor can be formed in the dielectric layer located above the first substrate to form a word line of the semiconductor device; and a source line metal layer connected to the source through a connecting through hole and a metal layer to form a source line of the semiconductor device.

[0060] Figure 2AFIG. 1 is a schematic cross-sectional view of a semiconductor substrate provided in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2A As shown, the semiconductor substrate 200 includes: a first substrate 210, and a dielectric layer 220 located on the first substrate 210. A field effect transistor including a source 211S, a drain 211D and a gate 211G is formed in the first substrate 210. A plurality of connecting through holes 221 and a multi-layer metal layer 222 are formed in the dielectric layer 220. The metal layer 222a connected to the gate 211G through the connecting through hole 221 constitutes a word line. The metal layer 222b connected to the source 211S through the connecting through hole 221 and the metal layer 222 constitutes a source line.

[0061] It can be understood that multiple metal layers may be formed in the dielectric layer, and adjacent metal layers are connected via connecting vias.

[0062] In step S102, a dielectric layer and at least one connecting through hole in the dielectric layer are formed on the surface of the semiconductor substrate, and the top surface of each of the at least one connecting through hole is flush with the top surface of the dielectric layer.

[0063] According to some embodiments, forming a dielectric layer and at least one connecting through hole in the dielectric layer on the surface of the semiconductor substrate includes: first, forming a dielectric material layer on the surface of the semiconductor substrate; then, performing a planarization process on the dielectric material layer to form a dielectric layer; then, performing a patterning process on the dielectric layer to form at least one through hole in the dielectric layer; and finally, performing a filling process on the at least one through hole to fill the at least one through hole with metal material.

[0064] See also Figure 2B and Figure 2C , shows a schematic diagram of an exemplary structure formed after steps S101 to S102 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 2B is a cross-sectional view of an exemplary structure formed, Figure 2C Schematic diagram of a plan view of an exemplary structure formed.

[0065] In some embodiments, Figure 2B and Figure 2C As shown, a dielectric layer 230 and at least one connecting through hole 231 in the dielectric layer 230 are formed on the semiconductor substrate 200 . The top surface of the connecting through hole 231 is flush with the top surface of the dielectric layer 230 .

[0066] In some embodiments, Figure 2BAs shown, a plurality of field effect transistors are formed in the semiconductor substrate 200 , and each of the at least one connecting through hole 231 is conductively connected to a drain 211D of a field effect transistor among the plurality of field effect transistors through a connecting through hole 221 in a dielectric layer 220 in the semiconductor substrate 200 and a metal layer 222 .

[0067] In some embodiments, Figure 2C As shown, at least one connecting through hole includes at least one row of connecting through holes, and each row of connecting through holes in the at least one row of connecting through holes includes a plurality of connecting through holes along a first direction (such as Figure 2C A plurality of through holes are arranged as shown by arrows X in the figure, wherein the direction perpendicular to the first direction is the second direction, such as Figure 2C As shown in Y.

[0068] In step S103, the dielectric layer is patterned to form at least one boss located in the dielectric layer, and each boss in the at least one boss includes one or more connecting through holes in the at least one connecting through hole.

[0069] In some embodiments, step S103, patterning the dielectric layer to form at least one boss in the dielectric layer, comprises:

[0070] First, a photolithography process is performed to form a patterned mask layer, which covers the area where the at least one boss is to be formed; then, the dielectric layer is etched using the patterned mask layer as a mask to form the at least one boss; finally, the patterned mask layer is removed.

[0071] In some embodiments, the number of the at least one connecting through hole formed in step S102 may be one or more. In step S103, the patterned mask layer is formed to cover the top of each of the at least one connecting through hole and expose a portion of the dielectric layer between two adjacent connecting through holes, so that each of the at least one boss formed includes one connecting through hole.

[0072] In some embodiments, the number of the at least one connecting through hole formed at step S102 is multiple, where Figure 2C As shown, at least one row of connecting through holes is included, and each row of connecting through holes in the at least one row of connecting through holes includes a plurality of connecting through holes arranged along a first direction. In step S103, the patterned mask layer formed covers each row of connecting through holes in the at least one row of connecting through holes and exposes a portion of the dielectric layer located between two adjacent rows of connecting through holes, so that each of the at least one boss formed is a strip-shaped boss extending along the first direction and includes one row of connecting through holes in the at least one row of connecting through holes.

[0073] By forming a patterned mask layer that covers each row of connection through holes in at least one row of connection through holes and exposes the portion of the dielectric layer between two adjacent rows of connection through holes, a strip-shaped boss corresponding to each row of connection through holes, extending along the first direction and including a corresponding row of connection through holes is formed. In the photolithography process of forming the patterned mask layer, the accuracy of the photolithography process is controlled to allow the mask layer to cover one row of connection through holes. Compared with forming at least one boss corresponding to at least one connection through hole, each boss includes one connection through hole, it is possible to ensure and improve the yield and reliability of the product while reducing the accuracy of the photolithography process.

[0074] See also Figure 2D and Figure 2E , which shows a schematic diagram of an exemplary structure formed after steps S101 to S103 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 2D is a schematic plan view of an exemplary structure formed, Figure 2E For along Figure 2D Schematic diagram of the cross-sectional structure along the dotted line 2d direction.

[0075] In some embodiments, Figure 2D and Figure 2E As shown, a plurality of connecting through holes 231 are arranged in a row, and the formed boss 241 is a strip-shaped boss extending along the first direction and includes the connecting through holes 231 arranged in a row.

[0076] In some embodiments, the at least one connecting through hole formed in step S102 includes multiple rows of connecting through holes arranged in parallel, and each row of connecting through holes in the multiple rows of connecting through holes includes multiple connecting through holes arranged along the first direction. In step S103, the patterned mask layer formed covers at least one sub-region, each of the at least one sub-region covers two adjacent rows of connecting through holes in the multiple rows of connecting through holes and the region between the two adjacent rows of connecting through holes, and a portion of the dielectric layer is exposed between two adjacent sub-regions in the at least one sub-region, so that each of the at least one boss formed is a block boss extending along the first direction and includes two adjacent rows of connecting through holes in the multiple rows of connecting through holes.

[0077] By forming a patterned mask layer including at least one sub-region covering two adjacent rows of connection through holes in the plurality of rows of connection through holes and the region between the two adjacent rows of connection through holes, and exposing a portion of the dielectric layer between two adjacent sub-regions in the at least one sub-region, at least one boss is formed, each of which is a block-shaped boss including two adjacent rows of connection through holes in the plurality of rows of connection through holes. In the photolithography process of forming the patterned mask layer, the accuracy of the photolithography process is controlled to allow the mask layer to cover the two rows of connection through holes. Compared with the case where each boss in the at least one boss is a strip-shaped boss extending along the first direction and including a row of connection through holes, the yield and reliability of the product are further guaranteed and improved while reducing the accuracy of the photolithography process.

[0078] See also Figure 2F and Figure 2G , which shows a schematic diagram of an exemplary structure formed after steps S101 to S103 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 2F is a schematic plan view of an exemplary structure formed, Figure 2G For along Figure 2F Schematic diagram of the cross-sectional structure of the dotted line 2f.

[0079] In some embodiments, Figure 2F As shown, the plurality of connecting through holes 231 are arranged in two rows, and each of the at least one boss 241 is a block-shaped boss extending along the first direction and includes the connecting through holes 231 arranged in two rows. Figure 2G As shown, the boss 241 includes two rows of connecting through holes 231 and a dielectric layer between the two rows of connecting through holes 231 .

[0080] At step S104, at least one covering layer is formed, wherein each of the at least one covering layer covers a portion of each of one or more of the at least one bottom electrode layer and extends to cover at least one side wall of the bottom electrode layer, and the portion is located on one of the at least one connecting through hole covered by the bottom electrode layer.

[0081] The semiconductor device manufactured by the method for manufacturing a semiconductor device according to some embodiments of the present disclosure is an RRAM. The covering layer includes a bottom electrode, a dielectric layer, and a top electrode stacked in sequence from bottom to top. In step S104, forming at least one covering layer includes: first, depositing a bottom electrode material layer, a dielectric material layer, and a top electrode material layer in sequence to cover each of the at least one boss; then, forming a mask layer, the mask layer at least covering the area where the at least one covering layer is to be formed; finally, using the mask layer as a mask, etching the bottom electrode material layer, the dielectric material layer, and the top electrode material layer in sequence.

[0082] In some embodiments, the material of the bottom electrode material layer includes titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a composite of one or more of the foregoing and other metals.

[0083] In some embodiments, the material of the dielectric material layer includes a transition metal oxide, for example, one or more of hafnium oxide (HfOx), aluminum oxide (AlOx), tantalum oxide (TaOx), or a combination of one or more of the foregoing and other composite materials.

[0084] In some embodiments, the material of the top electrode material layer includes metal nitride or metal. The metal nitride may be, for example, titanium nitride (TiN) or tantalum nitride (TaN) or the metal may be, for example, titanium (Ti) or tantalum (Ta).

[0085] In some embodiments, each of the at least one boss formed in step S103 includes a connecting through hole; each of the at least one covering layer formed in step S104 covers a through hole and one side or both sides of a boss corresponding to the through hole.

[0086] In some embodiments, each of the at least one boss formed in step S103 is a strip boss extending along the first direction and includes a row of connecting through holes in at least one row of connecting through holes; each of the at least one covering layer formed in step S104 covers a through hole and one side or both sides of a strip boss where the through hole is located in the second direction.

[0087] See also Figure 2H and Fig.2I , which shows a schematic diagram of an exemplary structure formed after steps S101 to S104 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 2H is a schematic plan view of an exemplary structure formed, Fig.2I For along Figure 2H Schematic diagram of the cross-sectional structure of the dotted line 2h.

[0088] In some embodiments, Figure 2H As shown, each of the at least one boss 241 is a strip-shaped boss extending along the first direction and includes a row of connecting through holes 231 (such as Figure 2H Each of the at least one covering layer 251 covers a through hole in the boss 241 and extends to cover both sides of the boss 241. Fig.2I As shown, the covering layer 251 covers a connecting through hole 231 and extends to cover both sides of the boss 241 where the connecting through hole 231 is located.

[0089] In some embodiments, each of the at least one boss formed in step S103 is a block-shaped boss extending along the first direction and includes two adjacent rows of connecting through holes in the plurality of rows of connecting through holes. Each of the at least one covering layer formed in step S104 covers a through hole and one side of a block-shaped boss where the through hole is located in the second direction.

[0090] See also Figure 2J and Figure 2K , which shows a schematic diagram of an exemplary structure formed after steps S101 to S104 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 2J is a schematic plan view of an exemplary structure formed, Figure 2K For along Figure 2J Schematic diagram of the cross-sectional structure of the dotted line 2j.

[0091] In some embodiments, Figure 2J As shown, each of the at least one boss 241 is a block-shaped boss extending along the first direction and includes two rows of connecting through holes 231 (such as Figure 2J Each of the at least one covering layer 251 covers a connecting through hole in the boss 241 and extends to cover one side of the boss 241, which is close to the connecting through hole 231 covered by the boss 241. Figure 2K As shown, each covering layer 251 covers a connecting through hole 231 and extends to cover one side of the boss 241 where the connecting through hole 231 is located, and the side is close to the covered connecting through hole 231 .

[0092] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is also provided, comprising: providing a semiconductor substrate; forming a dielectric layer and at least one connecting through hole located in the dielectric layer on the surface of the semiconductor substrate, the top surface of each of the at least one connecting through hole being flush with the top surface of the dielectric layer; forming at least one bottom electrode layer, each of the at least one bottom electrode layer covering one or more of the at least one connecting through hole; and forming at least one covering layer, wherein each of the at least one covering layer covers a portion of each of the one or more bottom electrode layers in the at least one bottom electrode layer and extends to cover at least one side wall of the bottom electrode layer, the portion being located on one of the at least one connecting through hole covered by the bottom electrode layer.

[0093] At least one bottom electrode layer is formed on a dielectric layer on the surface of a semiconductor substrate, each bottom electrode layer covers one or more through holes in the dielectric layer, and at least one covering layer is formed, each covering layer covers a portion of each bottom electrode layer in one or more bottom electrode layers in at least one bottom electrode layer and extends to cover at least one side wall of the bottom electrode layer, and the portion is located on one of the at least one connecting through holes covered by the bottom electrode layer, so that the structure formed by the covering layer above the bottom electrode layer covering each connecting through hole has a corner. After the semiconductor device is formed, due to the sharp corner at the corner, when the initial voltage is applied, the electric field strength at the sharp corner at the corner is enhanced compared with the planar structure, and it is easier to form a conductive filament, so that the conductive filament in the dielectric layer between the top electrode and the bottom electrode of the covering layer can be made at a lower voltage, thereby reducing the initial voltage of the RRAM. At the same time, since the conductive filament is easy to form, in the storage process, a smaller SET voltage is applied to achieve the RRAM being set to "1" (set), and the write SET voltage is also reduced.

[0094] Furthermore, according to the manufacturing method of the semiconductor device disclosed in the present invention, a RRAM device is formed by forming a bottom electrode layer and forming a covering layer covering the side wall of at least one side of the bottom electrode layer, so that the process of forming the RRAM device is compatible with the CMOS process, and each step can adopt a mature CMOS process step, so that the process of manufacturing the RRAM device is highly stable and the yield of the manufactured RRAM is high.

[0095] Figure 3 is a schematic flowchart of a method 300 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0096] In step S301 , a semiconductor substrate is provided.

[0097] According to some embodiments, the semiconductor substrate may include a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, or the like, in which a field effect transistor (MOSFET) is formed.

[0098] In some embodiments, the semiconductor substrate also includes a first substrate on which a field effect transistor is formed and a dielectric layer located above the first substrate, wherein the first substrate may be a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator substrate, etc.; a connecting through hole filled with a conductive metal material and a metal layer located above the connecting through hole may be formed in the dielectric layer.

[0099] In some embodiments, a word line metal layer connected to the gate of the field effect transistor may be formed in the dielectric layer located above the first substrate to form a word line of the semiconductor device.

[0100] Figure 4AFIG. 1 is a cross-sectional view showing an exemplary structure of a semiconductor substrate provided in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 4A As shown, the semiconductor substrate 400 includes: a first substrate 410, and a dielectric layer 420 located on the first substrate 410. A field effect transistor including a source 411S, a drain 411D and a gate 411G is formed in the first substrate 410. A plurality of connecting through holes 421 and a multi-layer metal layer 422 are formed in the dielectric layer 420. The metal layer 422a connected to the gate 411G through the connecting through hole constitutes a word line. The metal layer 422b connected to the source 411S through the connecting through hole and the metal layer constitutes a source line.

[0101] It can be understood that multiple metal layers may be formed in the dielectric layer, and adjacent metal layers are connected via connecting vias.

[0102] In step S302, a dielectric layer and at least one connecting through hole in the dielectric layer are formed on the surface of the semiconductor substrate, and the top surface of each of the at least one connecting through hole is flush with the top surface of the dielectric layer.

[0103] According to some embodiments, forming a dielectric layer and at least one connecting through hole in the dielectric layer on the surface of the semiconductor substrate includes: first, forming a dielectric material layer on the surface of the semiconductor substrate; then, performing a planarization process on the dielectric material layer to form a dielectric layer; then, performing a patterning process on the dielectric layer to form at least one through hole in the dielectric layer; and finally, performing a filling process on the at least one through hole to fill the at least one through hole with metal material.

[0104] See also Figure 4B and Figure 4C , which shows a schematic diagram of an exemplary structure formed after steps S301 to S302 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 2B is a cross-sectional view of an exemplary structure formed, Figure 2C Schematic diagram of a plan view of an exemplary structure formed.

[0105] In some embodiments, Figure 4B As shown, a dielectric layer 430 and at least one connecting through hole 431 in the dielectric layer 430 are formed on the semiconductor substrate 400 . The top surface of the connecting through hole 431 is flush with the top surface of the dielectric layer 430 .

[0106] In some embodiments, Figure 4BAs shown, a plurality of field effect transistors are formed in the semiconductor substrate 400 , and each of the at least one connecting through hole 431 is conductively connected to a drain 411D of a field effect transistor among the plurality of field effect transistors through a connecting through hole 421 in a dielectric layer 420 in the semiconductor substrate 400 and a metal layer 422 .

[0107] In some embodiments, Figure 4C As shown, at least one row of connecting through holes includes at least one row of connecting through holes, and each row of connecting through holes in the at least one row of connecting through holes includes a plurality of connecting through holes along a first direction (such as Figure 4C Multiple through holes arranged as shown by arrow X in the figure.

[0108] In step S303, at least one bottom electrode layer is formed.

[0109] In some embodiments, step S303, forming at least one bottom electrode layer on a semiconductor substrate includes: first forming a bottom electrode material layer to cover the dielectric layer and at least one connecting through hole in the dielectric layer; then, forming a patterned mask layer on the bottom electrode material layer to cover the area where the at least one bottom electrode layer is to be formed; finally, performing an etching process using the patterned mask layer as a mask to etch the bottom electrode material layer, thereby forming the at least one bottom electrode layer.

[0110] In some embodiments, the material of the bottom electrode material layer includes titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a composite of one or more of the foregoing and other metals.

[0111] In some embodiments, the bottom electrode material layer is etched by performing a wet etching process.

[0112] In some embodiments, the number of the at least one connecting through hole formed in step S302 may be one or more. In step S303, the patterned mask layer is formed to cover a portion of the bottom electrode material layer on each of the at least one connecting through hole and expose a portion of the bottom electrode material layer on a portion of the dielectric layer between two adjacent connecting through holes, so that each of the at least one bottom electrode layer formed covers one of the at least one connecting through hole.

[0113] In some embodiments, the number of the at least one connecting through hole formed at step S302 is multiple, where Figure 4CAs shown, at least one row of connecting through holes is included, and each row of connecting through holes in the at least one row of connecting through holes includes a plurality of connecting through holes arranged along a first direction. In step S303, the patterned mask layer is formed to cover the bottom electrode material layer on each row of connecting through holes in the at least one row of connecting through holes and expose the bottom electrode material layer on a portion of the dielectric layer located between two adjacent rows of connecting through holes in the dielectric layer, so that each bottom electrode layer in the at least one bottom electrode layer formed is a strip-shaped bottom electrode layer extending along the first direction and covers one row of connecting through holes in the at least one row of connecting through holes.

[0114] By forming a bottom electrode material layer covering each row of connection through holes in at least one row of connection through holes and exposing the bottom electrode material layer on a portion of the dielectric layer located between two adjacent rows of connection through holes in the dielectric layer, a strip-shaped bottom electrode layer corresponding to each row of connection through holes, extending along the first direction and covering the corresponding row of connection through holes is formed. In the photolithography process of forming a patterned mask layer, the accuracy of the photolithography process is controlled to make the mask layer cover the bottom electrode material layer on a row of connection through holes. Compared with forming at least one bottom electrode layer corresponding to at least one connection through hole, so that each bottom electrode layer covers one connection through hole, it is possible to ensure and improve the yield and reliability of the product while reducing the accuracy of the photolithography process.

[0115] See also Figure 4D and Figure 4E , which shows a schematic diagram of an exemplary structure formed after steps S301 to S303 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 4D is a schematic plan view of an exemplary structure formed, Figure 4E For along Figure 4D The cross-sectional view is shown along the dashed line 4d.

[0116] In some embodiments, Figure 4D and Figure 4E As shown, a plurality of connection through holes 431 are arranged in a row, and the bottom electrode layer 441 is a strip-shaped bottom electrode layer extending along the first direction and covers the connection through holes 431 arranged in a row.

[0117] In some embodiments, the at least one connecting through hole formed in step S302 includes multiple rows of connecting through holes arranged in parallel, and each row of connecting through holes in the multiple rows of connecting through holes includes multiple connecting through holes arranged along the first direction. In step S303, the patterned mask layer formed includes at least one sub-region, each of the at least one sub-region covers a portion of the bottom electrode material layer on two adjacent rows of connecting through holes in the multiple rows of connecting through holes and a portion of the bottom electrode material layer on a portion of the dielectric layer between the two adjacent rows of connecting through holes, and a portion of the bottom electrode material layer is exposed between two adjacent sub-regions in the at least one sub-region, so that each of the at least one bottom electrode layer formed is a block bottom electrode layer extending along the first direction and covers two adjacent rows of connecting through holes in the multiple rows of connecting through holes.

[0118] By forming a patterned mask layer including at least one sub-region covering a portion of the bottom electrode material layer on two adjacent rows of connection through holes in a plurality of rows of connection through holes and a portion of the bottom electrode material layer on a portion of the dielectric layer between the two adjacent rows of connection through holes, and exposing a portion of the bottom electrode material layer between two adjacent sub-regions in at least one sub-region, at least one boss is formed, each of which is a block-shaped bottom electrode covering a portion of the bottom electrode material layer on two adjacent rows of connection through holes in a plurality of rows of connection through holes and a portion of the dielectric layer between the two adjacent rows of connection through holes. In the photolithography process of forming the patterned mask layer, the accuracy of the photolithography process is controlled to allow the mask layer to cover two rows of connection through holes, and compared with forming each of the at least one bottom electrode layer as a strip-shaped bottom electrode layer extending along the first direction and covering one row of connection through holes, the yield and reliability of the product are further guaranteed and improved while reducing the accuracy of the photolithography process.

[0119] See also Figure 4F and 4G , which shows a schematic diagram of an exemplary structure formed after steps S101 to S103 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 4F is a schematic plan view of an exemplary structure formed, Figure 4G For along Figure 4F Schematic diagram of the cross-sectional structure of the dotted line 4f.

[0120] In some embodiments, Figure 4F As shown, a plurality of connecting through holes 431 (such as Figure 4F Each of the at least one bottom electrode layer 441 is a block electrode extending along the first direction and covers the connection through holes 431 arranged in two rows and a portion of the dielectric layer between the two rows of connection through holes 431. Figure 4GAs shown, the bottom electrode layer 441 covers two rows of connecting through holes 431 and the dielectric layer between the two rows of connecting through holes 431 .

[0121] At step S304, at least one covering layer is formed, wherein each of the at least one covering layer covers a portion of a bottom electrode layer among one or more bottom electrode layers among the at least one bottom electrode layer and extends to cover at least one side wall of the bottom electrode layer, and the portion is located on one connecting through hole among at least one connecting through hole covered by the bottom electrode layer.

[0122] The semiconductor device manufactured by the method for manufacturing a semiconductor device according to some embodiments of the present disclosure is an RRAM. The covering layer includes a dielectric layer and a top electrode stacked in sequence from bottom to top. At step S304, forming at least one covering layer includes: first, depositing a covering material layer to cover the at least one bottom electrode layer, the covering material layer includes a dielectric material layer and a top electrode material layer stacked in sequence from bottom to top; then, forming a patterned mask layer, the patterned mask layer at least covers the area where the at least one covering layer is to be formed; finally, etching the covering material layer using the patterned mask layer as a mask.

[0123] In some embodiments, the material of the dielectric material layer includes a transition metal oxide, for example, one or more of hafnium oxide (HfOx), aluminum oxide (AlOx), tantalum oxide (TaOx), or a combination of one or more of the foregoing and other composite materials.

[0124] In some embodiments, the material of the top electrode material layer includes metal nitride or metal, the metal nitride may be, for example, titanium nitride (TiN) or tantalum nitride (TaN) or the metal may be, for example, titanium (Ti) or tantalum (Ta).

[0125] In some embodiments, each of the at least one bottom electrode layer formed in step S303 covers one of the at least one connecting through holes formed in step 302, and the patterned mask layer in step S304 covers the dielectric material layer and the top electrode material layer above each bottom electrode layer, so that the at least one covering layer formed covers one of the at least one bottom electrode layers formed in step S303 and extends to cover one side wall or two side walls of the bottom electrode layer.

[0126] In some embodiments, the at least one connecting through hole formed in step 302 includes at least one row of connecting through holes, each row of connecting through holes in the at least one row of connecting through holes includes a plurality of connecting through holes arranged along a first direction, and each of the at least one bottom electrode layer formed in step S303 is a strip electrode layer extending along the first direction and covers a row of connecting through holes in the at least one row of connecting through holes; the patterned mask layer in step S304 covers the covering material layer on the portion of the bottom electrode material layer located above each connecting through hole, so that each covering layer in the at least one covering layer formed corresponds to each connecting through hole in the at least one connecting through hole, so as to cover the portion of the bottom electrode layer covering the corresponding connecting through hole in the at least one bottom electrode layer located on the corresponding connecting through hole.

[0127] See also Figure 4H and Fig. 4I FIG. 1 is a schematic diagram showing an exemplary structure formed after steps S101 to S104 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 4H is a schematic plan view of an exemplary structure formed, Fig. 4I For along Figure 4H Schematic diagram of the cross-sectional structure of the dotted line 4h.

[0128] In some embodiments, Figure 4H As shown, each of the at least one bottom electrode layer 441 is a strip electrode extending along the first direction and covers a row of connecting through holes 431 (such as Figure 4H as shown by the dashed line in the middle) and a portion of the dielectric layer between two adjacent connecting through holes 431 in the row of connecting through holes 431; Figure 4H and Fig. 4I As shown, each of the at least one covering layer 451 covers a portion of the bottom electrode layer 441 located above each of the connection through holes 431 in the row of connection through holes 431 , and extends to cover both sides of the portion located in the second direction.

[0129] It can be understood that in some embodiments, at least one connecting through hole formed in step 302 includes multiple rows of connecting through holes arranged in parallel, each row of connecting through holes in the multiple rows of connecting through holes includes multiple connecting through holes arranged along a first direction, and each of the at least one bottom electrode layer formed in step S303 is a block electrode layer covering two adjacent rows of connecting through holes in the multiple rows of connecting through holes; the patterned mask layer in step S304 may also cover the covering material layer on the portion of the bottom electrode material layer located above each connecting through hole, so that each of the at least one covering layer formed corresponds to each connecting through hole in the at least one connecting through hole, so as to cover the portion of the bottom electrode layer covering the corresponding connecting through hole in the at least one bottom electrode layer located on the corresponding connecting through hole and extend to cover one side of the bottom electrode layer.

[0130] In some embodiments, the at least one connecting through hole formed in step 302 includes at least one row of connecting through holes, each row of the at least one row of connecting through holes includes a plurality of connecting through holes arranged along a first direction, and each of the at least one bottom electrode layer formed in step S303 is a strip electrode layer extending along the first direction and covering a row of connecting through holes in the at least one row of connecting through holes; the patterned mask layer in step S304 includes a plurality of sub-regions, each sub-region extending along a second direction, and a covering material layer covered by the sub-region is located above a portion of the bottom electrode layer above each connecting through hole in a row of connecting through holes arranged in parallel in the second direction among the multiple rows of connecting through holes; so that each covering layer in the at least one covering layer extends along a second direction perpendicular to the first direction, and corresponds to a row of connecting through holes in the multiple rows of connecting through holes arranged in parallel in the second direction, so as to cover a portion of the at least one bottom electrode layer located on each connecting through hole in the row of connecting through holes.

[0131] See also Figure 4J and Figure 4K , shows a schematic diagram of an exemplary structure formed after steps S101 to S104 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 4J is a schematic plan view of an exemplary structure formed, Figure 4K along Figure 4J Schematic diagram of the cross-sectional structure of the dotted line 4j.

[0132] In some embodiments, Figure 4J As shown, each of the at least one bottom electrode layer 441 is a strip electrode extending along the first direction and covers a row of connecting through holes 231 (such as Figure 4JAs shown by the dotted line in the circle) and a portion of the dielectric layer between two adjacent connecting through holes 231 in the row of connecting through holes 231; Figure 4J and Figure 4K Each of the at least one covering layer 451 extends along the second direction and covers a portion of the bottom electrode layer above each connection through hole in the same row of connection through holes in the multiple rows of connection through holes 231, thereby extending to cover both sides of the portion of the bottom electrode layer in the second direction.

[0133] In the process of forming the covering layer, a patterned mask layer including a plurality of sub-regions is formed, each sub-region extends along the second direction, and the covering material layer covered by the sub-region is located on the portion of the bottom electrode layer above each of the connection through holes in a row of the multiple rows of connection through holes arranged in parallel in the second direction; so as to form at least one covering layer, each extending along the second direction perpendicular to the first direction and corresponding to a row of the multiple rows of connection through holes arranged in parallel in the second direction, so as to cover the portion of the at least one bottom electrode layer located on each of the connection through holes in the row. In the photolithography process of forming the patterned mask layer, the accuracy of the photolithography process is controlled to make the mask layer cover one of the multiple rows of connection through holes, and compared with forming at least one covering layer each covering the portion of the at least one bottom electrode layer located on one of the connection through holes in the row of connection through holes, the yield and reliability of the product are further guaranteed and improved while reducing the accuracy of the photolithography process.

[0134] In some embodiments, at least one connecting through hole formed in step 302 includes multiple rows of connecting through holes arranged in parallel, each row of connecting through holes in the multiple rows of connecting through holes includes multiple connecting through holes arranged along a first direction, and each of the at least one bottom electrode layer formed in step S303 is a block electrode layer extending along the first direction and covering two adjacent rows of connecting through holes in the multiple rows of connecting through holes; the patterned mask layer in step S304 includes multiple sub-regions, each sub-region extends along a second direction, and the covering material layer covered by the sub-region covers a portion of at least one bottom electrode layer located above two connecting through holes in the multiple rows of connecting through holes that are respectively covered by two adjacent bottom electrode layers and located in the same row; so that each covering layer in at least one covering layer extends along a second direction perpendicular to the first direction, and covers a portion of at least one bottom electrode layer located above two connecting through holes in the multiple rows of connecting through holes that are respectively covered by two adjacent bottom electrode layers and located in the same row.

[0135] See also Figure 4L and Figure 4M, shows a schematic diagram of an exemplary structure formed after steps S101 to S104 in a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 4L is a schematic plan view of an exemplary structure formed, Figure 4M For along Figure 4L Schematic diagram of the cross-sectional structure of the dotted line 41.

[0136] In some embodiments, Figure 4L As shown, at least one bottom electrode layer 441 includes a bottom electrode layer group consisting of a first bottom electrode 441a and a second bottom electrode layer 441b, and the first bottom electrode 441a and the second bottom electrode layer 441b respectively cover two adjacent rows of connecting through holes 431, and one row of the two rows of connecting through holes 431 covered by the first bottom electrode 441a is adjacent to one row of the two rows of connecting through holes 231 covered by the second bottom electrode layer 441b.

[0137] Each of the at least one covering layer 451 extends along the second direction and corresponds to two adjacent connecting through holes in the second direction in the four columns of connecting through holes covered by the bottom electrode layer group (including the first bottom electrode 441a and the second bottom electrode layer 441b) to cover the portion of the bottom electrode layer group located on each of the two connecting through holes, and the two connecting through holes are respectively covered by the two bottom electrode layers in the bottom electrode layer group.

[0138] By forming a patterned mask layer including a plurality of sub-regions in the process of forming the covering layer, each sub-region extends along the second direction, and the covering material layer covered by the sub-region covers the portion of at least one bottom electrode layer located above two connecting through holes in the multiple rows of connecting through holes, which are respectively covered by two adjacent bottom electrode layers and located in the same row; so as to form at least one covering layer, each extending along the second direction perpendicular to the first direction and covering the portion of at least one bottom electrode layer located above two connecting through holes in the multiple rows of connecting through holes, which are respectively covered by two adjacent bottom electrode layers and located in the same row. In the photolithography process of forming the patterned mask layer, the accuracy of the photolithography process is controlled to make the mask layer cover two connecting through holes in the same row of the multiple rows of connecting through holes, and compared with forming at least one covering layer, each covering the portion of at least one bottom electrode layer located above one connecting through hole in the row of connecting through holes, the yield and reliability of the product are further guaranteed and improved while reducing the accuracy of the photolithography process.

[0139] In some embodiments, Figure 4H-4MAs shown, the at least one connecting through hole includes at least one row of connecting through holes, each row of connecting through holes in the at least one row of connecting through holes includes a plurality of connecting through holes arranged along a first direction, each of the at least one bottom electrode layer is a strip electrode layer extending along the first direction and covering one row of connecting through holes in the at least one row of connecting through holes, or each of the at least one bottom electrode layer is a block electrode layer covering two adjacent rows of connecting through holes in the plurality of rows of connecting through holes; the method for manufacturing a semiconductor device according to the present disclosure also includes:

[0140] The at least one bottom electrode layer is patterned to form a plurality of bottom electrodes, each of the plurality of bottom electrodes corresponds to each of the connection through holes in the at least one row of connection through holes, and a portion of the dielectric layer is exposed between two adjacent bottom electrodes of the plurality of bottom electrodes.

[0141] At least one bottom electrode layer is patterned to form a bottom electrode corresponding to each connecting through hole, so that adjacent bottom electrodes are insulated, and finally the formation of the RRAM device is completed.

[0142] See 4N and Fig.4O , showing a semiconductor manufacturing method according to some embodiments of the present disclosure, Figure 4H and Fig. 4I A schematic diagram of an exemplary structure formed after at least one bottom electrode layer in the exemplary structure shown is patterned. Figure 4N is a schematic plan view of an exemplary structure formed, Fig.4O For along Figure 4N A cross-sectional view along the dashed line 4n in FIG.

[0143] like Figure 4N As shown, at least one bottom electrode layer 441 is patterned to form a plurality of bottom electrodes 441a (eg, Figure 4N ), so that each of the bottom electrodes 441a in the plurality of bottom electrodes 441a is connected to each of the at least one connecting through hole 431 formed in step S302 (as shown in the dashed rectangular box in the middle). Figure 4N 4 and 4, and each of the at least one covering layer 451 corresponds to each of the at least one connecting through hole 431. Fig.4O As shown, each capping layer 451 covers two side walls of a bottom electrode 441 a.

[0144] See 4P and Figure 4Q , showing a semiconductor manufacturing method according to some embodiments of the present disclosure, Figure 4J and Figure 4KA schematic diagram of an exemplary structure formed after at least one bottom electrode layer in the exemplary structure shown is patterned. Figure 4P is a schematic plan view of an exemplary structure formed, Figure 4Q For along Figure 4P Schematic diagram of the cross-sectional structure of the dotted line 4p in FIG.

[0145] like Figure 4P As shown, at least one bottom electrode layer 441 is patterned to form a plurality of bottom electrodes 441a (eg, Figure 4P ), so that each of the bottom electrodes 441a in the plurality of bottom electrodes 441a is connected to each of the at least one connecting through hole 431 formed in step S302 (as shown in the dashed rectangular box in the middle). Figure 4P Correspondingly, one of the at least one covering layer 451 extends along the second direction and covers the bottom electrode 441a on each of the connecting through holes 431 in a row of connecting through holes 431 arranged in parallel in the second direction (as shown in the dotted circle frame in the figure). Figure 4Q As shown, each capping layer 451 extends to cover two side walls of two bottom electrodes 441 a.

[0146] See 4R and Figure 4S , showing a semiconductor manufacturing method according to some embodiments of the present disclosure, Figure 4L and Figure 4M A schematic diagram of an exemplary structure formed after at least one bottom electrode layer in the exemplary structure shown is patterned. Figure 4R is a schematic plan view of an exemplary structure formed, Figure 4S For along Figure 4R Schematic diagram of the cross-sectional structure of the dotted line 4r.

[0147] like Figure 4R As shown, at least one bottom electrode layer 441 is patterned to form a plurality of bottom electrodes 441a (eg, Figure 4R ), so that each of the bottom electrodes 441a in the plurality of bottom electrodes 441a is connected to each of the at least one connecting through hole 431 formed in step S302 (as shown in the dashed rectangular box in the middle). Figure 4R Correspondingly, each of the at least one covering layer 451 extends along the second direction and covers two adjacent bottom electrodes 441a on two adjacent connecting through holes 431 arranged in parallel in the second direction.

[0148] like Figure 4SAs shown, each covering layer 451 extends to cover one side wall of each of two adjacent bottom electrodes 441 a , and the two covered side walls of the two adjacent bottom electrodes 441 a are adjacent.

[0149] In some embodiments, after patterning at least one bottom electrode layer, it also includes: forming an interlayer dielectric layer, which exposes the top surface of each of the at least one covering layer formed in step S304; and forming at least one metal layer located above the interlayer dielectric layer to electrically connect each of the at least one covering layer to an external circuit, and the at least one metal layer constitutes a bit line.

[0150] According to another aspect of the present disclosure, there is also provided a semiconductor device, including:

[0151] Semiconductor substrate;

[0152] a dielectric layer located on the surface of the semiconductor substrate and at least one connecting through hole located in the dielectric layer, wherein the dielectric layer further comprises at least one boss, and each of the at least one boss comprises one or more connecting through holes in the at least one connecting through hole; and

[0153] At least one covering layer, each of the at least one covering layer covers one of the at least one connecting through hole and extends to cover at least one side wall of the boss where the connecting through hole is located.

[0154] Since the dielectric layer located on the surface of the semiconductor substrate includes at least one boss, each of the at least one boss includes one of the at least one connecting through holes located in the dielectric layer, so that the covering layer covering each of the at least one connecting through holes can extend to cover the side wall of the boss corresponding to the connecting through hole, that is, the covering layer forms a cap-type structure, and the corners of the cap-type structure have sharp corners. When the formed semiconductor device is an RRAM device, and when a voltage is applied, a strong electric field is easily formed at the sharp corners of the corners of the cap-type structure, thereby forming a conductive filament, so that the operation of the RRAM can be achieved at a lower voltage, thereby reducing the operating voltage of the RRAM.

[0155] According to some embodiments, the semiconductor substrate may include a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, or the like, in which a field effect transistor (MOSFET) is formed.

[0156] In some embodiments, the semiconductor substrate also includes a first substrate on which a field effect transistor is formed and a dielectric layer located above the first substrate, wherein the first substrate may be a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator substrate, etc.; a connecting through hole filled with a conductive metal material and a metal layer located above the connecting through hole may be formed in the dielectric layer.

[0157] In some embodiments, a word line metal layer connected to the gate of the field effect transistor can be formed in the dielectric layer located above the first substrate to form a word line of the semiconductor device; and a source line metal layer connected to the source through a connecting through hole and a metal layer to form a source line of the semiconductor device.

[0158] See also Fig.2I , showing a schematic cross-sectional structure diagram of a semiconductor device according to some embodiments of the present disclosure.

[0159] like Fig.2I As shown, according to some embodiments of the present disclosure, the semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a first substrate 210 formed with a field effect transistor and a dielectric layer 220 located on the first substrate 210, wherein the first substrate 210 can be a silicon substrate, a silicon germanium substrate or a silicon-on-insulator substrate, etc.; a connecting through hole 221 filled with a conductive metal material and a metal layer 222 located above the connecting through hole can be formed in the dielectric layer 220.

[0160] In some embodiments, continue to see Fig.2I A word line metal layer 222a connected to the gate electrode 211G of the field effect transistor may be formed in the dielectric layer 220 located on the first substrate 210 to form a word line of the semiconductor device, and a source line metal layer 222b connected to the source electrode 211S through the connecting through hole 221 and the metal layer 222 to form a source line of the semiconductor device.

[0161] Continue to view Fig.2I According to some embodiments of the present disclosure, the semiconductor device also includes a dielectric layer 230 located on the surface of the semiconductor substrate and a plurality of connecting through holes 231 located in the dielectric layer 230, wherein the dielectric layer 230 also includes a plurality of bosses 241, and each boss 241 includes one or more connecting through holes 231 among the at least one connecting through hole 231.

[0162] Continue to view Fig.2I According to some embodiments of the present disclosure, the semiconductor device further includes a plurality of covering layers 251 , each covering layer 251 covering a connecting through hole 231 and extending to cover two side walls of the boss 241 where the connecting through hole 231 is located.

[0163] like Fig.2IAs shown, since the covering layer 251 covers the through hole 231 and extends to cover the two side walls of the boss 241 where the connecting through hole 231 is located, the covering layer 251 forms a cap-type structure. Fig.2I The positions indicated by the arrows C1 and C2 in the middle have sharp corners. When voltage is applied to the device, a strong electric field is easily formed at the two corners, thereby forming conductive filaments, so that the RRAM can be operated at a lower voltage, thereby reducing the operating voltage of the RRAM.

[0164] In some embodiments, the at least one connecting through hole includes at least one row of connecting through holes, each row of connecting through holes in the at least one row of connecting through holes includes a plurality of connecting through holes arranged along a first direction, each of the at least one boss is a strip-shaped boss extending along the first direction and includes a row of connecting through holes in the at least one row of connecting through holes.

[0165] like Figure 2H , showing that according to Fig.2I 2H is a schematic plan view of a semiconductor device, wherein a plurality of connecting through holes 231 (as indicated by the circular dotted line in 2H) are provided in a dielectric layer 230, wherein the plurality of connecting through holes 231 are arranged in parallel in a plurality of rows, and each row includes a plurality of connecting through holes 231 arranged along a first direction (as indicated by the arrow X in 2H). The dielectric layer 230 further includes a plurality of bosses 241, each of which is a strip-shaped boss extending along the first direction and includes a row of connecting through holes 231 in the plurality of rows of connecting through holes.

[0166] In some embodiments, the at least one connecting through hole includes multiple rows of connecting through holes arranged in parallel, each row of connecting through holes in the multiple rows of connecting through holes includes multiple connecting through holes arranged along a first direction, and each of the at least one boss is a block boss extending along the first direction and includes two adjacent rows of connecting through holes in the multiple rows of connecting through holes.

[0167] 2J and 2K, schematic diagrams of the structure of a semiconductor device according to some embodiments of the present disclosure are shown. Figure 2J is a plan view of a semiconductor device. Figure 2K For along Figure 2J Schematic diagram of the cross-sectional structure of the dotted line 2j.

[0168] In some embodiments, Figure 2J As shown, the semiconductor device includes a plurality of connecting through holes 231 (such as Figure 2J The plurality of connecting through holes 231 are arranged in parallel in a plurality of rows, each row including a plurality of connecting through holes 231 along a first direction (such as Figure 2JEach of the at least one boss 241 is a block-shaped boss extending along the first direction and includes two rows of connecting through holes 231. Each of the at least one covering layer 251 covers one connecting through hole in the boss 241 and extends to cover one side of the boss 241, which is close to the connecting through hole 231 covered by the boss 241. Figure 2K As shown, the covering layer 251 covers a connecting through hole 231 and extends to cover one side of the boss 241 where the connecting through hole 231 is located, and the side is close to the covered connecting through hole 231 .

[0169] like Figure 2K As shown, since the covering layer 251 covers a connecting through hole 231 and extends to cover one side of the boss 241 where the connecting through hole 231 is located, the structure formed by the covering layer has a corner (such as Figure 2K When voltage is applied to the device, a strong electric field is easily formed at the two corners, thereby forming conductive filaments, so that the RRAM can be operated at a lower voltage, thereby reducing the operating voltage of the RRAM.

[0170] In some embodiments, the capping layer includes a bottom electrode, a dielectric layer, and a top electrode sequentially stacked from bottom to top.

[0171] In some embodiments, the material of the bottom electrode includes titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a composite of one or more of the foregoing and other metals.

[0172] In some embodiments, the material of the dielectric layer includes a transition metal oxide, such as one or more of hafnium oxide (HfOx), aluminum oxide (AlOx), tantalum oxide (TaOx), or a combination of one or more of the foregoing and other composite materials.

[0173] In some embodiments, the material of the top electrode includes metal nitride or metal. The metal nitride may be, for example, titanium nitride (TiN) or tantalum nitride (TaN) or the metal may be, for example, titanium (Ti) or tantalum (Ta).

[0174] In some embodiments, the semiconductor device in the above embodiments adopts Figure 1 and Figure 2A-2K A method for manufacturing a semiconductor device is described.

[0175] According to another aspect of the present disclosure, there is also provided a semiconductor device, including:

[0176] Semiconductor substrate;

[0177] A dielectric layer located on the surface of the semiconductor substrate and at least one connecting through hole located in the dielectric layer, wherein the top surface of each of the at least one connecting through hole is flush with the top surface of the dielectric layer;

[0178] at least one bottom electrode, each of the at least one bottom electrode covering one of the at least one connecting through-hole; and

[0179] At least one covering layer, wherein each of the at least one covering layer covers each of one or more of the at least one bottom electrode and extends to cover at least one sidewall of the bottom electrode.

[0180] Since at least one bottom electrode layer is covered on the dielectric layer on the surface of the semiconductor substrate, each bottom electrode layer covers one or more through holes in the dielectric layer, and at least one covering layer is covered on at least one bottom electrode layer, each covering layer covers a portion of each bottom electrode layer in one or more bottom electrode layers in at least one bottom electrode layer and extends to cover at least one side wall of the bottom electrode layer, and the portion is located on one of the at least one connecting through holes covered by the bottom electrode layer, so that the covering layer located on the bottom electrode layer covering each connecting through hole forms a cap-type structure, and the corner of the cap-type structure has a sharp corner. After the RRAM device is formed, and when the initial voltage is applied, the sharp corner at the corner of the cap-type structure is easier to form a conductive filament than the planar structure due to the enhanced electric field strength, so that the conductive filament in the dielectric layer between the bottom electrode and the top electrode of the covering layer can be made at a lower voltage, thereby reducing the initial voltage of the RRAM. At the same time, since the conductive filament is easy to form, in the storage process, applying a smaller SET voltage can achieve the RRAM being set to "1" (set), and the SET voltage of the RRAM can also be reduced.

[0181] According to some embodiments, the semiconductor substrate may include a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, or the like, in which a field effect transistor (MOSFET) is formed.

[0182] In some embodiments, the semiconductor substrate also includes a first substrate on which a field effect transistor is formed and a dielectric layer located above the first substrate, wherein the first substrate may be a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator substrate, etc.; a connecting through hole filled with a conductive metal material and a metal layer located above the connecting through hole may be formed in the dielectric layer.

[0183] In some embodiments, a word line metal layer connected to the gate of the field effect transistor can be formed in the dielectric layer located above the first substrate to form a word line of the semiconductor device; and a source line metal layer connected to the source through a connecting through hole and a metal layer to form a source line of the semiconductor device.

[0184] In some embodiments, each bottom electrode in the at least one bottom electrode layer covers one connection through hole in the at least one connection through hole on the surface of the semiconductor substrate.

[0185] In some embodiments, the material of the bottom electrode includes titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a composite of one or more of the foregoing and other metals.

[0186] In some embodiments, each of the at least one covering layer corresponds to one of the at least one connecting through-hole to cover the bottom electrode of the at least one bottom electrode layer covering the corresponding connecting through-hole.

[0187] See also Figure 4N and Fig.4O , showing a schematic diagram of the structure of some semiconductor devices according to the present disclosure. Among them, Figure 4N is a schematic diagram of the planar structure of a semiconductor device. Fig.4O for Figure 4N Schematic diagram of the cross-sectional structure in the direction of the dotted line 4n.

[0188] like Figure 4N and Fig.4O As shown, according to some embodiments of the present disclosure, the semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a first substrate 410 on which a field effect transistor is formed and a dielectric layer 420 located on the first substrate 410, wherein the first substrate 410 can be a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator substrate, etc.; a connecting through hole 421 filled with a conductive metal material and a metal layer 422 located above the connecting through hole can be formed in the dielectric layer 420.

[0189] In some embodiments, continue to see Fig.4O A word line metal layer 422a connected to the gate electrode 411G of the field effect transistor may be formed in the dielectric layer 420 located above the first substrate 410 to form a word line of the semiconductor device, and a source line metal layer 422b connected to the source electrode 411S through the connecting through hole 421 and the metal layer 422 to form a source line of the semiconductor device.

[0190] Continue to view Fig.4O According to some embodiments of the present disclosure, the semiconductor device further includes a dielectric layer 430 located on the surface of the semiconductor substrate and a plurality of connecting through holes 431 located in the dielectric layer 430 .

[0191] Continue to view Fig.4O The semiconductor device according to some embodiments of the present disclosure further includes a plurality of bottom electrodes 441 a , each of the plurality of bottom electrodes 441 a covering one of the plurality of connection through-holes 431 .

[0192] Continue to view Fig.4O The semiconductor device according to some embodiments of the present disclosure further includes a plurality of capping layers 451 , each of the plurality of capping layers 451 covering two side walls of each of the plurality of bottom electrodes 441 a .

[0193] like Fig.4O As shown, since the covering layer 451 covers the two side walls of the bottom electrode 441a, the covering layer 251 forms a cap-type structure. Fig.4O The positions indicated by the arrows C3 and C4 in the middle have sharp corners. When voltage is applied to the device, a strong electric field is easily formed at the two corners, thereby forming conductive filaments, so that the RRAM can be operated at a lower voltage, thereby reducing the operating voltage of the RRAM.

[0194] In some embodiments, the at least one connecting through-hole comprises a plurality of rows of connecting through-holes arranged in parallel, each row of connecting through-holes in the plurality of connecting through-holes comprises a plurality of connecting through-holes arranged along a first direction, and wherein,

[0195] Each of the at least one covering layer extends along a second direction perpendicular to the first direction and corresponds to a row of connecting through holes in the multiple rows of connecting through holes arranged in parallel in the second direction to cover a bottom electrode of the at least one bottom electrode covering each connecting through hole in the row.

[0196] See also Figure 4P and Figure 4Q , showing a schematic diagram of the structure of some semiconductor devices according to the present disclosure. Among them, Figure 4P is a schematic diagram of the planar structure of a semiconductor device. Figure 4Q for Figure 4P Schematic diagram of the cross-sectional structure along the dotted line 4p direction.

[0197] like Figure 4P and 4QAs shown, at least one connecting through hole 431 in the dielectric layer 430 includes multiple rows of connecting through holes 431 arranged in parallel (as shown in the dotted circular frame in the figure). A plurality of bottom electrodes 441a are covered on the dielectric layer 430 (as shown in the dotted rectangular frame in the figure), and each of the multiple bottom electrodes 441a covers one connecting through hole 431 in at least one connecting through hole 431 (as shown in the dotted circular frame in the figure). Each covering layer 451 in the at least one covering layer 451 extends along the second direction (as shown by the arrow Y in the figure), and corresponds to a row of connecting through holes arranged in parallel in the second direction in the multiple rows of connecting through holes 431, so as to cover the bottom electrode 441a covering each connecting through hole in the row of connecting through holes in the multiple bottom electrodes 441a and extend to cover the two side walls of the bottom electrode 441a.

[0198] and Fig.4O The semiconductor device shown is similar to Figure 4Q As shown, since the covering layer 451 covers the two side walls of the bottom electrode 441a, the covering layer 451 forms a cap-type structure. Figure 4Q The positions indicated by the arrows C5 and C6 in the middle have sharp corners. When voltage is applied to the device, a strong electric field is easily formed at the two corners, thereby forming conductive filaments, so that the RRAM can be operated at a lower voltage, thereby reducing the operating voltage of the RRAM.

[0199] In some embodiments, the at least one connecting through hole included in the dielectric layer above the semiconductor substrate of the semiconductor device according to the present disclosure includes multiple rows of connecting through holes arranged in parallel, each row of connecting through holes in the multiple connecting through holes includes multiple connecting through holes arranged along a first direction, and wherein,

[0200] Two adjacent rows of connection through holes in the plurality of rows of connection through holes constitute a connection through hole group, and the first row of connection through holes in the first connection through hole group and the second row of connection through holes in the second connection through hole group in the adjacent two connection through hole groups in the plurality of connection through holes constituted by the plurality of connection through holes are adjacent, and wherein,

[0201] Each of the at least one covering layer extends along a second direction and corresponds to two adjacent connecting through holes in the second direction to cover the bottom electrode layer located on each of the two connecting through holes, and the two connecting through holes are respectively located in two adjacent connecting through hole groups among the multiple connecting through hole groups, and the second direction is perpendicular to the first direction.

[0202] See 4R and Figure 4S , showing a schematic diagram of the structure of some semiconductor devices according to the present disclosure. Among them, Figure 4R is a schematic diagram of the planar structure of a semiconductor device. Figure 4S for Figure 4R Schematic diagram of the cross-sectional structure in the direction of the dotted line 4r.

[0203] like Figure 4R and 4S As shown, at least one connecting through hole 431 in the dielectric layer 430 includes a plurality of rows of connecting through holes 431 arranged in parallel (eg, Figure 4R The dielectric layer 430 is covered with a plurality of bottom electrodes 441a (as shown in the dotted circle frame). Figure 4R Each of the bottom electrodes 441a covers at least one of the connection through holes 431 (as shown in the dashed rectangular box in the middle), and each of the bottom electrodes 441a covers at least one of the connection through holes 431 (as shown in the dashed rectangular box in the middle). Figure 4R (shown in the dotted circle box).

[0204] Two adjacent rows of connection through holes 431 in the plurality of rows of connection through holes 431 constitute a connection through hole group, and each of the at least one covering layer 451 is arranged along the second direction (eg Figure 4R The bottom electrode 441a is shown as an arrow Y in the middle and extends to correspond to two adjacent connecting through holes 431 arranged in parallel in the second direction, so as to cover a bottom electrode 441a of each connecting through hole in the plurality of bottom electrodes 441a and extend to cover a side wall of the bottom electrode 441a.

[0205] like Figure 4S As shown, since the cover layer 451 covers one side of the bottom electrode 441a, the structure formed by the cover layer has a corner (eg Figure 4S When voltage is applied to the device, a strong electric field is easily formed at the two corners, thereby forming conductive filaments, so that the RRAM can be operated at a lower voltage, thereby reducing the operating voltage of the RRAM.

[0206] In some embodiments, the capping layer includes a dielectric layer and a top electrode stacked sequentially from bottom to top.

[0207] In some embodiments, the material of the dielectric layer includes a transition metal oxide, such as one or more of hafnium oxide (HfOx), aluminum oxide (AlOx), tantalum oxide (TaOx), or a combination of one or more of the foregoing and other composite materials.

[0208] In some embodiments, the material of the top electrode includes metal nitride or metal. The metal nitride may be, for example, titanium nitride (TiN) or tantalum nitride (TaN) or the metal may be, for example, titanium (Ti) or tantalum (Ta).

[0209] In some embodiments, the semiconductor device in the above embodiments adopts Figure 3 and Figure 4A-4SA method for manufacturing a semiconductor device is described.

[0210] Although the present disclosure has been illustrated and described in detail in the drawings and in the foregoing description, such illustration and description should be considered illustrative and exemplary rather than restrictive; the present disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure and the appended claims, those skilled in the art will be able to understand and implement variations to the disclosed embodiments when practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps that are not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; Forming a dielectric layer and at least one connecting through hole in the dielectric layer on the surface of the semiconductor substrate, wherein the top surface of each of the at least one connecting through hole is flush with the top surface of the dielectric layer; Patterning the dielectric layer to form at least one boss in the dielectric layer, each boss in the at least one boss including one or more connecting through holes in the at least one connecting through hole; and At least one covering layer is formed, each of the at least one covering layer covers one of the at least one connecting through hole and extends to cover at least one side wall of the boss where the connecting through hole is located.

2. The method according to claim 1, wherein: The at least one connecting through hole includes at least one row of connecting through holes, each row of connecting through holes in the at least one row of connecting through holes includes a plurality of connecting through holes arranged along a first direction, and each of the at least one boss is a strip-shaped boss extending along the first direction and includes a row of connecting through holes in the at least one row of connecting through holes.

3. The method according to claim 1, wherein: The at least one connecting through hole comprises a plurality of rows of connecting through holes arranged in parallel, each row of the plurality of rows of connecting through holes comprises a plurality of connecting through holes arranged along a first direction, and each of the at least one boss is a block-shaped boss extending along the first direction and comprises two adjacent rows of connecting through holes in the plurality of rows of connecting through holes.

4. The method according to any one of claims 1 to 3, wherein: The covering layer includes a bottom electrode, a dielectric layer and a top electrode stacked in sequence from bottom to top, and the forming of at least one covering layer includes: Depositing a bottom electrode material layer, a dielectric material layer and a top electrode material layer in sequence to cover each of the at least one boss; forming a third mask layer, the third mask layer at least covering a region where the at least one covering layer is to be formed; and Using the third mask layer as a mask, the bottom electrode material layer, the dielectric material layer and the top electrode material layer are etched in sequence.

5. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; Forming a dielectric layer and at least one connecting through hole in the dielectric layer on the surface of the semiconductor substrate, wherein the top surface of each of the at least one connecting through hole is flush with the top surface of the dielectric layer; forming at least one bottom electrode layer, each of the at least one bottom electrode layer covering one or more of the at least one connecting through hole; and At least one covering layer is formed, wherein each of the at least one covering layer covers a portion of each of one or more of the at least one bottom electrode layer and extends to cover at least one side wall of the bottom electrode layer, and the portion is located on one of the at least one connecting through hole covered by the bottom electrode layer.

6. The method according to claim 5, wherein: The at least one connecting through hole comprises at least one row of connecting through holes, each row of connecting through holes in the at least one row of connecting through holes comprises a plurality of connecting through holes arranged along a first direction, and each of the at least one bottom electrode layer is a strip electrode layer extending along the first direction and covers one row of connecting through holes in the at least one row of connecting through holes.

7. The method according to claim 5, wherein: The at least one connecting through hole comprises a plurality of rows of connecting through holes arranged in parallel, each row of the plurality of connecting through holes comprises a plurality of connecting through holes arranged along a first direction, and each of the at least one bottom electrode layer is a block electrode layer covering two adjacent rows of connecting through holes in the plurality of rows of connecting through holes.

8. The method according to claim 6 or 7, wherein: Each of the at least one covering layer corresponds to each of the at least one connecting through hole to cover a portion of the at least one bottom electrode layer covering the corresponding connecting through hole located on the corresponding connecting through hole.

9. The method according to claim 6, wherein: The at least one row of connecting through holes comprises a plurality of rows of connecting through holes arranged in parallel, each of the at least one covering layer extends along a second direction perpendicular to the first direction, and corresponds to a row of connecting through holes arranged in parallel in the second direction among the plurality of rows of connecting through holes, so as to cover a portion of the at least one bottom electrode layer located on each connecting through hole in the row of connecting through holes.

10. The method according to claim 7, wherein: The at least one bottom electrode layer comprises a plurality of bottom electrode layer groups, each of the plurality of bottom electrode layer groups respectively covers two adjacent rows of connection through holes in the plurality of rows of connection through holes, and a first row of connection through holes in the two rows of connection through holes covered by a first bottom electrode layer in the bottom electrode layer group is adjacent to a second row of connection through holes in the two rows of connection through holes covered by a second electrode layer, and wherein, Each of the at least one covering layer extends along the second direction and corresponds to two adjacent connecting through holes located in the second direction in the four columns of connecting through holes covered by each of the multiple bottom electrode layer groups, so as to cover the portion of the bottom electrode layer group located on each of the two connecting through holes, and the two connecting through holes are respectively covered by two bottom electrode layers in the bottom electrode layer group, and the second direction is perpendicular to the first direction.

11. The method according to claim 6 or 7, further comprising: The at least one bottom electrode layer is patterned to form a plurality of bottom electrodes, each of the plurality of bottom electrodes corresponds to each of the connection through holes in the at least one row of connection through holes, and a portion of the dielectric layer is exposed between two adjacent bottom electrodes of the plurality of bottom electrodes.

12. The method according to claim 6 or 7, wherein: The covering layer includes a dielectric layer and a top electrode stacked in sequence from bottom to top, and the forming of at least one covering layer includes: Depositing a covering material layer to cover the at least one bottom electrode layer and a portion of the dielectric layer exposed between any two of the at least one bottom electrode layer, the covering material layer comprising a dielectric material layer and a top electrode material layer stacked sequentially from bottom to top to cover the at least one bottom electrode layer; forming a third mask layer, the third mask layer at least covering a region where the at least one covering layer is to be formed; and The dielectric material layer and the top electrode material layer are etched using the third mask layer as a mask.

13. A semiconductor device comprising: Semiconductor substrate; a dielectric layer located on the surface of the semiconductor substrate and at least one connecting through hole located in the dielectric layer, wherein the dielectric layer further comprises at least one boss, and each of the at least one boss comprises one or more connecting through holes in the at least one connecting through hole; and At least one covering layer, each of the at least one covering layer covers one of the at least one connecting through hole and extends to cover at least one side wall of the boss where the connecting through hole is located.

14. The semiconductor device according to claim 13, wherein: The at least one connecting through hole includes at least one row of connecting through holes, each row of connecting through holes in the at least one row of connecting through holes includes a plurality of connecting through holes arranged along a first direction, and each of the at least one boss is a strip-shaped boss extending along the first direction and includes a row of connecting through holes in the at least one row of connecting through holes.

15. The semiconductor device according to claim 13, wherein: The at least one connecting through hole comprises a plurality of rows of connecting through holes arranged in parallel, each row of the plurality of rows of connecting through holes comprises a plurality of connecting through holes arranged along a first direction, and each of the at least one boss is a block-shaped boss extending along the first direction and comprises two adjacent rows of connecting through holes in the plurality of rows of connecting through holes.

16. The semiconductor device according to any one of claims 13 to 15, wherein: Each of the at least one capping layer includes a bottom electrode, a dielectric layer, and a top electrode sequentially stacked from bottom to top.

17. The semiconductor device according to any one of claims 13 to 15, wherein: Produced by a method according to any one of claims 1-6.

18. A semiconductor device comprising: Semiconductor substrate; A dielectric layer located on the surface of the semiconductor substrate and at least one connecting through hole located in the dielectric layer, wherein the top surface of each of the at least one connecting through hole is flush with the top surface of the dielectric layer; at least one bottom electrode, each of the at least one bottom electrode covering one of the at least one connecting through-hole; as well as At least one covering layer, wherein each of the at least one covering layer covers each of one or more of the at least one bottom electrode and extends to cover at least one side wall of the bottom electrode, and wherein each of the at least one covering layer corresponds to one of the at least one connecting through hole to cover the bottom electrode in the at least one bottom electrode layer covering the corresponding connecting through hole.

19. The semiconductor device according to claim 18, wherein: The at least one connecting through-hole comprises a plurality of rows of connecting through-holes arranged in parallel, each row of connecting through-holes in the plurality of rows of connecting through-holes comprises a plurality of connecting through-holes arranged along a first direction, and wherein, Each of the at least one covering layer extends along a second direction perpendicular to the first direction and corresponds to a row of connecting through holes in the multiple rows of connecting through holes arranged in parallel in the second direction to cover a bottom electrode of the at least one bottom electrode covering each connecting through hole in the row.

20. The semiconductor device according to claim 18, wherein The at least one connecting through-hole comprises a plurality of rows of connecting through-holes arranged in parallel, each row of connecting through-holes in the plurality of rows of connecting through-holes comprises a plurality of connecting through-holes arranged along a first direction, and wherein, Two adjacent rows of connection through holes in the plurality of rows of connection through holes constitute a connection through hole group, and the first row of connection through holes in the first connection through hole group and the second row of connection through holes in the second connection through hole group in the adjacent two connection through hole groups in the plurality of connection through holes constituted by the plurality of connection through holes are adjacent, and wherein, Each of the at least one covering layer extends along a second direction and corresponds to two adjacent connecting through holes in the second direction to cover the bottom electrode layer located on each of the two connecting through holes, and the two connecting through holes are respectively located in two adjacent connecting through hole groups among the multiple connecting through hole groups, and the second direction is perpendicular to the first direction.

21. The semiconductor device according to any one of claims 18 to 20, wherein: Each of the at least one capping layer includes a dielectric layer and a top electrode sequentially stacked from bottom to top.

22. The semiconductor device according to any one of claims 18 to 20, wherein: Produced by a method according to any one of claims 7-12.

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