A generalized linear active disturbance rejection phase-locked loop and its control circuit

Abstract

The present invention discloses a generalized linear active disturbance rejection phase-locked loop and its control circuit, belonging to the technical field of power electronic converter control. The control circuit includes a grid voltage sampling circuit, an inductor current sampling circuit, a power switch tube driving circuit, and a digital control unit; the digital control unit includes an abc / dq converter, a dq / αβ converter, an active current PI regulator, a reactive current PI regulator, an SPWM controller, an adder, a subtractor, a multiplier, a divider, an integrator, and a proportionality unit. The generalized linear active disturbance rejection phase-locked loop can improve the rapidity of the phase-locked loop by adjusting the ratio of the controller input gain and the observer input gain, and achieve fast and accurate tracking of the grid phase angle.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic converter control, and particularly relates to a generalized linear active disturbance rejection phase-locked loop and its control circuit. Background Art

[0002] Grid connection synchronization technology is an important part of grid connection control technology. Whether accurate phase information of the power grid can be obtained directly determines the quality of the grid-connected current of the grid-connected converter. Power grids with a high proportion of new energy and in remote areas usually show a weak grid situation, where phase and frequency jumps, three-phase imbalance, harmonics and other operating conditions are likely to occur, interfering with the grid-connected converter's acquisition of accurate grid phase information. The existing technical literature "Se-Kyo Chung, A phase tracking system for three phase utility interface inverters, IEEE Transactions on Power Electronics, vol.15, no.3, pp.431-438, May 2000." proposed a Synchronous reference frame phase-locked loop (SRF-PLL). The SRF-PLL uses a PI regulator as the loop filter of the phase-locked loop. The SRF-PLL has a simple structure and is easy to implement. However, when the power grid is distorted, there is a large error in the phase locking of the SRF-PLL. The existing technical literature "Z. Xie, Y Chen, W Wu, W Gong, L Zhou, X Zhou, J.M Guerrero, Admittance Modeling and Sta bility Analysis of Grid-Connected Inverter With LADRC-PLL, I EEETransactions on Industrial Electronics, vol.68, no.12, pp.12272-12284, Dec2021" proposed a Linear active disturbance phase-locked loop (LADRC-PLL). The LADRC-PLL uses an LADRC regulator to replace the PI controller as the loop filter of the phase-locked loop. Compared with the PI regulator, the LADRC regulator has better high-frequency harmonic suppression ability. Therefore, the LADRC-PLL has better performance in unbalanced grid conditions such as imbalance and harmonics. However, the dynamic performance of the LADRC-PLL is worse than that of the SRF-PLL, resulting in difficulty in achieving fast phase locking for the LADRC-PLL in operating conditions such as phase and frequency jumps. Therefore, it is necessary to study a phase-locked loop and control circuit that simultaneously possess anti-interference and rapidity. Summary of the Invention

[0003] To solve the technical problems mentioned in the above background art, the present invention proposes a generalized linear active disturbance rejection phase-locked loop and its control circuit.

[0004] To achieve the above technical objectives, the technical solution of the present invention is as follows:

[0005] A generalized linear active disturbance rejection phase-locked loop and its control circuit, the phase-locked loop is used for a three-phase inverter composed of a DC power supply, a DC bus capacitor, first to sixth switching tubes, three-phase output filter inductors, and a three-phase AC power grid; the control circuit part of the three-phase inverter includes a generalized linear active disturbance rejection phase-locked loop circuit and a grid-connected current control circuit;

[0006] The generalized linear active disturbance rejection phase-locked loop circuit includes a grid voltage sampling circuit, a first abc / dq converter, a first divider, first to third subtractors, first to third adders, first to third integrators, and first to fourth proportionality units;

[0007] Three input terminals of the grid voltage sampling circuit are correspondingly connected to the connection points of the three-phase output filter inductors and the three-phase AC power grid; three output terminals of the grid voltage sampling circuit are correspondingly connected to the input terminals of the first abc / dq converter, and the output terminal of the third integrator is connected to the input terminals of the first abc / dq converter; the second output terminal of the first abc / dq converter u gq is connected to the positive input terminal of the first subtractor, and the output terminal of the first integrator is connected to the negative input terminal of the first subtractor; the output terminal of the first subtractor is connected to the input terminal of the second proportionality unit, the output terminal of the second proportionality unit is connected to the positive input terminal of the first adder, the output terminal of the second adder is connected to the other positive input terminal of the first adder, and the output terminal of the first adder is connected to the input terminal of the first integrator; the output terminal of the first subtractor is connected to the input terminal of the third proportionality unit, the output terminal of the third proportionality unit is connected to the input terminal of the second integrator, the output terminal of the second integrator is connected to the positive input terminal of the second adder, and the output terminal of the fourth proportionality unit is connected to the other positive input terminal of the second adder; a reference signal u qref is connected to the positive input terminal of the second subtractor, and the output terminal of the first integrator is connected to the negative input terminal of the second subtractor; the output terminal of the second subtractor is connected to the input terminal of the first proportionality unit, the output terminal of the first proportionality unit is connected to the positive input terminal of the third subtractor, and the output terminal of the second integrator is connected to the negative input terminal of the third subtractor; the output terminal of the third subtractor is connected to the multiplier input terminal of the first divider, and a controller input gain b is connected to the divisor input terminal of the first divider; the output terminal of the first divider is connected to the input terminal of the fourth proportionality unit; the output terminal of the first divider is connected to the positive input terminal of the third adder, and a grid angular frequency reference signal ω gConnect to the other positive input terminal of the third adder; the output terminal of the third adder is connected to the input terminal of the third integrator, and the output of the third integrator obtains the grid phase θ pll ;

[0008] The grid-connected current control circuit includes an inductor current sampling circuit, a power switch tube driving circuit, a second abc / dq converter, an active current PI regulator, a reactive current PI regulator, a dq / αβ converter, an SPWM controller, a fourth to fifth subtractor;

[0009] The three input terminals of the inductor current sampling circuit are respectively connected to the connection points of the three-phase output filter inductor and the three-phase AC grid; the three output terminals of the inductor current sampling circuit are connected to the input terminal of the second abc / dq converter, and the output terminal of the third integrator is connected to the input terminal of the second abc / dq converter; the first output terminal of the second abc / dq converter i gd is connected to the negative input terminal of the fourth subtractor, and the active current reference signal i dref is connected to the positive input terminal of the fourth subtractor. The output terminal of the fourth subtractor is connected to the input terminal of the active current PI regulator, and the output terminal of the active current PI regulator is connected to the input terminal of the dq / αβ converter; the second output terminal of the second abc / dq converter i gq is connected to the negative input terminal of the fifth subtractor, and the reactive current reference signal i qref is connected to the positive input terminal of the fifth subtractor. The output terminal of the fifth subtractor is connected to the input terminal of the reactive current PI regulator, and the output terminal of the reactive current PI regulator is connected to the other input terminal of the dq / αβ converter; the output terminal of the dq / αβ converter is connected to the input terminal of the SPWM controller, and the output terminal of the SPWM controller is connected to the input terminal of the power switch tube driving circuit. The output terminals of the power switch tube driving circuit are the driving signals of the first to sixth switch tubes u GS1 ~ u GS6 。

[0010] Further, the gain k of the first proportionality p is a constant, the gain β1 of the second proportionality is 10 times the gain k of the first proportionality p , that is, 10×k p , and the gain β2 of the third proportionality is 25 times the square of the gain k of the first proportionality p , that is, 25×k p 2 。

[0011] Further, the controller input gain bis a constant, and the fourth proportional gain b eso is the controller input gain b is 0.707 times of, that is, 0.707× b .

[0012] Beneficial effects brought by adopting the above technical solution:

[0013] The present invention can enable the phase-locked loop to achieve fast phase locking under working conditions such as grid phase and frequency jumps, and at the same time has the ability to suppress high-frequency harmonics. Therefore, the phase-locked loop and control circuit designed by the present invention have broad application prospects in power grids showing a weak grid situation, such as those with a high proportion of new energy and remote areas. Brief Description of the Drawings

[0014] Figure 1 is the control circuit diagram of the present invention;

[0015] Figure 2 is the dynamic waveform of the tracking error of the phase-locked loop of the present invention when the grid undergoes a phase jump;

[0016] Figure 3 is the dynamic waveform of the tracking error of the phase-locked loop of the present invention when the grid undergoes a frequency jump;

[0017] Figure 4 is the dynamic waveform of the tracking error of the phase-locked loop of the present invention when the grid undergoes a voltage sag;

[0018] Figure 5 is the dynamic waveform of the tracking error of the phase-locked loop of the present invention when there are harmonics in the grid. Detailed Embodiments

[0019] The technical solution of the present invention will be described in detail below with reference to the drawings.

[0020] A generalized linear active disturbance rejection phase-locked loop and its control circuit, the control circuit diagram is as shown in Figure 1 . The phase-locked loop is used for a three-phase inverter composed of a DC power supply 1, a DC bus capacitor 2, first to sixth switching tubes 3, a three-phase output filter inductor 4, and a three-phase AC grid 5; the control circuit part 6 of the three-phase inverter includes a generalized linear active disturbance rejection phase-locked loop circuit and a grid-connected current control circuit;

[0021] The generalized linear active disturbance rejection phase-locked loop circuit includes a grid voltage sampling circuit, a first abc / dq converter, a first divider, first to third subtractors, first to third adders, first to third integrators, and first to fourth proportional gains;

[0022] The three input terminals of the grid voltage sampling circuit are correspondingly connected to the connection points between the three-phase output filter inductors and the three-phase AC grid; the three output terminals of the grid voltage sampling circuit are correspondingly connected to the input terminals of the first abc / dq converter, and the output terminal of the third integrator is connected to the input terminals of the first abc / dq converter; the second output terminal of the first abc / dq converter u gq is connected to the positive input terminal of the first subtractor, and the output terminal of the first integrator is connected to the negative input terminal of the first subtractor; the output terminal of the first subtractor is connected to the input terminal of the second proportionality unit, the output terminal of the second proportionality unit is connected to the positive input terminal of the first adder, the output terminal of the second adder is connected to the other positive input terminal of the first adder, and the output terminal of the first adder is connected to the input terminal of the first integrator; the output terminal of the first subtractor is connected to the input terminal of the third proportionality unit, the output terminal of the third proportionality unit is connected to the input terminal of the second integrator, the output terminal of the second integrator is connected to the positive input terminal of the second adder, and the output terminal of the fourth proportionality unit is connected to the other positive input terminal of the second adder; the reference signal u qref is connected to the positive input terminal of the second subtractor, and the output terminal of the first integrator is connected to the negative input terminal of the second subtractor; the output terminal of the second subtractor is connected to the input terminal of the first proportionality unit, the output terminal of the first proportionality unit is connected to the positive input terminal of the third subtractor, and the output terminal of the second integrator is connected to the negative input terminal of the third subtractor; the output terminal of the third subtractor is connected to the multiplier input terminal of the first divider, and the controller input gain b is connected to the divisor input terminal of the first divider; the output terminal of the first divider is connected to the input terminal of the fourth proportionality unit; the output terminal of the first divider is connected to the positive input terminal of the third adder, and the grid angular frequency reference signal ω g is connected to the other positive input terminal of the third adder; the output terminal of the third adder is connected to the input terminal of the third integrator, and the output of the third integrator obtains the grid phase θ pll ;

[0023] The grid-connected current control circuit includes an inductor current sampling circuit, a power switch tube driving circuit, a second abc / dq converter, an active current PI regulator, a reactive current PI regulator, a dq / αβ converter, an SPWM controller, and a fourth to fifth subtractor;

[0024] The three input terminals of the inductor current sampling circuit are respectively connected to the connection points between the three-phase output filter inductors and the three-phase AC grid; the three output terminals of the inductor current sampling circuit are connected to the input terminals of the second abc / dq converter, and the output terminal of the third integrator is connected to the input terminals of the second abc / dq converter; the first output terminal of the second abc / dq converter i gd is connected to the negative input terminal of the fourth subtractor, and the active current reference signali dref is connected to the positive input terminal of the fourth subtractor, the output terminal of the fourth subtractor is connected to the input terminal of the active current PI regulator, and the output terminal of the active current PI regulator is connected to the input terminal of the dq / αβ converter; the second output terminal of the second abc / dq converter i gq is connected to the negative input terminal of the fifth subtractor, the reactive current reference signal i qref is connected to the positive input terminal of the fifth subtractor, the output terminal of the fifth subtractor is connected to the input terminal of the reactive current PI regulator, and the output terminal of the reactive current PI regulator is connected to the other input terminal of the dq / αβ converter; the output terminal of the dq / αβ converter is connected to the input terminal of the SPWM controller, the output terminal of the SPWM controller is connected to the input terminal of the power switch tube drive circuit, and the output terminals of the power switch tube drive circuit are the drive signals of the first to sixth switch tubes u GS1 ~ u GS6 .

[0025] The gain kp of the first proportionality regulator is a constant, and the gain β1 of the second proportionality regulator is 10 times that of the first proportionality regulator k p , that is, 10×k p , and the gain β2 of the third proportionality regulator is 25 times the square of the first proportionality regulator k p , that is, 25×k p 2 .

[0026] The controller input gain b is a constant, and the gain of the fourth proportionality regulator b eso is 0.707 times that of the controller input gain b , that is, 0.707× b .

[0027] Experimental verification: Figure 2 、 Figure 3 、 Figure 4 and Figure 5 are the experimental waveforms of the grid phase tracking when the three-phase inverter uses the control circuit of the present invention. Among them u AN is the grid voltage of phase A, u BN is the grid voltage of phase B, u CN is the grid voltage of phase C, Figure 2 is the error dynamic waveform of the phase-locked loop when the grid undergoes a phase mutation condition, Figure 3 is the error dynamic waveform of the phase-locked loop when the grid undergoes a frequency mutation condition. It can be seen that the phase-locked loop circuit of the present invention can achieve the fastest phase tracking,Figure 3 It is the error dynamic waveform of the phase-locked loop when the power grid has a voltage sag condition. Figure 4 It is the error dynamic waveform of the phase-locked loop when the power grid has a harmonic condition. It can be seen that the phase-locked loop circuit of the present invention can achieve a relatively small phase error.

[0028] The embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. A generalized linear active disturbance rejection phase-locked loop and its control circuit. The phase-locked loop is used for a three-phase inverter composed of a DC power supply, a DC bus capacitor, first to sixth switching tubes, three-phase output filter inductors, and a three-phase AC power grid. The control circuit part of the three-phase inverter includes a generalized linear active disturbance rejection phase-locked loop circuit and a grid-connected current control circuit. It is characterized in that: The generalized linear active disturbance rejection phase-locked loop circuit includes a grid voltage sampling circuit, a first abc / dq converter, a first divider, first to third subtractors, first to third adders, first to third integrators, and first to fourth proportionality regulators; The three input terminals of the grid voltage sampling circuit are correspondingly connected to the connection points between the three-phase output filter inductors and the three-phase AC grid; the three output terminals of the grid voltage sampling circuit are correspondingly connected to the input terminals of the first abc / dq converter, and the output terminal of the third integrator is connected to the input terminals of the first abc / dq converter; the second output terminal of the first abc / dq converter u gq is connected to the positive input terminal of the first subtractor, and the output terminal of the first integrator is connected to the negative input terminal of the first subtractor; the output terminal of the first subtractor is connected to the input terminal of the second proportionality device, the output terminal of the second proportionality device is connected to the positive input terminal of the first adder, the output terminal of the second adder is connected to the other positive input terminal of the first adder, and the output terminal of the first adder is connected to the input terminal of the first integrator; the output terminal of the first subtractor is connected to the input terminal of the third proportionality device, the output terminal of the third proportionality device is connected to the input terminal of the second integrator, the output terminal of the second integrator is connected to the positive input terminal of the second adder, and the output terminal of the fourth proportionality device is connected to the other positive input terminal of the second adder; the reference signal u qref is connected to the positive input terminal of the second subtractor, and the output terminal of the first integrator is connected to the negative input terminal of the second subtractor; the output terminal of the second subtractor is connected to the input terminal of the first proportionality device, the output terminal of the first proportionality device is connected to the positive input terminal of the third subtractor, and the output terminal of the second integrator is connected to the negative input terminal of the third subtractor; the output terminal of the third subtractor is connected to the multiplier input terminal of the first divider, and the controller input gain b is connected to the divisor input terminal of the first divider; the output terminal of the first divider is connected to the input terminal of the fourth proportionality device; the output terminal of the first divider is connected to the positive input terminal of the third adder, and the grid angular frequency reference signal ω g is connected to the other positive input terminal of the third adder; the output terminal of the third adder is connected to the input terminal of the third integrator, and the output of the third integrator gives the grid phase θ pll ; The grid-connected current control circuit includes an inductor current sampling circuit, a power switch tube drive circuit, a second abc / dq converter, an active current PI regulator, a reactive current PI regulator, a dq / αβ converter, an SPWM controller, and fourth to fifth subtractors; The three input terminals of the inductor current sampling circuit are respectively connected to the connection points between the three-phase output filter inductors and the three-phase AC power grid; the three output terminals of the inductor current sampling circuit are connected to the input terminals of the second abc / dq converter, and the output terminal of the third integrator is connected to the input terminals of the second abc / dq converter; the first output terminal of the second abc / dq converter i gd is connected to the negative input terminal of the fourth subtractor, and the active current reference signal i dref is connected to the positive input terminal of the fourth subtractor. The output terminal of the fourth subtractor is connected to the input terminal of the active current PI regulator, and the output terminal of the active current PI regulator is connected to the input terminal of the dq / αβ converter; the second output terminal of the second abc / dq converter i gq is connected to the negative input terminal of the fifth subtractor, and the reactive current reference signal i qref is connected to the positive input terminal of the fifth subtractor. The output terminal of the fifth subtractor is connected to the input terminal of the reactive current PI regulator, and the output terminal of the reactive current PI regulator is connected to the other input terminal of the dq / αβ converter; the output terminal of the dq / αβ converter is connected to the input terminal of the SPWM controller, and the output terminal of the SPWM controller is connected to the input terminal of the power switch tube drive circuit. The output terminals of the power switch tube drive circuit are the drive signals of the first to sixth switch tubes u GS1 ~ u GS6 ; The gain k of the first proportionality factor p is a constant, and the gain β1 of the second proportionality factor is 10 times the gain k of the first proportionality factor p , i.e., 10×k p , and the gain β2 of the third proportionality factor is 25 times the square of the gain k of the first proportionality factor p , i.e., 25×k p 2 ; The controller input gain b is a constant, and the fourth proportional gain b eso is 0.707 times the controller input gain b, that is, 0.707 × b.

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