Amplification circuit and optical navigation device

Abstract

An amplification circuit operable in one of a sampling mode and a sustain mode includes an amplifier and a current supply circuit to supply a first bias current to the amplifier during a power saving time interval when the amplification circuit is operated in the sampling mode and to supply a second bias current to the amplifier when the amplification circuit is operated in the sustain mode, wherein the first bias current is less than the second bias current. An optical navigation device is also provided. The present application can reduce the power consumption of the amplification circuit.

Description

TECHNICAL FIELD

[0001] The present invention relates to an amplification circuit and an optical navigation device using the same, and in particular, to an amplification circuit with lower power consumption and an optical navigation device using the same. BACKGROUND

[0002] Prior art optical navigation devices (e.g. optical mouse) can include multiple amplification circuits, which usually include amplifiers that consume a lot of power when operating. The more amplifiers, the more power is consumed. This can reduce the battery life in the optical navigation device.

[0003] Therefore, there is a need for a new amplification circuit with lower power consumption. SUMMARY

[0004] It is an object of the present invention to disclose an amplification circuit with lower power consumption.

[0005] It is another object of the present invention to disclose an optical navigation device with lower power consumption.

[0006] One embodiment of the present invention discloses an amplification circuit, operable in one of a sampling mode and a sustain mode, comprising: an amplifier; and a current supply circuit configured to supply a first bias current to the amplifier during a power saving time interval when the amplification circuit is operating in the sampling mode, and configured to supply a second bias current to the amplifier when the amplification circuit is operating in the sustain mode; wherein the first bias current is less than the second bias current.

[0007] Another embodiment of the present invention discloses an optical navigation device, comprising an optical sensor and an amplification circuit. The optical sensor is configured to sense optical data to generate an optical sensing signal. The amplification circuit is configured to process the optical sensing signal, and is operable in one of a sampling mode and a sustain mode, comprising: an amplifier; and a current supply circuit configured to supply a first bias current to the amplifier during a power saving time interval when the amplification circuit is operating in the sampling mode, and configured to supply a second bias current to the amplifier when the amplification circuit is operating in the sustain mode; wherein the first bias current is less than the second bias current.

[0008] According to the foregoing embodiments, the power consumption of the amplification circuit can be reduced. Moreover, the electronic device using such an amplification circuit can have a longer battery life. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A circuit diagram of an amplification circuit according to one embodiment of the present invention is shown.

[0010] Figure 2A block diagram of a current supply circuit according to an embodiment of the present application is shown.

[0011] Figure 3 and Figure 4 Waveform diagrams of signals used to control the amplification circuit in Figure 1 and the current supply circuit in Figure 2 are shown according to different embodiments of the present application.

[0012] Figure 5 and Figure 6 Detailed circuits of the current supply circuit shown in Figure 2 are shown.

[0013] Figure 7 A block diagram of a switch control signal generation circuit according to an embodiment of the present application is shown.

[0014] Figure 8 , Figure 9 and Figure 10 Circuit diagrams of detailed circuits of the switch control signal generation circuit shown in Figure 7 are shown according to different embodiments of the present application.

[0015] Figure 11 Waveform diagrams of signals for the circuits shown in Figure 8 , Figure 9 and Figure 10 are shown.

[0016] Figure 12 A block diagram of an optical navigation system using the amplification circuit disclosed in the present application according to an embodiment of the present application is shown.

[0017] In the drawings:

[0018] 100 amplification circuit

[0019] 101 amplifier

[0020] 103 current supply circuit

[0021] 700 switch control signal generation circuit

[0022] 701 mode control circuit

[0023] 703 first logic circuit

[0024] 705 delay circuit

[0025] 707 gate circuit

[0026] 709 output logic circuit

[0027] 1001 OR gate

[0028] 1200 optical navigation device

[0029] AA amplifier

[0030] AD_1, AD_2 ADC

[0031] BT thermal code converter

[0032] BH one-hot encoding converter

[0033] CK clock signal

[0034] CK / 2 divide-by-two clock signal

[0035] CF, CM capacitor

[0036] CS_1, CS_2 current source

[0037] CCS constant current source

[0038] DO, GO output signal

[0039] DL_1 first delay unit

[0040] DL_2 second delay unit

[0041] DL_3 third delay unit

[0042] DP D-type flip-flop

[0043] FA front-end amplifier

[0044] G_1, G_2, G_3, G_4 gate

[0045] I_B1, I_B2, I_B3, I_BN current

[0046] I_bias bias current

[0047] SW, SW_1, SW_(n-2), S_S1, S_S2, S_H1, S_H2 switch

[0048] SEN switch control signal

[0049] SW_S, SW_S1, SW_S(n-2) selection switch

[0050] SEN[0], SEN[1], SEN[n-2] selection signal

[0051] Vin input voltage

[0052] Vout output voltage

[0053] SS sampling mode signal

[0054] SS_DLY switch delay mode signal

[0055] HS hold mode signal

[0056] HS_DLY hold delay mode signal

[0057] SEN switch control signal

[0058] RS_1, RS_2, RH_1, RL_1, RL_2 rising edge

[0059] FH_1, FS_1, FH_2, FL_1 falling edge

[0060] PST power save time interval

[0061] STI sample time interval

[0062] NT normal energy time interval

[0063] PM_1, PM_2, PM_3, PM_4, PW_N P-MOSFET

[0064] inverted hold delay mode signal

[0065] inverted hold mode signal HS

[0066] SWC switch control code

[0067] TC[0], TC[0], TC[2], TC[X], OHC[0], OHC[1], OHC[2] bit

[0068] NG_1 first AND gate

[0069] NG_2 second AND gate

[0070] NG_3 third AND gate

[0071] NG_4 fourth AND gate

[0072] NG_5 fifth AND gate

[0073] NCG non-overlapping clock generator

[0074] IV_1-IV_n inverters

[0075] PA pixel array DETAILED DESCRIPTION

[0076] The present invention will be described below with reference to several embodiments. It should be noted that the elements in each embodiment may be implemented by hardware (e.g., a device or circuit) or firmware (e.g., at least one program written to a microprocessor). Furthermore, the terms "first," "second," and similar descriptions in the following description are used only to define different elements, parameters, data, signals, or steps, and are not intended to limit their order.

[0077] Figure 1 A circuit diagram of an amplifier circuit according to an embodiment of the present invention is shown. Figure 1 As shown, the amplifier circuit 100 can operate in either sampling mode or sustain mode, and includes an amplifier 101, a current supply circuit 103, switches S_S1, S_S2, S_H1, S_H2, and capacitors CF and CM. When the amplifier circuit 100 operates in sampling mode, switches S_S1 and S_S2 are on (conducting), but switches S_H1 and S_H2 are off (not conducting). In this case, the input voltage Vin can charge capacitors CP and CM. Conversely, when the amplifier circuit 100 operates in sustain mode, switches S_S1 and S_S2 are off, and switches S_H1 and S_H2 are on. The amplifier 101 receives a bias current I_bias generated by the current supply circuit 103, so that the components in the amplifier 101 can operate under appropriate conditions to generate an output voltage Vout.

[0078] In one embodiment, when the amplifier circuit operates in sampling mode, the bias current I_bias is a first bias current during the power-saving time interval, and when the amplifier circuit operates in sustain mode, it is a second bias current. The first bias current is less than the second bias current. The amplifier circuit 100 is a switched-capacitor amplifier circuit. However, the present invention is not limited to applications in switched-capacitor amplifier circuits, nor is it limited to applications in circuits with... Figure 1 The amplifier circuit shown has the circuit structure shown.

[0079] Figure 2 A block diagram of a current supply circuit 103 according to an embodiment of the present invention is shown. Figure 2 As shown, the current supply circuit 103 includes current sources CS_1 and CS_2 and a switch SW. Current sources CS_1 and CS_2 generate currents I_B1 and I_B2, respectively. During the power-saving period of the sampling mode, the switch SW, controlled by the switch control signal SEN, is closed, so the bias current I_bias is current I_B1 (the first bias current). Furthermore, in the sustain mode, the switch SW is open, so the bias current I_bias is I_B1 + I_B2 (the second bias current).

[0080] Figure 3 and Figure 4 Waveform diagrams of signals according to different embodiments of the present invention are illustrated, these signals being used for controlamplification circuit in Figure 1 and Figure 2 current supply circuit in Figure 3 In an embodiment of the application, the sampling mode signal SS is used to control Figure 1 switches S_S1 and S_S2 in Figure 1 switches S_H1 and S_H2 in Figure 2 When the sampling mode signal SS has a high logic value (i.e. sampling mode), switches S_S1 and S_S2 are on, and when the sampling mode signal SS has a low logic value, switches S_S1 and S_S2 are off. When the hold mode signal HS has a high logic value (i.e. hold mode), switches S_H1 and S_H2 are on, and when the hold mode signal HS has a low logic value, switches S_H1 and S_H2 are off. When the switch control signal SEN has a high logic value (i.e. power saving time interval PST), switch SW in Figure 1 and Figure 2 bias current I_bias in Figure 2 is a first bias current (I_B1). Conversely, when the switch control signal SEN has a low logic value, switch SW in Figure 1 and Figure 2 bias current I_bias in

[0081] According to the waveform diagram shown in Figure 3 , the amplification circuit 100 operates in sampling mode during the sampling time interval STI. The power saving time interval PST only occupies a portion of the sampling time interval STI. Furthermore, in an embodiment, the power saving time interval PST is inversely proportional to the speed at which the amplification circuit reaches a steady state of operation. That is, if the amplification circuit 100 can reach a steady state of operation in a short time (i.e. has a high speed), the power saving time interval PST can be set to be longer, in order to save more power. Conversely, if the amplification circuit 100 needs a longer time to reach a steady state of operation (i.e. has a low speed), the power saving time interval PST needs to be set to be shorter. The completion of the sampling action can mean, for example, that the capacitors CP and CM have been charged to the voltage level of the input voltage Vin. The action of the "amplification circuit 100 reaching a steady state of operation" can be, for example, the amplification circuit 100 completing its DC biasing state.

[0082] Please refer again to Figure 3 , since the power saving time interval PST only occupies a portion of the sampling time interval STI, the sampling time interval STI also includes a normal power time interval NT. In an embodiment, the current supply circuit 103 provides the second bias current to the amplifier 101 during the normal power time interval NT.

[0083] In Figure 3 the embodiment, the rising edge RS_1 of the sampling mode signal SS, the falling edge FH_1 of the hold mode signal HS, and the rising edge RL_1 of the switch control signal SEN occur simultaneously. Also, the falling edge FS_1 of the sampling mode signal SS and the rising edge RH_1 of the hold mode signal HS occur simultaneously. However, in reality, there can be a time delay between these edges. For example, as shown in Figure 4 Fig. 6, there is a time delay between the rising edge RS_1 of the sampling mode signal SS, the falling edge FH_1 of the hold mode signal HS, and the rising edge RL_1 of the switch control signal SEN, and there is also a time delay between the falling edge FS_1 of the sampling mode signal SS and the rising edge RH_1 of the hold mode signal HS. This time delay can be intentionally set for the operation of the amplification circuit 100, or it can be caused by the limitation of the components of the amplification circuit 100. Such variations should also fall within the scope of the present application.

[0084] Figure 2 The current supply circuit 103 in Figure 5 Fig. 5 can be implemented by various circuits. Figure 2 Fig. 6 shows the detailed circuit of the current supply circuit shown in Figure 5 Fig. 5. As shown in Fig. 6, the current supply circuit 103, which is a current mirror circuit in this embodiment, includes P-MOSFETs PM_1, PM_2, PM_3, PM_4 (switch SW), and a constant current source CCS. The P-MOSFETs PM_1, PM_2, PM_3, PM_4 can be controlled to supply one of the first bias current (I_B1) and the second bias current (I_B1+I_B2), and can be replaced with N-MOSFETs.

[0085] Figure 2 In Figure 5 the embodiment, the current supply circuit 103 includes two branches that supply the current I_B1 and the current I_B2, respectively. However, the current supply circuit 103 can include more than two branches. As shown in Figure 6As shown, the current supply circuit 103 includes more than two branches, which include a constant current source CCS, PMOSFET PM_1-PM_N, switches SW, SW_1...SW_(n-2), and selection switches SW_S, SW_S1...SW_S(n-2). The switches SW, SW_1...SW_(n-2) are controlled by the switch control signal SEN, and the selection switches SW_S, SW_S1...SW_S(n-2) are controlled by different bits of the selection signal SEN[0], SEN[1]...SEN[n-2]. By controlling the switches SW, SW_1...SW_(n-2) and the selection switches SW_S, SW_S1...SW_S(n-2), the bias current I_bias can be any combination of the currents I_B1...I_BN. By such a structure, the bias current I_bias can be further reduced in the power saving time interval PST, and the power consumption can be further reduced.

[0086] Various circuits can be used to generate the switch control signal SEN. Figure 7 A block diagram of a switch control signal generation circuit 700 for an embodiment of the present application. As shown, the switch control signal generation circuit 700 includes a binary to thermometer code converter BT, a binary to one hot code converter BH, a mode control circuit 701, a first logic circuit 703, a delay circuit 705, a gate circuit 707, and an output logic circuit 709. Figure 7

[0087] The mode control circuit 701 is used to receive a clock signal CK to generate a sampling mode signal SS, a hold mode signal HS, and an inverted and delayed hold mode signal The binary to thermometer code converter BT is used to receive a switch control code SWC. The first logic circuit 703, which includes at least one logic gate, is used to receive an output signal of the binary to thermometer code converter BT. The delay circuit 705 is used to receive an output signal of the first logic circuit 703. The binary to one hot code converter BH is used to receive the switch control code SWC. The gate circuit 707 is used to pass at least a portion of an output signal DO of the delay circuit 705 according to an output signal of the binary to thermometer code converter BH and a bit TC[X] of the output signal of the binary to thermometer code converter BT. The output logic circuit 709 is used to generate the switch control signal SEN according to the output signal DO of the delay circuit 705, an output signal GO of the gate circuit 707, and the inverted and delayed hold mode signal The switch control signal SEN is generated.

[0088] Figure 7 The block diagram as shown can be implemented by various circuits. Figure 8 , Figure 9 and​Figure 10 Fig. 1 illustrates a circuit diagram of a switch control signal generation circuit according to a first embodiment of the present application; Figure 7 Fig. 2 illustrates a circuit diagram of a detailed circuit of the switch control signal generation circuit shown in Fig. 1. Reference is made to Figure 8 Figure 9 Figure 10 Fig. 3 illustrates a circuit diagram of a detailed circuit of the switch control signal generation circuit shown in Fig. 1. Reference is made to Figure 7 Fig. 4 illustrates a circuit diagram of a detailed circuit of the switch control signal generation circuit shown in Fig. 1. Reference is made to

[0089] As shown in Fig. 1, the first logic circuit 703 includes a plurality of AND gates NG_1-NG_3 for receiving in parallel the bits TC[0]-TC[2] of the output signal of the thermometer code converter BT. In addition, the delay circuit 705 includes a plurality of delay units DL_1-DL_2 for receiving in parallel the output signals of the AND gates NG_1-NG_3. The gate circuit 707 includes a plurality of gates G_1-G_4, which are controlled by different bits OHC[0]-OHC[2] of the output signal of the one-hot code converter BH. In addition, the gate circuit 707 includes a gate G_4, which receives the inverted value of the first bit TC[0] of the output signal of the thermometer code converter BT. Figure 8

[0090] In particular, the first logic circuit 703 includes a first AND gate NG_1, a second AND gate NG_2 and a third AND gate NG_3. The delay circuit 705 includes a first delay unit DL_1, a second delay unit DL_2 and a third delay unit DL_3. The first AND gate NG_1 is arranged to receive the clock signal CK and the first bit TC[0] of the output signal of the thermometer code converter BT. The second AND gate NG_2 is arranged to receive the second bit TC[1] of the output signal of the thermometer code converter BT. The first delay unit DL_1 is coupled to the output of the first AND gate NG_1, and the second AND gate NG_2 further receives the output signal of the first delay unit DL_1. The third AND gate NG_3 is connected to the second delay unit DL_2 in a similar manner as the second AND gate NG_2 is connected to the first delay unit DL_1, and thus will not be described again. The third delay unit DL_3 is coupled between the third AND gate NG_3 and the gate G_3. The gates G_1-G_3 receive the output signals of the first delay unit DL_1, the second delay unit DL_2 and the third delay unit DL_3, respectively.

[0091] The thermometer code converter BT and the one-hot code converter BH are converters for converting one code into another code, so that the subsequent circuit can be controlled by the input thereof. Table 1 illustrates an example of the relationship between the bits TC[0]-TC[2] of the output signal of the thermometer code converter BT, the bits OHC[0]-OHC[2] of the output signal of the one-hot code converter BH and the switch control code SWC. The skilled person will understand the specific details of the thermometer code converter BT and the one-hot code converter BH, and thus will not be described again.​​​

[0092]

[0093]

[0094] Table 1

[0095] Figure 9 A circuit diagram of a mode control circuit 701 according to an embodiment of the present invention is shown. Figure 9 As shown, the mode control circuit 701 includes a D-type flip-flop DP, a non-overlapping clock generator NCG, and inverters IV_1-IV_n. The D-type flip-flop DP is used to divide the clock signal CK to generate a divided clock signal CK / 2, which is then fed to the output logic circuit 709. The non-overlapping clock generator NCG generates a switch mode signal SS, a sustain mode signal HS, a delay switching mode signal SS_DLY, and a delay sustain mode signal HS_DLY. One of the inverters IV_1-IV_n receives the delay sustain mode signal HS_DLY to generate an inverted delay sustain mode signal. The details of the non-overlapping clock generator (NCG) are well known to those skilled in the art and will not be repeated here for the sake of brevity.

[0096] Figure 10 A circuit diagram of an output logic circuit 709 according to an embodiment of the present invention is shown. Figure 10 As shown, the output logic circuit 709 includes a fourth AND gate NG_4, a fifth AND gate NG_5, and an OR gate 1001. The fourth AND gate NG_4 is used to receive the frequency-divided signal of the clock signal CK (i.e., the frequency-divided clock signal CK / 2) and to receive the inverted delay sustain mode signal. OR gate 1001 is used to receive one of the output signals of delay circuit 705 and to selectively receive the output signal of gate circuit 707. Specifically, one input terminal of OR gate 1001 selectively receives... Figure 8 The gates G_1-G_ shown receive output signals from the first delay unit DL_1, the second delay unit DL_2, and the third delay unit DL_3. Another input terminal of the OR gate 1001 receives the output signal from the first delay unit DL_1. The fifth AND gate NG_5 receives the output signal from the fourth AND gate NG_4 and the output signal from the OR gate 1001 to generate the switch control signal SEN.

[0097] Figure 11 for Figure 8 , Figure 9 as well as Figure 10 The waveform diagram of the signal in the circuit shown. More specifically, Figure 11The clock signal CK, the divided clock signal CK / 2, the sampling mode signal SS, the delayed switch mode signal SS_DLY, the hold mode signal HS, the delayed hold mode signal HS_DLY, the inverted delayed hold mode signal The output signal DO of the delay circuit 705, the output signal GO of the gate circuit 707, and the switch control signal SEN. As shown, the output signal DO and the output signal GO vary with different switch control codes SWC, so that different switch control signals SEN can be generated. Therefore, the current provided by the current source in Figure 11 Figure 2

[0098] The foregoing amplification circuit can be applied in an optical navigation device, but is not limited thereto. Figure 12 A block diagram of an optical navigation system 1200 using the amplification circuit disclosed herein is shown in accordance with an embodiment of the present application. As shown, the optical navigation device 1200, such as an optical mouse or an optical touch sensing device, includes a pixel array PA (i.e., an optical sensor), a plurality of front-end amplifiers FA (only two of which are shown), and a plurality of ADCs (Analog to Digital Converters) AD_1, AD_2 (only two of which are shown). The pixel array PA is used to sense optical data (e.g., images) to generate optical sensing signals, and the front-end amplifiers FA and the amplifiers AA in the ADCs AD_1, AD_2 are used to process the optical sensing signals. Figure 12

[0099] The amplified and digitized optical sensing signals are transmitted to a digital core for further processing. The optical navigation device 1200 can determine the relative position between the optical navigation device 1200 and an object (e.g., a table top or a finger) based on the optical data sensed by the pixel array PA. Since the optical navigation device 1200 includes a plurality of amplification circuits, the power consumption can be greatly reduced if the amplification circuits employ the architecture described in the foregoing embodiments. Therefore, the battery operation time of the optical navigation device 1200 can be prolonged. This advantage is particularly significant when the optical navigation device 1200 operates in a low power start-up mode.

[0100] In one embodiment, when the optical navigation device 1200 operates in a start-up mode, the current supply circuit 103 supplies a first bias current (e.g., I_B1 in Figure 2 a second bias current (e.g., I_B1+I_B2 in Figure 2 and a third bias current (e.g., I_B1+I_B2+I_B3 in Figure 2 ​​​one of I_B1 and I_B2) to an amplifier in the amplification circuit. In the low power startup mode, the optical navigation device 1200 does not need high quality optical data to determine the relative position, so the second bias current or the third bias current from the current supply circuit 103 can be disabled. This action can be achieved by Figure 6 The circuit shown in FIG. 12 is used to achieve the low power startup mode, but is not limited thereto. In one embodiment, the startup mode refers to the optical navigation device 1200 operating at a higher speed or requiring higher quality optical data, and the low power startup mode refers to the optical navigation device 1200 operating at a lower speed or requiring lower quality optical data.

[0101] According to the foregoing embodiments, the power consumption of the amplification circuit can be reduced. Moreover, the electronic device using the amplification circuit can have a longer battery operating time.

[0102] The foregoing is only the preferred embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. An amplifier circuit capable of operating in either a sampling mode or a sustain mode, characterized in that, comprising: an amplifier; a current supply circuit for providing a first bias current to the amplifier during a power saving time interval when the amplifying circuit operates in a sampling mode, and for providing a second bias current to the amplifier when the amplifying circuit operates in a sustain mode; wherein the first bias current is less than the second bias current; and a switch control signal generating circuit comprising: a mode control circuit for receiving a clock signal to generate a sampling mode signal, a sustain mode signal, and an inverted delayed sustain mode signal, wherein the amplifying circuit operates in one of the sampling mode and the sustain mode according to the sampling mode signal and the sustain mode signal; a hot code converter for receiving a switch control code; a first logic circuit for receiving an output signal of the hot code converter; a delay circuit for receiving an output signal of the first logic circuit; a one-hot encoder converter for receiving the switch control code; a gate circuit for passing at least a portion of the output signal of the delay circuit according to an output signal of the one-hot encoder converter and a bit of the output signal of the hot code converter; an output logic circuit for generating the switch control signal according to the output signal of the delay circuit, an output signal of the gate circuit, and the inverted delayed sustain mode signal; wherein the current supply circuit comprises a switch controlled by the switch control signal; when the switch is closed, the current supply circuit generates the first bias current, and when the switch is open, the current supply circuit generates the second bias current.

2. The amplification circuit of claim 1, wherein the amplifying circuit operates in the sampling mode during a sampling time interval, wherein the power saving time interval only occupies a portion of the sampling time interval, and the power saving time interval is inversely proportional to a speed at which the amplifying circuit completes a direct current bias state of the amplifying circuit.

3. The amplification circuit of claim 1, wherein the amplifying circuit operates in the sampling mode during a sampling time interval, the sampling mode comprising the power saving time interval and a normal power time interval, wherein the current supply circuit provides the second bias current to the amplifier during the normal power time interval.

4. The amplifying circuit of claim 3, wherein: the first logic circuit comprises a plurality of AND gates for receiving bits of the output signal of the hot code converter in parallel; the delay circuit comprises a plurality of delay units for receiving output signals of the AND gates in parallel; the gate circuit comprises a plurality of gates controlled by different bits of the output signal of the one-hot encoder converter.

5. The amplifying circuit of claim 4, wherein: the first logic circuit comprises: a first AND gate for receiving the clock signal and a first bit of the output signal of the hot code converter; a second AND gate for receiving a second bit of the output signal of the hot code converter; the delay circuit comprises: a first delay unit coupled to an output of the first AND gate, wherein the second AND gate further receives an output signal of the first delay unit.

6. The amplification circuit of claim 1, wherein, the output logic circuit comprises: a fourth AND gate for receiving a divided signal of the clock signal and for receiving the inverted delayed sustain mode signal; an OR gate for selectively passing one of the output signals from the delay circuit through the gate circuit; a fifth AND gate for receiving the output signal of the fourth AND gate and the output signal of the OR gate to generate the switch control signal.

7. An optical navigation device, characterized by comprising: an optical sensor for sensing optical data to generate an optical sensing signal; and an amplification circuit for processing the optical sensing signal, operable in one of a sampling mode and a sustain mode, comprising: an amplifier; a current supply circuit for providing a first bias current to the amplifier during a power saving time interval when the amplification circuit is operated in the sampling mode, and for providing a second bias current to the amplifier when the amplification circuit is operated in the sustain mode; wherein the first bias current is less than the second bias current; and a switch control signal generation circuit, comprising: a mode control circuit for receiving a clock signal to generate a sampling mode signal, a sustain mode signal, and an inverted sustain mode signal, wherein the amplification circuit is operated in one of the sampling mode and the sustain mode according to the sampling mode signal and the sustain mode signal; a hot code converter for receiving a switch control code; a first logic circuit for receiving an output signal of the hot code converter; a delay circuit for receiving an output signal of the first logic circuit; a one-hot encoder converter for receiving the switch control code; a gate circuit for passing at least a portion of the output signal of the delay circuit according to bits of the output signal of the one-hot encoder converter and the output signal of the hot code converter; an output logic circuit for generating the switch control signal according to the output signal of the delay circuit, an output signal of the gate circuit, and the inverted sustain mode signal; wherein the current supply circuit comprises a switch controlled by the switch control signal; when the switch is closed, the current supply circuit generates the first bias current, and when the switch is open, the current supply circuit generates the second bias current.

8. The optical navigation device of claim 7, wherein, the amplification circuit is operated in the sampling mode during a sampling time interval, wherein the power saving time interval only occupies a portion of the sampling time interval, and the power saving time interval is inversely proportional to a speed at which the amplification circuit completes a DC bias state of the amplification circuit.

9. The optical navigation device of claim 7, wherein, the amplification circuit is operated in the sampling mode during a sampling time interval, the sampling mode comprising the power saving time interval and a normal power time interval, wherein the current supply circuit provides the second bias current to the amplifier during the normal power time interval.

10. The optical navigation device of claim 7, wherein: the first logic circuit comprises a plurality of AND gates for receiving bits of the output signal of the hot code converter in parallel; the delay circuit comprises a plurality of delay units for receiving output signals of the AND gates in parallel; the gate circuit comprises a plurality of gates controlled by different bits of the output signal of the one-hot encoder converter.

11. The optical navigation device of claim 10, wherein: the first logic circuit comprises: a first AND gate to receive the clock signal and to receive a first bit of the output signal of the thermometer converter; a second AND gate to receive a second bit of the output signal of the thermometer converter; the delay circuit comprises: a first delay unit coupled to an output of the first AND gate, wherein the second AND gate further receives an output signal of the first delay unit.

12. The optical navigation device of claim 7, wherein, wherein the output logic circuit comprises: a fourth AND gate to receive a divided clock signal of the clock signal and to receive the inverted delay-maintained mode signal; an OR gate to selectively pass one of the output signals from the delay circuit through the gate circuit; a fifth AND gate to receive an output signal of the fourth AND gate and an output signal of the OR gate to generate the switch control signal.

13. The optical navigation device of claim 7, wherein: when the optical navigation device operates in a start-up mode, the current supply circuit provides one of the first bias current, the second bias current, and the third bias current to the amplifier; when the optical navigation device operates in a low-power start-up mode, the current supply circuit does not provide the first bias current and the third bias current.

Images