Image sensing device

Abstract

An image sensing device includes: a pixel array of pixels that are operable to sense light to generate pixel signals and are operable to operate in one of a plurality of modes when sensing light, wherein a first pixel of the pixel array is controlled to operate in a mode selected from the plurality of modes and is configured to output a pixel signal in response to light incident on the first pixel; and an analog-to-digital converter ADC, which is connected to the pixel array to receive the pixel signal from the first pixel and is configured to set an input range indicating a voltage range of the pixel signal based on the mode selected for the first pixel when generating the pixel signal, and perform analog-to-digital conversion of the pixel signal generated by the first pixel based on the input range of the analog-to-digital converter ADC to generate pixel data representing the pixel signal.

Description

Technical Field

[0001] The techniques and implementations disclosed in this patent document generally relate to an image sensing device including pixels capable of operating in various modes. Background Art

[0002] Image sensing devices capture optical images by converting light into electrical signals using photosensitive semiconductor materials. With the development of the automotive, medical, computer, and communications industries, demand for high-performance image sensing devices is increasing in various fields such as smartphones, digital cameras, game consoles, the Internet of Things (IoT), robotics, security cameras, and medical micro cameras.

[0003] Image sensing devices can be broadly categorized as CCD (charge coupled device) image sensing devices and CMOS (complementary metal oxide semiconductor) image sensing devices. Compared to CMOS image sensing devices, CCD image sensing devices provide better image quality, but they tend to consume more power and are larger. Compared to CCD image sensing devices, CMOS image sensing devices are smaller in size and consume less power. In addition, CMOS sensors are manufactured using CMOS manufacturing technology, so the photosensitive element and other signal processing circuits can be integrated into a single chip, allowing miniaturized image sensing devices to be produced at a lower cost. For these reasons, CMOS image sensing devices are being developed for many applications, including mobile devices. Summary of the Invention

[0004] Various embodiments of the disclosed technology are directed to an image sensing device including an analog-to-digital converter (ADC) configured to perform an operation suitable for a mode of pixels.

[0005] According to an embodiment of the disclosed technology, an image sensing device may include: a pixel array of pixels operable to sense light to generate pixel signals and operable to operate in one of a plurality of modes when sensing light, wherein a first pixel of the pixel array is controlled to operate in a mode selected from the plurality of modes and is configured to output a pixel signal in response to light incident on the first pixel; and an analog-to-digital converter (ADC) connected to the pixel array to receive a pixel signal from the first pixel and configured to set an input range indicating a voltage range of the pixel signal based on the mode selected for the first pixel when generating the pixel signal, and perform analog-to-digital conversion of the pixel signal generated by the first pixel based on the input range of the analog-to-digital converter (ADC) to generate pixel data representing the pixel signal.

[0006] According to another embodiment of the disclosed technology, an image sensing device may include: a pixel operable to sense light in one of different modes having different sensing characteristics and configured to output a pixel signal in response to incident light when controlled to operate in a mode selected from the different modes; an analog-to-digital converter (ADC) configured to receive a pixel signal from the pixel operating in the selected mode and convert the pixel signal into pixel data based on an input range of the ADC set according to a mode selected from the different modes in which the pixel operates when sensing incident light; and a timing controller coupled to communicate with the ADC and configured to control the ADC to set an input range of the ADC based on the selected mode of the pixel. The input range is a voltage range within which the ADC is operable to perform analog-to-digital conversion of the pixel signal when the pixel signal is within the input range.

[0007] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0010] Figure 2 is a diagram showing some implementations based on the disclosed technology. Figure 1 A conceptual diagram illustrating an example of a method of changing the input range of an analog-to-digital converter (ADC) of an image sensing device is shown.

[0011] Figure 3 Some implementations based on the disclosed technology are shown Figure 1 A circuit diagram showing an example of the internal structure of an ADC.

[0012] Figure 4 is a control diagram showing some implementations of the disclosed technology. Figure 3 A graph showing an example of the method of varying the input range of the ADC.

[0013] Figure 5 is a circuit diagram illustrating an example of a pixel based on some implementations of the disclosed technology.

[0014] Figure 6 This is a diagram showing some implementations based on the disclosed technology. Figure 5A conceptual diagram of an example of a method of controlling the input range of an ADC by a pixel is shown.

[0015] Figure 7A is a graph showing an example of a dynamic range achieved by a comparative example of the disclosed technology.

[0016] Figure 7B is a graph illustrating an example of the dynamic range achieved by one implementation of the disclosed technology.

[0017] Figure 8A Some implementations based on the disclosed technology are shown Figure 1 A diagram showing an example of an operating scheme of a pixel array is shown.

[0018] Figure 8B Some implementations based on the disclosed technology are shown Figure 1 FIG. 1 is a diagram illustrating another example of an operating scheme of a pixel array.

[0019] Figure 8C It is shown that it can be used as Figure 8A Single pixel shown and / or Figure 8B A circuit diagram of an example of a pixel with binning pixel operation is shown.

[0020] Figure 9 This is a diagram showing some implementations based on the disclosed technology. Figure 8C A conceptual diagram of an example of a method of controlling the input range of an ADC by a pixel is shown.

[0021] Figure 10A It shows Figure 8A A diagram showing an example of pixel data for multiple single pixels.

[0022] Figure 10B This is a comparative example showing the disclosed technology. Figure 8B A diagram of an example of pixel data for multiple binned pixels is shown.

[0023] Figure 10C Some implementations based on the disclosed technology are shown Figure 8B A diagram showing an example of pixel data for a merged pixel is shown. DETAILED DESCRIPTION

[0024] The disclosed technology provides implementations and examples of image sensing device designs that include pixels capable of operating in various modes. Some implementations of the disclosed technology relate to image sensing devices that include an analog-to-digital converter (ADC) configured to perform operations corresponding to the pixel modes. The disclosed technology provides various implementations of image sensing devices that can change the input range of the analog-to-digital converter (ADC) based on each pixel mode to obtain pixel data optimized for each pixel mode. The disclosed technology can be implemented in various ways to provide one or more effects, characteristics, advantages, or benefits.

[0025] Figure 1 is a block diagram illustrating an image sensing device 100 according to an embodiment of the disclosed technology.

[0026] Reference Figure 1 , the image sensing device 100 may include a pixel array 110, a row driver 120, a correlated double sampler (CDS) 130, an analog-to-digital converter (ADC) 140, an output buffer 150, a column driver 160, and a timing controller 170. For example only Figure 1 While the components of image sensing device 100 are shown, this patent document encompasses numerous other alterations, substitutions, variations, changes, and modifications.

[0027] The pixel array 110 may include a plurality of unit imaging pixels arranged in rows and columns. In one example, the plurality of unit imaging pixels may be arranged in a two-dimensional pixel array including rows and columns. In another example, the plurality of unit imaging pixels may be arranged in a three-dimensional pixel array. The plurality of unit pixels may convert an optical input scene or received incident light into an electrical signal on a unit pixel basis (where each unit pixel generates an electrical signal representing light received by the unit pixel) or on a pixel group basis (where different adjacent unit pixels are grouped together to generate, for a pixel group, electrical signals representing light received by different pixels within the pixel group, and the different unit pixels in the pixel group share at least some internal circuitry). The pixel array 110 may receive drive signals including a row select signal, a pixel reset signal, and a transfer signal from the row driver 120. Upon receiving the drive signals, the corresponding imaging pixels in the pixel array 110 may be enabled to perform optical sensing and / or signal processing operations corresponding to the row select signal, the pixel reset signal, and the transfer signal.

[0028] The row driver 120 may enable the pixel array 110 to perform certain operations on the imaging pixels in the corresponding row based on command and control signals provided by a controller circuit such as the timing controller 170. In some implementations, the row driver 120 may select one or more imaging pixels arranged in one or more rows of the pixel array 110. The row driver 120 may generate a row select signal to select one or more rows from the plurality of rows. The row driver 120 may sequentially enable a pixel reset signal for resetting the imaging pixels corresponding to at least one selected row and a transfer signal for the pixels corresponding to the at least one selected row. Thus, as analog signals generated by the respective imaging pixels in the selected row, a reference signal and an image signal may be sequentially transmitted to the CDS 130. The reference signal may be an electrical signal provided to the CDS 130 when a sensing node (e.g., a floating diffusion node) of the imaging pixel is reset, and the image signal may be an electrical signal provided to the CDS 130 when photocharge generated by the imaging pixel accumulates in the sensing node.

[0029] CMOS image sensors can use correlated double sampling (CDS) to remove unwanted pixel offset values ​​(referred to as fixed pattern noise) by sampling the pixel signal twice to remove the difference between the two samples. In one example, correlated double sampling (CDS) can remove unwanted pixel offset values ​​by comparing the pixel output voltages obtained before and after the photocharge generated by incident light accumulates in the sensing node, allowing only the pixel output voltage based on the incident light to be measured. In some embodiments of the disclosed technology, CDS 130 can sequentially sample and maintain the voltage levels of the reference signal and image signal provided to each of the multiple column lines from pixel array 110. That is, CDS 130 can sample and maintain the voltage levels of the reference signal and image signal corresponding to each column of pixel array 110.

[0030] In some implementations, the CDS 130 may transmit the reference signal and the image signal of each column as a correlated double sampling signal to the ADC 140 based on a control signal from the timing controller 170 .

[0031] ADC 140 is used to convert the analog CDS signal into a digital signal. In some implementations, ADC 140 can be implemented as a ramp comparator ADC. The ramp comparator ADC may include a comparator circuit for comparing the analog pixel signal with a reference signal such as a ramp signal that ramps up or down, and a timer counts until the voltage of the ramp signal matches the analog pixel signal. In some embodiments of the disclosed technology, ADC 140 can convert the correlated double sampling signal generated by CDS 130 for each column into a digital signal and output the digital signal. ADC 140 can perform counting and calculation operations based on the correlated double sampling signal of each column and the ramp signal provided from the timing controller 170. In this way, ADC 140 can eliminate or reduce noise (e.g., reset noise) originating from imaging pixels when generating digital image data.

[0032] ADC 140 may include a plurality of column counters. Each column of pixel array 110 is coupled to a column counter, and image data may be generated by converting a correlated double sampling signal received from each column into a digital signal using the column counter. In another embodiment of the disclosed technology, ADC 140 may include a global counter to convert the correlated double sampling signal corresponding to each column into a digital signal using a global code provided by the global counter.

[0033] The output buffer 150 may temporarily hold the column-based image data provided from the ADC 140 to output the image data. In one example, the image data provided from the ADC 140 to the output buffer 150 may be temporarily stored in the output buffer 150 based on a control signal of the timing controller 170. The output buffer 150 may provide an interface to compensate for a data rate difference or a transmission rate difference between the image sensing device 100 and other devices.

[0034] The column driver 160 may select a column of the output buffer upon receiving a control signal from the timing controller 170, and sequentially output image data temporarily stored in the selected column of the output buffer 150. In some implementations, upon receiving an address signal from the timing controller 170, the column driver 160 may generate a column selection signal based on the address signal and select a column of the output buffer 150, thereby outputting image data from the selected column of the output buffer 150 as an output signal.

[0035] The timing controller 170 may be coupled to control operations of the row driver 120 , the ADC 140 , the output buffer 150 , and the column driver 160 .

[0036] The timing controller 170 may be coupled to or otherwise communicate with the row driver 120, the column driver 160, and the output buffer 150 to provide the row driver 120, the column driver 160, and the output buffer 150 with clock signals required for the operation of the various components of the image sensing device 100, control signals for timing control, and address signals for selecting rows or columns. In embodiments of the disclosed technology, the timing controller 170 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0037] The timing controller 170 may include a mode selector 180 and an input range (IR) controller 190, which are coupled to allow the input range (IR) controller 190 to receive information about the mode selected by the mode selector 180 so that the input range (IR) controller 190 can control the ADC 140 based on the selected mode. The mode selector 180 may determine the mode of each pixel of the pixel array 110 and may transmit information about the determined mode to the row driver 120 and the IR controller 190.

[0038] In some implementations, the mode of each pixel may refer to an operating mode corresponding to each of a plurality of conversion gains (e.g., high conversion gain HCG, medium conversion gain MCG, and low conversion gain LCG) implemented for improved imaging sensing under different lighting conditions to form a high dynamic range (HDR) image. The conversion gain may refer to a ratio of converting the amount of photocharge generated in each pixel into a voltage of a pixel signal output from the pixel.

[0039] In some other implementations, the mode of each pixel may include an operating mode corresponding to the number of unit pixels that can be simultaneously read out from the shared pixel structure (e.g., a single mode and a merged mode). Here, the single mode may refer to an operating mode in which the number of unit pixels that can be simultaneously read out from the shared pixel structure is set to "1", and the merged mode may refer to an operating mode in which the number of unit pixels that can be simultaneously read out from the shared pixel structure is set to 2 or greater.

[0040] In some implementations, all pixels included in pixel array 110 may be controlled to operate in the same mode selected from different available modes. In some other implementations, pixels included in pixel array 110 may operate in different modes when imaging an object. For example, in an operation in which pixel array 110 images an object, some pixels of pixel array 110 may operate in a specific mode, and the remaining pixels may operate in one or more modes different from the specific mode.

[0041] The IR controller 190 may be coupled to or communicate with the ADC 140 to control the ADC 140 to perform analog-to-digital conversion (ADC) processing on the pixel signal of each pixel within an input range corresponding to the mode of each pixel. In some implementations, the input range of the ADC 140 may refer to a voltage range of a pixel signal that can be effectively converted into digital pixel data within a predetermined output range (e.g., a digital number (DN) of 0 to 1023). In this case, effective conversion of a pixel signal may indicate that the digital number (DN) of the pixel data of the ADC 140 increases or decreases in response to an increase or decrease in the voltage of the pixel signal. Although pixel signals within the input range of the ADC 140 can be converted into digital pixel data corresponding to the pixel signal, if the pixel signal is not within the input range of the ADC 140, such pixel signal may not be correctly converted into pixel data corresponding to the pixel signal. For example, if the pixel signal exceeds the input range of the ADC 140, the pixel signal is converted into saturated pixel data that does not correspond to the pixel signal.

[0042] Figure 2 is a diagram showing some implementations based on the disclosed technology. Figure 1 A conceptual diagram illustrating an example of a method of changing an input range of an analog-to-digital converter (ADC) 140 in the image sensing device 100 is shown.

[0043] Reference Figure 2 , Figure 1 The pixels 200 in the pixel array 110 in FIG. 1 may be operated in any one of a plurality of available modes MD1 to MDn (where “n” is an integer of 2 or greater). For example, the plurality of modes MD1 to MDn may refer to modes having different conversion gains, or may refer to modes having different numbers of pixels that can be read out simultaneously from a shared pixel structure, but is not limited thereto. The pixels 200 may be included in Figure 1 One of the unit pixels in the pixel array 110 shown.

[0044] The mode selector 180 may select a mode for the pixels 200 and may generate a mode selection signal (MSS) corresponding to the selected mode. The mode selector 180 may select the mode for the pixels 200 under the control of an external device (e.g., an image processor) and / or may select the mode for the pixels 200 based on a predetermined algorithm. In addition, the mode selector 180 may enable the pixels 200 included in the pixel array 110 to operate in the same mode, or may enable the included pixels 200 to operate in different modes.

[0045] The row driver 120 can receive the mode selection signal (MSS) of the mode selector 180 and generate a pixel control signal corresponding to the mode selection signal (MSS), thereby enabling each pixel 200 to be driven in a mode corresponding to the mode selection signal (MSS) among multiple modes MD1~MDn.

[0046] The IR controller 190 may receive a mode selection signal (MSS) from the mode selector 180 and generate an input range control signal (ICS) corresponding to the received mode selection signal (MSS). This control may then control the ADC 140 to set the input range of the ADC 140 based on the mode selection information in the received mode selection signal (MSS). The ADC 140 may receive the input range control signal (ICS) and set the input range corresponding to the received input range control signal (ICS). For example, assuming that the first to Nth modes MD1-MDn correspond to a plurality of input ranges IR1-IRn, respectively, the ADC 140 receiving the input range control signal (ICS) corresponding to the Kth mode (MDk) (where "k" is any one of 1-n) may be configured to have a kth input range (IRk). In this case, the ADC 140 may convert the pixel signal (PS) output from the pixel 200 driven in the kth mode (MDk) within the kth input range (IRk), thereby generating pixel data. Here, the pixel signal (PS) may be a correlated double sampling (CDS) signal obtained when the CDS 130 performs a CDS process between a reference signal and an image signal.

[0047] Figure 3 Some implementations based on the disclosed technology are shown Figure 1 FIG. 1 is a circuit diagram showing an example of the internal structure of the ADC 140 .

[0048] Reference Figure 3 , the ADC 140 is configured to receive a pixel signal (PS) from the pixel 200 and may include a ramp signal generator 300, a comparator 350, and a counter 370. Figure 3 Not shown in FIG. 1 , a correlated double sampler (CDS) 130 may be coupled between the pixel 200 and the ADC 140 , and the pixel signal (PS) received by the ADC 140 may be a correlated double sampled (CDS) signal.

[0049] The ramp signal generator 300 can generate a ramp signal (V ramp ), whose voltage decreases at a slope corresponding to the input range control signal (ICS).

[0050] The ramp signal generator 300 may include a ramp bias supply circuit 310 , a current generator 320 , and a ramp slope controller 330 .

[0051] The ramp bias supply circuit 310 may include a first switch SW1 and a ramp capacitor (Cr).

[0052] The first switch SW1 may selectively supply a ramp bias voltage (RB) having a predetermined voltage level to the current generator 320. The first switch SW1 may operate under the control of the timing controller 170. The first switch SW1 may be turned on during a period when the ramp signal generator 300 is enabled, so that the ramp bias voltage (RB) may be supplied to the current generator 320.

[0053] Although not shown in the figure, the ramp bias voltage (RB) can be generated by a bias voltage generator, and the bias voltage generator can include a bandgap reference (BGR) circuit for generating a reference voltage and a gain generator for generating the ramp bias voltage (RB) by controlling the gain of the reference voltage. Other circuit designs can also be implemented to generate the ramp bias voltage (RB).

[0054] The ramp capacitor (Cr) may be coupled between the power supply voltage (VDDr) and the first node N1 to which the first switch SW1 and the current generator 320 are connected, so that the ramp capacitor (Cr) may stabilize the voltage of the first node N1. That is, the ramp capacitor (Cr) may remove noise (e.g., high-frequency noise) that may be included in the ramp bias voltage (RB).

[0055] The current generator 320 may generate a current that decreases sequentially over time by receiving a ramp bias voltage (RB) having a predetermined voltage level. The current generator 320 may include a plurality of unit cells connected in parallel to each other. Each unit cell may include transistors TR1 to TRm (where "m" is an integer of 2 or greater) and second switches SW21 to SW2m. Figure 3 , the current generator 320 includes M unit cells.

[0056] The first unit cell may include a first transistor TR1 and a second switch SW21 .

[0057] The transistor TR1 may be coupled between the second switch SW21 and the power supply voltage (VDDr), with a gate electrode of the transistor TR1 coupled to the first node N1. The transistor TR1 may transmit a current corresponding to the ramp bias voltage (RB) supplied to the first node N1 to the second switch SW21. For example, the transistor TR1 may be a P-type metal oxide semiconductor (PMOS) transistor.

[0058] The second switch SW21 may be coupled between the transistor TR1 and the second node N2 and may supply the current of the transistor TR1 to the second node N2 under the control of the timing controller 170 .

[0059] Each of the second to mth unit cells may have a structure and operation corresponding to the first unit cell, and therefore, for the sake of simplicity, redundant descriptions thereof will be omitted herein. Furthermore, transistors TR1 to TRm may have the same specifications (e.g., channel width, channel length, etc.), and thus may generate the same amount of current when receiving the same ramp bias voltage (RB).

[0060] When the ramp signal (V ramp ), the current generator 320 may vary or change the number of the second switches SW21-SW2m to be turned on according to the control signal of the timing controller 170. For example, when the ramp signal (V ramp ) begins, all second switches SW21-SW2m may be turned on, and then any of the second switches SW21-SW2m may be turned off in sequence at predetermined time intervals. Therefore, the number of second switches to be turned off may increase over time, and after (m-1) times the predetermined time has elapsed, all second switches SW21-SW2m may be turned off. Therefore, the current flowing into the second node N2 may decrease over time. At this time, since the predetermined time is very short, it is assumed that the current flowing into the second node N2 decreases linearly.

[0061] The ramp slope controller 330 may control the ramp signal (V ramp ). In some implementations, the ramp slope controller 330 may include a variable resistor whose resistance changes according to the input range control signal (ICS). Here, the variable resistor may be coupled between the second node N2 and the ground voltage (VSSr).

[0062] Ramp signal (V ramp ) may flow into the second node N2 and may correspond to the product of the resistance of the variable resistor and the current flowing into the second node N2 and then flowing through the variable resistor. When the current flowing into the second node N2 decreases linearly by the operation of the current generator 320, the ramp signal (V ramp The slope of the voltage decrease of the ramp signal (V ramp ) can increase the slope of the voltage drop. As the resistance of the variable resistor decreases, the ramp signal (V ramp ) can reduce the slope of the voltage drop.

[0063] In addition, the ramp signal (V ramp The slope of the voltage drop of ) can determine the input range of ADC 140, and its detailed description will be referred to later. Figure 4 given.

[0064] The comparator 350 can compare the pixel signal (PS) with the ramp signal (V ramp ) is compared, so a signal with the pixel signal (PS) and the ramp signal (V ramp ) corresponds to the comparison signal (CMP). For example, if the level of the pixel signal (PS) is higher than the ramp signal (V ramp ), the comparison signal (CMP) may have a logic low level. On the contrary, if the level of the pixel signal (PS) is lower than the ramp signal (V ramp ), the comparison signal (CMP) may have a logic high level.

[0065] The counter 370 may perform counting by synchronizing with an edge (e.g., a rising edge or a falling edge) of a clock signal (CLK), and may perform counting until the comparison signal (CMP) transitions from a first level (e.g., a logic high level) to a second level (e.g., a logic low level), so that the counter 370 may output the accumulated count value as pixel data (PDA). In this case, the clock signal (CLK) may refer to a square wave signal that alternates between a high level and a low level at specific time intervals, and may be received from the timing controller 170.

[0066] Figure 4 is a control diagram showing some implementations of the disclosed technology. Figure 3 A graph showing an example of a method for varying the input range of the ADC 140 is shown.

[0067] exist Figure 4 In the graph shown, the X-axis may represent time and the Y-axis may represent voltage. Figure 4 In FIG, the first to third ramp signals (V ramp1 ~V ramp3 ). The first to third ramp signals (V ramp1 ~V ramp3 ) may have a constant voltage before the first time point (t1) and may decrease linearly after the first time point (t1).

[0068] The second ramp signal (V ramp2 ) can have a slope smaller than the first ramp signal (V ramp1 ) slope, the third ramp signal (V ramp3 ) can have a slope greater than the first ramp signal (V ramp1 If the first ramp signal (V ramp1 ), the second ramp signal (V ramp2 ). In addition, the third ramp signal (Vramp3 ).

[0069] From the first to the third ramp signal (V ramp1 ~V ramp3 ) starts to linearly decrease to a second time point (t2) after a predetermined time has elapsed from the first time point (t1) can be defined as a countable range. The countable range can refer to Figure 3 The maximum time period during which the counter 370 can continuously perform counting may correspond to the product of the period of the clock signal (CLK) and the maximum number of such counting times of the counter 370 (e.g., 1024). For convenience of description, the maximum number of counting times will be referred to as the maximum number of counts hereinafter. In this case, the countable range may be defined by the maximum number of counts indicating the output range of the ADC 140 and may be determined based on the performance of the counter 370.

[0070] For example, when Figure 4 The first ramp signal (V ramp1 ) and the pixel signal (PS) are input to the comparator 350, the counter 370 may have a value greater than the first ramp signal (V ramp1 ) is counted at a third time point (t3) of the value of ), and the accumulated count value can be output as pixel data (PDA).

[0071] In another example, when Figure 4 The second ramp signal (V ramp2 ) and the pixel signal (PS) are input to the comparator 350, the pixel signal (PS) does not have a value higher than the second ramp signal (V ramp2 ). As a result, the counter 370 may perform counting from the first time point (t1) to the second time point (t2), and may output the accumulated count value as the pixel data (PDA). However, the above count value may refer to a saturated output value and may not correspond to the pixel data (PDA) obtained by valid conversion of the pixel signal (PS).

[0072] In another example, when Figure 4 The third ramp signal (V ramp3 ) and the pixel signal (PS) are input to the comparator 350, the counter 370 may have a value greater than the third ramp signal (V ramp3 ) is counted at a fourth time point (t4) of the value of ), and the accumulated count value can be output as pixel data (PDA).

[0073] As described above, the input range of the ADC 140 may refer to a voltage range of a pixel signal that may be effectively converted into pixel data (PDA) within a predetermined output range of the ADC 140 (eg, a digital number (DN) of 0 to 1023).

[0074] When the first ramp signal (V ramp1 ) is input to the comparator 350, the voltage range of the pixel signal that can be effectively converted into pixel data within the countable range predetermined by the output range of the ADC 140 corresponds to the middle input range (IR1). Figure 4 In the example shown in FIG, the value of the pixel signal (PS) is within the middle input range (IR1) and can therefore be effectively converted into pixel data.

[0075] When the second ramp signal (V ramp2 ) is input to the comparator 350, the voltage range of the pixel signal that can be effectively converted into pixel data within the countable range predetermined by the output range of the ADC 140 corresponds to the small input range (IR2). Figure 4 In the example shown in FIG, the value of the pixel signal (PS) is not within the small input range (IR2) and therefore cannot be effectively converted into pixel data.

[0076] When the third ramp signal (V ramp3 ) is input to the comparator 350, the voltage range of the pixel signal that can be effectively converted into pixel data within the countable range predetermined by the output range of the ADC 140 corresponds to the large input range (IR3). Figure 4 In the example shown in FIG, the value of the pixel signal (PS) is within the large input range (IR3) and can therefore be efficiently converted into pixel data.

[0077] along with Figure 3 As the resistance value of the variable resistor shown decreases, the slope of the ramp signal can decrease, so that the input range of ADC140 can also decrease. Figure 3 As the resistance value of the variable resistor increases, the slope of the ramp signal increases, thereby increasing the input range of the ADC 140. Therefore, the resistance value of the variable resistor included in the ramp signal generator 300 is adjusted to control the input range of the ADC 140.

[0078] In addition, with the third ramp signal (V ramp3 ) is input to the comparator 350, when the first ramp signal (V ramp1 ) is input to the comparator 350, Figure 4 The pixel signal (PS) shown can be converted into pixel data with a larger value. This is because when the third ramp signal (V ramp3) is input to the comparator 350, a counting operation is performed during a period from the first time point (t1) to the fourth time point (t4), and when the first ramp signal (V ramp1 ) is input to the comparator 350, a counting operation is performed during a period from the first time point (t1) to the third time point (t3). Therefore, the resistance value of the variable resistor included in the ramp signal generator 300 is adjusted to control the value of the pixel data obtained by conversion of the same pixel signal.

[0079] Figure 5 is a circuit diagram illustrating an example of a pixel 500 based on some implementations of the disclosed technology.

[0080] Reference Figure 5 , pixel 500 may correspond to an example of any one pixel included in pixel array 110 .

[0081] The pixel 500 may include a photoelectric conversion element (PD), a transfer transistor (TX), a reset transistor (RX), a floating diffusion region (FD), a first conversion gain (CG) transistor CX1 and a second conversion gain (CG) transistor CX2, first to third capacitors C1 to C3, a source follower transistor (SF), and a selection transistor (SX). Although for convenience of description, Figure 5 Pixel 500 is shown as including only one photoelectric conversion element PD, but other implementations are possible. In some other implementations, pixel 500 may also be a shared pixel including multiple photoelectric conversion elements (PD). In this case, multiple transfer transistors (TX) may be provided corresponding to the multiple photoelectric conversion elements (PD).

[0082] Each photoelectric conversion element (PD) can generate and accumulate photocharges corresponding to the intensity of incident light. For example, each photoelectric conversion element (PD) can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0083] If the photoelectric conversion element (PD) is implemented as a photodiode, the photoelectric conversion element (PD) may be a region in which a second conductive impurity (eg, N-type impurity) is doped in a substrate including a first conductive impurity (eg, P-type impurity).

[0084] A transfer transistor (TX) may be coupled between the photoelectric conversion element (PD) and the floating diffusion region (FD). The transfer transistor (TX) may be turned on or off in response to a transfer control signal (TG). When the transfer transistor (TX) is turned on, photocharge accumulated in the corresponding photoelectric conversion element (PD) may be transferred to the floating diffusion region (FD).

[0085] The reset transistor (RX) may be coupled between the floating diffusion region (FD) and the power supply voltage (VDDpx), and the voltage of the floating diffusion region (FD) may be reset to the power supply voltage (VDDpx) in response to the reset control signal (RG). In this case, although the power supply voltage (VDDpx) may be Figure 3 The supply voltage (VDDr) shown is the same, but other implementations are possible.

[0086] The floating diffusion region (FD) can accumulate photocharges received from the transfer transistor (TX). The floating diffusion region (FD) can be coupled to a first capacitor C1 connected to a ground terminal. For example, the floating diffusion region (FD) can be a region doped with a second conductive impurity (e.g., N-type impurities) in a substrate (e.g., a P-type substrate) containing a first conductive impurity. In this case, the substrate and the impurity-doped region can be modeled as the first capacitor C1 acting as a junction capacitor.

[0087] The first CG transistor CX1 may be coupled between the floating diffusion region (FD) and the second capacitor C2 and may selectively connect the second capacitor C2 to the floating diffusion region (FD) in response to a first DCG control signal CG1 .

[0088] The second CG transistor CX2 may be coupled between the floating diffusion region (FD) and the third capacitor C3 and may selectively connect the third capacitor C3 to the floating diffusion region (FD) in response to the second DCG control signal CG2 .

[0089] Each of the second capacitor C2 and the third capacitor C3 may include at least one of a metal-insulator-metal (MIM) capacitor, a metal-insulator-polysilicon (MIP) capacitor, a metal-oxide-semiconductor (MOS) capacitor, and a junction capacitor.

[0090] The pixel 500 is operable in three modes, ie, a high conversion gain (HCG) mode, a medium conversion gain (MCG) mode, and a low conversion gain (LCG) mode.

[0091] In this case, conversion gain (CG) may refer to the ratio of converting the amount of photocharge generated in each pixel in response to the intensity of incident light into the voltage of the pixel signal output from the pixel. The conversion gain may be determined by the capacitance of the floating diffusion region (FD) where the photocharge is accumulated and converted into the pixel signal.

[0092] Assuming that the capacitance of the floating diffusion region (FD) is relatively small, when predetermined photocharges accumulate in the floating diffusion region (FD), a relatively large change in voltage of the floating diffusion region (FD) may occur, so that a relatively large change in voltage of the electrical signal generated by the source follower transistor (SF) may occur, resulting in an increase in the conversion gain (CG) of the pixel 500. Conversely, assuming that the capacitance of the floating diffusion region (FD) is relatively large, when predetermined photocharges accumulate in the floating diffusion region (FD), a relatively small change in voltage of the floating diffusion region (FD) may occur, so that a relatively small change in voltage of the electrical signal generated by the source follower transistor (SF) may occur, resulting in a decrease in the conversion gain (CG) of the pixel 500.

[0093] The high conversion gain (HCG) mode may refer to a mode in which the amount of increase in the response of the pixel in response to an increase in the intensity of the incident light is relatively large. Here, the response may refer to a pixel signal generated by the pixel 500 in response to sensing the intensity of the incident light. Therefore, the HCG mode may refer to an operating mode with relatively high sensitivity to the incident light, and the HCG mode may be a mode suitable for capturing scenes with low illumination. When the pixel 500 operates in the HCG mode, each of the first CG transistor CX1 and the second CG transistor CX2 may be turned off, and the floating diffusion area (FD) may be connected to the first capacitor C1 so that the floating diffusion area (FD) may have a capacitance corresponding to the first capacitor C1.

[0094] The low conversion gain (LCG) mode may refer to a mode in which the increase in the pixel's response to an increase in the intensity of incident light is relatively small. Therefore, the LCG mode may refer to an operating mode with relatively low sensitivity to incident light, and the LCG mode may be a mode suitable for capturing scenes with high illumination. When the pixel 500 operates in the LCG mode, each of the first CG transistor CX1 and the second CG transistor CX2 may be turned on, and the floating diffusion region (FD) may be coupled to the first to third capacitors C1 to C3 so that the floating diffusion region (FD) may have a capacitance corresponding to the sum of the capacitances of the first to third capacitors C1 to C3 coupled in parallel with each other.

[0095] The medium conversion gain (MCG) mode may refer to a mode in which the increase in the response of the pixel in response to an increase in the intensity of the incident light is relatively medium. Therefore, the MCG mode may refer to an operating mode in which the sensitivity to the incident light is between the sensitivity of the HCG mode and the sensitivity of the LCG mode, and the MCG mode may be a mode suitable for capturing scenes of medium illumination. To this end, when the pixel 500 operates in the MCG mode, the first CG transistor CX1 may be turned on and the second CG transistor CX2 may be turned off, and the floating diffusion area (FD) may be connected to the first and second capacitors C1~C2 so that the floating diffusion area (FD) may have a capacitance corresponding to the sum of the capacitances of the first and second capacitors C1~C2 connected in parallel to each other. Here, medium illumination may refer to an illumination condition in which the intensity of the incident light is distributed in various illumination ranges from a high illumination range to a low illumination range without being biased towards a specific illumination range such as high illumination or low illumination.

[0096] The capacitances of the first to third capacitors C1 to C3 may be predetermined through experiments to satisfy the sensitivity required in the HCG mode, the sensitivity required in the MCG mode, and the sensitivity required in the LCG mode.

[0097] High dynamic range (HDR) can be achieved using a response of the HCG mode suitable for low illumination, a response of the MCG mode suitable for medium illumination, and a response of the LCG mode suitable for high illumination. Compared to a case where only one mode is used, when the HCG mode, the MCG mode, and the LCG mode are used simultaneously, the pixel 500 may have a high dynamic range (HDR) corresponding to a range from the minimum value (i.e., the lowest value) of the dynamic range of the HCG mode to the maximum value (i.e., the highest value) of the dynamic range of the LCG mode. In this case, the dynamic range may refer to a range of the intensity of incident light (or photocharge) that enables the pixel 500 to have a valid response (i.e., a response indicating the intensity of the incident light).

[0098] The source follower transistor (SF) can be connected between the selection transistor (SX) and the power supply voltage (VDDpx), can amplify the change in the potential of the floating diffusion area (FD) that receives the photocharge accumulated in the photoelectric conversion element (PD), and can transmit the amplified result to the selection transistor (SX).

[0099] The selection transistor (SX) can be connected between the source follower transistor (SF) and the output signal line, and can be turned on by selecting the control signal (SEL) so that the selection transistor (SX) can output the electrical signal received from the source follower transistor (SF) as the pixel signal (PS).

[0100] although Figure 5Pixels designed to use three different conversion gains are shown, but other implementations are possible as long as the pixels use at least two different conversion gains.

[0101] Figure 5 The illustrated structure of pixels designed to use three different conversion gains is merely an example, and other implementations are possible.

[0102] Figure 6 It shows the Figure 5 A conceptual diagram of an example of a method of controlling the input range of an ADC by a pixel is shown. Figure 7A is a graph showing an example of a dynamic range achieved by a comparative example of the disclosed technology. Figure 7B is a graph illustrating an example of the dynamic range achieved by one implementation of the disclosed technology.

[0103] Reference Figure 6 , assuming that the linear well capacity (LWC) of the photoelectric conversion element (PD) included in the pixel 500 is set to 1600[e]. The linear well capacity (LWC) may refer to a photocharge storage capacity indicating the maximum amount of photocharge that can be generated and accumulated within a predefined range in which the response of the photoelectric conversion element (PD) can be converted into a valid response. Therefore, assuming that the amount of photocharge accumulated in the photoelectric conversion element (PD) is within the linear well capacity (LWC), the corresponding response to the photocharge amount (or incident light intensity) may have linearity. Unlike the LWC concept, the full well capacity (FWC) may refer to a photocharge storage capacity indicating the maximum amount of photocharge that can be generated and accumulated by the photoelectric conversion element (PD) to the greatest extent. Therefore, the amount of photocharge ranging from LWC to FWC can be accumulated (or stored) in the photoelectric conversion element (PD), but the response corresponding to the photocharge amount ranging from LWC to FWC may have nonlinearity, and the corresponding response to the photocharge amount from LWC to FWC may be invalid.

[0104] about Figure 6 , the photoelectric conversion element (PD) can accumulate and store the photocharge amount in the range of 0 to 1600 in response to the incident light intensity. Hereinafter, for the convenience of description and better understanding of the disclosed technology, the photocharge amount in the range of 0 to 1600 will be referred to as 0 to 1600 photocharges.

[0105] Expose using specific values Figures 6 to 7B , but those values ​​are just examples and other values ​​are possible.

[0106] It is assumed that 0 to 700 photocharges can be accumulated under low illumination conditions (also called low-light conditions) where the intensity of the incident light is relatively weak, it is assumed that 400 to 1600 photocharges can be accumulated under high illumination conditions (also called high-light conditions) where the intensity of the incident light is relatively strong, and it is also assumed that 0 to 1000 photocharges can be accumulated under medium illumination conditions (also called medium-light conditions) where the intensity of the incident light is distributed in various ranges.

[0107] Assume that under low illumination conditions, the pixel 500 operates in the HCG mode suitable for low illumination, and the conversion gain of the HCG mode is set to 0.2mV / e. Assume that under high illumination conditions, the pixel 500 operates in the LCG mode suitable for high illumination, and the conversion gain of the LCG mode is set to 0.0625mV / e. Assume that under medium illumination conditions, the pixel 500 operates in the MCG mode suitable for medium illumination, and the conversion gain of the MCG mode is set to 0.125mV / e. In this case, the conversion gain of 1mV / e may refer to the gain of a pixel signal that can convert only one photocharge into 1mV.

[0108] Under low illumination conditions, 0 to 700 photocharges accumulated can be converted into pixel signals (PS_L) of 0 to 140 mV in the floating diffusion region (FD) corresponding to a conversion gain of 0.2 mV / e. Under high illumination conditions, 400 to 1600 photocharges accumulated can be converted into pixel signals (PS_H) of 25 to 100 mV in the floating diffusion region (FD) corresponding to a conversion gain of 0.0625 mV / e. Under medium illumination conditions, 0 to 1000 photocharges accumulated can be converted into pixel signals (PS_M) of 0 to 125 mV in the floating diffusion region (FD) corresponding to a conversion gain of 0.125 mV / e.

[0109] In the following description, it is assumed that the output range of the ADC 140 is set to 0 to 1000 [DN].

[0110] It is also assumed that, as a comparative example of the disclosed technology, the input range of the ADC 140 is fixed to a third input range (IR_M) of 0 to 125 mV. In the comparative example, since the input range of the ADC 140 is fixed to the third input range (IR_M) of 0 to 125 mV, a pixel signal (PS_M) of 0 to 125 mV obtained under medium illumination conditions can be effectively converted into pixel data (PDA_M) of 0 to 1000 [DN] throughout the entire range.

[0111] However, for a pixel signal (PS_L) of 0 to 140 mV obtained under low illumination conditions, only a portion of the pixel signal (PS_L) corresponding to 0 to 125 mV within the third input range (IR_M) of ADC 140 can be effectively converted into pixel data (PDA_L) of 0 to 1000 [DN], and the remaining portion of the pixel signal (PS_L) exceeding 125 mV may remain in the margin without being effectively converted into pixel data (PDA_L). In this case, the margin may refer to the range of photocharge or pixel signal that cannot be effectively converted into pixel data. As the margin increases, the size of the dynamic range of image sensing device 100 becomes smaller.

[0112] For a pixel signal (PS_H) of 25 to 100 mV obtained under high illumination conditions, since the range of 25 to 100 mV is within the third input range (IR_M) (i.e., 0 to 125 mV), the entire pixel signal (PS_H) of 25 to 100 mV can be effectively converted into pixel data (PDA_H). Assuming that the pixel signal (PS_M) of 0 to 125 mV is converted into pixel data (PDA_M) of 0 to 1000 [DN], it is assumed that the pixel data (PDA_H) corresponding to the pixel signal (PS_H) has a range of 200 to 800 [DN]. In this case, the maximum value (800 [DN]) of the pixel data (PDA_H) does not reach the maximum value (1000 [DN]) of the output range of ADC 140. If photocharges exceeding 1600 [e] indicating a linear well capacity (LWC) are accumulated in the photoelectric conversion element (PD), the pixel signal (PS_H) and pixel data (PDA_H) corresponding to the photocharges exceeding 1600 [e] may have nonlinearity, so that the corresponding response may be regarded as an invalid response. The pixel data (PDA_H) that may include the invalid response may be regarded as unreliable data. In this case, the pixel data (PDA_H) may be substantially unusable data, so that the entire pixel data (PDA_H) may be processed as an invalid response.

[0113] Therefore, assuming that the maximum value (800 [DN]) of the pixel data (PDA_H) corresponding to the LWC (1600 [e]) of the photoelectric conversion element (PD) does not reach the maximum value (1000 [DN]) of the output range of ADC 140, the entire pixel data (PDA_H) can be processed as an invalid response.

[0114] exist Figure 7A In the graph, the X-axis represents the photocharge amount and the Y-axis represents the pixel data (PDA). Figure 7A The graph of FIG shows the pixel response under low illumination conditions, the pixel response under medium illumination conditions, and the pixel response under high illumination conditions according to the comparative example of the disclosed technology. Figure 7A In the example above, the saturation level may refer to the maximum value of the pixel data that can be output from the ADC 140. In the above example, the saturation level may be set to 1000 [DN]. In the following description, the above example will be referred to. Figure 7A Individual responses shown.

[0115] First, under low illumination conditions where 0 to 700 photocharges are generated, the response (HCG+IR_M) obtained when the photocharges are converted into pixel data with a high conversion gain (HCG) and a third input range (IR_M) can be classified as a valid response corresponding to 0 to 625 photocharges and an invalid response corresponding to 626 to 700 photocharges. Here, a valid response (indicated by a solid line) may refer to a response that corresponds to and can indicate the intensity of incident light, and an invalid response (indicated by a dotted line) may refer to a response that does not correspond to and cannot indicate the intensity of incident light. The pixel signal (PS_L) obtained when more than 625 photocharges are converted to a high conversion gain (HCG) may exceed the third input range (IR_M) of ADC 140, resulting in a margin in the pixel signal (PS_L).

[0116] Under medium illumination conditions where 0 to 1000 photocharges are generated, a response (MCG+IR_M) obtained when the photocharges are converted into pixel data with a medium conversion gain (MCG) and a third input range (IR_M) may include a valid response (indicated by a solid line) corresponding to 0 to 1000 photocharges. Under medium illumination conditions, the photocharges can be effectively converted into pixel data without causing a residual.

[0117] Under high illumination conditions where 400 to 1600 photocharges are generated, the response (LCG + IR_M) obtained when the photocharges are converted into pixel data with a low conversion gain (LCG) and a third input range (IR_M) may include an invalid response (indicated by a dotted line) corresponding to the 400 to 1600 photocharges. This is because the response (LCG + IR_M) does not reach a saturation level (i.e., is undersaturated) and the entire response corresponding to the 400 to 1600 photocharges corresponds to an invalid response.

[0118] Therefore, according to the comparative example of the disclosed technology, the dynamic range of the pixel 500 operating in each of the HCG mode, the MCG mode, and the LCG mode may correspond to a range of 0 to 1000 photocharges. Here, the size of this range of 0 to 1000 photocharges may be smaller than the range of 0 to 1600 photocharges that can be accumulated in the photoelectric conversion element (PD).

[0119] Hereinafter, unlike the comparative example case, an implementation based on the disclosed technology will be described in which the input range of the ADC 140 is changed for each mode.

[0120] If the operation mode of the pixel 500 is set to the MCG mode, the input range of the ADC 140 can be set to a third input range (IR_M) of 0 to 125 mV. Throughout the entire range, the pixel signal (PS_M) of 0 to 125 mV generated under medium illumination conditions where 0 to 1000 photocharges can be effectively converted into pixel data (PDA_M) of 0 to 1000 [DN].

[0121] If the operating mode of the pixel 500 is set to HCG mode, the input range of the ADC 140 can be set to the first input range (IR_L) of 0 to 140 mV. Throughout the entire range, a pixel signal (PS_L) of 0 to 140 mV generated under low illumination conditions, which can generate 0 to 700 photocharges, can be effectively converted into pixel data (PDA_L) of 0 to 1000 [DN]. In HCG mode, if the input range of the ADC 140 is set to the first input range (IR_L), all photocharges or all pixel signals can be effectively converted into pixel data by the ADC 140, so there is no margin.

[0122] If the operation mode of the pixel 500 is set to the LCG mode, the input range of the ADC 140 can be set to the second input range (IR_H) of 0 to 100 mV. Throughout the entire range, the pixel signal (PS_H) of 25 to 100 mV generated under high illumination conditions that can generate 400 to 1600 photocharges can be effectively converted into pixel data (PDA_H) of 250 to 1000 [DN]. In the LCG mode, if the input range of the ADC 140 is set to the second input range (IR_H), the maximum value (1000 [DN]) of the pixel data (PDA_H) can reach the maximum value (1000 [DN]) of the output range of the ADC 140, so that the pixel data (PDA_H) of 250 to 1000 [DN] can be used as valid data.

[0123] exist Figure 3 and Figure 4 The method of varying (or changing) the input range of the ADC 140 has been disclosed in , so for the sake of description convenience, its redundant description will be omitted herein.

[0124] exist Figure 7B In the graph, the X-axis represents the photocharge amount and the Y-axis represents the pixel data (PDA). Figure 7B The graphs in FIG. 1 show pixel responses under low illumination conditions, pixel responses under medium illumination conditions, and pixel responses under high illumination conditions based on some implementations of the disclosed technology. In addition, in order to illustrate the effects of the embodiments of the disclosed technology, Figure 7BFurther shown in FIG. 5 are other responses obtained by comparative examples of the disclosed technology.

[0125] First, under low illumination conditions where 0 to 700 photocharges are generated, the response (HCG+IR_L) obtained when the photocharges are converted into pixel data with a high conversion gain (HCG) and a first input range (IR_L) may include a valid response (indicated by a solid line) corresponding to 0 to 700 photocharges. In other words, Figure 7A The responses shown (HCG+IR_M) are different, Figure 7B The response (HCG+IR_L) may not include margin. The margin may increase power consumption without contributing to the extension of dynamic range, so it may be preferable that the margin be minimized.

[0126] Under medium illumination conditions where 0 to 1000 photocharges are generated, the response (MCG + IR_M) obtained when the photocharges are converted to pixel data with a medium conversion gain (MCG) and a third input range (IR_M) may include a valid response (indicated by a solid line) corresponding to 0 to 1000 photocharges. In other words, under medium illumination conditions, the photocharges can be effectively converted into pixel data throughout the entire range of these photocharges.

[0127] Under high illumination conditions where 400 to 1600 photocharges are generated, the response (LCG+IR_H) obtained when the photocharges are converted into pixel data with a low conversion gain (LCG) and a second input range (IR_H) may include a valid response (indicated by a solid line) corresponding to 400 to 1600 photocharges. In other words, Figure 7A The responses shown (LCG+IR_M) are different. Figure 7B The response (LCG+IR_H) reaches Figure 7B The “saturation” in the figure indicates the saturation level, so that the entire response corresponding to 400 to 1600 photocharges can correspond to the effective response. Figure 7A Differently, the dynamic range can be extended to a photocharge range of more than 1000 photocharges.

[0128] Therefore, in some implementations of the disclosed technology, the dynamic range of the pixel 500 operating in each of the HCG mode, the MCG mode, and the LCG mode may correspond to a range of 0 to 1600 photocharges. This range of 0 to 1600 photocharges may refer to a photocharge range in which the photoelectric conversion element (PD) can accumulate 0 to 1600 photocharges.

[0129] In addition, in some implementations of the disclosed technology, one of the various indicators indicating the performance of the image sensing device 100 (i.e., the "Kadc" value) can be improved. Here, the "Kadc" value may refer to the conversion efficiency capable of converting the received photocharge into pixel data. Considering the performance of the image sensing device 100, it may be desirable that the "Kadc" value be adjusted to maintain uniformity over the entire range of pixel data. The "Kadc" value may be proportional to the input range of the ADC 140 and may be inversely proportional to the conversion gain (mV / e). In some implementations, as the conversion gain increases (e.g., in the order of LCG→MCG→HCG), the input range of the ADC 140 is controlled to increase sequentially. As a result, the input range of the ADC 140 for each operating mode can be determined in such a way that the "Kadc" value becomes uniform regardless of the operating mode.

[0130] For the range of 0 to 700 photocharges, both the response (HCG+IR_L) and the response (MCG+IR_M) can have effective responses. However, the greater the increase in pixel data compared to the increase in photocharge, the better the signal-to-noise ratio (SNR) and resolution of the pixel data. As a result, Figure 7B The response (HCG+IR_L) can be used to synthesize HDR images.

[0131] Similarly, for the range of 700 to 1000 photocharges, both the response (MCG+IR_M) and the response (LCG+IR_H) may have valid responses, but the response (MCG+IR_M) may be used to synthesize an HDR image.

[0132] Figure 8A It shows Figure 1 FIG. 1 is a diagram illustrating an example of an operating scheme of pixel array 110 . Figure 8B It shows Figure 1 FIG. 1 is a diagram illustrating another example of an operating scheme of pixel array 110 .

[0133] When the pixel array 110 operates in single mode, Figure 8A 8. In this case, the single mode may refer to an operation mode in which pixel signals output from pixels included in the pixel array 110 correspond to photocharges generated and accumulated in only one photoelectric conversion element.

[0134] The portion 800a of the pixel array 110 may include a plurality of single pixels arranged in a (4×8) matrix array (S11 to S48). The pixel array 110 may have a structure in which the single pixels included in the portion 800a of the pixel array 110 are arranged in a matrix array including a predetermined number of rows and a predetermined number of columns. Figure 8AIn the symbol "Sab" indicating each single pixel, "a" may refer to the row to which the corresponding single pixel belongs, and "b" may refer to the column to which the corresponding single pixel belongs. For example, the single pixel "S34" may indicate that the corresponding single pixel belongs to the third row and the fourth column.

[0135] In the single mode, each of the single pixels S11 to S48 may generate and output a pixel signal corresponding to photocharges generated and accumulated in only one photoelectric conversion element.

[0136] Reference Figure 8B , when the pixel array 110 operates in the binning mode, a portion 800b corresponding to the pixel array 110 is shown. The binning mode may refer to an operation mode in which pixel signals output from pixels included in the pixel array 110 correspond to photocharges generated and accumulated in a plurality of photoelectric conversion elements.

[0137] The portion 800b of the pixel array 110 may include a plurality of binning pixels (B11 to B28) arranged in a (2×8) matrix array. The pixel array 110 may have a structure in which the binning pixels included in the portion 800b of the pixel array 110 are arranged in a matrix array including a predetermined number of rows and a predetermined number of columns. Figure 8B In the symbol "Bab" indicating each binning pixel, "a" may refer to the row to which the corresponding binning pixel belongs, and "b" may refer to the column to which the corresponding binning pixel belongs. For example, the binning pixel "B24" may indicate that the binning pixel belongs to the second row and the fourth column.

[0138] When pixels corresponding to the same region operate in both single mode and merge mode, portion 800a of pixel array 110 may refer to some pixels each serving as an operation unit in single mode, and portion 800b of pixel array 110 may refer to some pixels each serving as an operation unit in merge mode. For example, when single pixels S11 and S21 and merged pixel B11 belong to the same region, single mode may be enabled based on single pixels S11 and S21, and merge mode may be enabled based on merged pixel B11.

[0139] In the binning mode, each of the binning pixels B11 to B28 can generate a pixel signal corresponding to the photocharges generated and accumulated in two photoelectric conversion elements. Although, for ease of description, the above example discloses that each binning pixel used in the binning mode generates a pixel signal corresponding to the photocharges of two photoelectric conversion elements, other implementations are possible. It should be noted that each binning pixel used in the binning mode can also generate a pixel signal corresponding to the photocharges of three or more photoelectric conversion elements.

[0140] Figure 8C It is shown that it can be used as Figure 8A Single pixel shown and / or Figure 8BA circuit diagram of an example pixel showing a binned pixel operation is shown.

[0141] Reference Figure 8C , pixel 800c may correspond to single pixels S11 and S21 or a merged pixel B11. In other words, pixel 800c may operate as two single pixels S11 and S21 in a single mode, or may operate as a merged pixel B11 in a merged mode. Figure 8C Single pixels S11 and S21 or binned pixel B11 are shown, but other implementations are possible, and it should be noted that other single pixels or other binned pixels are configured to have a structure and operation corresponding to that of pixel 800c.

[0142] The pixel 800c may include a first photoelectric conversion element PD s11 and the second photoelectric conversion element PD s21 , first and second transfer transistors TX1 and TX2 , a floating diffusion region (FD), a reset transistor (RX), a source follower transistor (SF), and a select transistor (SX). Figure 8C The operations and functions of the above-mentioned constituent elements of the pixel 800c shown are similar to those of FIG. Figure 5 The pixels 500 shown are substantially the same as those shown. For ease of description, the following will focus on Figure 5 The characteristics of the pixel 500 are described in detail in terms of different characteristics. Figure 8C Pixel 800c is shown.

[0143] The pixel 800c may include two photoelectric conversion elements PD s11 and PD s21 And two transfer transistors TX1 and TX2. The first photoelectric conversion element PD s11 The generated photocharge can be transferred to the floating diffusion region (FD) through the first transfer transistor TX1 and then transferred to the floating diffusion region (FD) by the second photoelectric conversion element PD. s21 The generated photocharges may be transferred to the floating diffusion region (FD) through the second transfer transistor TX2. The floating diffusion region (FD) may be simultaneously connected to the photoelectric conversion element PD according to the operations of the transfer transistors TX1 and TX2. s11 and PD s21 , or can be connected to the photoelectric conversion element PD s11 and PD s21 Any one of .

[0144] The floating diffusion region (FD) may be coupled to the first capacitor (C1). Figure 5 ,although Figure 8C Omitted Figure 5First and second CG transistors CX1 and CX2 and second and third capacitors C2 and C3 are shown, but it should be noted that according to another embodiment, at least one CG transistor may be coupled to the floating diffusion region (FD).

[0145] The first photoelectric conversion element (PD s11 ) may be included in the single pixel S11, the second photoelectric conversion element (PD s21 ) may be included in the single pixel S21. In other words, the combined pixel B11 may include a first photoelectric conversion element (PD s11 ) and the second photoelectric conversion element (PD s21 ).

[0146] During the single mode, in the first readout section, the first photoelectric conversion element (PD s11 ) can be transferred to the floating diffusion region (FD), thereby generating and outputting a pixel signal corresponding to the potential of the floating diffusion region (FD). s21 ) can be transferred to the floating diffusion region (FD), thereby generating and outputting a pixel signal corresponding to the potential of the floating diffusion region (FD). That is, during the single mode, the first photoelectric conversion element (PD) s11 ) can be converted into an electric signal so that the electric signal is then output and is converted by the second photoelectric conversion element (PD s21 ) generated by the photoelectric conversion element (PD) can be converted into an electrical signal so that the electrical signal is then output. s11 ) generated by the photoelectric charge and the electrical signal from the second photoelectric conversion element (PD s21 )The electrical signals of the photocharges generated can be output independently of each other.

[0147] During the binning mode, the first photoelectric conversion element (PD) is accumulated in only one readout section. s11 ) and the photocharge accumulated in the second photoelectric conversion element (PD s21 ) are simultaneously transferred to the floating diffusion region (FD), thereby generating and outputting a pixel signal corresponding to the potential of the floating diffusion region (FD). That is, during the binning mode, the first photoelectric conversion element (PD) s11 ) and the photoelectric charge generated by the second photoelectric conversion element (PD s21 )The photocharges generated can be simultaneously converted into electrical signals so that the electrical signals are then output.

[0148] In the merge mode, although the resolution of the merge mode can be reduced to half that of the single mode, the processing time consumed to form only one frame can be reduced to half that of the single mode, and the merge mode can be more preferably used to form pixel data that is considered effective under low illumination conditions with a small amount of light. Therefore, the timing controller 170 can select the mode of the pixel array 110 under the control of an external device (e.g., an image processor) or under the control of a predefined algorithm.

[0149] Figure 9 It shows the Figure 8C FIG. 8 is a conceptual diagram illustrating an example of a method of controlling the input range of the ADC 140 using a pixel 800 c .

[0150] Figure 9 , a defective pixel (indicated by “defective pixel”) and a normal pixel are shown in FIG. Each of the defective pixel and the normal pixel can be used as the above-mentioned single pixel.

[0151] A defective pixel may refer to a pixel that accumulates at least a reference photocharge amount (e.g., 90[e]) in the photoelectric conversion element even under a dark condition (i.e., a no-light condition) in which no incident light occurs, due to a defect in the pixel itself (e.g., the occurrence of a dark current, etc.). Conversely, a normal pixel may refer to a pixel that does not accumulate a photocharge under a dark condition, or may refer to a pixel that accumulates a photocharge less than a reference photocharge amount under a dark condition. In other words, even when a photocharge less than a reference photocharge amount is accumulated, the corresponding pixel may be determined to be a normal pixel, but for the convenience of description and a better understanding of the disclosed technology, it is assumed that Figure 9 It is impossible for photocharge to accumulate in a normal pixel. In this case, the reference photocharge amount may be a photocharge corresponding to the threshold pixel data used as a reference value for determining whether the corresponding pixel is a defective pixel. More specifically, when any pixel accumulates photocharge of the reference photocharge amount or more, the corresponding pixel may be determined to be a defective pixel. Conversely, when any pixel accumulates photocharge less than the reference photocharge amount, the corresponding pixel may be determined to be a normal pixel.

[0152] exist Figure 9 In the example shown in FIG, in binning mode, the photoelectric conversion element of a defective pixel may transfer 90% of photocharge to the floating diffusion region (FD), while the photoelectric conversion element of a normal pixel may not transfer photocharge to the floating diffusion region (FD). As a result, in binning mode, 90% of photocharge may be accumulated in the floating diffusion region (FD).

[0153] Although specific numerical values ​​are used as examples for the convenience of description and better understanding of the disclosed technology, Figure 9 The implementation is shown in the accompanying drawings, but other implementations are also possible.

[0154] In both single mode and binning mode, pixel 800c may have the same conversion gain (CG) (eg, 0.1 [mV / e]).

[0155] Assuming that pixel 800c includes a defective pixel and a normal pixel, the 90 photocharges accumulated in the photoelectric conversion element of the defective pixel in the merging mode can be transferred to the floating diffusion area (FD), so that the 90 photocharges can be converted into a pixel signal (PS_D) of 9 [mV] according to the conversion gain (CG) of 0.1 [mV / e].

[0156] In some implementations, for ease of description and a better understanding of the disclosed technology, it is assumed that the output range of the ADC 140 is fixed to 0 to 1000 [DN]. Under dark conditions, when the pixel data of a specific pixel (e.g., a single pixel or a merged pixel) is equal to or greater than the threshold pixel data of 80 [DN], the specific pixel may be determined as a defective pixel. In addition, under dark conditions, when the pixel data of a specific pixel (e.g., a single pixel or a merged pixel) is less than the threshold pixel data of 80 [DN], the specific pixel may be determined as a normal pixel. The determination of a defective pixel or a normal pixel may be performed by an image processor (not shown), and the image processor (not shown) may use the pixel data of other pixels adjacent to the defective pixel to perform interpolation of the pixel data of the defective pixel.

[0157] According to a comparative example of the disclosed technology, assuming that the input range of the ADC 140 in the single mode and the input range of the ADC 140 in the binning mode are both fixed to the fourth input range (IR_S) of 0 to 90 mV, a 9 mV pixel signal (PS_D) generated by the binning pixel under dark conditions can be converted into pixel data (PDA_S) of 100 [DN]. That is, the pixel data (PDA_S) of the binning pixel may correspond to 100 [DN], which exceeds the 80 [DN] of the indication threshold pixel data, and thus the binning pixel may be determined as a defective pixel.

[0158] In some implementations, the input range of the ADC 140 in single mode and the input range of the ADC 140 in merge mode may be determined differently from each other. For example, the input range of the ADC 140 in single mode may be set to a fourth input range (IR_S) of 0 to 90 mV, and the input range of the ADC 140 in merge mode may be set to a fifth input range (IR_B) of 0 to 120 mV, which is greater than the fourth input range (IR_S) of 0 to 90 mV. In this case, under dark conditions, the 9 mV pixel signal (PS_D) generated by the merged pixel may be converted into pixel data (PDA_B) of 75 [DN]. That is, the pixel data (PDA_B) of the merged pixel may be set to 75 [DN], which is less than 80 [DN] indicating the threshold pixel data, so that the merged pixel may be determined as a normal pixel.

[0159] In some implementations, the input range of the ADC 140 in the single mode and the input range of the ADC 140 in the binning mode may be determined differently from each other, so that a ratio for determining a binned pixel as a defective pixel may be adjusted.

[0160] Figure 10A It shows Figure 8A A diagram showing an example of pixel data for multiple single pixels.

[0161] Reference Figure 10A , showing pixel data of each of the single pixels S11 to S48 under dark conditions. The following will refer to a diagram showing the output range of the ADC 140 (0 to 1000 [DN]), the fourth input range of the ADC 140 (0 to 90 [mV]), the conversion gain (0.1 [mV / e]), and the threshold pixel data. Figure 9 Detailed description Figure 10A .

[0162] exist Figure 10A , the pixel signal of the single pixel S16 may be converted into the pixel data 200. In this case, the pixel signal of the single pixel S16 may correspond to 18 [mV].

[0163] The pixel signal of the single pixel S23 may be converted into pixel data 100. In this case, the pixel signal of the single pixel S23 may correspond to 9 [mV].

[0164] The pixel signal of the single pixel S32 may be converted into the pixel data 120. In this case, the pixel signal of the single pixel S32 may correspond to 10.8 [mV].

[0165] The pixel signal of each of the single pixels S35 and S45 may be converted into pixel data 40. In this case, the pixel signal of each of the single pixels S35 and S45 may correspond to 3.6 [mV].

[0166] The pixel signal of the single pixel S37 may be converted into pixel data 1000. In this case, the pixel signal of the single pixel S37 may correspond to 90 [mV].

[0167] from Figure 10A It can be seen that the pixel signal of each of the remaining single pixels (eg, S11, S12, etc.) may be converted into pixel data 0. In this case, the pixel signal of each single pixel may correspond to 0 [mV].

[0168] Each of the single pixels S16, S23, S32, and S37 has pixel data of at least 80 [DN] (indicating threshold pixel data), so that the corresponding pixel can be determined as a defective pixel. Each of the remaining pixels other than the single pixels S16, S23, S32, and S37 has pixel data less than 80 [DN] (indicating threshold pixel data), so that the corresponding pixel can be determined as a normal pixel.

[0169] Therefore, if Figure 10A As shown, the ratio of the number of defective pixels to the total number of pixels (ie, the ratio of defective pixels, hereinafter referred to as defect ratio) can be expressed by 4 / 32 (=1 / 8).

[0170] Figure 10B This is a comparative example showing the disclosed technology. Figure 8B A diagram of an example of pixel data for multiple binned pixels is shown.

[0171] Reference Figure 10B , showing pixel data of each of the binned pixels B11 to B28 under dark conditions. The following will refer to a diagram showing the output range of the ADC 140 (0 to 1000 [DN]), the fourth input range of the ADC 140 (0 to 90 [mV]), the conversion gain (0.1 [mV / e]), and the threshold pixel data. Figure 9 Detailed description Figure 10B In other words, according to the comparative example of the disclosed technology, even in the binning mode, when the ADC 140 has the fourth input range 0 to 90 [mV] in the same manner as in the single mode, pixel data of binning pixels B11 to B28 will be described below with reference to the accompanying drawings.

[0172] The pixel signal of the combined pixel B13 may be the sum of the pixel signals of the single pixels S13 and S23 , may correspond to 9 [mV], and may be converted into pixel data 100 through the fourth input range of 0 to 90 [mV].

[0173] The pixel signal of the combined pixel B16 may be the sum of the pixel signals of the single pixels S16 and S26 , may correspond to 18 [mV], and may be converted into the pixel data 200 through the fourth input range of 0 to 90 [mV].

[0174] The pixel signal of the combined pixel B22 may be the sum of the pixel signals of the single pixels S32 and S42 , may correspond to 10.8 [mV], and may be converted into the pixel data 120 through the fourth input range of 0 to 90 [mV].

[0175] The pixel signal of the combined pixel B25 may be the sum of the pixel signals of the single pixels S35 and S45 , may correspond to 7.2 [mV], and may be converted into pixel data 80 through the fourth input range of 0 to 90 [mV].

[0176] The pixel signal of the combined pixel B27 may be the sum of the pixel signals of the single pixels S37 and S47 , may correspond to 90 [mV], and may be converted into pixel data 1000 through the fourth input range of 0 to 90 [mV].

[0177] from Figure 10B It can be seen that the pixel signal of each of the remaining binning pixels (eg, B11, B12, etc.) may be converted into pixel data 0. In this case, the pixel signal of each binning pixel may correspond to 0 [mV].

[0178] Each of the merged pixels B13, B16, B22, B25, and B27 has pixel data of at least 80 [DN] (indicating threshold pixel data), so the corresponding pixel can be determined as a defective pixel. Each of the remaining pixels other than the merged pixels B13, B16, B22, B25, and B27 has pixel data less than 80 [DN] (indicating threshold pixel data), so the corresponding pixel can be determined as a normal pixel.

[0179] Therefore, if Figure 10B As shown, the ratio of the number of defective pixels to the total number of pixels (ie, the defect ratio) can be represented by 5 / 16.

[0180] Figure 10C Some implementations based on the disclosed technology are shown Figure 8B A diagram showing an example of pixel data for a merged pixel is shown.

[0181] Reference Figure 10C , showing pixel data of each of the binned pixels B11 to B28 under dark conditions. The following will refer to a diagram showing the output range of the ADC 140 (0 to 1000 [DN]), the fifth input range of the ADC 140 (0 to 120 [mV]), the conversion gain (0.1 [mV / e]), and the threshold pixel data. Figure 9 Detailed description Figure 10C In other words, according to the comparative example of the disclosed technology, when the ADC 140 has a fifth input range of 0 to 120 [mV] in the binning mode in a manner different from the single mode, pixel data of binning pixels B11 to B28 will be described below with reference to the accompanying drawings.

[0182] The pixel signal of the combined pixel B13 may be the sum of the pixel signals of the single pixels S13 and S23 , may correspond to 9 [mV], and may be converted into pixel data 75 through the fifth input range of 0 to 120 [mV].

[0183] The pixel signal of the combined pixel B16 may be the sum of the pixel signals of the single pixels S16 and S26 , may correspond to 18 [mV], and may be converted into pixel data 150 through the fifth input range of 0 to 120 [mV].

[0184] The pixel signal of the combined pixel B22 may be the sum of the pixel signals of the single pixels S32 and S42 , may correspond to 10.8 [mV], and may be converted into pixel data 90 through the fifth input range of 0 to 120 [mV].

[0185] The pixel signal of the combined pixel B25 may be the sum of the pixel signals of the single pixels S35 and S45 , may correspond to 7.2 [mV], and may be converted into pixel data 60 through the fifth input range of 0 to 120 [mV].

[0186] The pixel signal of the combined pixel B27 may be the sum of the pixel signals of the single pixels S37 and S47 , may correspond to 90 [mV], and may be converted into pixel data 1000 through the fifth input range of 0 to 120 [mV].

[0187] from Figure 10C It can be seen that the pixel signal of each of the remaining binning pixels (eg, B11, B12, etc.) may be converted into pixel data 0. In this case, the pixel signal of each binning pixel may correspond to 0 [mV].

[0188] Each of the merged pixels B16, B22, and B27 has pixel data of at least 80 [DN] (indicating threshold pixel data), so the corresponding pixel can be determined as a defective pixel. Each of the remaining pixels other than the merged pixels B16, B22, and B27 has pixel data less than 80 [DN] (indicating threshold pixel data), so the corresponding pixel can be determined as a normal pixel.

[0189] Therefore, if Figure 10C As shown, the ratio of the number of defective pixels to the total number of pixels (ie, the defect ratio) can be represented by 3 / 16.

[0190] Since defective pixels require additional processing by an image processor (not shown), the image processor must perform interpolation using pixel data of adjacent pixels of the defective pixel, so power consumption required for image processing may inevitably increase, and image quality may deteriorate due to such interpolation.

[0191] like Figure 10C As shown, according to one embodiment of the disclosed technology, the input range of ADC 140 can be controlled in binning mode, so that the ratio of defective pixels (i.e., defect ratio) can be reduced. As a result, in binning mode, power consumption unnecessary for image processing of defective pixels can be reduced, and interpolation processing can be omitted from image processing, resulting in improved image quality.

[0192] As apparent from the above description, an image sensing device based on some implementations of the disclosed technology can change the input range of an analog-to-digital converter (ADC) in response to various pixel modes, thereby acquiring pixel data optimized for each pixel mode.

[0193] Although a number of exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments are contemplated based on what is described and / or illustrated in this patent document.

[0194] CROSS-REFERENCE TO RELATED APPLICATIONS

[0195] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2021-0046554, filed on April 9, 2021, the disclosure of which is incorporated herein by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a pixel array of pixels operable to sense light to generate pixel signals and operable to operate in one of a plurality of modes when sensing light, wherein a first pixel of the pixel array is controlled to operate in a mode selected from the plurality of modes and to output a pixel signal in response to light incident on the first pixel; an analog-to-digital converter ADC coupled to the pixel array to receive the pixel signal from the first pixel and set an input range indicating a voltage range of the pixel signal based on the mode selected for the first pixel when generating the pixel signal, and perform analog-to-digital conversion of the pixel signal generated by the first pixel based on the input range of the analog-to-digital converter ADC to generate pixel data representing the pixel signal; a mode selector that generates a mode selection signal corresponding to a mode selected for the first pixel; a row driver coupled to communicate with the mode selector to receive the mode selection signal for the first pixel and generate a pixel control signal for driving the first pixel to operate in the selected mode; and an input range controller coupled to communicate with the mode selector to receive the mode selection signal and to generate an input range control signal corresponding to the selected mode, wherein the input range controller is coupled to communicate with the analog-to-digital converter ADC to send the input range control signal to the analog-to-digital converter ADC for performing analog-to-digital conversion of the pixel signal generated by the first pixel.

2. The image sensing device according to claim 1, wherein The analog-to-digital converter ADC comprises: a ramp signal generator configured to generate a ramp signal, the voltage of the ramp signal decreasing at a slope corresponding to the input range control signal; a comparator coupled to the ramp signal generator to receive the ramp signal and generate a comparison signal corresponding to a relationship in magnitude between the pixel signal and the ramp signal; and A counter is coupled to the comparator to receive the comparison signal and perform counting until the comparison signal transitions from a first level to a second level different from the first level, and outputs a cumulative count value as the pixel data.

3. The image sensing device according to claim 2, wherein: The ramp signal generator comprises: a current generator that receives a ramp bias voltage having a constant voltage level and generates a current that decreases with time; and A variable resistor controls a slope of the ramp signal generated by the current according to the input range control signal.

4. The image sensing device according to claim 3, wherein: The analog-to-digital converter ADC: As the resistance value of the variable resistor decreases, the input range of the analog-to-digital converter ADC is reduced; and As the resistance value of the variable resistor increases, the input range of the analog-to-digital converter ADC increases.

5. The image sensing device according to claim 1, wherein The multiple modes include: a single mode in which the pixel signal output from the first pixel corresponds to photocharge generated and accumulated in one photoelectric conversion element; and A binning mode in which the pixel signal output from the first pixel corresponds to photocharges generated and accumulated in a plurality of photoelectric conversion elements.

6. The image sensing device according to claim 5, wherein: The analog-to-digital converter (ADC) has a fourth input range for the first pixel operating in the single mode and a fifth input range for the first pixel operating in the binning mode, the fifth input range being greater than the fourth input range.

7. An image sensing device, comprising: a pixel array of pixels operable to sense light to generate pixel signals and operable to operate in one of a plurality of modes when sensing light, wherein a first pixel of the pixel array is controlled to operate in a mode selected from the plurality of modes and to output a pixel signal in response to light incident on the first pixel; and an analog-to-digital converter ADC coupled to the pixel array to receive the pixel signal from the first pixel and set an input range indicating a voltage range of the pixel signal based on the mode selected for the first pixel when generating the pixel signal, and perform analog-to-digital conversion of the pixel signal generated by the first pixel based on the input range of the analog-to-digital converter ADC to generate pixel data representing the pixel signal, The multiple modes include: a high conversion gain HCG mode in which an increase in the response of the pixel in response to an increase in the intensity of incident light is relatively large; and a low conversion gain LCG mode in which the increase in the response of the pixel in response to an increase in the intensity of incident light is relatively small, Wherein, the first pixel includes: a floating diffusion region that accumulates therein photocharges corresponding to the intensity of the incident light and is coupled to a first capacitor; a first conversion gain CG transistor coupled between the floating diffusion region and a second capacitor; and a second conversion gain CG transistor coupled between the floating diffusion region and a third capacitor, in, In the high conversion gain HCG mode, each of the first conversion gain CG transistor and the second conversion gain CG transistor is turned off; and In the low conversion gain LCG mode, each of the first conversion gain CG transistor and the second conversion gain CG transistor is turned on.

8. The image sensing device according to claim 7, wherein: The analog-to-digital converter ADC sets a first input range for the first pixel operating in the high conversion gain HCG mode and sets a second input range for the first pixel operating in the low conversion gain LCG mode, the second input range being smaller than the first input range.

9. The image sensing device according to claim 7, wherein: The multiple modes also include: A medium conversion gain MCG mode, in which the increase in the response of the pixel in response to an increase in the intensity of the incident light is less than the increase in the response of the pixel in response to an increase in the intensity of the incident light in the high conversion gain HCG mode and is greater than the increase in the response of the pixel in response to an increase in the intensity of the incident light in the low conversion gain LCG mode.

10. The image sensing device according to claim 9, wherein: The analog-to-digital converter (ADC) has a third input range for the first pixel operating in the medium conversion gain (MCG) mode, the third input range being smaller than the first input range and larger than the second input range.

11. The image sensing device according to claim 10, wherein: In the medium conversion gain MCG mode, the first conversion gain CG transistor is turned on, and the second conversion gain CG transistor is turned off.

12. An image sensing device, comprising: a pixel operable to sense light in one of different modes having different sensing characteristics and to output a pixel signal in response to incident light when controlled to operate in a mode selected from the different modes; an analog-to-digital converter ADC that receives the pixel signal from the pixel operating in the selected mode and converts the pixel signal into pixel data based on an input range of the analog-to-digital converter ADC set according to a mode selected from the different modes of operating the pixel when sensing the incident light; as well as a timing controller coupled to communicate with the analog-to-digital converter (ADC) and to control the analog-to-digital converter (ADC) to set the input range of the analog-to-digital converter (ADC) based on the selected mode of the pixels, in, The input range is a voltage range in which the analog-to-digital converter ADC is operable to perform analog-to-digital conversion of the pixel signal when the pixel signal is within the input range. The different modes include: a high conversion gain (HCG) mode in which the amount of increase in response of the pixel to an increase in the intensity of the incident light is relatively large; and In the low conversion gain LCG mode, the increase in the pixel response to an increase in the intensity of the incident light is relatively small. The pixels include: a floating diffusion region that accumulates therein photocharges corresponding to the intensity of the incident light and is coupled to a first capacitor; a first conversion gain CG transistor coupled between the floating diffusion region and a second capacitor; and a second conversion gain CG transistor coupled between the floating diffusion region and a third capacitor, in, In the high conversion gain HCG mode, each of the first conversion gain CG transistor and the second conversion gain CG transistor is turned off; and In the low conversion gain LCG mode, each of the first conversion gain CG transistor and the second conversion gain CG transistor is turned on.

13. The image sensing device according to claim 12, wherein: The different modes include a single mode in which the pixel signal output from the pixel corresponds to photocharge generated and accumulated in one photoelectric conversion element and a binning mode in which the pixel signal output from the pixel corresponds to photocharge generated and accumulated in a plurality of photoelectric conversion elements.

14. The image sensing device according to claim 12, wherein: The analog-to-digital converter ADC includes a variable resistor having a resistance value that changes based on a mode selected from the different modes for operating the pixel.

15. The image sensing device according to claim 14, wherein: The analog-to-digital converter ADC changes the input range using the resistance value of the variable resistor.

16. The image sensing device according to claim 14, wherein: The analog-to-digital converter ADC determines a value of the pixel data based on the resistance value of the variable resistor.

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