Column signal processing method and processing circuit of image sensor

Abstract

The present invention provides a column signal processing method and processing circuit of an image sensor, wherein the reference signals and pixel signals of all rows are latched in the same storage unit in succession by a comparator, and the comparator only needs to perform data interaction with the same storage unit, thereby reducing the power consumption caused by the increase in the load of the comparator due to the latching of the reference signals and pixel signals of different rows in different storage units, thereby reducing the noise interference caused by the flipping of different column signals, and improving the imaging quality. After the reference signal and the pixel signal are read out to the digital processing unit, the image data of the image sensor is obtained by the algorithm processing of the digital processing unit, that is, the algorithm processing of the reference signal and the pixel signal is not performed inside the column signal processing circuit, so the column signal processing circuit has a simple structure, fewer metal layers, and the process and circuit design are relatively easy to implement, and the power consumption and noise caused by the algorithm processing can be further reduced.

Description

Technical Field

[0001] The invention relates to a column signal processing method and a processing circuit of an image sensor. Background Art

[0002] In the CMOS Image Sensor (CIS) chip, the pixel unit converts the exposure into an electrical signal PXD, which can reflect the exposure. At the same time, a ramp signal RAMP is generated in the ramp circuit. When the ramp signal starts to rise or fall, the counter starts counting. The comparator in the analog to digital converter (ADC) compares the PXD signal with the RAMP signal. When the two values ​​are equal, the column signal flips and the counter value at that moment is locked in the storage unit, thereby converting the analog signal of the pixel unit into a digital signal, which is also the signal quantization process.

[0003] As the number of pixels in CIS chips in portable electronic devices such as mobile phones gradually increases, the amount of data that needs to be stored is also increasing, and the power consumption of the comparator during the data latch stage is also increasing. At the same time, since the power consumption of the comparator is large during the comparison period, the noise caused by the flipping of different column signals will affect each other, causing the power supply voltage to be disturbed and cause voltage fluctuations, resulting in the influence of quantized data and deterioration of image quality.

[0004] In response to the above problems, the existing solution is to place a sampling capacitor between the power supply and the ground to isolate the influence of noise and reduce the fluctuation of the power supply voltage. However, this technical method only reduces the fluctuation of the power supply voltage, but does not reduce the power consumption generated by the comparator during the comparison and latching of signals, and does not solve the problem of noise generation from the source, so the effect is limited. Summary of the invention

[0005] The object of the present invention is to provide a column signal processing method and processing circuit of an image sensor, which can reduce the power consumption of a comparator during comparison and latching of signals, thereby reducing noise interference caused by flipping of different column signals, improving the imaging quality of the image sensor, and improving the overall performance of the image sensor.

[0006] Based on the above considerations, one aspect of the present invention provides a column signal processing method for an image sensor, comprising: when the image sensor quantizes the reference signal and the pixel signal, the comparator successively latches the reference signal and the pixel signal of all rows in the same storage unit to reduce the increase in noise caused by the increase in the load of the comparator caused by latching the reference signal and the pixel signal of different rows in different storage units; after the comparator successively latches the reference signal and the pixel signal in the same storage unit, the reference signal and the pixel signal latched in the same storage unit are transferred to other storage units; the reference signal and the pixel signal transferred to other storage units are read out to the digital processing unit, and the digital processing unit performs algorithm processing to obtain the image data of the image sensor.

[0007] Preferably, the processing steps of each row of reference signal and pixel signal include: the comparator latches the reference signal to the write storage unit and transfers it to the temporary storage unit; the comparator latches the pixel signal to the write storage unit; the reference signal is transferred to the reference signal read storage unit and the pixel signal is transferred to the pixel signal read storage unit; the reference signal and pixel signal are read out to the digital processing unit, and the digital processing unit performs algorithm processing to obtain a row of image data of the image sensor.

[0008] Preferably, the step of reading out the reference signal and the pixel signal of the previous row is performed in parallel with the step of latching the reference signal and the pixel signal of the next row.

[0009] Preferably, each row of reference signals includes N reference signals, wherein N is a positive integer, and the processing steps of each row of reference signals include: the comparator latches the nth reference signal to the write storage unit and transfers it to the nth temporary storage unit; wherein 1≤n≤N, the above steps are repeated until all N reference signals are successively transferred to the corresponding temporary storage units; and one reference signal among the N reference signals is selected and transferred to the reference signal read storage unit.

[0010] Preferably, the write storage unit is the storage unit closest to the comparator among all the storage units.

[0011] Preferably, the signal transfer step between the storage units adopts a low voltage difference transmission mode.

[0012] Preferably, the signal transfer step between the storage units is located during the non-comparison time of the comparator.

[0013] Preferably, the storage unit is a static random access memory, which can store more than two stable states; before writing a stable state to the static random access memory, the static random access memory is set to an unstable state adjacent to the stable state, thereby improving the efficiency of writing the stable state to the static random access memory.

[0014] Another aspect of the present invention provides a column signal processing circuit of an image sensor, comprising: a comparator and multiple storage units. When the image sensor quantizes a reference signal and a pixel signal, the comparator latches the reference signal and the pixel signal of all rows in the same storage unit in succession, and then transfers the reference signal and the pixel signal latched in the same storage unit to other storage units. Then, the reference signal and the pixel signal transferred to the other storage units are read out to an external digital processing unit. The digital processing unit performs algorithm processing to obtain image data of the image sensor.

[0015] Preferably, the multiple storage units include: a write storage unit connected to the comparator, used to latch the reference signals and pixel signals of all rows; a temporary storage unit connected to the write storage unit, used to temporarily store the reference signal; a reference signal read storage unit connected to the temporary storage unit, used to store the reference signal to be read; and a pixel signal read storage unit connected to the write storage unit, used to store the pixel signal to be read.

[0016] Preferably, the temporary storage unit comprises: N temporary storage units, each used to store N reference signals correspondingly, wherein N is a positive integer.

[0017] Preferably, the write storage unit is the storage unit closest to the comparator among all the storage units.

[0018] Preferably, the transmission lines between the storage units are respectively connected to reference voltages, so as to implement the signal transfer step between the storage units in a low voltage difference transmission mode.

[0019] Preferably, the storage unit is a static random access memory.

[0020] The column signal processing method and processing circuit of the image sensor of the present invention have the following advantages:

[0021] (1) The reference signals and pixel signals of all rows are latched in the same storage unit in succession by the comparator. The comparator only needs to exchange data with the same storage unit, which reduces the power consumption caused by the increase in the load of the comparator due to the reference signals and pixel signals of different rows being latched in different storage units, thereby reducing the noise interference caused by the flipping of different column signals and improving the imaging quality.

[0022] (2) After the reference signal and the pixel signal are read out to the digital processing unit, they are processed by the algorithm of the digital processing unit to obtain the image data of the image sensor. That is to say, the algorithm processing of the reference signal and the pixel signal is not performed inside the column signal processing circuit. Therefore, the column signal processing circuit has a simple structure, fewer metal layers, and the process and circuit design are relatively easy to implement. In addition, the power consumption and noise caused by the algorithm processing can be further reduced.

[0023] (3) By adopting at least four storage units, namely, a write storage unit, a temporary storage unit, a reference signal read storage unit, and a pixel signal read storage unit, the read step of the reference signal and pixel signal of the previous row and the latch step of the reference signal and pixel signal of the next row are realized in parallel, thereby improving the column signal processing rate.

[0024] (4) N temporary storage units may be used to store N reference signals of each row respectively, which is applicable to image sensors in dual conversion gain (DCG) mode.

[0025] (5) The memory cell to be written is the memory cell closest to the comparator among all the memory cells, so as to further reduce the latch load.

[0026] (6) The signal transfer step between storage units preferably adopts a low voltage difference transmission method, which reduces the power consumption of the data transfer process and reduces the total power consumption.

[0027] (7) The signal transfer steps between storage units are arranged to be completed during the non-comparison time of the comparator, thereby effectively reducing the power consumption of the comparator during the comparison time.

[0028] (8) The signal storage unit preferably adopts a static random access memory (SRAM) structure to effectively reduce the chip area. The static random access memory can store more than two stable states. Before writing a stable state to the static random access memory, the static random access memory is set to an unstable state adjacent to the stable state, thereby improving the efficiency of writing the stable state to the static random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0030] Figure 1 It is a structural schematic diagram of a column signal processing circuit of an existing image sensor;

[0031] Figure 2 A timing diagram of a column signal processing method of an existing image sensor;

[0032] Figure 3 is a schematic structural diagram of a column signal processing circuit of an image sensor according to an embodiment of the present invention;

[0033] Figure 4 for Figure 3 A timing diagram of a column signal processing method of an image sensor;

[0034] Figure 5 is a schematic structural diagram of a column signal processing circuit of an image sensor according to another embodiment of the present invention;

[0035] Figure 6 for Figure 5 A timing diagram of a column signal processing method of an image sensor;

[0036] Figure 7 A circuit diagram of a storage unit in a column signal processing circuit of an image sensor of the present invention;

[0037] Figure 8 A schematic diagram of a low voltage difference transmission mode in a column signal processing circuit of an image sensor of the present invention;

[0038] Fig. 9 The circuit diagram is a low voltage difference transmission mode in a column signal processing circuit of an image sensor of the present invention.

[0039] In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout different drawings. DETAILED DESCRIPTION

[0040] In order to solve the above-mentioned problems in the prior art, the present invention provides a column signal processing method and processing circuit of an image sensor, wherein the reference signals and pixel signals of all rows are latched in the same storage unit in succession by a comparator. The comparator only needs to exchange data with the same storage unit, thereby reducing the power consumption caused by the increase in the load of the comparator due to the latching of reference signals and pixel signals of different rows in different storage units, thereby reducing the noise interference caused by the flipping of different column signals, improving the imaging quality, and improving the overall performance of the image sensor.

[0041] In the following specific description of the preferred embodiments, reference will be made to the attached drawings which constitute a part of the present invention. The attached drawings show by way of example specific embodiments that can implement the present invention. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present invention. It will be appreciated that other embodiments may be utilized, and structural or logical modifications may also be made without departing from the scope of the present invention. Therefore, the following specific description is not restrictive, and the scope of the present invention is limited by the appended claims.

[0042] Figure 1The structure of a column signal processing circuit of a conventional image sensor is shown. Figure 2 The timing chart of a conventional column signal processing method of an image sensor is shown.

[0043] like Figure 1 As shown, the column signal processing circuit 100 of the existing image sensor includes a comparator 110, multiple storage units 120 and a readout logic driver (not shown), wherein the storage unit 120 includes a first reference signal storage unit 121, a first pixel signal storage unit 122, a second reference signal storage unit 123, and a second pixel signal storage unit 124.

[0044] In image sensor chips, in order to reduce image noise, correlation sampling is usually used to read the electrical signal of the pixel unit twice, namely the reference signal and the pixel signal, and the two are subtracted to reduce image noise. In addition, image sensors generally read the entire image by reading pixel information line by line. Therefore, Figure 1 The first reference signal storage unit 121 is responsible for storing reference signals of odd rows, the first pixel signal storage unit 122 is responsible for storing pixel signals of odd rows, the second reference signal storage unit 123 is responsible for storing reference signals of even rows, the second pixel signal storage unit 124 is responsible for storing pixel signals of even rows, and the readout logic driver is responsible for reading the signal data in the storage unit to the external digital processing unit 130, and the digital processing unit 130 obtains the image data of the image sensor after algorithm processing.

[0045] Specifically, the timing of the column signal processing method is as follows: Figure 2 As shown: in stage S101, the comparator 110 latches the reference signal of the odd row in the first reference signal storage unit 121; in stage S102, the comparator 110 latches the pixel signal of the odd row in the first pixel signal storage unit 122; in stage S103, the comparator 110 latches the reference signal of the even row in the second reference signal storage unit 123; in stage S104, the comparator 110 latches the pixel signal of the even row in the second pixel signal storage unit 124; at the same time as stages S103 and S104, the readout logic driver also reads out the data in the first reference signal storage unit 121 and the first pixel signal storage unit 122 to the external digital processing unit 130 (i.e., stages S105 and S106); in stages S107 and S108, the readout logic driver reads out the data in the second reference signal storage unit 123 and the second pixel signal storage unit 124 to the external digital processing unit 130.

[0046] That is to say, in the column signal processing circuit of the conventional image sensor, when the reference signal and the pixel signal are quantized, the comparator 110 is required to perform latching operations on the first reference signal storage unit 121, the first pixel signal storage unit 122, the second reference signal storage unit 123, and the second pixel signal storage unit 124 at different stages. In physical implementation, since the four storage units 121, 122, 123, and 124 need to interact with the comparator 110 for data, the driving load of the comparator 110 becomes larger, the power consumption for signal latching is increased, and the noise interference when different column signals are flipped is increased.

[0047] The column signal processing method and column processing circuit of the image sensor of the present invention are described in detail below in conjunction with specific embodiments.

[0048] Figure 3 FIG. 2 shows a structure of a column signal processing circuit of an image sensor according to an embodiment of the present invention. Figure 4 FIG. 1 is a timing diagram of a column signal processing method of an image sensor according to an embodiment of the present invention.

[0049] like Figure 3 As shown, the column signal processing circuit 200 of the image sensor of the present invention includes a comparator 210, a plurality of storage units 220 and a readout logic driver (not shown), wherein the storage unit 220 includes a write storage unit 221, a temporary storage unit 222, a reference signal readout storage unit 223, and a pixel signal readout storage unit 224. The write storage unit 221 connected to the comparator 110 is used to latch the reference signal and pixel signal of all rows; the temporary storage unit 222 connected to the write storage unit 221 is used to temporarily store the reference signal; the reference signal readout storage unit 223 connected to the temporary storage unit 222 is used to store the reference signal to be read out; and the pixel signal readout storage unit 224 connected to the write storage unit 221 is used to store the pixel signal to be read out.

[0050] Specifically, the timing sequence of the column signal processing method of the image sensor of the present invention is as follows: Figure 4As shown: in stage S201, the comparator 210 latches the reference signal into the write storage unit 221; in stage S202, the reference signal is transferred to the temporary storage unit 222; in stage S203, the comparator 210 latches the pixel signal into the write storage unit 221; in stages S204 and S205, the reference signal is transferred to the reference signal read storage unit 223 and the pixel signal is transferred to the pixel signal read storage unit 224; in stages S206 and S207, the reference signal and the pixel signal are read out to the digital processing unit 230, and at the same time, In stage S208, the comparator 210 latches the reference signal of the next row into the write storage unit 221. In stage S209, the reference signal is transferred to the temporary storage unit 222. In stage S210, the comparator 210 latches the pixel signal of the next row into the write storage unit 221. In stages S211 and S212, the reference signal is transferred to the reference signal read storage unit 223 and the pixel signal is transferred to the pixel signal read storage unit 224. In stages S213 and S214, the reference signal and the pixel signal are read out to the digital processing unit 230.

[0051] That is, the processing steps of each row of reference signals and pixel signals include: the comparator 210 latches the reference signal to the write storage unit 221 and transfers it to the temporary storage unit 222; the comparator 210 latches the pixel signal to the write storage unit 221; transfers the reference signal to the reference signal readout storage unit 223 and transfers the pixel signal to the pixel signal readout storage unit 224; reads the reference signal and pixel signal to the digital processing unit 230, and then the digital processing unit 230 performs algorithm processing to obtain a row of image data of the image sensor. Preferably, the reading step of the reference signal and pixel signal of the previous row is parallel to the latching step of the reference signal and pixel signal of the next row to increase the column signal processing rate.

[0052] It can be seen that when the image sensor of the present invention quantizes the reference signal and the pixel signal, the comparator 210 latches the reference signal and the pixel signal of all rows in the same storage unit (write storage unit 221) in turn, and then transfers the reference signal and the pixel signal latched in the same storage unit to other storage units. Since the comparator 210 only needs to interact with the same storage unit for data, compared with the image sensor of the prior art, the power consumption caused by the increase in the load of the comparator due to the reference signal and the pixel signal of different rows being latched in different storage units is reduced, thereby reducing the noise interference caused by the flipping of different column signals and improving the imaging quality. Preferably, the write storage unit 221 is the storage unit closest to the comparator 210 among all the storage units 220, so as to further reduce the latch load.

[0053] In addition, after the reference signal and the pixel signal are read out to the digital processing unit 230, they are processed by the algorithm of the digital processing unit 230 to obtain the image data of the image sensor. That is to say, the algorithm processing of the reference signal and the pixel signal is not performed inside the column signal processing circuit. Therefore, the column signal processing circuit has a simple structure, fewer metal layers, and the process and circuit design are relatively easy to implement, and the power consumption and noise caused by the algorithm processing can be further reduced.

[0054] The column processing circuit of the image sensor of the present invention can also use N temporary storage units 222, which are respectively used to store N reference signals of each row, wherein N is a positive integer, so that the column signal processing circuit and column signal processing method of the present invention can be used for image sensors in dual conversion gain (DCG) mode. The processing steps of each row of reference signals include: the comparator latches the nth reference signal into the write storage unit and transfers it to the nth temporary storage unit; wherein 1≤n≤N, repeating the above steps until all N reference signals are successively transferred to the corresponding temporary storage units; selecting one of the N reference signals to transfer to the reference signal readout storage unit.

[0055] exist Figure 5 , Figure 6 In another preferred embodiment shown, two temporary storage units (ie, the first temporary storage unit 322A and the second temporary storage unit 322B) are taken as an example to show a structural schematic diagram and a method timing diagram of a column processing circuit of an image sensor in a DCG mode.

[0056] Specifically, in stages S301 and S302, the comparator 310 latches the first reference signal into the write storage unit 321 and transfers it to the first temporary storage unit 322A; in stages S303 and S304, the comparator 310 latches the second reference signal into the write storage unit 321 and transfers it to the second temporary storage unit 322B; in stage S305, the comparator 310 latches the pixel signal into the write storage unit 321; in stages S306 and S307, one of the first and second reference signals (herein, the first reference signal in the first temporary storage unit is selected as an example) is transferred to the reference signal read storage unit 323 and the pixel signal is transferred to the pixel signal read storage unit 324; in stages S308 and S309, the first reference signal and the pixel signal are read out to the digital processing unit 330, and then the digital processing unit 330 performs algorithm processing to obtain a row of image data of the image sensor. Simultaneously with stages S308 and S309, the latching and transfer steps S310, S311, S312, S313, and S314 of the reference signal and pixel signal of the next row are performed. That is, the readout step of the reference signal and pixel signal of the previous row is carried out in parallel with the latching step of the reference signal and pixel signal of the next row to increase the column signal processing rate.

[0057] Figure 7 A preferred embodiment of the storage unit 220 in the image sensor column processing circuit of the present invention is shown. The storage unit 220 adopts a static random access memory (SRAM) structure, which is composed of four N-type transistors N0, N1, N2, and N3 and two P-type transistors P0 and P1, wherein N0, N1, P0, and P1 are used for data storage, and N2 and N3 are used for data reading. The storage unit of this static random access memory structure has an area advantage compared to ordinary latches, and can effectively reduce the chip area. In addition, the static random access memory can store more than two stable states; before writing a certain stable state to the static random access memory, the static random access memory is set to an unstable state adjacent to the stable state, thereby improving the efficiency of writing the stable state to the static random access memory.

[0058] In order to further reduce power consumption, the signal transfer step between the storage units 220 preferably adopts a low voltage difference transmission method to reduce the power consumption of the signal transfer process; and the signal transfer step between the storage units 220 can be arranged to be completed during the non-comparison time of the comparator 210 to reduce the power consumption of the comparator comparison time, thereby reducing the total power consumption.

[0059] Figure 8 , Fig. 9Taking the signal transfer between the write storage unit 221 and the temporary storage unit 222 as an example, a schematic diagram and a circuit diagram of the low voltage difference transmission mode are shown. Among them, the write storage unit 221 and the temporary storage unit 222 are both implemented by static random access memory, and the transmission pre-charging circuit 225 between the write storage unit 221 and the temporary storage unit 222 is connected to the reference voltage Vref respectively, and the working process is divided into a pre-charging stage and a transmission stage. In the pre-charging stage, the three N-type transistors N8, N9, and N10 are turned on, and the two transmission lines BL and BLb are pre-charged to the Vref voltage by the Vref reference voltage. In the transmission stage, the three N-type transistors N8, N9, and N10 are turned off. The four N-type transistors N4, N5, N6, and N7 are turned on, and bit1 and bit1b drive the two transmission lines BL and BLb respectively. In the end stage of pre-charging, take bit1 and bit1b as V1 and ground voltage respectively as an example. The BL voltage will be driven by bit1 to increase the voltage; the BLb voltage will be driven by bit1b to reduce the voltage. BL and BLb drive bit2b and bit2 through transistors N6 and N7 respectively, thereby transferring data from the write storage unit 221 to the temporary storage unit 222. The requirement for voltage V1, Vref is V1>Vref, so that the voltage of BL and Blb varies above and below Vref, thereby realizing the process of low voltage difference transmission.

[0060] In summary, the column signal processing method and processing circuit of the image sensor of the present invention latches the reference signals and pixel signals of all rows in the same storage unit in succession through a comparator. The comparator only needs to interact with the same storage unit for data, which reduces the power consumption caused by the increase in the load of the comparator due to the latching of reference signals and pixel signals of different rows in different storage units, thereby reducing the noise interference caused by the flipping of different column signals and improving the imaging quality. After the reference signal and pixel signal are read out to the digital processing unit, the image data of the image sensor is obtained by the algorithm processing of the digital processing unit, that is, the algorithm processing of the reference signal and pixel signal is not performed inside the column signal processing circuit, so the column signal processing circuit has a simple structure, fewer metal layers, and the process and circuit design are relatively easy to implement, and the power consumption and noise caused by the algorithm processing can be further reduced.

[0061] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, in any case, the embodiments should be considered exemplary and non-restrictive. Furthermore, it is apparent that the term "comprising" does not exclude other elements and steps, and the wording "a" does not exclude the plural. Multiple elements stated in a device claim may also be implemented by one element. The words first, second, etc. are used to indicate names and do not indicate any particular order.

Claims

1. A column signal processing method for an image sensor, characterized in that: include: When the image sensor quantizes the reference signal and the pixel signal, the comparator latches the reference signal and the pixel signal of all rows in the same storage unit in succession, so as to reduce the increase of noise caused by the increase of the load of the comparator due to the reference signal and the pixel signal of different rows being latched in different storage units; The comparator successively latches the reference signal and the pixel signal in the same storage unit, and then transfers the reference signal and the pixel signal latched in the same storage unit to other storage units; The reference signal and pixel signal transferred to other storage units are read out to the digital processing unit, and the digital processing unit performs algorithm processing to obtain image data of the image sensor.

2. The column signal processing method of the image sensor according to claim 1, characterized in that: The processing steps for each line of reference signal and pixel signal include: The comparator latches the reference signal into the write storage unit and transfers it to the temporary storage unit; The comparator latches the pixel signal into the write storage unit; transferring the reference signal to a reference signal readout storage unit and transferring the pixel signal to a pixel signal readout storage unit; The reference signal and the pixel signal are read out to a digital processing unit, and the digital processing unit performs algorithm processing to obtain a line of image data of the image sensor.

3. The column signal processing method of the image sensor according to claim 2, characterized in that: The readout step of the reference signal and pixel signal of the previous row is paralleled with the latching step of the reference signal and pixel signal of the next row.

4. The column signal processing method of the image sensor according to claim 2, characterized in that: Each row of reference signals includes N reference signals, where N is a positive integer. The processing steps of each row of reference signals include: The comparator latches the nth reference signal into the write storage unit and transfers it to the nth temporary storage unit; Wherein, 1≤n≤N, the above steps are repeated until all N reference signals are transferred to the corresponding temporary storage units in sequence; One of the N reference signals is selected and transferred to a reference signal reading storage unit.

5. The column signal processing method of the image sensor according to claim 2, characterized in that: The write storage unit is the storage unit closest to the comparator among all the storage units.

6. The column signal processing method of the image sensor according to claim 1, characterized in that: The signal transfer step between the storage units adopts a low voltage difference transmission mode.

7. The column signal processing method of the image sensor according to claim 1, characterized in that: The signal transfer step between the storage units is located during the non-comparison time of the comparator.

8. The column signal processing method of the image sensor according to claim 1, characterized in that: The storage unit is a static random access memory, which can store more than two stable states; before writing a stable state to the static random access memory, the static random access memory is set to an unstable state adjacent to the stable state, thereby improving the efficiency of writing the stable state to the static random access memory.

9. A column signal processing circuit for an image sensor, characterized in that: include: A comparator and multiple storage units. When the image sensor quantizes the reference signal and the pixel signal, the comparator latches the reference signal and the pixel signal of all rows in the same storage unit in turn, and then transfers the reference signal and the pixel signal latched in the same storage unit to other storage units. Then, the reference signal and the pixel signal transferred to the other storage units are read out to an external digital processing unit. The digital processing unit performs algorithm processing to obtain the image data of the image sensor.

10. The column signal processing circuit of the image sensor according to claim 9, characterized in that: The plurality of storage units include: A write storage unit connected to the comparator, for latching reference signals and pixel signals of all rows; A temporary storage unit connected to the write storage unit, used for temporarily storing the reference signal; A reference signal readout storage unit connected to the temporary storage unit, used for storing a reference signal to be read out; The pixel signal readout storage unit connected to the write storage unit is used to store the pixel signal to be read out.

11. The column signal processing circuit of the image sensor according to claim 10, characterized in that: The temporary storage unit comprises: The N temporary storage units are respectively used to store N reference signals, where N is a positive integer.

12. The column signal processing circuit of the image sensor according to claim 10, characterized in that: The write storage unit is the storage unit closest to the comparator among all the storage units.

13. The column signal processing circuit of the image sensor according to claim 9, characterized in that: The transmission lines between the storage units are respectively connected to reference voltages, so as to realize the signal transfer step between the storage units in a low voltage difference transmission mode.

14. The column signal processing circuit of the image sensor according to claim 9, characterized in that: The storage unit is a static random access memory.

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