Driving backplane, display panel and display device

Abstract

The present disclosure provides a driving backplane, a display panel and a display device, including a driving backplane, comprising: a substrate, comprising a display area and a fan-out area located on at least one side of the display area; the display area comprises a plurality of pixel units arranged in an array, and a plurality of signal lines connected to the pixel units, and the plurality of signal lines extend along a first direction; the fan-out area comprises a fan-out line, the fan-out line is connected to the signal line, the fan-out line comprises a first end close to the display area and a second end away from the display area, the width of the first end is greater than the width of the second end; at least one signal line is connected to at least one fan-out line through a connecting line, and the connecting line extends along a second direction.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving backplane, a display panel and a display device. Background Art

[0002] Sub-millimeter or even micrometer-scale light-emitting diodes based on the principle of inorganic light-emitting diodes are self-luminous devices like OLEDs. Like organic light-emitting diodes (OLEDs), they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared to OLEDs that emit light based on organic matter. Summary of the invention

[0003] The present disclosure provides a driving backplane, a display panel and a display device, and the specific scheme is as follows:

[0004] In one aspect, an embodiment of the present disclosure provides a driving backplane, comprising:

[0005] A substrate, comprising a display area and a fan-out area located at least on one side of the display area;

[0006] The display area includes a plurality of pixel units arranged in an array, and a plurality of signal lines connected to the pixel units, wherein the signal lines extend along a first direction;

[0007] The fan-out area includes a plurality of fan-out lines connected to the plurality of signal lines, the fan-out lines include a first end close to the display area and a second end away from the display area, and a width of the first end is greater than a width of the second end;

[0008] At least one of the signal lines is connected to at least one of the fan-out lines via a connecting line, and the connecting line extends along the second direction.

[0009] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, the length of the connecting line is greater than or equal to the spacing distance between two adjacent pixel units in the second direction, and less than or equal to the sum of the width of a single pixel unit column and the spacing distance between two adjacent pixel units.

[0010] Optionally, in the driving backplane provided in the embodiment of the present disclosure, the signal line connected to the fan-out line through the connecting line is connected to the outermost pixel unit column.

[0011] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, at least one of the signal lines is directly connected to at least one of the fan-out lines.

[0012] Optionally, in the above-mentioned driving backplane provided in an embodiment of the present disclosure, the fan-out area is folded at a side opposite to the display side of the driving backplane, and a minimum distance between the connecting line and the bending axis in the first direction is greater than 150 μm.

[0013] Optionally, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, the minimum distance between the fan-out line and the boundary of the base substrate in the second direction is greater than 1000 μm.

[0014] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, a gap between two adjacent signal lines in the second direction and a gap between two adjacent connection lines in the first direction are respectively greater than 100 μm.

[0015] Optionally, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, the fan-out area includes a first fan-out area located at one side of the display area;

[0016] Part of the fan-out lines in the first fan-out area are connected to the signal line through the connecting line, and the remaining part of the fan-out lines are directly connected to the signal line.

[0017] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, the fan-out area also includes a second fan-out area, and the second fan-out area and the first fan-out area are respectively located on both sides of the display area in the second direction; the fan-out line of the second fan-out area is directly connected to the signal line.

[0018] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, all the signal lines include: a plurality of data signal lines, a plurality of reference signal lines and a plurality of positive signal lines;

[0019] Each pixel unit column is electrically connected to one of the data signal lines, one of the reference signal lines and one of the positive signal lines; and the distances between the data signal line, the reference signal line, the positive signal line and the boundary of the substrate corresponding to each pixel unit column increase in sequence;

[0020] All of the pixel units constitute M pixel unit columns arranged in sequence in the second direction; wherein the outermost two pixel unit columns are respectively the first pixel unit column and the Mth pixel unit column, and in the second direction, the distance between the data signal line corresponding to the first pixel unit column and the boundary of the substrate is smaller than the distance between the data signal line corresponding to the Mth pixel unit column and the boundary of the substrate;

[0021] The data signal lines respectively corresponding to the first pixel unit column, the second pixel unit column and the Mth pixel unit column are connected to the fan-out lines of the first fan-out area through the connecting lines;

[0022] The data signal lines respectively corresponding to the 3rd pixel unit column to the (M-1)th pixel unit column are directly connected to the fan-out lines of the first fan-out area;

[0023] The plurality of reference signal lines and the plurality of positive signal lines are directly connected to the fan-out lines of the second fan-out region.

[0024] Optionally, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, all the signal lines further include: transfer signal lines between the data signal line and the reference signal line, and between the Mth pixel unit column and the boundary of the substrate, each of the transfer signal lines being electrically connected to a pixel unit row;

[0025] The transfer signal line between the data signal line and the reference signal line corresponding to the first pixel unit column, the transfer signal line between the data signal line and the reference signal line corresponding to the M-th pixel unit column, and the transfer signal line between the M-th pixel unit column and the boundary of the substrate are connected to the fan-out line of the first fan-out area through the connecting line;

[0026] The transfer signal lines between the data signal lines and the reference signal lines respectively corresponding to the 3rd pixel unit column to the (M-1)th pixel unit column are directly connected to the fan-out lines of the first fan-out area.

[0027] Optionally, the driving backplane provided in the embodiment of the present disclosure further includes a plurality of scanning signal lines, wherein the scanning signal lines extend along the second direction between the pixel unit rows, and each of the scanning signal lines is electrically connected to a corresponding transfer signal line.

[0028] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, it includes a first conductive layer and a second conductive layer which are sequentially arranged on the base substrate and insulated from each other;

[0029] The data signal line, the reference signal line, the positive signal line and the switching signal line are located in the first conductive layer, and the scanning signal line is located in the second conductive layer.

[0030] Optionally, the driving backplane provided in the embodiment of the present disclosure further includes: a first binding area provided on a side of the first fan-out area away from the display area, and a second binding area provided on a side of the second fan-out area away from the display area; wherein,

[0031] The first binding area is provided with a first chip; the fan-out line of the first fan-out area is bound and connected to the first chip;

[0032] The second binding area is provided with a second chip and a third chip, and the second chip and the third chip are symmetrically arranged about the central axis of the display area in the first direction;

[0033] The fan-out line in the second fan-out area located on one side of the central axis of the display area in the first direction is bound and connected to the second chip, and the fan-out line located on the other side of the central axis of the display area in the first direction is bound and connected to the third chip.

[0034] On the other hand, an embodiment of the present disclosure provides a display panel, including the above-mentioned driving backplane, and a plurality of micro light emitting diodes electrically connected to the driving backplane.

[0035] On the other hand, an embodiment of the present disclosure provides a display device, comprising the above-mentioned multiple display panels, wherein the multiple display panels are spliced ​​together. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the structure of a driving backplane provided in an embodiment of the present disclosure;

[0037] Figure 2 for Figure 1 Schematic diagram of the enlarged structure of the middle NA region;

[0038] Figure 3 for Figure 2 Schematic diagram of a fan-out line in ;

[0039] Figure 4 for Figure 2 An enlarged structural diagram of four fan-out lines symmetrically arranged about the symmetry axis Q;

[0040] Figure 5 for Figure 1 Schematic diagram of the enlarged structure of the middle LD region;

[0041] Figure 6 for Figure 1 Schematic diagram of the enlarged structure of the middle RD region;

[0042] Figure 7 A schematic diagram of another structure of a driving backplane provided in an embodiment of the present disclosure;

[0043] Figure 8 A schematic diagram of another structure of a driving backplane provided in an embodiment of the present disclosure;

[0044] Fig. 9 A schematic diagram of another structure of a driving backplane provided in an embodiment of the present disclosure;

[0045] Fig.10 for Figure 1Schematic diagram of the structure of a pixel unit P. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that the size and shape of the figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0048] Micro / mini-LED technology is to shrink the size of existing inorganic light-emitting diodes (LEDs) to 500μm or less, which is about 1% of the size of existing LEDs. Then, through mass transfer technology, the micron-scale Micro / mini-LEDs are transferred to the driver backplane, thus forming Micro / mini-LED displays of various sizes. A major advantage of Micro / mini LEDs is that they can be spliced ​​together, using multiple small-sized panels to create large-sized panels.

[0049] In the related art of splicing a plurality of small-sized panels to form a large-sized panel, in order to reduce the splicing gap, the fan-out area of ​​the small-sized panel can be set on the opposite surface of the display side to reduce the size of the non-display area of ​​a single small-sized panel, so as to make the size of the splicing seam between adjacent panels as small as possible. However, the inventors found that since the display area is directly connected to the fan-out area, and the distance between the signal line located at the outermost side close to the edge of the panel and the edge of the panel is less than 100 μm, if the fan-out area located on the display side is directly bent to the opposite surface of the display side, then during the bending process, the edge signal line will inevitably be damaged due to the large bending stress at the edge, resulting in a broken line defect.

[0050] In order to at least solve the above technical problems existing in the related art, the embodiment of the present disclosure provides a driving backplane, such as Figure 1 As shown, it may include:

[0051] A substrate, comprising a display area AA and a fan-out area (eg, a first fan-out area FA1 and / or a second fan-out area FA2) located at at least one side of the display area AA;

[0052] The display area AA includes a plurality of pixel units P arranged in an array, and a plurality of signal lines L (such as C1, D1, H2, etc.) connected to the pixel units P. 11 , H 12 , V1, etc.), the signal line extends along the first direction Y;

[0053] The fan-out area (eg, the first fan-out area FA1 and / or the second fan-out area FA2) includes a plurality of signal lines L (eg, C1, D1, H 11 , H 12 , V1, etc.), the fan-out line F includes a first end b close to the display area AA and a second end a away from the display area AA, and the width d2 of the first end b is greater than the width d1 of the second end a. Figure 2 and Figure 3 As shown;

[0054] At least one signal line L (eg, C1 , D1 , etc.) is connected to at least one fan-out line F via a connection line E, and the connection line E extends along the second direction X.

[0055] In the above-mentioned driving backplane provided in the embodiment of the present disclosure, by setting a connecting line E extending in the second direction X, and using the connecting line E to connect the signal line (such as C1, D1, etc.) extending in the first direction Y to the fan-out line F, the minimum distance d between the fan-out line F and the side of the substrate parallel to the first direction Y is increased, so that when the fan-out area is bent to the opposite side of the display side (i.e., the back side), the distance between the fan-out line F and the boundary of the substrate is increased, and the broken line of the fan-out line F caused by excessive edge bending stress can be effectively improved, thereby also avoiding the cracks on the fan-out line F extending to the signal line (such as C1, D1, etc.) and causing cracks in the signal line (such as C1, D1, etc.), thereby effectively improving the product yield. It can be understood that the material of the substrate is a flexible material, such as polyimide, so as to be able to realize the operation of bending a partial area of ​​the substrate.

[0056] It should be noted that in Figure 1 The connection relationship of each signal line L is only given as an example, and the thickness and width of the line do not represent the actual shape and actual width of the signal line L.

[0057] See also Figure 1 In the present disclosure, the fan-out area may include a first fan-out area FA1 and a second fan-out area FA2, and the second fan-out area FA2 and the first fan-out area FA1 are respectively located at both sides of the display area AA in the second direction X;

[0058] A first binding area BA1 is provided on a side of the first fan-out area FA1 away from the display area AA, and a second binding area BA2 is provided on a side of the second fan-out area FA2 away from the display area AA; wherein the first binding area BA1 is provided with a first chip IC1; the second binding area BA2 is provided with a second chip IC2 and a third chip IC3, and the second chip IC2 and the third chip IC3 are symmetrically arranged about a central axis Z of the display area AA in the first direction Y;

[0059] One end of some fan-out lines F in the first fan-out area FA1 is connected to the signal line L (for example, C1, D1, etc.) through the connection line E, and one end of the remaining fan-out lines F is directly connected to the signal line L (for example, C1, D1, etc.). m , D m The other ends of all the fan-out lines F of the first fan-out area FA1 are bound and connected to the first chip IC;

[0060] One end of all fan-out lines F in the second fan-out area FA2 is directly connected to the signal line L (for example, H 11 , H 12, V1, etc.), the other end of the fan-out line F on the side of the central axis Z of the display area AA on the first direction Y in the second fan-out area FA2 is bound and connected to the second chip IC2, and the other end of the fan-out line F on the other side of the central axis Z of the display area AA on the first direction Y is bound and connected to the third chip IC3.

[0061] This arrangement can reasonably utilize the space on both sides of the display area AA for wiring the fan-out lines F, solving the problem of limited wiring space for the fan-out lines F on one side of the display area AA. In addition, each fan-out line F can be connected to the chip nearby, thereby effectively reducing the space of the fan-out area and facilitating the realization of a narrow frame.

[0062] Figures 2 to 4 In the example, the signal line L of the display area AA is connected to the second chip IC2 via the fan-out line F of the second fan-out area FA2 to illustrate the specific wiring method of the fan-out line F. When the signal line L is connected to the third chip IC3 via the fan-out line F, and the signal line L is connected to the first chip IC1 via the fan-out line F, reference can be made to Figure 2 and Figure 4 To design the fan-out line F.

[0063] See also Figure 2 and Figure 3 The second binding area BA2 may also include a plurality of binding electrodes PD, and the binding electrodes PD are bound and connected to the second chip IC2. In some embodiments, the binding electrodes PD may also be bound and connected to components such as a flexible circuit board. Therefore, the number and size of the binding electrodes PD need to match the second chip IC2 or the flexible circuit board and other components to which they are bound and connected. In order to ensure the thinness and narrow frame of the overall device, the size of the second chip IC2 or the flexible circuit board and other components is generally small, and the size of each binding electrode PD is relatively small.

[0064] However, unlike other electronic devices such as liquid crystal display devices and touch devices, in order to ensure the performance of the product, the signal line on the driving backplane needs to have a certain line width, which needs to be 3.8 mm or even larger, and due to the limitation of the design space, the signal line L cannot be directly connected to the corresponding binding electrode PD. In the embodiment of the present disclosure, the signal line L is connected to the corresponding binding electrode PD by setting a fan-out line F, and the line width d1 of at least one fan-out line F at the first end a is smaller than the line width d2 at the second end b, and at least one fan-out line F includes a first straight portion F1 and an oblique portion F2, wherein the extension direction of the oblique portion F2 has a certain angle with the first direction Y, so that the space in the driving backplane can be reasonably utilized, so that the signal line L can be connected to the corresponding binding electrode 30. The above-mentioned connection method in the embodiment of the present disclosure can reduce the area of ​​the fan-out area, which is more conducive to the narrow frame design.

[0065] It should be noted that, in the embodiment of the present disclosure, the line width of the fan-out line F can be understood as the width of the fan-out line F in a direction perpendicular to its own extension direction.

[0066] In specific implementation, the number of binding electrodes PD connected to each signal line L can be determined according to the width of the second binding area BA2, the number of signal lines L in the driving backplane, etc. Figure 3 In the figure, a signal line L connected to a binding electrode PD is taken as an example for illustration. In a specific implementation, a signal line L may also be connected to a plurality of binding electrodes PD. The corresponding relationship between the signal line L and the binding electrode PD is not limited here.

[0067] In the disclosed embodiment, the line width d1 of at least one fan-out line F at the first end a is smaller than the line width d2 at the second end b. For example, in the direction from the first end a of the fan-out line F to the second end b, the line width of at least one fan-out line F tends to gradually increase. It should be noted here that the line width of the fan-out line F may gradually increase from the first end a to the second end b, or the line width of a certain part of the fan-out line F gradually increases, and the line width of the remaining part may remain unchanged, as long as the line width of the fan-out line F tends to gradually increase as a whole.

[0068] In specific implementation, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, if Figure 3 As shown, in the direction from the first end a of the fan-out line F to the second end b, the line width of the oblique line portion F2 in the direction perpendicular to its own extension direction gradually increases, and the line width of the oblique line portion F2 is greater than or equal to the line width of the first straight line portion F1. In other words, in the direction from the second end b of the fan-out line F to the first end a, the line width of the oblique line portion F2 gradually narrows, and the extension direction of the oblique line portion F2 has a certain angle with the first direction Y, so that the oblique line portion F2 is inclined toward the binding electrode PD, so that the fan-out line F can connect the signal line L with the corresponding binding electrode PD, and fully utilize the wiring space of the driving backplane.

[0069] Optionally, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, as Figure 3 As shown, the first straight line portion F1 of at least one fan-out line F includes two sub-side edges along the first direction Y (such as Figure 3As shown in F1a and F1b in FIG, the portions of the first straight line portion F1 corresponding to the overlapping areas of the projections of the two sub-sides in the first direction Y respectively have the same width perpendicular to the first direction Y. By providing the first straight line portion F1 extending along the first direction Y in the fan-out line F, the fan-out line F and the binding electrode PD can be connected, and the portions of the first straight line portion F1 corresponding to the overlapping areas of the projections of the two sub-sides in the first direction Y respectively have the same width perpendicular to the first direction Y, thereby obtaining the first straight line portion F1 that matches the width of the corresponding binding electrode and meets the spacing requirement between adjacent connection lines, and can avoid short circuit or signal crosstalk between adjacent connection lines.

[0070] It should be noted that, in the embodiment of the present disclosure, the part of the first straight line portion F1 corresponding to the overlapping area of ​​the projections of the two sub-sides in the first direction Y has a consistent line width perpendicular to the first direction Y. It can be understood that: the difference in the line width of the first straight line portion F1 at various positions in the part is less than the set value, that is, the line width of the first straight line portion F1 at various positions in the part is approximately the same.

[0071] In practical applications, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, Figure 2 and Figure 3 As shown, in the second direction X, the length of each first straight line portion F1 in the first direction Y increases first and then decreases; the second direction X is a direction perpendicular to the first direction Y. Figure 2 As shown in the figure, the straight line portion of the fan-out line F connected to the second binding area BA2 is the first straight line portion F1. Figure 2 It can be clearly seen that in the second direction X, that is, the direction from left to right in the figure, the length of the first straight portion F1 in the first direction Y shows a trend of first increasing and then decreasing. That is to say, among the multiple fan-out lines F in the driving backplane, the length of the first straight portion F1 corresponding to the middle position of the second chip IC2 is larger, and the length of the first straight portion F1 corresponding to the positions on both sides is smaller. In this way, the space of the second fan-out area FA2 can be more reasonably utilized, so that the signal line L can be connected to the corresponding binding electrode PD.

[0072] Among the multiple signal lines L in the driving backplane, the signal line L at the middle position of the second chip IC2 is closer to the second chip IC2, so the fan-out line F connected to the signal line L at the middle position of the second chip IC2 includes a shorter oblique line portion F2, while the signal lines L at the two side positions are farther away from the second chip IC2, so the fan-out line F connected to the signal lines L at the two side positions includes a longer oblique line portion F2. Therefore, by setting the length of the first straight line portion F1 at the middle position to be larger and the length of the first straight line portion F1 at the two side positions to be smaller, the space of the second fan-out area FA2 can be more reasonably utilized.

[0073] Furthermore, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, if Figure 2 As shown, in the second direction X, the lengths of the first straight line portions F1 in the first direction Y are symmetrically distributed along the symmetry axis Q of the second chip IC2 in the first direction Y. In this way, the space of the second fan-out area FA2 can be more reasonably utilized, which facilitates the wiring design in the second fan-out area FA2, so that each fan-out line F in the second fan-out area FA2 can meet the requirements of the circuit setting.

[0074] It should be noted that in the embodiments of the present disclosure, see Figure 3 The length of the first straight line portion F1 in the first direction Y can be understood as: the length of the portion of the first straight line portion F1 corresponding to the overlapping area of ​​the projections of the two sub-side edges F1a and F1b in the first direction Y is mainly the length of the area with consistent line width in the first straight line portion F1.

[0075] Figure 4 for Figure 2 A partial enlarged schematic diagram of four connecting lines symmetrically arranged about the symmetry axis Q is shown in FIG. Figure 4 As shown, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, on one side of the symmetry axis Q, the length of one of the two sub-sides of each first straight portion F1 close to the symmetry axis Q is greater than or equal to the length of the other sub-side, Figure 4 In the diagram, the sub-side close to the symmetry axis Q is F1b, and the sub-side far from the symmetry axis Q is F1a, that is, the length of the sub-side F1b in each first straight line portion F1 is greater than the length of the sub-side F1a, and any two first straight line portions F1 arranged along the second direction X, any one of the two sub-sides of one of the first straight line portions F1 closer to the symmetry axis Q is greater than or equal to any one of the two sub-sides of the other first straight line portion F1. Figure 4 In the embodiment, on the one hand, of the two first straight portions F1 on the left side of the symmetry axis Q, the length of the two sub-sides of the first straight portion F1 closer to the symmetry axis Q is greater than the length of the two sub-sides of the other first straight portion. By setting in this way, a first straight portion F1 with a smaller width can be obtained to meet the spacing requirement between adjacent fan-out lines F and prevent signal crosstalk between adjacent signal lines L. On the other hand, the larger of the two angles between the sub-side F1a of the first straight portion F1 and the side of the oblique portion F2 connected thereto is the first angle, and the smaller of the two angles between the sub-side F1b and the side of the oblique portion F2 connected thereto is the second angle. Then, on one side of the symmetry axis Q, the farther the distance between the first straight portion F1 and the symmetry axis Q is, the larger the first angle is and the smaller the second angle is. For example Figure 4In the two adjacent fan-out lines F on the right side of the symmetry axis Q, the first angle θ1 is smaller than the first angle θ2, and the second angle γ1 is larger than the second angle γ2.

[0076] Furthermore, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, at least one of the plurality of fan-out lines F may further include: a second straight line portion F3 extending along the first direction Y;

[0077] The oblique line portion F2 is connected to the signal line L through the second straight line portion F3;

[0078] The line width of the second straight line portion F3 is greater than or equal to the line width of the oblique line portion F2.

[0079] In the disclosed embodiment, by setting the second straight portion F2, the length and inclination of the oblique portion F2 in each fan-out line F can be adjusted, so that each signal line L can be connected to the corresponding binding electrode PD through the fan-out line F, and a certain distance is maintained between each fan-out line F to avoid short-circuiting of adjacent fan-out lines F, thereby making more reasonable use of space, making the second fan-out area FA2 occupy a smaller space in the first direction Y, and being more conducive to narrow frame design.

[0080] In specific implementation, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, if Figure 3 As shown, the second straight line portion F3 of at least one fan-out line F includes two sub-side edges along the first direction Y (such as Figure 3 As shown in F3a and F3b in FIG. 1 , the portions of the second straight line portion F3 corresponding to the overlapping areas of the projections of the two sub-sides in the first direction Y have the same width perpendicular to the first direction Y, so that short circuits between adjacent fan-out lines F can be avoided.

[0081] It should be noted that, in the embodiment of the present disclosure, the part of the second straight line portion F3 corresponding to the overlapping area of ​​the projections of the two sub-sides in the first direction Y has a consistent width perpendicular to the first direction Y. It can be understood that: the line width difference of the second straight line portion F3 at various positions in this part is less than the set value, that is, the line width of the second straight line portion F3 at various positions in this part is approximately the same.

[0082] In practical applications, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, Figure 2 and Figure 3 As shown, in the second direction X, the length of each second straight line portion F3 in the first direction Y tends to decrease first and then increase; the second direction X is a direction perpendicular to the first direction Y. Figure 2 As shown in the figure, the straight line portion of the fan-out line F connected to the signal line L is the second straight line portion F3. Figure 2It can be clearly seen that in the second direction X, that is, the direction from left to right in the figure, the length of the second straight portion F3 in the first direction Y shows a trend of first decreasing and then increasing. That is to say, among the multiple fan-out lines F in the driving backplane, the length of the second straight portion F3 at the middle position of the second chip IC2 is smaller, and the length of the second straight portion F3 at the two side positions is larger. In this way, the space of the second fan-out area FA2 can be more reasonably utilized, so that the signal line L can be connected to the corresponding binding electrode PD.

[0083] Among the multiple signal lines L in the driving backplane, the signal line L at the middle position of the second chip IC2 is closer to the second chip IC2, so the oblique part F2 contained in the fan-out line F connected to the signal line L at the middle position of the second chip IC2 can be shorter, while the signal lines L at the two side positions are farther away from the second chip IC2, so the oblique part F2 of the fan-out line F corresponding to the signal lines L at the two side positions needs to be longer. In the embodiment of the present disclosure, by setting the length of the first straight line part F1 at the middle position to be larger and the length of the first straight line part F1 at the two side positions to be smaller, and setting the length of the second straight line part F3 at the middle position to be smaller and the length of the second straight line part F3 at the two side positions to be larger, the length and inclination of the oblique part F2 in each fan-out line F can be adjusted, so that the signal line L can be connected to the corresponding binding electrode PD through the fan-out line F, and the space of the second fan-out area FA2 can be more reasonably utilized.

[0084] Furthermore, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, if Figure 2 As shown, in the second direction X, the lengths of the second straight line portions F3 in the first direction Y are symmetrically distributed along the symmetry axis Q of the second chip IC2 in the first direction Y. In this way, the space of the second fan-out area FA2 can be more reasonably utilized, which facilitates the wiring design in the second fan-out area FA2, so that the fan-out lines F in the second fan-out area FA2 can meet the requirements of circuit settings.

[0085] It should be noted that in the embodiments of the present disclosure, see Figure 3 The length of the second straight line portion F3 in the first direction Y can be understood as: the length of the part of the second straight line portion F3 corresponding to the overlapping area of ​​the projections of the two sub-side edges F3a and F3b in the first direction Y is mainly the length of the area with consistent line width in the second straight line portion F3.

[0086] like Figure 4 As shown, taking four connecting lines symmetrically arranged about the symmetry axis Q as an example, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, on one side of the symmetry axis Q, the length of one of the two sub-sides of each second straight line portion F3 close to the symmetry axis Q is less than or equal to the length of the other sub-side, Figure 4In the diagram, the sub-side close to the symmetry axis Q is F3b, and the sub-side far from the symmetry axis Q is F3a as an example, that is, the length of the sub-side F3b in each second straight line portion F3 is less than the length of the sub-side F3a, and any two second straight line portions F3 arranged along the second direction X, any one of the two sub-sides of one of the second straight line portions F3 closer to the symmetry axis Q is less than or equal to any one of the two sub-sides of the other second straight line portion F3, for example Figure 4 In the embodiment, on the one hand, of the two second straight portions F3 on the left side of the symmetry axis Q, the lengths of the two sub-sides of the second straight portion F3 closer to the symmetry axis Q are smaller than the lengths of the two sub-sides of the other second straight portion. By setting in this way, a second straight portion with a smaller width can be obtained to meet the spacing requirements between adjacent connecting lines and prevent signal crosstalk between adjacent signal lines. On the other hand, the smaller of the two angles between the sub-side F3a of the second straight portion F3 and the side of the oblique portion F2 connected thereto is the third angle, and the larger of the two angles between the sub-side F3b and the side of the oblique portion F2 connected thereto is the fourth angle. Then, on one side of the symmetry axis Q, the farther the distance between the second straight portion 303 and the symmetry axis Q is, the smaller the third angle is and the larger the fourth angle is. For example, Figure 4 In the two adjacent fan-out lines F on the right side of the symmetry axis Q, the third angle β1 is greater than the third angle β2, and the fourth angle α1 is less than the fourth angle α2.

[0087] In practical applications, in the above-mentioned driving backplane provided by the embodiment of the present disclosure, Figure 2 and Figure 3 As shown, the signal line L is connected to the corresponding binding electrodes PD through the fan-out line F, and the line width d2 of the fan-out line F at the second end b is set to be consistent with the line width of the signal line L. The line width of the fan-out line F can be made larger without increasing the difficulty of wiring, thereby making the resistance of the fan-out line F smaller, ensuring the product performance of the driving backplane is better. It should be noted that in the embodiment of the present disclosure, the line width of the fan-out line F at the second end b is consistent with the line width of the signal line L, which means that the difference between the line width of the fan-out line F at the second end b and the line width of the signal line L is less than the set value, that is, the line width of the fan-out line F at the second end b is approximately equal to the line width of the signal line L.

[0088] In addition, in the embodiment of the present disclosure, the line width d2 of the fan-out line F at the second end b is consistent with the line width of the signal line L. In a specific implementation, the line width d2 of the fan-out line F at the second end b may also be greater than or equal to the line width of the signal line L, as long as it can meet the circuit design requirements in the driving backplane. The line width of the connecting line is not limited here.

[0089] Furthermore, the line width d1 of the fan-out line F at the first end a is set to be greater than the width of each correspondingly connected binding electrode PD. In order to ensure the performance of the product, the minimum width of the fan-out line F needs to be greater than the set threshold, and the size of the binding electrode PD connected to the fan-out line F is small. Therefore, the line width d1 of the fan-out line F at the first end a can be set to be greater than the width of each correspondingly connected binding electrode PD. When the fan-out line F is connected to multiple binding electrodes PD, the line width d1 of the fan-out line F at the first end a can be greater than the sum of the total width and the gap of each corresponding binding electrode PD. For example, the signal line L is connected to three binding electrodes PD through the fan-out line F, and the line width of the fan-out line F at the first end a is greater than the total width of the three binding electrodes PD and the gap between the three binding electrodes PD. In this way, the width of the fan-out line F can be further increased, thereby further reducing the resistance of the fan-out line F. It should be noted that the line width of the fan-out line F at the first end a is greater than the width of each correspondingly connected binding electrode PD, and it is necessary to ensure that a certain distance is maintained between adjacent fan-out lines F to prevent short circuits between adjacent fan-out lines F.

[0090] Specifically, in the driving backplane provided by the embodiment of the present disclosure, the line width of the signal line L is 20 to 130 times the line width of the binding electrode PD.

[0091] In a specific implementation, the line width of the binding electrode PD is about 70 μm, while the line width of the signal line L is between 1500 μm and 9000 μm. It can be seen that in the micro-LED display device, the line width of the signal line L in the driving backplane is quite different from the line width of the binding electrode PD, so the wiring of the fan-out area is difficult. In the embodiment of the present disclosure, the signal line L is connected to the corresponding binding electrode PD by setting the fan-out line, which solves the technical problem of the difficulty of wiring in the fan-out area.

[0092] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 5 and Figure 6 As shown, the length of the connection line E may be greater than or equal to the spacing distance d3 between two adjacent pixel units P in the second direction X, and less than or equal to the sum of the width d4 of a single pixel unit column and the spacing distance d3 between two adjacent pixel units P. It should be understood that if the wiring space allows, the length of the connection line E is as long as possible, that is, the minimum distance between the outermost signal line L or the outermost fan-out line F and the side of the substrate parallel to the first direction Y should be maximized, thereby reducing the disconnection defect caused by the bending stress generated by the mechanical action.

[0093] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, as Figure 1As shown, the signal line L (eg, C1, D1, etc.) connected to the fan-out line F through the connecting line E is connected to the outermost pixel unit column. This arrangement facilitates wiring design and can ensure that the wiring resistance is small.

[0094] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, as Figure 1 As shown, when the distance between the wiring and the left and right boundaries of the substrate is large, the stress is less affected, so at least one signal line L (for example, H 11 , H 12 , V1, etc.) is directly connected to at least one fan-out line F. In some embodiments, the minimum distance d5 from the signal line L connected to the at least one fan-out line F to the left edge of the substrate may be 320 μm, and the minimum distance d6 from the signal line L connected to the at least one fan-out line F to the right edge of the substrate may be 175 μm. Figure 1 shown.

[0095] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, the fan-out area (for example, the first fan-out area FA1 and / or the second fan-out area FA2) can be folded at the opposite side of the display side of the driving backplane. In this case, the minimum distance d' between the connecting line E and the bending axis K in the first direction Y can be set to be greater than 150 μm. Figure 1 shown.

[0096] After the fan-out area is folded toward the back of the driving backplane based on the bending axis K, multiple display side panels are spliced. The minimum distance d' between the connection line E and the bending axis K in the first direction Y is set to be greater than 150μm, which can effectively avoid the connection line E being affected by the splicing stress and the like when the boundary at the bending axis K is used as a splicing boundary during the subsequent splicing process due to the small distance from the bending axis K. In some embodiments, the connection line E can be located in the display area AA, so that the connection line E can completely avoid the area that needs to be bent, thereby reducing the influence of the bending stress on the connection line E.

[0097] Optionally, in the above-mentioned driving backplane provided in the embodiment of the present disclosure, in order to reduce the influence of bending stress, splicing stress, etc. as much as possible, as shown in FIG. Figure 1 , Figure 5 and Figure 6 As shown, the minimum distance d between the fan-out line F and the boundary (ie, the left and right boundaries) of the substrate in the second direction X may be greater than 1000 μm. In some embodiments, the distance d may be equal to 1250 μm.

[0098] Optionally, in the driving backplane provided in the embodiment of the present disclosure, in order to avoid short circuit of adjacent wirings or signal crosstalk, the gap between two adjacent signal lines L in the second direction X and the gap between two adjacent connection lines E in the first direction Y can be set to be greater than 100 μm respectively.

[0099] Although, Figure 1 There is no special design for the signal lines with the second fan-out area FA2, but it can be understood that according to the concept of the present invention, the signal lines with the 1st pixel unit column and the Mth pixel column can be narrowed toward the inner side of the driving backplane through the connecting lines extending along the second direction X, and then connected to the fan-out lines in the second fan-out area FA2, thereby further improving the reliability of the driving backplane.

[0100] In some embodiments, Figure 1 , Figures 7 to 9 As shown, the plurality of signal lines L may include a plurality of data signal lines D extending along a first direction Y. m , multiple reference signal lines V m , multiple positive signal lines H m1 , H m2 And multiple transfer signal lines C n ; wherein m is an integer greater than or equal to 1 and less than or equal to M, M is the total number of pixel unit columns; n is an integer greater than or equal to 1 and less than or equal to N, N is the total number of pixel unit rows; in the present disclosure, multiple scanning signal lines S may also be provided n , each scanning signal line S n Extending along a second direction X between each pixel unit row;

[0101] Each pixel unit column is connected to a data signal line D m , a reference signal line V m and a positive signal line H m ; Each transfer signal line C n Through a scanning signal line S n Connected to a pixel unit row, so that the signal line C n To the corresponding scanning signal line S n Provide a scanning signal, so that the signal source for providing the scanning signal can be set on the transfer signal line C n Avoid the scanning signal line S n Chips for providing scanning signals are arranged at both ends.

[0102] In some embodiments, Figure 1 and Figure 7As shown, when the number N of pixel unit rows in the display area AA is the same as the number M of pixel unit columns, that is, when N = M, a transfer signal line C is correspondingly arranged on one side of each pixel unit column n , and only one transfer signal line C is arranged between every two adjacent pixel unit columns n . For example, a transfer signal line C2 corresponding to and electrically connected to the scan signal line S2 is arranged on the right side of the second column of pixels

[0103] In some embodiments, as Figure 8 shown, when the number N of pixel unit rows in the display area AA is less than the number M of pixel unit columns, that is, when N < M, a transfer signal line C is correspondingly arranged on one side of some pixel unit columns n , the number of these pixel unit columns is N, and there is no transfer signal line C on one side of some other pixel unit columns n , the number of these pixel unit columns is (M - N), and there is no transfer signal line C between every two adjacent pixel unit columns in these pixel unit columns at this time n . For example, no transfer signal line C is arranged on the right side of the second column of pixels n , and the transfer signal line C2 corresponding to and electrically connected to the scan signal line S2 is arranged on one side of other pixel unit columns

[0104] In some embodiments, as Fig. 9 shown, when the number N of pixel unit rows in the display area AA is greater than the number M of pixel unit columns, that is, when N > M, at least one transfer signal line C is correspondingly arranged on one side of each pixel unit column n , a transfer signal line C is correspondingly arranged on one side of some pixel unit columns n , and there is no transfer signal line C arranged on one side of some other pixel unit columns n , and two transfer signal lines C are arranged between two adjacent columns of pixel units n . For example, a transfer signal line C2 corresponding to and electrically connected to the scan signal line S2 is arranged on the right side of the second column of pixels, and a transfer signal line C 20 corresponding to and electrically connected to the scan signal line S 20 .

[0105] Specifically, taking Figure 1 shown as an example, the setting of the connection line E in the present disclosure is described. In Figure 1 , the data signal line D m , reference signal line V m , and positive electrode signal line H m corresponding to each pixel unit column increase in distance from the boundary of the substrate in sequence;

[0106] The plurality of pixel units P constitute M pixel unit columns arranged in sequence in the second direction X; wherein the outermost two pixel unit columns are the first pixel unit column and the Mth pixel unit column, and in the second direction X, the first pixel unit column corresponds to the data signal line D m The distance between the substrate and the substrate boundary is smaller than the data signal line D corresponding to the Nth pixel unit column. m The distance between the substrate and the substrate boundary; in other words, Figure 1 , M pixel unit columns are arranged along the second direction X, including the m-th pixel unit column, where 1≤m≤M, and is an integer;

[0107] The first pixel unit column, the second pixel unit column and the Mth pixel unit column correspond to the data signal lines D1, D2 and D M connected to the fan-out line F of the first fan-out area FA via a connecting line E;

[0108] The data signal lines D3 to D4 corresponding to the 3rd pixel unit column to the (M-1)th pixel unit column are respectively M-1 Directly connected to the fan-out line F of the first fan-out area FA1;

[0109] Multiple reference signal lines V1 to V M And multiple positive signal lines H 11 To H M1 , H 12 To H M2 Directly connected to the fan-out line F of the second fan-out area FA2.

[0110] By M The fan-out lines F are connected via the connection lines E, so that the distance between the fan-out lines F and the boundary of the base substrate is increased, thereby effectively reducing the disconnection of the fan-out lines F due to mechanical movement.

[0111] Continue to see Figure 1 , transfer signal line C n Specifically, it can be located on the data signal line D corresponding to each pixel unit column. m With reference signal line V m and between the Mth pixel unit column and the boundary of the substrate;

[0112] The transfer signal line C1 between the data signal line D1 corresponding to the first pixel unit column and the reference signal line V1, the data signal line D corresponding to the Mth pixel unit column M With reference signal line V M The transfer signal line C N-1 , and a transfer signal line C between the Mth pixel unit column and the boundary of the substrate N, connected to the fan-out line F of the first fan-out area FA1 through the connecting line E;

[0113] The transfer signal lines C3 to C4 between the data signal lines and the reference signal lines corresponding to the 3rd pixel unit column to the (M-1)th pixel unit column respectively N-2 , directly connected to the fan-out line F of the first fan-out area FA.

[0114] By connecting the transfer signal lines C1, C N-1 and C N The fan-out lines F are connected via the connection lines E, so that the distance between the fan-out lines F and the boundary of the base substrate is increased, thereby effectively reducing the disconnection of the fan-out lines F due to mechanical movement.

[0115] Optionally, the driving backplane provided in the embodiment of the present disclosure may include a first conductive layer and a second conductive layer sequentially arranged on the substrate and insulated from each other; in some embodiments, the data signal line D extending along the first direction Y may be m , reference signal line V m , Positive signal line H m1 , H m2 And transfer signal line C n The scanning signal line S is disposed in the first conductive layer and extends along the second direction X. n It is arranged on the second conductive layer to realize reasonable wiring.

[0116] In addition, the present disclosure may further include a third conductive layer, which is located on the side of the second conductive layer away from the substrate, and an insulating layer is provided between the second conductive layer and the third conductive layer. In some embodiments, the third conductive layer includes a pixel driver chip and a plurality of pins, wherein the plurality of pins are subsequently connected to inorganic light emitting diodes of different colors. Specifically, Figure 5 and Figure 6 As shown, the pixel driving chip has a first signal terminal O1, a second signal terminal O2, a third signal terminal O3, a fourth signal terminal O4, a fifth signal terminal O5 and a sixth signal terminal O6. Among them, the first signal terminal O1 is connected to the pin corresponding to the cathode R- of the first color inorganic light emitting diode, the second signal terminal O2 of the pixel driving chip is connected to the pin corresponding to the cathode G- of the second color inorganic light emitting diode, the third signal terminal O3 of the pixel driving chip is connected to the pin corresponding to the cathode B- of the third color inorganic light emitting diode, and the fourth signal terminal O4 of the pixel driving chip is connected to the data signal line D n Connect the fifth signal terminal O5 of the pixel driving chip to the scanning signal line S n Connect the sixth signal terminal O6 of the pixel driving chip to the reference signal line V mConnect the pin corresponding to the positive electrode R+ of the first color inorganic light emitting diode to the positive electrode signal line H m1 Connect the pin corresponding to the positive electrode G+ of the second color inorganic light emitting diode to the positive electrode signal line H m2 Connect the pin corresponding to the positive electrode B+ of the third color inorganic light-emitting diode to the positive signal line H m2 In some embodiments, Fig.10 As shown, each pixel unit P may include: sub-pixels P' of at least three colors and the above-mentioned pixel driver chip that drives each sub-pixel P' to emit light. Each sub-pixel P' includes at least one light-emitting device LED, which may be, for example, a micro inorganic light-emitting diode. In some embodiments, each pixel unit P may include three sub-pixels P', each sub-pixel P' includes one or two light-emitting devices LED. Specifically, Fig.10 It is shown in the figure that each sub-pixel P' includes two light-emitting devices LED, and the six light-emitting devices LED contained in one pixel unit P are arranged in three rows and two columns. The three rows of light-emitting devices LED can be the first color light-emitting device R, the second color light-emitting device G and the third color light-emitting device B from bottom to top.

[0117] Among them, the first color light emitting device R can be the above-mentioned first color inorganic light emitting diode, the second color light emitting device G can be the above-mentioned second color inorganic light emitting diode, and the third color light emitting device B can be the above-mentioned third color inorganic light emitting diode, and they are connected to the pins in the above-mentioned manner. It should be noted that when each sub-pixel P' includes a light emitting device LED, among every two pairs of pins respectively arranged corresponding to the first color inorganic light emitting diode, the second color inorganic light emitting diode, and the third color inorganic light emitting diode, only one pair of pins is bound to the inorganic light emitting diode of the corresponding color, and the other pair of pins is reserved.

[0118] In addition, Fig.10 Middle reference signal line V m It is used to provide a negative signal to the pixel driver chip, and the pixel driver chip is configured to scan the signal line S n Under the control of the enable, so as to receive the data signal line D m The transmitted signal enables the pixel driver chip to respectively transmit signals to the positive signal line H at different time periods to the sub-pixels P' of different colors. m1 or H m2 and the reference signal line V m A current path is formed therebetween to enable the corresponding sub-pixel P' to emit light.

[0119] On the other hand, the embodiment of the present disclosure provides a display panel, including the above-mentioned driving backplane provided in the embodiment of the present disclosure, and a plurality of micro-LEDs electrically connected to the driving backplane. Since the principle of solving the problem by the display panel is similar to the principle of solving the problem by the above-mentioned driving backplane, the implementation of the display panel can refer to the embodiment of the above-mentioned driving backplane, and the repeated parts will not be repeated.

[0120] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned multiple display panels provided in the embodiment of the present disclosure, wherein the multiple display panels are spliced ​​and arranged. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display panel, the implementation of the display device can refer to the embodiment of the above-mentioned display panel, and the repeated parts will not be repeated.

[0121] In some embodiments, the display device includes but is not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will understand that the structure of the above-mentioned display device does not constitute a limitation on the display device, and the display device may include more or less of the above-mentioned components, or a combination of certain components, or different component arrangements. In the embodiments of the present disclosure, the display device includes but is not limited to displays, mobile phones, tablet computers, televisions, wearable electronic devices, laptops, digital photo frames, navigators, smart watches, fitness wristbands, personal digital assistants, and any other products or components with display functions.

[0122] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A driving backplane, wherein: include: A substrate, comprising a display area and a fan-out area located at least on one side of the display area; The display area includes a plurality of pixel units arranged in an array, and a plurality of signal lines connected to the pixel units, wherein the signal lines extend along a first direction; The fan-out area includes a fan-out line, the fan-out line is connected to the signal line, the fan-out line includes a first end close to the display area and a second end away from the display area, and the width of the first end is greater than the width of the second end; At least one of the signal lines is connected to at least one of the fan-out lines via a connecting line, and the connecting line extends along the second direction; The length of the connecting line is greater than or equal to the spacing distance between two adjacent pixel units in the second direction; At least a portion of the base substrate is bent to an opposite side, and the fan-out area and the display area are respectively located on opposite sides of the same surface of the base substrate; The signal line connected to the fan-out line through the connection line is connected to the outermost pixel unit column.

2. The driving backplane according to claim 1, wherein: The length of the connecting line is less than or equal to the sum of the width of the pixel unit in the second direction and the spacing distance between two adjacent pixel units.

3. The driving backplane according to claim 1, wherein: At least one of the signal lines is directly connected to at least one of the fan-out lines.

4. The driving backplane according to claim 1, wherein: The fan-out area is folded at a side opposite to the display side of the driving backplane, and a minimum distance between the connecting line and the bending axis in the first direction is greater than 150 μm.

5. The driving backplane according to claim 1, wherein: A minimum distance between the fan-out line and a boundary of the base substrate in the second direction is greater than 1000 μm.

6. The driving backplane according to claim 1, wherein: A gap between two adjacent signal lines in the second direction and a gap between two adjacent connection lines in the first direction are greater than 100 μm.

7. The driving backplane according to any one of claims 1 to 6, wherein: The fan-out area includes a first fan-out area located at one side of the display area; Part of the fan-out lines in the first fan-out area are connected to the signal line through the connecting line, and the remaining part of the fan-out lines are directly connected to the signal line.

8. The driving backplane according to claim 7, wherein: The fan-out area further includes a second fan-out area, and the second fan-out area and the first fan-out area are respectively located on both sides of the display area in the second direction; the fan-out line of the second fan-out area is directly connected to the signal line.

9. The driving backplane according to claim 8, wherein: All of the signal lines include: a plurality of data signal lines, a plurality of reference signal lines and a plurality of positive signal lines; Each pixel unit column is electrically connected to one of the data signal lines, one of the reference signal lines and one of the positive signal lines; and the distances between the data signal line, the reference signal line, the positive signal line and the boundary of the substrate corresponding to each pixel unit column increase in sequence; All of the pixel units constitute M pixel unit columns arranged in sequence in the second direction; wherein the outermost two pixel unit columns are respectively the first pixel unit column and the Mth pixel unit column, and in the second direction, the distance between the data signal line corresponding to the first pixel unit column and the boundary of the substrate is smaller than the distance between the data signal line corresponding to the Mth pixel unit column and the boundary of the substrate; The data signal lines respectively corresponding to the first pixel unit column, the second pixel unit column and the Mth pixel unit column are connected to the fan-out lines of the first fan-out area through the connecting lines; The data signal lines respectively corresponding to the 3rd pixel unit column to the (M-1)th pixel unit column are directly connected to the fan-out lines of the first fan-out area; The plurality of reference signal lines and the plurality of positive signal lines are directly connected to the fan-out lines of the second fan-out region.

10. The driving backplane according to claim 9, wherein: All of the signal lines further include: transfer signal lines between the data signal line and the reference signal line, and between the Mth pixel unit column and the boundary of the substrate, each of the transfer signal lines being electrically connected to a pixel unit row; The transfer signal line between the data signal line and the reference signal line corresponding to the first pixel unit column, the transfer signal line between the data signal line and the reference signal line corresponding to the M-th pixel unit column, and the transfer signal line between the M-th pixel unit column and the boundary of the substrate are connected to the fan-out line of the first fan-out area through the connecting line; The transfer signal lines between the data signal lines and the reference signal lines respectively corresponding to the 3rd pixel unit column to the (M-1)th pixel unit column are directly connected to the fan-out lines of the first fan-out area.

11. The driving backplane according to claim 10, wherein: It also includes a plurality of scanning signal lines, which extend along the second direction between the pixel unit rows, and each of the scanning signal lines is electrically connected to a corresponding transfer signal line.

12. The driving backplane according to claim 11, wherein: It includes a first conductive layer and a second conductive layer which are sequentially arranged on the substrate and insulated from each other; The data signal line, the reference signal line, the positive signal line and the switching signal line are located in the first conductive layer, and the scanning signal line is located in the second conductive layer.

13. The driving backplane according to any one of claims 8 to 12, wherein: It also includes: a first binding area set on a side of the first fan-out area away from the display area, and a second binding area set on a side of the second fan-out area away from the display area; wherein, The first binding area is provided with a first chip; the fan-out line of the first fan-out area is bound and connected to the first chip; The second binding area is provided with a second chip and a third chip, and the second chip and the third chip are symmetrically arranged about the central axis of the display area in the first direction; The fan-out line in the second fan-out area located on one side of the central axis of the display area in the first direction is bound and connected to the second chip, and the fan-out line located on the other side of the central axis of the display area in the first direction is bound and connected to the third chip.

14. A display panel, wherein: It comprises a driving backplane as described in any one of claims 1 to 13, and a plurality of micro light emitting diodes electrically connected to the driving backplane.

15. A display device, wherein: It comprises a plurality of display panels as claimed in claim 14, wherein the plurality of display panels are spliced ​​together.

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