Receiver Circuit with Interference Detection

Abstract

A receiver circuit includes an ADC (102), a processing channel (136), and an interference detection path (116). The processing channel (136) is configured to process data samples provided by the ADC (102) and includes a notch filter (110). The interference detection path (116) is configured to detect interference in the data samples and includes a limiter, a limiter error circuit, and an interference detection circuit. The limiter is configured to limit the input of the notch filter (110). The limiter error circuit is configured to calculate the error of the limiter. The interference detection circuit is configured to detect an interference signal in the error of the limiter and set the notch filter (110) to attenuate the interference signal.

Description

Background Art

[0001] Wired communication networks, such as Ethernet, are used to provide communication in various applications. For example, in automotive applications, Ethernet is used to provide communication for safety systems and infotainment systems. In such systems, the reliability of Ethernet communication is important. Summary of the Invention

[0002] A receiver circuit includes an analog-to-digital converter (ADC), a notch filter, a limiter, a limiter error circuit, and an interference detection circuit. The ADC includes an output. The notch filter includes a signal input, an interference frequency input, and an output. The signal input is coupled to the output of the ADC. The limiter includes an input and an output. The input of the limiter is coupled to the input of the notch filter. The limiter error circuit includes a first input, a second input, and an error output. The first input is coupled to the input of the limiter. The second input is coupled to the output of the limiter. The interference detection circuit includes an input and an interference frequency output. The input of the interference detection circuit is coupled to the error output of the limiter error circuit. The interference frequency output is coupled to the interference frequency input of the notch filter.

[0003] A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC and includes a notch filter. The interference detection path is configured to detect interference in the data samples and includes a limiter, a limiter error circuit, and an interference detection circuit. The limiter is configured to limit the input of the notch filter. The limiter error circuit is configured to calculate the error of the limiter. The interference detection circuit is configured to detect an interference signal in the error of the limiter and set the notch filter to attenuate the interference signal.

[0004] A digital signal processing circuit includes a first processing channel, a second processing channel, and an interference detection path. The first processing channel is configured to process a first data sample received from an ADC and includes a first notch filter configured to filter the first data sample. The second processing channel is configured to process a second data sample received from the ADC and includes a second notch filter configured to filter the second data sample. The interference detection path is configured to detect interference signals in the first data sample and the second data sample. The interference detection path includes a first limiter, a first limiter error circuit, a second limiter, a second limiter error circuit, a multiplexer, and an interference detection circuit. The first limiter is configured to limit the input of the first notch filter. The first limiter error circuit is configured to calculate the error of the first limiter. The second limiter is configured to limit the output of the second notch filter. The second limiter error circuit is configured to calculate the error of the second limiter. The multiplexer is configured to select the error of the second limiter or the error of a third limiter as an interference source signal. The interference detection circuit is configured to detect interference signals in the interference source signal and set the first notch filter and the second notch filter to attenuate the interference signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] DETAILED DESCRIPTION OF VARIOUS EXAMPLES WILL NOW BE REFERRED TO THE ACCOMPANYING DRAWINGS, WHEREIN:

[0006] Figure 1 FIG. shows a block diagram of an example receiver physical layer circuitry for including detection and filtering of interference signals.

[0007] Figure 2 FIG. shows a graph of an example frequency domain limiter input calculated with a 512 sample Fast Fourier Transform (FFT);

[0008] Figure 3 FIG. shows a graph of an example time domain limiter error signal.

[0009] Figure 4 FIG. shows a graph of an example frequency domain limiter error signal calculated with a 512 sample FFT.

[0010] Figure 5 FIG. shows an example interference signal spectrum derived from limiter error signals with and without symbol errors.

[0011] Figure 6 FIG. shows a block diagram of an example notch filter operating at the full symbol rate of the receiver.

[0012] Figure 7 FIG. shows a block diagram of an example notch filter circuit including notch filters in each processing path of the receiver.

[0013] Figure 8 A block diagram showing an example interference detection path suitable for use in a receiver.

[0014] Figure 9 A graph showing an example of the sample timing of a signal at half the sampling frequency in multiple processing paths for a receiver.

[0015] Figure 10 Shows an example interference detection enabling circuit suitable for use with Figure 8 the interference detection path. A block diagram of the example interference detection enabling circuit.

[0016] Figure 11 A flowchart showing an example method for operating an interference detection circuitry in a receiver.

[0017] Figure 12 Shows an example method for interference detection in an Figure 8 interference detection path. A flowchart of the example method for interference detection. DETAILED DESCRIPTION

[0018] In automotive and other applications, Ethernet physical layer circuits (such as Ethernet receivers) are expected to provide reliable communication in the presence of radio frequency interference (RFI). Some Ethernet receiver circuits use fast Fourier transform (FFT)-based interference detection to employ RFI suppression to control a notch filter that attenuates interference. However, detecting RFI in the presence of signals and echoes requires a high-resolution FFT (e.g., a 16384-sample FFT), which increases the circuit area and cost of the receiver.

[0019] The receiver circuits disclosed herein use limiter error to identify interference signals. Limiter error does not include signals or echoes. The size of the FFT applied to identify interference signals and the time required to identify interference signals are greatly reduced. For example, a 512-sample FFT is applied in some embodiments, which reduces the circuit area and cost of the receiver. The receiver includes a dedicated interference detection path (which lacks a notch filter) for determining whether an interference signal is present. When the interference detection path does not detect an interference signal, the notch filter in the data processing channel of the receiver is turned off to save power. Turning off the notch filter when no interference signal is present also improves the signal-to-noise ratio of the processing channel.

[0020] Figure 1A block diagram of an example receiver circuit 100 including detection and filtering of interference signals is shown. Receiver circuit 100 can be applied to an Ethernet receiver or other wired or wireless receiver circuits. Receiver circuit 100 includes an analog-to-digital converter (ADC) 102 and digital signal processing circuitry 103 coupled to ADC 102. In some embodiments of receiver circuit 100, ADC 102 is an interleaved ADC. In some alternative embodiments, filters (such as high-pass filters), delays, amplifiers, and clock generation circuitry may be included and coupled directly or indirectly between the incoming RF signal and ADC 102.

[0021] Digital signal processing circuitry 103 includes a first-in first-out (FIFO) memory 104. FIFO memory 104 stores digital samples received from ADC 102 and provides each sample to one of a plurality (N) of processing channels. Processing channels 136 and 138 are shown in Figure 1 . Processing channels 136 and 138 receive and process digital samples generated by ADC 102 from FIFO memory 104. Some embodiments of digital signal processing circuitry 103 may include more than two processing channels. For example, an embodiment of digital signal processing circuitry 103 may include six processing channels. One or more of the processing channels are coupled to interference detection path 116 and interference detection enable circuitry 118.

[0022] Each processing channel includes an echo cancellation circuitry 106, a multiplier, a digital equalizer 108, a notch filter circuit 110, a feed-forward equalizer 112, an adder, and a limiter. In some embodiments of digital signal processing circuitry 103, the limiter is a three-level pulse amplitude modulation (PAM-3) limiter. In processing channel 136, echo cancellation circuitry 106 is coupled to digital equalizer 108 via multiplier 107. Echo cancellation circuitry 106 multiplies the received symbols by an echo cancellation coefficient to reduce echo in the received signal. Digital equalizer 108 is a digital filter that corrects for inter-symbol interference (ISI) caused by the transmission channel. Digital equalizer 108 is coupled to notch filter circuit 110. Notch filter circuit 110 attenuates interference signals in the received signal. Notch filter circuit 110 is coupled to feed-forward equalizer 112. Feed-forward equalizer 112 corrects for pre-cursor ISI (ISI caused by previously transmitted symbols). Feed-forward equalizer 112 may be implemented as a finite impulse response (FIR) filter. Feed-forward equalizer 112 is coupled to limiter 113 via adder 111. The components of other processing channels (such as processing channel 138) are similarly connected.

[0023] The digital signal processing circuit 103 includes a fine gain control circuit 126, a decision feedback equalization (DFE) circuit 124, a clock recovery circuit 132, an ADC gain control circuit 128, and a timing error detector circuit 130, each circuit being coupled to one or more of the limiters. The fine gain control circuit 126 is coupled to the input of a multiplier (e.g., multiplier 107) and to the output of a limiter (e.g., limiter 113) to control the fine gain applied to the output of the echo cancellation circuitry 106. The DFE circuit 124 is coupled to an adder (e.g., adder 111) at the input of the limiter to provide equalization feedback to the input of the limiter. The clock recovery circuit 132 is coupled to a clock source (not shown) to adjust the phase of the clock signal provided to the ADC 102.

[0024] The ADC gain control circuit 128 adjusts the gain of the signal at one or more outputs of the FIFO memory 104 to equalize the amplitudes of the samples output by the interleaved ADCs of the ADC 102. The gain adjustment is provided to the digital samples generated by the first ADC of the ADC 102, while no gain adjustment is provided to the digital samples generated by the second ADC of the ADC 102, such that the gains applied to the digital samples of the first ADC and the second ADC are equal. In an alternative embodiment, gain adjustment is provided to the digital samples from both ADCs to equalize the gains.

[0025] The timing error detector circuit 130 determines the timing error (skew) of the ADCs of the ADC 102 and controls the delay of the clock applied to time the operation of the ADCs to reduce the timing skew.

[0026] The coarse automatic gain control 134 analyzes the amplitude of the signal output of the FIFO memory 104 and adjusts the amplitude to a predetermined range by providing a coarse gain control signal to a gain control circuit (e.g., a programmable gain amplifier) (not shown), which provides the signal to be digitized to the ADC 102.

[0027] The notch filter circuit 110, the interference detection path 116, and the interference detection enable circuit 118 operate to detect and attenuate interference signals (e.g., radio frequency interference) in the signals processed by the digital signal processing circuit 103. The interference detection path 116 detects the presence and frequency of the interference signal and sets the center frequency of the notch filter circuit 110 to attenuate the interference signal. The interference detection path 116 provides improved detection of the interference signal with reduced circuit complexity by applying the clipping error (e.g., of one or more processing channels), which is transformed to the frequency domain by a relatively small FFT (e.g., 512 samples) to identify the interference signal. The interference detection path 116 includes an FFT circuit 117 to transform the clipper error signal to a frequency domain signal. The interference detection path 116 can identify the interference signal by comparing the FFT bin magnitude values with a threshold. The bin magnitude exceeding the threshold can be regarded as indicating the interference signal.

[0028] In processing channel 136, the input 110A of the notch filter circuit 110 is coupled to the input 116A of the interference detection path 116 for providing the signal that has not been processed by the notch filter circuit 110. The interference frequency output 116B of the interference detection path 116 is coupled to the interference frequency input 110B of the notch filter circuit 110 for providing the notch filter parameter (e.g., the interference frequency). In processing channel 138, the input 110E of the notch filter circuit 110 is coupled to the input 116E of the interference detection path 116 for providing the signal that has not been processed by the notch filter circuit 110.

[0029] Figures 2 - 5 Illustrates the advantages of interference detection based on clipper error. Figure 2 Shows the input to the clipper whose output is transformed to the frequency domain using a 512-sample FFT. In Figure 2 , the x-axis represents the FFT bin and the y-axis represents the FFT magnitude. The interference signal cannot be clearly detected in the clipper input. A higher-resolution FFT (e.g., 16384-sample FFT) is required to identify the interference in the clipper input signal. Figure 3 Shows a graph of an example time-domain clipper error signal output by the clipper error circuit (see, e.g., Figure 8 ). In Figure 3 , the x-axis represents the sample index and the y-axis represents the clipper error. Figure 4 Shows Figure 3 's graph of the clipper error signal after being transformed to the frequency domain by the FFT circuit 117 using a 512-sample FFT. In Figure 4 , the x-axis represents the FFT bin and the y-axis represents the FFT magnitude. The frequency of the interference signal can be clearly identified at approximately bin 100 in the frequency-domain clipper error signal.

[0030] Figure 5 illustrates an example interference signal spectrum derived from a limiter error signal with sign errors. In Figure 5 , the x-axis represents frequency in megahertz, and the y-axis represents the FFT magnitude in decibels. Signals 502 and 504 each include sign errors at rates of 10 -2 and 10 -3 , respectively. Figure 5 illustrates that even in the presence of sign errors, the interference detection path 116 can clearly identify the interference signal using the signal spectrum derived from the frequency-domain limiter error.

[0031] After identifying the presence and frequency of the interference signal in the limiter error signal, the interference detection path 116 sets the notch filter circuit 110 to attenuate the interference signal. Figure 6 illustrates a block diagram of an example parallel notch filter 600 operating at the full symbol rate of the receiver. The parallel notch filter 600 includes a finite impulse response (FIR) section and an infinite impulse response (IRR) section in each processing channel. The notch transfer function N(z) is expressed as:

[0032]

[0033] where:

[0034] the FIR section is expressed in the numerator; and

[0035] the IIR section is expressed in the denominator.

[0036] Due to the lookahead computations required in the IIR section, implementation of the parallel notch filter 600 at high frequencies (e.g., 750 megahertz (MHz)) is difficult and expensive. The notch filter circuit 110 ( Figure 7 ) avoids the difficulties of the parallel notch filter 600 by implementing independent notch filters in each processing path. Figure 7A block diagram of an example notch filter circuit 110 is shown, which includes notch filters in each processing path of the receiver. Thus, for six processing channels, the notch filter circuit 110 includes six notch filters (notch filter 702, notch filter 704, notch filter 706, notch filter 708, notch filter 710, and notch filter 712), and each notch filter operates independently of the other notch filters. For example, notch filter 702 is coupled to limiter 113, and notch filter 708 is coupled to limiter 120. Each of the notch filters operates at a fraction (1 / N, where N is the number of processing paths) of the operating frequency of the parallel notch filter 600 (e.g., 125 MHz vs. 750 MHz). The multiple notch filters effectively create multiple notches in the spectrum of the signal processed by the digital signal processing circuit 103. However, for a relatively narrow notch width (e.g., 120 kHz), the impact of the notch on the signal-to-noise ratio is relatively small. The notch filter circuit 110 does not use look-ahead calculations, which greatly simplifies the implementation of the notch filter circuit 110 compared to the parallel notch filter 600 and reduces circuit area and cost.

[0037] In some embodiments of the digital signal processing circuit 103, the notch filter circuit 110 and the FFT circuit 117 consume a large amount of power (e.g., 30 mW) during operation. Return reference Figure 1 , when the notch filter circuit 110 is enabled to attenuate the interference signal, the interference signal no longer exists (or is very small) in the limiter error signal output by the limiter error circuit. Therefore, the limiter error signal generated by the limiter error circuit in any processing path (e.g., processing path 136 or 138) of the digital signal processing circuit 103 cannot be used to detect the persistence or non-persistence of the previously detected interference signal.

[0038] Figure 8 A block diagram of an example interference detection path 116 is shown, which enables the FFT circuit 117 and the notch filter circuit 110 to be turned off when the previously detected interference no longer exists. Since the interference signal is attenuated at the output of the notch filter circuit 110, the error of the limiter in the processing channel cannot be used to reliably detect interference. To provide reliable detection, the interference detection path 116 monitors the signal at the input of the notch filter circuit 110 to identify interference. The interference detection path 116 includes a first limiter path 822 and a second limiter path 824 that generate limiter errors for processing channel 136 and processing channel 138, respectively. The limiter errors generated in the limiter paths 822 and 824 are routed by the multiplexer 808 to the interference detection circuit 810.

[0039] The first clipping path 822 includes a delay circuit 802, a clipper 804, and a clipper error circuit 806. The delay circuit 802 provides a delay time that matches the delay of the notch filter circuit 110 and the feed-forward equalizer 112 (or any delay between the input of the notch filter circuit 110 and the input of the adder 111). The input 802A of the delay circuit 802 is coupled to the input 110A of the notch filter circuit 110 to receive a signal, and the output 802B of the delay circuit 802 is coupled to the input 804A of the clipper 804 via an adder 812. The adder 812 adds the delayed input of the notch filter circuit 110 received from the delay circuit 802 to the DFE feedback received from the DFE circuit 124 (the same DFE feedback provided to the adder 111). The clipper error circuit 806 calculates the clipper error of the clipper 804. The input 806A of the clipper error circuit 806 is coupled to the input 804A of the clipper 804, and the input 806B of the clipper error circuit 806 is coupled to the output 804B of the clipper 804. The output 806C of the clipper error circuit 806 is coupled to the input 810A of the interference detection circuit 810 via a multiplexer 808.

[0040] The second clipping path 824 includes a delay circuit 818, a clipper 814, and a clipper error circuit 816. The delay circuit 818 provides a delay that matches the delay of the notch filter circuit 110 and the feed-forward equalizer 112 (or any delay between the input of the notch filter circuit 110 and the input of the adder 111). The input 818A of the delay circuit 818 is coupled to the input 110D of the notch filter circuit 110 to receive a signal, and the output 818B of the delay circuit 818 is coupled to the input 814A of the clipper 814 via an adder 820. The adder 820 adds the delayed data received from the delay circuit 818 to the DFE feedback received from the DFE circuit 124 (the same DFE feedback provided to the adder 111). The clipper error circuit 816 calculates the clipper error of the clipper 814. The input 816A of the clipper error circuit 816 is coupled to the input 814A of the clipper 814, and the input 816B of the clipper error circuit 816 is coupled to the output 814B of the clipper 814. The output 816C of the clipper error circuit 816 is coupled to the input 810A of the interference detection circuit 810 via a multiplexer 808.

[0041] The output 810B of the interference detection circuit 810 is coupled to the interference frequency input 110B of the notch filter circuit 110 (e.g., the interference frequency input 702B of the notch filter 702, the interference frequency input 708B of the notch filter 708, etc.). When the interference detection circuit 810 detects an interference signal using a low-resolution FFT (e.g., a 512-sample FFT), some embodiments of the interference detection circuit 810 perform a higher-resolution FFT (e.g., a 2048- or 4096-sample FFT) on the frequencies within a small range (+ / - 2 bins) near the detected interference signal to better resolve the interference frequency. When the interference detection circuit 810 does not detect an interference signal, the interference detection circuit 810 disables (e.g., turns off) the FFT circuit 117 and the notch filter circuit 110 to reduce power consumption. When the notch filter circuit 110 is disabled, the notch filter circuit 110 passes the input data to its output without notch filtering. The delay of the data applied to the notch filter circuit 110 is the same when the notch filter circuit 110 is enabled or disabled.

[0042] When the interference detection path 116 detects interference via a single processing channel (e.g., data from the processing channel 136), an interference signal close to half of the sampling frequency (Fs / 2) may not be detected if the signal is sampled at or near the zero-crossing point. To address this issue, when no interference is detected in the first processing channel, the interference detection path 116 uses the second clipping path 824 to monitor data from the second processing channel (e.g., the processing channel 138). For example, when no interference is detected in the clipping error of the clipper 804, the interference detection path 116 monitors the clipping error of the clipper 814. When monitoring the clipping error of the clipper 814, the interference detection circuit 810 only transforms the frequency bins near the sampling point of the clipper 814 to reduce power consumption. The multiplexer 808 selects the clipping error output by the clipping error circuit 806 or the clipping error output by the clipping error circuit 816 as the interference source signal to be provided to the interference detection circuit 810 for interference detection. When no interference is detected in the clipping error output of the clipping error circuit 806, the multiplexer 808 selects the clipping error output of the clipping error circuit 816. The multiplexer 808 includes an input 808A coupled to the output 806C of the clipping error circuit 806, an input 808B coupled to the output 816C of the clipping error circuit 816, and an output 808C coupled to the input 810A of the interference detection circuit 810.

[0043] Figure 9A graph showing example sample points of six parallel processing channels of an Fs / 2 tone, where Fs is the processing path sampling frequency. If processing channel 136 samples the tone at a zero crossing (suppressing detection of Fs / 2 interference), then the other processing channels do not sample at zero crossings. In Figure 9 , processing channel 138 samples the tone at its peak. Thus, interference detection path 116 uses data from processing channel 136 and processing channel 138 to monitor the limiter error to detect interference. When monitoring the limiter error of data from processing channel 138, interference detection circuit 810 only transforms the frequency interval near the sample points of processing channel 138 to reduce power consumption in some embodiments of interference detection circuit 810.

[0044] Figure 10 A block diagram showing an example interference detection enable circuit 118 is presented. Interference detection enable circuit 118 monitors the mean square error (MSE) of limiter 804 and limiter 814 to detect the presence of an interference signal and determines whether to enable interference detection circuit 810. Interference detection enable circuit 118 includes input 118A, input 118B, output 118C, power circuit 1002, low-pass filter circuit 1004, threshold comparison circuit 1006, and adder 1008. Input 118B is coupled to output 806C of limiter error circuit 806 (see Figure 8 ). Input 118A is coupled to output 816C of limiter error circuit 816 (see Figure 8 ). Output 118C is coupled to enable input 810C of interference detection circuit 810 and enable input 116D of interference detection path 116 (see Figure 8)。The adder 1008 adds the limiter error of the limiter 804 and the limiter error of the limiter 814. The input 1008B of the adder 1008 is coupled to the output 806C of the limiter error circuit 806, and the input 1008A of the adder 1008 is coupled to the output 816C of the limiter error circuit 816. The output 1008C of the adder 1008 is coupled to the power circuit 1002. The power circuit 1002 calculates the power of the added limiter error signal (e.g., calculates the square of the added limiter error signal). The power circuit 1002 provides a power signal to the low-pass filter circuit 1004. The low-pass filtered power signal is provided to the threshold comparison circuit 1006. The threshold comparison circuit 1006 compares the output of the low-pass filter circuit 1004 with a threshold. If the output of the low-pass filter circuit 1004 exceeds the threshold, the interference detection enabling circuit 118 triggers / enables the interference detection circuit 810 to detect an interference signal. Before the interference detection enabling circuit 118 triggers / enables the interference detection circuit 810 to detect an interference signal, the interference detection circuit 810 and the notch filter circuit 110 are disabled / turned off to reduce power consumption.

[0045] Figure 11 A flowchart of an example method 1100 for operating an interference detection circuit system in a receiver is shown. Although depicted in sequence for convenience, at least some of the illustrated actions may be performed in a different order and / or in parallel. Additionally, some embodiments may perform only some of the illustrated actions. The operations of the method 1100 are performed by an implementation of the receiver circuit 100.

[0046] In block 1102, a received signal is received, and the receiver circuit 100 begins initialization to allow operation.

[0047] In block 1104, the various filters and control loops of the receiver circuit 100 are initialized. For example, the coarse gain and fine gain applied to the input signal are adjusted via the coarse automatic gain control 134 and the fine gain control circuit 126. The gain and timing of the interleaved ADC are adjusted via the ADC gain control circuit 128 and the timing error detector circuit 130. The phase of the clock signal provided to the ADC is adjusted via the clock recovery circuit 132. The various equalizers of the digital signal processing circuit 103 are initialized, such as the digital equalizer 108, the feed-forward equalizer 112, and the DFE circuit 124. The training echo cancellation circuit system 106 is trained.

[0048] In block 1106, the receiver circuit 100 processes the received signal in steady-state operation, and the control loops initialized in block 1104 are operating. Due to the interdependence between the loops, the presence of an interference signal may cause the loops to unlock.

[0049] In block 1108, the interference detection enabling circuit 118 compares the MSE of limiters 804 and 814 with a threshold. If the MSE exceeds the threshold, the interference detection enabling circuit 118 enables the interference detection path 116 to detect an interference signal.

[0050] In block 1110, the interference detection path 116 analyzes the limiter error to determine whether an interference signal is present. Figure 12 Additional description of the operation of block 1110 is provided.

[0051] If no interference signal is detected in block 1110, method 1100 continues at block 1106. If an interference signal is detected, the control loop of the receiver circuit 100 is locked (updating of loop parameters is disabled) to prevent link instability, and execution continues at block 1112.

[0052] In block 1112, the interference detection path 116 provides operating parameters (e.g., notch frequency information) to the notch filter circuit 110 and initiates the operation of the notch filter circuit 110. The notch filter circuit 110 is not engaged in the data path (i.e., the notch filter circuit outputs unfiltered data). The notch filter circuit 110 processes the received data and is allowed to stabilize. When the notch filter circuit 110 is not engaged in the data path, the delay applied to the unfiltered data passing through the notch filter circuit 110 is the same as the delay when the notch filter circuit 110 is engaged in the data path.

[0053] In block 1114, the notch filter circuit 110 has stabilized (e.g., a predetermined stabilization interval has expired) and is engaged in the data path. That is, the notch-filtered data generated by the notch filter circuit 110 is provided to the feed-forward equalizer 112, adder 111, limiter 113, limiter 120, etc.

[0054] In block 1116, the notch filter circuit 110 is operating and the update of the control loop is re-enabled. The interference detection path 116 continues to analyze the data at the input of the notch filter circuit 110 to detect the presence of an interference signal. If no interference signal is detected, or the frequency of the detected interference signal changes, then in block 1118, the interference detection path 116 disables the notch filter circuit 110 (e.g., the notch filter circuit 110 is disengaged from the data path and notch filtering is paused). Method 1100 continues at block 1110.

[0055] Figure 12FIG. 1200 is a flowchart showing an example method for interference detection. Although depicted in sequence for convenience, at least some of the illustrated actions may be performed in a different order and / or in parallel. Additionally, some embodiments may perform only some of the illustrated actions. The operations of method 1200 are performed as part of the execution of block 1110 of method 1100.

[0056] In block 1202, the interference detection circuit 810 analyzes the data on processing channel 136 to determine whether there is an interference signal. In various embodiments of method 1200, the data analyzed is the limiter error of limiter 804 or the limiter error of limiter 814. The interference detection circuit 810 applies a coarse (e.g., 512 samples) FFT to the limiter error to transform the limiter error into the frequency domain. Amplitude values in the frequency domain limiter error signal that exceed a threshold are considered interference signals.

[0057] If no interference signal is identified in block 1202, then in block 1204, the interference detection circuit 810 analyzes the data on processing channel 138 to determine whether there is an interference signal. In various embodiments of method 1200, the data analyzed is the limiter error of limiter 814. The interference detection circuit 810 applies a coarse (e.g., 512 samples) FFT to the limiter error to transform the limiter error into the frequency domain. Amplitude values in the frequency domain limiter error signal that exceed a threshold are considered interference signals. If no interference signal is identified, method 1200 continues in block 1202.

[0058] If an interference signal is identified in block 1202 or block 1204, then in block 1206, the interference detection circuit 810 applies a fine (e.g., 2048 samples or 4096 samples) FFT to better resolve the frequency of the interference signal. The interference detection circuit 810 applies the fine FFT to the limiter error, where the interference signal is detected only near the frequency of the interference signal identified using the coarse FFT.

[0059] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B; or (b) in a second example, if intervening component C does not substantially change the functional relationship between device A and device B, then device A is coupled to device B through intervening component C such that device B is controlled by device A via the control signal provided by device A. Further, in this specification, a device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof. Additionally, in this specification, a circuit or device that includes certain components may alternatively be adapted to be coupled to those components to form the circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as a voltage source and / or a current source) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the structure at the time of manufacture or after manufacture (e.g., by an end user and / or a third party).

[0060] As used herein, the terms "terminal," "node," "interconnect," and "pin" may be used interchangeably. Unless otherwise explicitly stated, these terms are generally used to mean an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components or their terminals.

[0061] Within the scope of the claims, modifications to the embodiments are possible, and other embodiments are possible.

Claims

1. A receiver circuit, comprising: An analog-to-digital converter, i.e., ADC, comprising an output; A notch filter, comprising: A signal input coupled to the output of the ADC; and An interference frequency input; A limiter, comprising: An input coupled to the signal input of the notch filter; and An output; A limiter error circuit, comprising: A first input coupled to the input of the limiter; A second input coupled to the output of the limiter; and An error output; An interference detection circuit, comprising: An input coupled to the error output of the limiter error circuit; and An interference frequency output coupled to the interference frequency input of the notch filter.

2. The receiver circuit according to claim 1, further comprising: A delay circuit, comprising: An input coupled to the input of the notch filter; and An output coupled to the input of the limiter.

3. The receiver circuit according to claim 1, wherein the interference detection circuit comprises a fast Fourier transform circuit, i.e., FFT circuit, coupled to the error output of the limiter error circuit.

4. The receiver circuit according to claim 1, wherein: The notch filter is a first notch filter; The limiter is a first limiter; And The receiver circuit comprises: A second notch filter, comprising: A signal input coupled to the output of the ADC; An interference frequency input coupled to the interference frequency output of the interference detection circuit; and A second limiter, comprising: An input coupled to the signal input of the second notch filter; and An output.

5. The receiver circuit according to claim 4, wherein: The limiter error circuit is a first limiter error circuit; And The receiver circuit comprises: A second limiter error circuit, comprising: A first input coupled to the input of the second limiter; A second input coupled to the output of the second limiter; and An error output coupled to the input of the interference detection circuit.

6. The receiver circuit according to claim 5, further comprising: A multiplexer, comprising: A first input coupled to the error output of the first limiter error circuit; A second input coupled to the error output of the second limiter error circuit; and An output, the output being coupled to the input of the interference detection circuit.

7. The receiver circuit according to claim 6, further comprising: An interference detection enable circuit, comprising: A first input coupled to the error output of the first limiter error circuit; A second input coupled to the error output of the second limiter error circuit; and An output coupled to the enable input of the interference detection circuit.

8. A receiver circuit, comprising: An analog-to-digital converter, i.e., ADC; A processing channel configured to process data samples provided by the ADC and comprising a notch filter; And An interference detection path configured to detect interference in the data samples and comprising: A limiter configured to limit the input of the notch filter; A limiter error circuit configured to calculate an error of the limiter; and An interference detection circuit configured to: Detect an interference signal in the error of the limiter; and Set the notch filter to attenuate the interference signal.

9. The receiver circuit according to claim 8, wherein the interference detection path includes: A delay circuit configured to: Delay the input of the notch filter by a delay time of the notch filter; And Provide the delayed input of the notch filter to the limiter.

10. The receiver circuit according to claim 8, wherein the interference detection circuit is configured to apply a fast Fourier transform, i.e., FFT, to the error of the limiter to identify the interference signal.

11. The receiver circuit according to claim 8, wherein: The interference detection circuit is configured to: Disable the notch filter based on non-detection of the interference signal; and Enable the notch filter based on detection of the interference signal; and The notch filter is configured to provide the same delay through the notch filter whether enabled or disabled.

12. The receiver circuit according to claim 8, wherein: The processing channel is a first processing channel; The notch filter is a first notch filter; The data sample is a first data sample; And The receiver circuit includes: A second processing channel configured to process second data samples provided by the ADC and including a second notch filter; And The interference detection circuit is configured to set the second notch filter to attenuate the interference signal.

13. The receiver circuit according to claim 12, wherein: The limiter is a first limiter; The limiter error circuit is a first limiter error circuit; And The interference detection path includes: A second limiter configured to limit the input of the second notch filter; A limiter error circuit configured to calculate an error of the second limiter; and A multiplexer configured to route the error of the second limiter to the interference detection circuit based on non-detection of interference in the error of the first limiter.

14. The receiver circuit according to claim 13, further comprising: An interference detection enable circuit configured to: Detect the presence of an interference signal based on the error of the first limiter and the error of the second limiter; And Enable the interference detection circuit based on the detected presence of the interference signal.

15. The receiver circuit according to claim 12, wherein: The receiver circuit includes N processing channels; The notch filter is configured to operate at 1 / N of the processing rate of the N processing channels; and The second processing channel is configured to process data samples obtained by the ADC that are N / 2 samples later than the data samples processed by the first processing channel.

16. A digital signal processing circuit, comprising: A first processing channel configured to process first data samples received from an ADC and including a first notch filter configured to filter the first data samples; A second processing channel configured to process second data samples received from the ADC and including a second notch filter configured to filter the second data samples; And An interference detection path configured to detect interference signals in the first data samples and the second data samples and including: A first limiter configured to limit the input of the first notch filter; A first limiter error circuit configured to calculate an error of the first limiter; A second limiter configured to limit the input of the second notch filter; A second limiter error circuit configured to calculate an error of the second limiter; A multiplexer configured to select the error of the first limiter or the error of the second limiter as an interference source signal; and An interference detection circuit configured to: Detect an interference signal in the interference source signal; and Set the first notch filter and the second notch filter to attenuate the interference signal.

17. The digital signal processing circuit according to claim 16, wherein the interference detection path includes: A first delay circuit configured to: Delay the input of the first notch filter by a delay time of the first notch filter; And Provide the delayed input of the first notch filter to the first limiter; and A second delay circuit configured to: Delay the input of the second notch filter by a delay time of the second notch filter; and Provide the delayed input of the second notch filter to the second limiter.

18. The digital signal processing circuit according to claim 16, wherein the interference detection circuit includes a fast Fourier transform circuit, i.e., an FFT circuit, configured to convert the interference source signal into a frequency domain signal to identify the interference signal.

19. The digital signal processing circuit according to claim 16, wherein: The interference detection circuit is configured to: In response to detection of the interference signal: disengage the first notch filter and the second notch filter for a stabilization interval; and After expiration of the stabilization interval: engage the first notch filter and the second notch filter.

20. The digital signal processing circuit according to claim 16, further comprising an interference detection enable circuit configured to: Detect the presence of the interference signal based on a sum of the error of the first limiter and the error of the second limiter exceeding a threshold; and Enable the interference detection circuit based on the detected presence of the interference signal.

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