Flash translation layer corresponding table processing method for solid-state storage device

Abstract

The present invention is a method for processing a flash translation layer corresponding table (FTL table for short) used in a solid-state storage device. When backing up the FTL table, the control circuit determines the size of the remaining space in the used block, and further determines whether to back up the complete FTL table to a blank block. When the remaining space in the used block is sufficient, the control circuit stores the modified content and the content change table in the FTL table in the remaining space in the used block. When the remaining space in the used block is insufficient, the control circuit stores the complete FTL table in a blank block.

Description

Technical Field

[0001] The present invention relates to a control method used in a solid-state storage device, and more particularly to a flash conversion layer corresponding table processing method used in a solid-state storage device. Background Art

[0002] As is known to all, a solid state device (SSD) uses a non-volatile memory as a main storage element. That is, after data is written into the non-volatile memory, once the system power is turned off, the data can still be saved in the non-volatile memory.

[0003] Please refer to Figure 1 , which is a schematic diagram of a conventional solid-state storage device. The solid-state storage device 10 includes a control circuit 110 , a buffering element 130 , and a non-volatile memory 120 . The control circuit 110 is connected to the buffering element 130 and the non-volatile memory 120 .

[0004] Outside the solid-state storage device 10, the control circuit 110 transmits instructions and data to the host 12 via an external bus 20. The external bus 20 may be a USB bus, a SATA bus, an M.2 bus, or a PCIe bus, etc. Furthermore, the buffer element 130 may also be directly designed in the control circuit 110. The buffer element 130 may be a volatile memory, such as a DRAM or SRAM. That is, when the system power is turned off, the contents stored in the buffer element 130 will disappear.

[0005] The non-volatile memory 120 includes a plurality of blocks, each of which includes a plurality of pages. For example, there are 1024 blocks in the non-volatile memory 120, and each block has 64 pages, and the capacity of each page is 16Kbytes. That is, the capacity of each block is 1Mbyte. Of course, the non-volatile memory 120 is not limited to only 1024 blocks, and the manufacturer of the non-volatile memory 120 can determine the number of pages in each block and the capacity of each page. That is, each block is not limited to only 64 pages, and each page is not limited to only 16Kbytes.

[0006] Furthermore, due to the characteristics of the non-volatile memory 120 , the control circuit 110 performs a program action based on a page as a basic unit, and the control circuit 110 performs a block erase action based on a block as a basic unit.

[0007] The storage space of the buffer element 130 is divided into multiple parts. The first part of the storage space of the buffer element 130 can be used as a data buffering area 132. The data buffering area 132 is used to temporarily store write data input by the host 12. For example, when the host 12 wants to store the write data in the non-volatile memory 120, the control circuit 110 receives the write data from the external bus 20 and temporarily stores it in the data buffering area 132. The control circuit 110 stores the write data in the non-volatile memory 120 from the data buffering area 132 in a timely manner.

[0008] The second portion of the storage space of buffer element 130 can be used as a flash translation layer table (FTL table) 136. In solid-state storage device 10, control circuit 110 uses FTL table 136 to quickly access data in non-volatile memory 120. The purpose of FTL table 136 is described in detail below.

[0009] Basically, the host 12 uses a logical block address (LBA address) to define the data storage location in the solid-state storage device 10. The non-volatile memory 120 uses a physical allocation address (PAA address) to define the data storage location in the non-volatile memory 120. Therefore, the solid-state storage device 10 needs to use an FTL table 136 to represent the mapping relationship between the LBA address and the PBA address, and the FTL table 136 is stored in the buffer element 130.

[0010] For example, when the host 12 issues a write command, the host 12 generates an LBA address and write data to instruct the control circuit 110 to store the write data in the LBA address. Then, the control circuit 110 determines a PAA address in the non-volatile memory 120 to store the write data. Furthermore, the control circuit 110 further records the mapping relationship between the LBA address and the PAA address in the FTL table 136.

[0011] When the host 12 issues a read command, the host 12 generates an LBA address. The control circuit 110 confirms the PAA address corresponding to the LBA address according to the FTL table 136, obtains the read data at the PAA address of the non-volatile memory 120, and returns it to the host 12. In other words, according to the content of the FTL table 136, the control circuit 110 can determine the PAA address according to the LBA address and find the read data in the non-volatile memory 120.

[0012] The following uses a simple example to introduce the operation process of the conventional solid-state storage device 10, the mapping relationship between the FTL table 136 and the non-volatile memory 120, and the backup and load of the FTL table 136. FIG. 2A to FIG. 2C , which is the mapping relationship between the FTL table and the non-volatile memory when the control circuit performs read and write operations. Please refer to FIG. 2D to FIG. 2E , which is a schematic diagram of the backup and loading of the FTL table when the power is turned on and off.

[0013] like Figure 2A As shown, the non-volatile memory 120 has 6 blocks B1-B6, each block has 4 storage spaces. In the FTL table 136, b11 represents the PAA address of the first storage space in the first block B1, b12 represents the PAA address of the second storage space in the first block B1, and so on. Furthermore, a, c, and d all represent a specific number.

[0014] When the solid-state storage device 10 receives power and operates normally, such as Figure 2A From the content of FTL table 136 in FIG. 1 , it can be seen that PAA address b11 is mapped to LBA address (a), PAA address b12 is mapped to LBA address (a+1), PAA address b13 is mapped to LBA address (a+2), and PAA address b14 is mapped to LBA address (a+3). That is, the first storage space of the first block B1 stores data D of LBA address (a). a The second storage space of the first block B1 stores data D at LBA address (a+1). a+1 The third storage space of the first block B1 stores data D at LBA address (a+2). a+2 The fourth storage space of the first block B1 stores data D at the LBA address (a+3). a+3 .

[0015] Similarly, PAA address b21 is mapped to LBA address (c). That is, the first storage space of the second block B2 stores data D of LBA address (c).c In addition, in the FTL table 136, other PAA addresses are not mapped to LBA addresses, which means that other storage spaces in the non-volatile memory 120 may not store data or store invalid data. In other words, other storage spaces in the non-volatile memory 120 do not store valid data.

[0016] Basically, the host 12 can issue a read command to control the solid-state storage device 10. For example, when the host 12 issues a read command and an LBA address (a+2) to the control circuit 110, the control circuit 110 performs a read action. At this time, the control circuit 110 confirms that the LBA address (a+2) corresponds to the PAA address b13 according to the FTL table 136. Therefore, the control circuit 110 reads the data D in the third storage space of the first block B1. a+2 , and sent back to the host 12 to complete the reading operation.

[0017] Of course, the host 12 can issue a write command to control the solid-state storage device 10. For example, Figure 2B As shown, when the host 12 issues a write command, an LBA address (d) and write data D d When the control circuit 110 receives the data, the control circuit 110 performs a write operation. At this time, the control circuit 110 adds a mapping relationship between the LBA address (d) and the PAA address b22 in the FTL table 136, and writes the data D d The second storage space stored in the second block B2 completes the writing operation.

[0018] Furthermore, the host 12 may also issue a write command to amend the data of the LBA address. Figure 2C As shown, the host 12 issues a write command, LBA address (a) to LBA address (a+3) and amended write data D a '~D a+3 'When the control circuit 110 is reached, the control circuit 110 performs a write operation. At this time, the control circuit 110 deletes the original mapping relationship between the LBA address (a) to the LBA address (a+3) and the PAA address b11 to b14, so that the data D in the four storage spaces in the first block B1 a ~D a+3Furthermore, the control circuit 110 maps the LBA address (a) to the LBA address (a+3) to the PAA addresses b23, b24, b31, and b32 in the FTL table 136, and writes the amended write data D a '~D a+3 'Stored in the third storage space of the second block B2, the fourth storage space of the second block B2, the first storage space of the third block B3, and the second storage space of the third block B3, and the writing operation is completed.

[0019] In addition, since the data in the first block B1 have all become invalid data, the control circuit 100 can perform an erase action at an appropriate time to erase the first block B1 into a blank block, which can be used to store data again.

[0020] Furthermore, before the power supply of the solid-state storage device 10 is about to stop, the control circuit 110 will completely back up the content of the FTL table 136 in the blank storage space of the non-volatile memory 120. For example, Figure 2D As shown, before the power is about to stop supplying (power off), Figure 2C The contents of the FTL table 136 in the buffer element 130 will be completely backed up in the first storage space (the shaded area) of the sixth block B6. After the power supply is stopped, the contents of the FTL table 136 stored in the buffer element 130 will disappear. Figure 2D As shown in FTL table 136.

[0021] Since the content of the FTL table 136 has been stored in the non-volatile memory 120 after the power supply is turned off, when the solid-state storage device 10 receives power on again, the control circuit 110 will first load the content of the FTL table 136 that was last backed up in the non-volatile memory 120 into the buffer element 130. After that, the solid-state storage device 10 can operate normally. Figure 2E As shown, when the power is turned on again, the control circuit 110 first loads the content in the first storage space of the sixth block B6 into the FTL table 136 in the buffer element 130 .

[0022] When the FTL table 136 is successfully loaded into the buffer element 130, the control circuit 110 of the solid-state storage device 10 can operate normally. That is, the solid-state storage device 10 can perform read and write operations according to the read and write commands of the host 12. In addition, the control circuit 110 will modify the FTL table 136 to modify the mapping relationship between the LBA address and the PAA address during the write operation.

[0023] Similarly, when the power supply is stopped again, the control circuit 110 will completely back up the content of the FTL table 136 in the blank storage space of the non-volatile memory 120 again, for example, the content of the FTL table 136 is completely backed up in the second storage space of the sixth block B6. When the solid-state storage device 10 receives power to start again, the control circuit 110 will first load the content of the FTL table 136 that was last backed up in the non-volatile memory 120 into the buffer element 130. That is, the content of the FTL table 136 that was last backed up in the second storage space of the sixth block B6 is loaded into the buffer element 130. The content previously stored in the first storage space of the sixth block B1 will become invalid data.

[0024] As can be seen from the above description, the FTL table 136 stores the mapping relationship between the LBA address and the PAA address. Once the content in the FTL table 136 is wrong, the control circuit 110 will not be able to find the correct data. Therefore, when the solid-state storage device 10 receives power and operates normally, the FTL table 136 will be stored in the buffer element 130 to facilitate fast reading, storage and modification of the mapping relationship between the LBA address and the PAA address. Before the power of the solid-state storage device 10 is stopped, the control circuit 110 will back up the complete FTL table 136 in the non-volatile memory 120. When the power of the solid-state storage device 10 is supplied again, the control circuit 110 will first load the last backed up complete FTL table 136 from the non-volatile memory 120 into the buffer element 130. After that, the solid-state storage device 10 can operate normally.

[0025] Of course, in addition to performing a write operation, the control circuit 110 will modify the mapping relationship in the FTL table 136, and there are other times when the FTL table 136 needs to be modified. For example, when the control circuit 110 performs garbage collection, the valid data in the block to be erased will be moved to other blocks. At this time, the control circuit 110 also needs to modify the mapping relationship in the FTL table 136. In other words, when valid data is written to the non-volatile memory 120, or when valid data is moved in the non-volatile memory 120, the control circuit 110 needs to modify the mapping relationship in the FTL table 136.

[0026] Please refer to FIG. 3A to FIG. 3D , which is a schematic diagram of the processing of the FTL table when the power of the conventional solid-state storage device is turned on / off. In practical applications, the capacity of the FTL table 136 will increase as the capacity of the non-volatile memory 120 increases. For example, Figure 3B As shown, the non-volatile memory 120 in the 4Gbyte solid-state storage device 10 includes four channels CH1 to CH4, each channel includes 1024 blocks, each block has 64 pages, and the capacity of each page is 16Kbytes. In the 4Gbyte solid-state storage device 10, the capacity required for the FTL table 136 of its buffer element 130 is approximately between 2Mbytes and 3Mbytes. That is, the capacity of the FTL table 136 is greater than the capacity of two blocks and less than the capacity of three blocks. Therefore, in this example, when the control circuit 110 backs up the FTL table 136 to the non-volatile memory 120, three blocks of the non-volatile memory 120 are required to store the FTL table 136.

[0027] by Figure 3A For example, when the power is turned on, the control circuit 110 stores the data in block B of the non-volatile memory 120. 4084 ~Block B 4086 The complete FTL table is loaded into the buffer element 130 .

[0028] like Figure 3B As shown, when the solid-state storage device 10 is operating normally, as long as valid data is written or moved in the non-volatile memory 120, the control circuit 110 modifies the FTL table 136 in the buffer element 130. The FTL table 136 is modified in a similar manner. FIG. 2A to FIG. 2E In other words, after the control circuit 110 modifies the FTL table 136 in the buffer element 130, the content of the FTL table 136 will be different from that of the block B. 4084 ~Block B 4086 Stored content.

[0029] like Figure 3C As shown, when the power of the solid-state storage device 10 is turned off, the control circuit 110 backs up the complete FTL 136 table stored in the buffer element 130 to the blank block B. 4087 ~Block B 4089 In addition, the original storage in block B 4084 ~Block B 4086 The content in becomes invalid data (indicated by cross lines).

[0030] Similarly, if Figure 3DAs shown, when the power is turned on, the control circuit 110 stores the last backup in the non-volatile memory 120 in block B. 4087 ~Block B 4089 The complete FTL table is loaded into the buffer element 130 .

[0031] According to the above example, after the power is turned on / off once, three blocks storing invalid data will appear in the non-volatile memory 120. In order to reuse these three blocks, the control circuit 110 will perform an erase operation to erase the three blocks storing invalid data into three blank blocks, and the number of program / erase cycles (P / E cycles) of these three blocks will increase by one.

[0032] As is known to all, in the non-volatile memory 120, the higher the number of programming / erasing times of a block, the easier it is to be damaged. In other words, the life time of the non-volatile memory 120 is related to the number of programming / erasing times of the block. According to the above example, if the power of the solid-state storage device 10 is turned on / off 100 times, 300 blocks storing invalid data will be generated in the non-volatile memory 120. After the erasing operation is performed, the number of programming / erasing times of each of the 300 blocks will increase once. In this way, the life time of the volatile memory 120 will be shortened. Summary of the invention

[0033] The invention relates to a flash conversion layer corresponding table processing method of a solid-state storage device. The solid-state storage device has a control circuit, a buffer element and a non-volatile memory. The control circuit is connected to the buffer element and the non-volatile memory. The flash translation layer correspondence table processing method includes the following steps: when a power supply of the solid-state storage device is turned on, a flash translation layer correspondence table is loaded from a plurality of used blocks in the non-volatile memory into the buffer element, wherein the capacity of the flash translation layer correspondence table is less than the total capacity of the plurality of used blocks; when a valid data is written into the non-volatile memory or the written data is moved in the non-volatile memory, the flash translation layer correspondence table in the buffer element is modified so that the flash translation layer correspondence table has at least one modified content, and a content change table is used to record the position of the at least one modified content in the flash translation layer correspondence table; it is determined whether a backup action is to be performed on the flash translation layer correspondence table; when it is determined that the backup action is to be performed on the flash translation layer correspondence table, it is determined whether to back up the complete flash translation layer correspondence table to the non-volatile memory according to the at least one modified content in the flash translation layer correspondence table and the total data volume of the content change table.

[0034] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of a known solid-state storage device. ;

[0036] FIG. 2A to FIG. 2C A mapping relationship between the FTL table and the non-volatile memory when the control circuit performs a read action and a write action;

[0037] FIG. 2D to FIG. 2E The diagram is a schematic diagram of backing up and loading the FTL table when the power is turned on and off;

[0038] FIG. 3A to FIG. 3D A schematic diagram of the processing of the FTL table when the power of a known solid-state storage device is turned on / off;

[0039] Figure 4 is a schematic diagram of a solid-state storage device of the present invention;

[0040] Figure 5A A FTL table processing method for a solid-state storage device of the present invention; and

[0041] FIG. 5B to FIG. 5H It is a schematic diagram of the processing of the FTL table when the power of the solid-state storage device of the present invention is turned on / off. DETAILED DESCRIPTION

[0042] The structural principle and working principle of the present invention are described in detail below in conjunction with the accompanying drawings:

[0043] As is known to all, during the normal operation of the solid-state storage device, when valid data in the non-volatile memory is written or moved, the control circuit needs to modify the mapping relationship in the FTL table in the buffer element. In order to solve the problem that the FTL table in the buffer element disappears due to normal power off or abnormal power off, before the solid-state storage device is normally powered off, a backup action of the FTL table is performed, that is, the content of the FTL table is stored in the non-volatile memory. In addition, during the normal operation of the solid-state storage device, a backup action of the FTL table is also performed regularly or irregularly.

[0044] In actual applications, between each backup of the FTL table, only a small portion of the content in the FTL table of the solid-state storage device may be modified, while most of the content is not modified. If the control circuit stores the complete FTL table in a blank block of the non-volatile memory each time the FTL table is backed up, the number of programming / erasing times of the non-volatile memory will increase rapidly, affecting the life of the solid-state storage device. In addition, multiple backups of the complete FTL table will also occupy too much storage space of the non-volatile memory, making the use efficiency of the storage space of the non-volatile memory worse.

[0045] The present invention proposes a FTL table processing method for a solid-state storage device. The present invention further plans a part in the buffer element of the solid-state storage device as a content changed table to record the position of the changed content in the FTL table. When backing up the FTL table, the control circuit can determine the method of backing up the FTL table. For example, the control circuit can only back up the modified content of the FTL table to the used block in the non-volatile memory, or the control circuit can back up the complete FTL table to the blank block of the non-volatile memory. The following is a detailed description.

[0046] Please refer to Figure 4 , which is a schematic diagram of a solid-state storage device of the present invention. The solid-state storage device 40 includes a control circuit 410, a buffer element 430 and a non-volatile memory 120, and the control circuit 410 is connected to the buffer element 430 and the non-volatile memory 120. Outside the solid-state storage device 40, the control circuit 410 transmits instructions and data to a host 12 via an external bus 20.

[0047] Similarly, the non-volatile memory 120 includes a plurality of blocks, each of which includes a plurality of pages. For example, there are 1024 blocks in the non-volatile memory 120, and each block has 64 pages, and the capacity of each page is 16Kbytes. That is, the capacity of each block is 1Mbyte. Of course, the non-volatile memory 120 is not limited to only 1024 blocks, and the manufacturer of the non-volatile memory 120 can determine the number of pages in each block and the capacity of each page. That is, each block is not limited to only 64 pages, and each page is not limited to only 16Kbytes.

[0048] Furthermore, due to the characteristics of the non-volatile memory 120, the control circuit 410 performs a program action based on a page as a basic unit, and the control circuit 410 performs a block erase action based on a block as a unit.

[0049] According to an embodiment of the present invention, the storage space of the buffer element 430 is divided into multiple parts. The first part of the storage space of the buffer element 430 is used as a data buffer 432, the second part of the storage space is used as an FTL table 436, and the third part of the storage space is used as a content change table 438.

[0050] The data buffer 432 is used to temporarily store write data input by the host 12. For example, when the host 12 wants to store the write data in the non-volatile memory 120, the control circuit 410 temporarily stores the write data received from the external bus 20 in the data buffer 432. The control circuit 410 stores the write data in the non-volatile memory 120 from the data buffer 432 in a timely manner.

[0051] The FTL table 436 is used to store the mapping relationship between the LBA address and the PBA address. When valid data in the non-volatile memory 120 is written or moved, the control circuit 410 will modify the mapping relationship in the FTL table 436. The FTL table 436 is modified in a similar manner. FIG. 2A to FIG. 2E , I will not go into details here.

[0052] According to an embodiment of the present invention, when the FTL table 436 is modified during the process of the solid-state storage device 40 receiving power and starting to operate, the FTL table 436 will have the modified content, and the location of the modified content will be recorded in the content change table 438. That is, in the second part of the storage space used by the buffer element 430 as the FTL table 436, the storage location of the modified content will be recorded in the content change table 438. In other words, the location where the content in the FTL table 436 is modified can be known from the content change table 438. Figure 2B For example, the FTL table 136 newly records the mapping relationship between the LBA address (d) and the PAA address b22. According to an embodiment of the present invention, the LBA address (d) is the modified content, and the control circuit 410 records the location where the LBA address (d) is stored in the FTL table 436 in the content change table 438.

[0053] Before the power of the solid-state storage device 40 is turned off, or when the solid-state storage device 40 is in normal operation and the FTL table backup action is to be performed, the control circuit 410 can decide whether to back up the complete FTL table according to the total amount of modified content in the content change table 438 and the FTL table 436. When the control circuit 410 decides not to back up the complete FTL table, the control circuit 410 can back up only the modified content of the FTL table 436 to the used block in the non-volatile memory 120 according to the content change table 438, and the unchanged content in the FTL table 436 will not be backed up to the non-volatile memory 120. Therefore, the amount of data backed up will be less, and the number of programming / erasing times of the block can be effectively reduced. Among them, the above-mentioned used block is the block in the non-volatile memory 120 that stores the FTL table that was backed up last time.

[0054] Please refer to Figure 5A , which is the FTL table processing method of the solid-state storage device of the present invention. When the power is turned on (step S502), the control circuit 410 loads the FTL table in the non-volatile memory 120 into the buffer element 430 (step S504). During the normal operation of the solid-state storage device 40, when writing or moving valid data (step 506), the control circuit 410 modifies the FTL table 436 in the buffer element 430 so that the FTL table 436 has the modified content, and records the location of the modified content in the FTL table 436 in the content change table 438 (step S508). Furthermore, when the solid-state storage device 40 does not intend to perform the backup action of the FTL table 436 (step S510), the solid-state storage device 40 continues to operate normally and returns to step S506. When the solid-state storage device 40 intends to perform the backup action of the FTL table 436 (step S510), the control circuit 410 determines whether to back up the complete FTL table 436 (step S512). Furthermore, when the control circuit 410 decides not to back up the complete FTL table 436 (step S512), the control circuit 410 backs up the modified content of the FTL table 436 in the buffer element 430 to the remaining space of the used block in the non-volatile memory 120 according to the content change table 438 (step S514). Otherwise, the control circuit 410 backs up the complete FTL table 136 in the buffer element 430 to the blank block in the non-volatile memory 120 (step S516).

[0055] Please refer to FIG. 5B to FIG. 5H , which is a schematic diagram of the FTL table processing of the solid-state storage device of the present invention. For example, Figure 5BAs shown, the non-volatile memory 120 in the 4Gbyte solid-state storage device 40 includes four channels CH1~CH4, each channel includes 1024 blocks, each block has 64 pages, and the capacity of each page is 16Kbytes. In the solid-state storage device 10, the capacity required for the FTL table 436 of the buffer element 430 is approximately between 2Mbytes and 3Mbytes. In other words, the capacity of the complete FTL table 436 is greater than the capacity of two blocks and less than the capacity of three blocks. Therefore, when backing up the complete FTL table 436, the control circuit 410 needs to use three blocks of the non-volatile memory 120 to store the complete FTL table 436, and the complete FTL table 436 cannot occupy the storage space of three blocks, and will generate residual space. As Figure 5B As shown, the FTL table 436 is stored in block B of the non-volatile memory 120. 4084 ~Block B 4086 , and block B 4086 There is still space left in A.

[0056] like Figure 5B As shown, when the power is turned on, the control circuit 410 stores the data in block B of the non-volatile memory 120. 4084 ~Block B 4086 The content of is loaded into the buffer element 430 and the FTL table 436 is established. Furthermore, since no valid data has been written or moved in the non-volatile memory 120, the content change table 438 in the buffer element 430 does not store any information.

[0057] When the solid-state storage device 40 is in normal operation, when valid data is written or moved in the non-volatile memory 120, the control circuit 410 modifies the FTL table 436 in the buffer element 430 so that the FTL table 436 has the modified content. According to the embodiment of the present invention, since the FTL table 436 is modified, the control circuit 410 also records the position of the modified content in the FTL table 436 in the content change table 438.

[0058] According to an embodiment of the present invention, the FTL table 436 is divided into a plurality of areas with a 16Kbyte page size as a unit, and each area corresponds to a different position in the FTL table 436. Each position corresponds to an address information in the buffer element 430.

[0059] like Figure 5CAs shown, during the normal operation of the solid-state storage device 40, the contents of the three regions in the FTL table 436 are modified to have modified contents 1 to 3. At this time, the control circuit 410 records the positions of the three modified regions in the FTL table 436 in the content change table 438, namely, position p, position q, and position r. In other words, from the position p, position q, and position r recorded in the content change table 438, the control circuit 410 can know that the modified contents 1 to 3 are stored in the three regions of the FTL table 436. Among them, the position p, position q, and position r are the address information of the corresponding regions in the storage element 430.

[0060] like Figure 5D As shown, when the solid-state storage device 40 is to perform a backup operation of the FTL table 436, for example, when the power of the solid-state storage device 40 is to be turned off, since the total data size of the modified contents 1 to 3 of the FTL table 436 and the content change table 438 is smaller than the total data size of the block B 4086 Therefore, the control circuit 410 backs up the modified contents 1 to 3 and the content change table 438 in block B. 4086 The remaining space in A. In other words, block B 4086 Since the remaining space A of the block is sufficient, the control circuit 410 backs up the modified contents 1 to 3 of the FTL table 436 and the content change table 438 in block B. 4086 The remaining space A in.

[0061] like Figure 5D As shown, when the control circuit 410 backs up the modified contents 1 to 3 and the content change table 438 in block B 4086 After the remaining space in A, block B 4086 The remaining space A in is reduced to the remaining space A'.

[0062] As shown in FIG. 5E , when the power of the solid-state storage device 40 is turned off, the contents stored in the buffer element 430 will disappear.

[0063] like Fig. 5F As shown, when the power is turned on again, the control circuit 410 stores the data in block B of the non-volatile memory 120. 4084 ~Block B 4086 The content of is loaded into the buffer element 430 and the FTL table 436 is established. According to the embodiment of the present invention, the control circuit 410 first reads the block B in sequence. 4084 ~Block B 4086and establish the previously backed-up FTL table. Next, the control circuit 410 updates the FTL table 436 according to the content change table 438 in the remaining space A. In other words, the control circuit 410 knows from the content change table 438 in the remaining space A that the contents in position p, position q, and position r in the FTL table 436 have been modified, and updates the backed-up modified contents 1 to 3 from the remaining space A to the areas corresponding to position p, position q, and position r in the FTL table 436, respectively, so that the contents of the FTL table 436 are exactly the same as the contents before the power is turned off. Furthermore, since valid data has not been written or moved in the non-volatile memory 120, the content change table 438 in the buffer element 430 does not store any information. In other words, the positions p, position q, and position r before the previous power was turned off are no longer stored in the content change table 438.

[0064] In addition to the above-mentioned method for loading the FTL table 436, in other embodiments of the present invention, another method may be used to load the FTL table 436. For example, when the control circuit 410 loads block B 4084 ~Block B 4086 In the process of loading the contents of the buffer element 430, the table 438 is changed according to the contents in the remaining space A. The area at position p of the FTL table 436 is directly replaced with content 1, the area at position q is directly replaced with content 2, and the area at position r is directly replaced with content 3. Therefore, when the FTL table 436 is established, its contents are exactly the same as before the power is turned off. That is, when reading block B 4084 ~Block B 4086 The FTL table 436 is established together with the modification contents 1 to 3 indicated by the content change table 438 during the process.

[0065] like Figure 5G As shown, when the solid-state storage device 40 is operating normally, valid data is written or moved in the non-volatile memory 120, and the control circuit 410 modifies the FTL table 436 in the buffer element 430 so that the FTL table 436 has the modified content. For example, the content of three areas in the FTL table 436 is modified and has modified content 4 to 6. At this time, the control circuit 410 records the positions of the three modified areas in the FTL table 436 in the content change table 438, that is, position x, position y, and position z. In other words, from the position x, position y, and position z recorded in the content change table 438, the control circuit 410 can know that the content in the three areas in the FTL table 436 has been modified. Among them, position x, position y, and position z are the address information of the corresponding areas in the storage element 430.

[0066] like Figure 5HAs shown, when the solid-state storage device 40 wants to perform the backup operation of the FTL table 436 again, for example, when the power of the solid-state storage device 40 is turned off, since the total amount of modified contents 4 to 6 of the FTL table 436 and the content change table 438 is greater than the total amount of data in block B 4086 Therefore, the control circuit 410 backs up the complete FTL table 436 in the blank block B. 4087 ~Blank Block B 4089 In addition, the original storage in block B 4084 ~ and Block B 4086 The content in block B becomes invalid data (indicated by cross lines). 4084 ~ and Block B 4086 The erase operation is performed to create a blank block.

[0067] Similarly, since the size of the complete FTL table 436 is smaller than three blank blocks B 4087 ~Blank Block B 4089 So when the FTL table 436 is backed up to the blank block B 4087 ~Blank Block B 4089 Afterwards, block B 4089 There will be a remaining space C inside.

[0068] Similarly, when the solid-state storage device 40 is powered on again, the control circuit 410 may use block B 4087 ~Block B 4089 The FTL table 436 is loaded. Furthermore, when the FTL table 436 is to be backed up, it is determined according to the remaining space C whether to back up the complete FTL table 436 in a blank block.

[0069] On the contrary, suppose that the total amount of modified contents 4 to 6 of the FTL table 436 and the content change table 438 is smaller than that of block B. 4086 If there is no remaining space A' in block B, the control circuit 410 will adopt the method of backing up the modified content, that is, backing up the modified content 4 to 6 and the content change table 438 in block B. 4086 In the remaining space A'.

[0070] As can be seen from the above description, the present invention provides a FTL table processing method for a solid-state storage device. When the FTL table 436 is to be backed up, the control circuit 410 determines the size of the remaining space in the used block for backing up the FTL table 436, and further determines whether to back up the complete FTL table 436 to a blank block. The used block is the block storing the FTL table backed up last time.

[0071] When there is enough remaining space in the used block, the control circuit 410 stores the modified contents 1-3 and the content change table 438 in the FTL table 436 in the remaining space in the used block. Conversely, when there is insufficient remaining space in the used block, the control circuit 410 backs up the complete FTL table 436 in a blank block.

[0072] In practical applications, in most cases, as long as the remaining space of the used block storing the previously backed-up FTL table is sufficient, the control circuit 410 will use the remaining space of the used block to perform the backup operation of the FTL table 436. When the backup operation of the FTL table 436 exceeds dozens of times, the control circuit 410 may perform a backup operation to back up the complete FTL table 436 in the blank block B. 4087 ~Blank Block B 4089 In other words, compared to the conventional FTL table processing method, the FTL table processing method of the present invention can indeed reduce the number of programming / erasing times of the non-volatile memory 120 and extend the life time of the volatile memory 120 .

[0073] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A method for processing a flash translation layer correspondence table of a solid-state storage device, the solid-state storage device having a control circuit, a buffer element, and a non-volatile memory, the control circuit being connected to the buffer element and the non-volatile memory, characterized in that, the method comprises the following steps: When a power supply of the solid-state storage device is turned on, a flash translation layer correspondence table is loaded from a plurality of used blocks in the non-volatile memory into the buffer element, wherein the capacity of the flash translation layer correspondence table is smaller than the total capacity of the used blocks; When valid data is written into the non-volatile memory or the valid data is moved in the non-volatile memory, the flash translation layer correspondence table in the buffer element is modified and a content change table is used to record the positions of the modified contents in the flash translation layer correspondence table; Determine whether to perform a backup operation on the flash translation layer correspondence table; When it is determined to perform the backup operation on the flash translation layer correspondence table, it is determined whether to back up the complete flash translation layer correspondence table to the non-volatile memory according to at least one modified content in the flash translation layer correspondence table and the total data volume of the content change table.

2. The processing method according to claim 1, characterized in that, further comprises the following steps: When it is determined to back up the complete flash translation layer correspondence table, the complete flash translation layer correspondence table in the buffer element is backed up to a plurality of blank blocks in the non-volatile memory; and When it is determined not to back up the complete flash translation layer correspondence table, according to the content change table, at least one modified content in the flash translation layer correspondence table is backed up to a remaining space in the used blocks.

3. The processing method according to claim 2, characterized in that, further comprises the following steps: When it is determined not to back up the complete flash translation layer correspondence table, the content change table is backed up to the remaining space in the used blocks.

4. The processing method according to claim 1, characterized in that, the flash translation layer correspondence table in the buffer element is divided into a plurality of regions. When a first region among the regions is modified, a first position corresponding to the first region is recorded in the content change table.

5. The processing method according to claim 4, characterized in that, the buffer element is a volatile memory, and the first position of the buffer element is an address information in the volatile memory.

6. The processing method according to claim 1, characterized in that, when the total data volume of at least one modified content in the flash translation layer correspondence table and the content change table is greater than a remaining space in the used blocks, it is determined to back up the complete flash translation layer correspondence table; and when the total data volume of at least one modified content in the flash translation layer correspondence table and the content change table is smaller than the remaining space in the used blocks, it is determined not to back up the complete flash translation layer correspondence table.

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