Method, device, electronic equipment and storage medium for processing integrated circuit layout

Abstract

The application provides a method and device for processing an integrated circuit layout, electronic equipment and a storage medium. The technical solution of the application comprises: obtaining a first integrated circuit layout with a multi-layer structure, each layer of the layout containing a pattern and pin information of the pattern; dispersing the first integrated circuit layout to obtain a second integrated circuit layout and first pin information; wherein the first pin information comprises pin information of all patterns in the first integrated circuit layout; screening the first pin information according to pin configuration information to obtain second pin information, which is used for being reserved in the second integrated circuit layout. By using the technical solution of the application, the specified pin information can be accurately reserved in the process of dispersing the layout.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit layout design, and in particular to a method and device for processing integrated circuit layout, electronic equipment and storage medium. BACKGROUND

[0002] After the layout design of an integrated circuit is completed, the layout is often flattened due to various processes. Flattening refers to flattening a layout composed of multiple layers.

[0003] At present, most integrated circuit layout design tools have a flattening function, but do not have a function of retaining specified pin information. Pin information refers to a port defined on a layout graph and having a net attribute. SUMMARY

[0004] The embodiments of the present application provide a method and device for processing integrated circuit layout, electronic equipment and storage medium to solve the problems in the related art, and the technical solutions are as follows.

[0005] In a first aspect, the embodiments of the present application provide a method for processing integrated circuit layout, comprising:

[0006] obtaining a first integrated circuit layout; wherein the first integrated circuit layout comprises a graph and pin information of the graph;

[0007] flattening the first integrated circuit layout to obtain a second integrated circuit layout and first pin information; wherein the first pin information comprises pin information of all graphs in the first integrated circuit layout;

[0008] screening the first pin information according to pin configuration information to obtain second pin information; wherein the second pin information is used to retain in the second integrated circuit layout.

[0009] In an embodiment, screening the first pin information according to pin configuration information to obtain second pin information comprises:

[0010] retaining or deleting pin information in the first pin information according to the pin configuration information to obtain the second pin information.

[0011] In an embodiment, the method further comprises:

[0012] protecting target pin information of the first integrated circuit layout before flattening the first integrated circuit layout;

[0013] According to the pin configuration information, pin information in the first pin information is reserved or deleted to obtain second pin information, including:

[0014] According to the pin configuration information, pin information in the first pin information is reserved or deleted to obtain second pin information.

[0015] In an embodiment, the method further includes:

[0016] The configuration instruction is preset, and the pin configuration information is preset based on the configuration instruction;

[0017] Or, a write request is received, and the pin configuration information is set based on the write request.

[0018] In an embodiment, the pin configuration information is obtained based on the write request, including:

[0019] In response to the write request of the pin configuration information, a write interface of the pin configuration information is displayed;

[0020] The pin configuration information is received through the write interface.

[0021] In an embodiment, the write interface includes a search box, and the search box is used to search pin information in a pin information database based on a keyword input into the search box to specify reservation or specified deletion, and the pin information database includes the first pin information.

[0022] In an embodiment, the pin configuration information is used to specify reservation or specified deletion of pin information, and the pin information includes an identifier of a pin, a device to which the pin belongs, and a layer on which the pin is located.

[0023] In an embodiment, the method further includes:

[0024] In the second integrated circuit layout, at least two patterns with the same attribute and intersection are merged into one pattern.

[0025] In a second aspect, an embodiment of the present application provides a device for processing an integrated circuit layout, including:

[0026] A layout acquisition module is configured to acquire a first integrated circuit layout; wherein the first integrated circuit layout includes a pattern and pin information of the pattern;

[0027] A layout scattering module is configured to scatter the first integrated circuit layout to obtain a second integrated circuit layout and first pin information; wherein the first pin information includes pin information of all patterns in the first integrated circuit layout;

[0028] a pin screening module configured to screen the first pin information according to the pin configuration information to obtain second pin information, wherein the second pin information is configured to be reserved in the second integrated circuit layout.

[0029] In an embodiment, the pin screening module comprises:

[0030] a pin deleting unit configured to reserve or delete pin information in the first pin information according to the pin configuration information to obtain second pin information.

[0031] In an embodiment, the apparatus further comprises a pin protection module configured to protect target pin information of the first integrated circuit layout before the first integrated circuit layout is scattered.

[0032] The pin deleting unit is specifically configured to reserve or delete un-protected pin information in the first pin information according to the pin configuration information to obtain second pin information.

[0033] In an embodiment, the apparatus further comprises:

[0034] a pin configuration information preset module configured to preset a configuration instruction and preset the pin configuration information based on the configuration instruction.

[0035] or a pin configuration information writing module configured to receive a writing request and set the pin configuration information based on the writing request.

[0036] In an embodiment, the pin configuration information writing module comprises:

[0037] a writing interface display unit configured to display a writing interface of the pin configuration information in response to a writing request of the pin configuration information.

[0038] a configuration information receiving unit configured to receive the pin configuration information through the writing interface.

[0039] In an embodiment, the writing interface comprises a search box configured to search pin information in a pin information database for specified reservation or specified deletion based on a keyword input into the search box, wherein the pin information database comprises the first pin information.

[0040] In an embodiment, the pin configuration information is configured to specify reservation or specified deletion of pin information, wherein the pin information comprises an identifier of a pin, a device to which the pin belongs, and a layer on which the pin is located.

[0041] In an embodiment, the apparatus further comprises:

[0042] a graph merging module, configured to merge the same attribute and intersecting graphs into one graph in the second integrated circuit layout.

[0043] In a third aspect, an electronic device is provided. The electronic device includes at least one processor, and a memory connected with the at least one processor in communication; and the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method for processing an integrated circuit layout according to any of the embodiments of the present application.

[0044] In a fourth aspect, a non-transitory computer readable storage medium is provided. The computer readable storage medium stores computer instructions, and the computer instructions are executed by a processor to implement the method for processing an integrated circuit layout according to any of the embodiments of the present application.

[0045] The advantages or beneficial effects of the above technical solutions at least include:

[0046] In the technical solutions provided by the present application, the integrated circuit layout of the multi-layer graph structure is scattered to obtain the scattered integrated circuit layout and pin information, and since the pin information includes the pin information of all graphs in the layout before scattering, the pin configuration information is used to screen the pin information, so that the useful pin information can be retained in the layout, and the redundant pin information is removed.

[0047] The above summary is only for the purpose of the description and is not intended to limit in any way. In addition to the above described exemplary aspects, embodiments and features, further aspects, embodiments and features of the present application will be readily apparent to those skilled in the art by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0048] In the drawings, like reference numerals refer to same or similar components throughout the several views. These drawings are not necessarily to scale. It should be understood that these drawings only depict some embodiments in accordance with the present disclosure and should not be considered to be limiting of the scope of the disclosure.

[0049] Figure 1 A flowchart of the method for processing an integrated circuit layout according to the embodiments of the present application is shown;

[0050] Figure 2A A cross-sectional schematic diagram of the first integrated circuit layout according to the embodiments of the present application is shown;

[0051] Figure 2B A cross-sectional schematic diagram of the second integrated circuit layout according to the embodiments of the present application is shown;

[0052] Figure 3A A schematic diagram of an interface for displaying a layout according to an embodiment of the present application;

[0053] Figure 3B A schematic diagram of a write interface on an interface for displaying a layout according to an embodiment of the present application;

[0054] Figure 4A A cross-sectional schematic diagram of a second integrated circuit layout before merging patterns according to an embodiment of the present application;

[0055] Figure 4B A cross-sectional schematic diagram of a second integrated circuit layout after merging patterns according to an embodiment of the present application;

[0056] Figure 4C A planar schematic diagram of a first layer pattern of a second integrated circuit layout before merging patterns according to an embodiment of the present application;

[0057] Figure 4D A planar schematic diagram of a first layer pattern of a second integrated circuit layout after merging patterns according to an embodiment of the present application;

[0058] Figure 5 A flow chart of a method for processing an integrated circuit layout according to an embodiment of the present application;

[0059] Figure 6 A structural block diagram of an apparatus for processing an integrated circuit layout according to an embodiment of the present application;

[0060] Figure 7 A structural block diagram of an apparatus for processing an integrated circuit layout according to an embodiment of the present application;

[0061] Figure 8 A structural block diagram of an electronic device for processing an integrated circuit layout according to an embodiment of the present application. DETAILED DESCRIPTION

[0062] In the following, only certain example embodiments are simply described. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and description are to be regarded as illustrative in nature and not as restrictive.

[0063] Integrated circuit layout design refers to mapping a circuit design circuit diagram or circuit description language to a physical description level so that a designed circuit can be mapped to a wafer for production.

[0064] An integrated circuit layout (IC Layout) is a planar geometric description of the physical situation of a real integrated circuit. Physical design converts the result of logic synthesis into a physical layout file through layout and routing technology. The layout can include device types, device sizes, relative positions between devices, and connection relationships between devices of the integrated circuit, and other related physical information graphics composed of graphics on different drawing layers.

[0065] After the integrated circuit layout design is completed, the layout is circulated due to various processes, and in order to ensure the safety of the layout during circulation, the layout needs to be scattered. The graphics and pin information in the scattered layout are chaotic, and the graphics of each layer before scattering and the relationship between the graphics of each layer cannot be seen, so as to achieve the effect of ensuring the safety of the layout. However, in the process of scattering the layout, the current layout design tool does not have the function of retaining specified pin information by itself. Therefore, the present application proposes a scheme to retain the specified pin information in the process of scattering the layout.

[0066] Figure 1 A flowchart of a method for processing an integrated circuit layout according to an embodiment of the present application is shown. As shown in the figure, the method can include: Figure 1

[0067] S110, obtaining a first integrated circuit layout; wherein the first integrated circuit layout includes graphics and pin information of the graphics;

[0068] S120, scattering the first integrated circuit layout to obtain a second integrated circuit layout and first pin information; wherein the first pin information includes pin information of all graphics in the first integrated circuit layout;

[0069] S130, screening the first pin information according to pin configuration information to obtain second pin information; wherein the second pin information is used to retain in the second integrated circuit layout.

[0070] For the layers of the layout, taking the CMOS process as an example, they are mainly divided into N-well layer, active area layer, polysilicon gate layer, N-select layer, P-select layer, contact hole layer, via hole layer, metal layer, text annotation layer, and pad layer.

[0071] The first integrated circuit layout has a three-dimensional structure, which can be understood as a structure divided into bays and layers. Each bay graphic includes one or more layer structure graphics. Each layer structure includes corresponding graphics and pin information of the graphics, which can be referred to as Hierarchy IC layout. For example, the graphics can include one or more components, the positions of the components, and the connection relationships between the components. The bays can intersect or not intersect.

[0072] ​Exemplarily, as shown in Figure 2A The first integrated circuit layout 201 includes three buildings A, B and C, the building A intersects with the building B, the building C does not intersect with the building A and the building B, and the buildings A, B and C each include six layers of patterns. Each building can be regarded as a pattern block composed of multiple layers of patterns, and the pattern blocks can intersect or not intersect with each other.

[0073] The second integrated circuit layout obtained by dispersing the first integrated circuit layout no longer has a building structure, but the layer structure still exists. Therefore, the building structure between the patterns of different layers cannot be obtained from the layout, which ensures the security of the layout in the circulation process.

[0074] Exemplarily, as shown in Figure 2B The second integrated circuit layout 202 includes six layers of patterns, and each layer of patterns includes multiple sub-patterns which can intersect or not intersect with each other. The second integrated circuit layout 202 is the layout obtained by dispersing the first integrated circuit layout 201 in Figure 2A The building structure in the layout is deleted and only shown in a dashed line.

[0075] The pin information can include a string of a port defined on a pattern of the layout and with a net attribute.

[0076] The pin configuration information is used to specify the pin information to be retained. It can include an identifier of the pin, a device to which the pin belongs, and a layer on which the pin is located, etc.

[0077] In some embodiments, the first integrated circuit layout can be dispersed by invoking a layout dispersing tool. After the layout is dispersed, the building structure in the layout is eliminated, and the patterns on the same layer cannot be distinguished from which building the pattern comes. For the pin information after the layout is dispersed, the existing technology cannot specify to retain or delete the pin information.

[0078] In the embodiments of the present application, after the layout is dispersed, the pin configuration information is used to filter the pin information to be retained, so as to improve the filtering efficiency and reduce the probability of errors.

[0079] In some embodiments, before the layout is dispersed, the target pin information of a specified layer to be retained can be protected, for example, by using a marking method, marked in a certain specific color, or using a set to record the pin information of the specified layer. After the layout is dispersed, because the pin information to be retained is marked, the pin information which is not marked can be deleted, so that the effect of retaining the pin information of the specified layer can also be achieved.

[0080] The specified layer can be a top layer, a certain middle layer or a bottom layer, etc.

[0081] Exemplarily, the foregoing method can further include: before dispersing the first integrated circuit layout, protecting pin information of a top layer pattern of the first integrated circuit layout. For example, the pin information of the top layer pattern can be marked in a manner of a set identifier, so that the pin information of the top layer pattern can be obviously distinguished from other pin information when the pin information is screened later, facilitating the reservation of the pin information of the top layer pattern, and achieving the effect of protecting the pin information of the top layer pattern.

[0082] Exemplarily, the step S130 of reserving or deleting the pin information in the first pin information according to the pin configuration information to obtain the second pin information can include:

[0083] Reserving or deleting the pin information not protected in the first pin information according to the pin configuration information to obtain the second pin information.

[0084] Exemplarily, for the pin information not protected in the first pin information, the pin information not specified to be reserved in the pin configuration information is deleted.

[0085] In the present example, the protected pin information is the pin information of the specified pattern. In the deletion process, the protected pin information is excluded, which not only accurately reserves the pin information specified in the pin configuration information, but also does not affect the pin information of the specified pattern, such as the pin information of the top layer pattern.

[0086] In the present example, if no pin information in the layout is marked, the pin information not specified to be reserved in the pin configuration information can be directly deleted.

[0087] Exemplarily, for the pin information not protected in the first pin information, the pin information specified to be deleted in the pin configuration information is deleted.

[0088] In some embodiments, the foregoing method can further include: setting a configuration instruction in advance, and presetting the pin configuration information based on the configuration instruction. In this way, when the first integrated circuit layout is obtained, the first integrated circuit layout can be directly dispersed according to the preset pin configuration information, and the pins in the first pin information are specified to be reserved or deleted.

[0089] The configuration instruction can be an operation code or a running configuration document, and the pin configuration information contained in the operation code or the running configuration document is specified to reserve or delete the pins, which is imported into a running program related to the method to perform the preset operation of the pin configuration information.

[0090] In some embodiments, the foregoing method can further include: receiving a write request of the pin configuration information; and setting the pin configuration information based on the write request. In some embodiments, the foregoing method can further include: receiving a write request of the pin configuration information; and setting the pin configuration information based on the write request.

[0091] In some embodiments, to improve user experience, a writing interface can be provided to facilitate user input of pin configuration information. The writing interface can be a graphical user interface (GUI).

[0092] Exemplarily, the obtaining of the pin configuration information based on the writing request can include:

[0093] In response to the writing request of the pin configuration information, displaying a writing interface of the pin configuration information;

[0094] Receiving the pin configuration information through the writing interface.

[0095] Exemplarily, in a software or program for processing a layout, the layout is displayed in an interface, and the interface can provide tools for designing or modifying the layout, which are displayed in a menu bar in the form of button graphics. As shown in Figure 3A The layout is displayed in an interface 301, and a menu bar 302 of the interface includes a pin configuration information writing button 303. As shown in Figure 3B When the user clicks the button 303 or types a shortcut key corresponding to the function of the button through a keyboard, the software displays a writing interface 304 in the interface 301 in response to the writing request of the pin configuration information. In the writing interface 304, there is an input box 305 of the pin configuration information.

[0096] In some embodiments, the writing interface can provide a selectable belonging layer of the pin information, a selectable pin identifier, a selectable belonging device, etc. The writing interface can also provide a custom input box of the pin information, through which the user can input pin information that he or she wants to keep or delete.

[0097] In some embodiments, the writing interface can include a search box and provide recent search keywords in the writing interface. The search box is used to search for corresponding pin information in a pin information database based on keywords input into the search box to specify keeping or deleting the pin information. The pin information database includes first pin information, i.e., pin information of all graphics in a first integrated circuit layout. The search keywords can include an identifier of a pin, an identifier of a layer where the pin is located, etc.

[0098] In some embodiments, a command line operation mode can also be adopted to provide a command line input interface for the user to input the pin configuration information. That is, in the case of receiving a writing request of pin configuration, a command line input interface is displayed; and the pin configuration information is received through the command line input interface.

[0099] In some embodiments, a command line input interface and the write interface of the pin configuration information described above can also be provided for the customer to select. Specifically, in the case of receiving a write request of the pin configuration, a selection interface of the command line input interface and the write interface of the pin configuration information is displayed; the interface selection result is received through the selection interface, and the interface corresponding to the interface selection result is displayed according to the received interface selection result; and the pin configuration information is received through the interface corresponding to the interface selection result.

[0100] In some embodiments, after the layout is scattered, the graphics located in the same layer can also be merged, the attributes are adjusted, and the like.

[0101] Exemplarily, in the second integrated circuit layout, the graphics with the same attributes and intersecting each other are merged into one graphic; wherein the attributes of the graphics at least include the layer to which the graphics belong. In this example, two or more graphics with the same attributes can be merged. For graphics with different attributes, they cannot be merged into one graphic because their attributes are not the same. For graphics that do not intersect or are not tangent, even if the attributes are the same, they cannot be merged into one graphic, and their original appearance can be retained.

[0102] Exemplarily, as shown in Figure 4A , the second integrated circuit layout includes six layers of graphics, and each layer of graphics can have some graphics intersecting each other and some graphics not intersecting each other. The merging operation is performed on each layer of graphics in the second integrated circuit layout, and then two graphics intersecting each other are merged into one graphic, and the part of the graphics intersecting each other is overlapped or considered as repeated, and the merging is to remove the repetition. The second integrated circuit layout after the merging operation can be as shown in Figure 4B . The above Figure 4A and Figure 4B are cross-sectional schematic views of the layout. The merging operation will be described from one layer of the layout below. Figure 4C-4D is a planar schematic view of a layer in the layout.

[0103] Exemplarily, as shown in Figure 4C , the first layer of graphics Layer1 of the second integrated circuit layout includes graphics Layer1-A, graphics Layer1-B, and graphics Layer1-C, the graphics Layer1-A intersects the graphics Layer1-B, and the graphics Layer1-C does not intersect the graphics Layer1-A and the graphics Layer1-B. Since the attribute of the gable has been deleted in the layout, the graphics are located in the same layer, and the attributes of the part intersecting each other are the same. Therefore, the merging is performed on the graphics with the same attributes, and the graphics of the repeated structure can be quickly removed. For the graphics located in different layers, their attributes are not the same, and the merging operation cannot be performed.

[0104] After the merging operation is performed on the first layer of graphics Layer1, the result can be as shown in Figure 4D Layer1-D is the result of merging Layer1-A and Layer1-B, which can be considered as the union of Layer1-A and Layer1-B. During the merging process, for the graphics of Layer1-A and Layer1-B that intersect, i.e., the overlapping graphics, the de-duplication is performed, and for the graphics of Layer1-A and Layer1-B that do not intersect, the graphics are directly retained. Layer1-C does not intersect with Layer1-A and Layer1-B, and thus is not merged with them.

[0105] For example, in the second integrated circuit layout, the graphics that do not belong to the set format are converted into the graphics of the set format. For example, the set format can be polygon.

[0106] For example, the graphics of the format of path are converted into the graphics of the format of polygon.

[0107] In some embodiments, before the first integrated circuit layout is scattered, the first integrated circuit layout can be copied and its name can be changed so as to backup the original data and avoid the loss of the original data. In the case that the operation performed on the layout is wrong, the original data can be used to re-operate.

[0108] Figure 5 A flowchart of a method of processing an integrated circuit layout according to an embodiment of the present application is shown. As shown in Figure 5 The method can be performed in the environment of Cadence virtuoso (a chip design tool developed by Cadence), and can include:

[0109] S210, input pin configuration information. In the virtuoso environment, in the case that a write request of pin configuration information is received, a write interface of the pin configuration information is displayed. The user can fill in the write interface the layout name for which the pin information needs to be preserved, the specified layer in the layout, and the pin information. After the user fills in the configuration information, the complete button is clicked. Then, the virtuoso receives the pin configuration information through the write interface, and saves the pin configuration information for backup.

[0110] S220, backup of the original layout. In the virtuoso environment, the layout of the multi-layer graphics structure that needs to be scattered is copied, and is named as a specified name, for example, layout-fm. Thus, the backup of the original layout data is achieved. The following operations are based on the layout with the name of layout-fm.

[0111] S230, marking pin information of top layer graphics to be reserved.

[0112] S240, dispersing the layout. The layout with the structure of the gate and the layer is dispersed to obtain the layout after the structure of the gate is deleted and the pin information. The pin information includes marked and unmarked pin information. In the unmarked pin information, the pin information not specified to be reserved in the pin configuration information is deleted. The marked pin information and the unmarked pin information after the corresponding pin information is deleted are reserved in the dispersed layout.

[0113] S250, merging graphics. In the layout obtained after the dispersion, graphics with the same attribute and intersection are merged into one graphic.

[0114] S260, graphic format conversion. In the layout obtained after the dispersion, graphics in the format of path are converted into graphics in the format of polygon.

[0115] S270, performing a save operation on the above operations.

[0116] It should be noted that the execution order between the steps in the embodiment is not limited. For example, step S210 can operate in parallel with step S230, and step S270 can operate in parallel with steps S230, S240, S250, S260.

[0117] In the embodiment, when the layout is dispersed, the pin information of the specified top layer graphics can be reserved, and the pin information not specified to be reserved in the pin configuration information is deleted, so that the dispersed layout can match the configuration information, and the pin information of the top layer graphics is not affected.

[0118] The embodiment can disperse the layout of the cell level, can improve the efficiency of dispersion and graphic conversion, and can backup the original data, and has the characteristics of high fault tolerance.

[0119] Figure 6 A flowchart of a device for processing integrated circuit layout according to an embodiment of the application is shown.

[0120] As shown in Figure 6 , the device can include:

[0121] The layout acquisition module 310 is configured to acquire a first integrated circuit layout; wherein the first integrated circuit layout includes graphics and pin information of the graphics;

[0122] The layout scattering module 320 is configured to scatter the first integrated circuit layout to obtain a second integrated circuit layout and first pin information, wherein the first pin information comprises pin information of all patterns in the first integrated circuit layout.

[0123] The pin screening module 330 is configured to screen the first pin information according to pin configuration information to obtain second pin information, wherein the second pin information is used to be reserved in the second integrated circuit layout.

[0124] In some embodiments, as shown in FIG. 3, the pin screening module 330 comprises: Figure 7

[0125] The pin deletion unit 331 is configured to reserve or delete pin information in the first pin information according to the pin configuration information to obtain second pin information.

[0126] In some embodiments, as shown in FIG. 3, the device further comprises a pin protection module 340 configured to protect target pin information of the first integrated circuit layout before scattering the first integrated circuit layout. Figure 7

[0127] The pin deletion unit 331 is configured to reserve or delete unprotected pin information in the first pin information according to the pin configuration information to obtain second pin information.

[0128] In some embodiments, as shown in FIG. 3, the device further comprises: Figure 7

[0129] The pin configuration information preset module 350 is configured to preset configuration instructions, and preset the pin configuration information based on the configuration instructions.

[0130] Or, the pin configuration information writing module 360 is configured to receive a writing request, and set the pin configuration information based on the writing request.

[0131] In some embodiments, as shown in FIG. 3, the pin configuration information writing module 360 comprises: Figure 7

[0132] The writing interface display unit 361 is configured to display a writing interface of the pin configuration information in response to a writing request of the pin configuration information.

[0133] The configuration information receiving unit 362 is configured to receive the pin configuration information through the writing interface.

[0134] ​​​​In some embodiments, the write interface comprises a search box for searching pin information in a pin information database based on a keyword input into the search box for specifying retention or specifying deletion, the pin information database comprising pin information of all patterns in the first integrated circuit layout.

[0135] In some embodiments, the pin configuration information is used for specifying retention or specifying deletion of pin information, the pin information comprising an identifier of a pin, a device to which the pin belongs, and a layer on which the pin is located.

[0136] In some embodiments, as shown in Figure 7 The apparatus can further include:

[0137] a pattern merging module 370, configured to merge at least two patterns with the same attribute and intersecting each other into one pattern in the second integrated circuit layout.

[0138] The functions of each module in the apparatuses of the embodiments of the present application can be referred to the corresponding description in the above method, which will not be repeated here.

[0139] According to the embodiments of the present application, the present application further provides an electronic device and a readable storage medium.

[0140] Figure 8 A schematic block diagram of an example electronic device 500 that can be used to implement embodiments of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application described and / or claimed in this document.

[0141] As shown in Figure 8 The electronic device 500 includes a computing unit 501 that can perform various appropriate actions and processes in accordance with a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. Various programs and data required for the operation of the electronic device 500 can also be stored in the RAM 503. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0142] A number of components in the device 500 are connected to the I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, an optical disk, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0143] The computing unit 501 can be various general and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 501 performs various methods and processes described above, such as the method of processing integrated circuit layouts. For example, in some embodiments, the method of processing integrated circuit layouts can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 508. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded onto the RAM 503 and executed by the computing unit 501, one or more steps of the method of processing integrated circuit layouts described above can be performed. Alternatively, in other embodiments, the computing unit 501 can be configured to perform the method of processing integrated circuit layouts by any other appropriate means, such as by means of firmware.

[0144] Various implementations of the systems and techniques described above herein can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0145] Program code for carrying out methods of the present application can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces a means for implementing the functions / acts specified in the flowcharts and / or block diagrams. The program code can be retrieved from a machine-readable medium or device and executed by a processor to produce a machine for implementing the functions / acts specified in the flowcharts and / or block diagrams. The program code can be executed as a stand-alone program, or in combination with other program codes, on the machine to produce a machine that implements the functions / acts specified in the flowcharts and / or block diagrams.

[0146] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable storage media can include, without limitation, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media can include, but are not limited to, an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0147] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0148] The systems and techniques described herein can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described herein), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0149] The computer system can include clients and servers. This relationship can be. The servers are typically remote from the clients with the interactions typically taking place over a communication network. The relationship between a client and a server is one of client-server relationship. The server can be a cloud server, a server of a distributed system, or a server incorporating blockchain.

[0150] It should be understood that the steps shown in the various forms above can be reordered, added to, or deleted from. For example, the steps recited in the present application can be executed in parallel, in series, or in a different order, as long as the desired results of the technology disclosed in the present application can be achieved, and the present application is not limited herein.

[0151] The specific embodiments described above are not intended to be limiting. One of skill in the art will understand that various modifications, combinations, sub-combinations, and alternatives can be made to the specific embodiments described above without departing from the scope of the disclosure. Any modifications, combinations, sub-combinations, and alternatives falling within the spirit and principles of the disclosure are intended to be included in the scope of the disclosure.

Claims

1. A method of processing an integrated circuit layout, characterized by, The method comprises the following steps: acquiring a first integrated circuit layout; wherein the first integrated circuit layout comprises graphics and pin information of the graphics; the first integrated circuit layout has a three-dimensional structure, and the three-dimensional structure comprises graphics located on different drawing layers and graphics composed of graphics located on different drawing layers; spreading the first integrated circuit layout to obtain a second integrated circuit layout and first pin information; wherein the first pin information comprises pin information of all graphics in the first integrated circuit layout; the second integrated circuit layout is a layer structure, and the layer structure comprises graphics located on different drawing layers; screening the first pin information according to pin configuration information to obtain second pin information; wherein the second pin information is used for reservation in the second integrated circuit layout.

2. The method of claim 1, wherein, The method further comprises the following steps: reserving or deleting pin information in the first pin information according to the pin configuration information to obtain second pin information.

3. The method of claim 2, wherein, The method further comprises the following steps: protecting target pin information of the first integrated circuit layout before spreading the first integrated circuit layout; reserving or deleting un-protected pin information in the first pin information according to the pin configuration information to obtain second pin information.

4. The method of claim 1, wherein, The method further comprises the following steps: pre-setting configuration instructions, and pre-setting the pin configuration information based on the configuration instructions; or, receiving a write request, and setting the pin configuration information based on the write request.

5. The method of claim 4, wherein, The method further comprises the following steps: in response to the write request of the pin configuration information, displaying a write interface of the pin configuration information; receiving the pin configuration information through the write interface.

6. The method of claim 5, wherein, The write interface comprises a search box, and the search box is used for searching pin information in a pin information database based on a keyword input into the search box to perform specified reservation or specified deletion; the pin information database comprises the first pin information.

7. The method according to any one of claims 1 to 6, characterized in that, The pin configuration information is used for specifying reservation or specifying deletion of pin information, and the pin information comprises an identifier of a pin, a device to which the pin belongs, and a layer on which the pin is located.

8. The method according to any one of claims 1 to 6, characterized in that, The method further comprises the following steps: merging graphics with the same attribute and intersection into one graphic in the second integrated circuit layout.

9. An apparatus for processing an integrated circuit layout, the apparatus comprising: The method comprises the following steps: a layout acquisition module is configured to acquire a first integrated circuit layout; wherein the first integrated circuit layout comprises graphics and pin information of the graphics; the first integrated circuit layout has a three-dimensional structure, and the three-dimensional structure comprises graphics located on different drawing layers and graphics composed of graphics located on different drawing layers; The layout scattering module is configured to scatter the first integrated circuit layout to obtain a second integrated circuit layout and first pin information, wherein the first pin information comprises pin information of all patterns in the first integrated circuit layout, and the second integrated circuit layout is a layer structure comprising patterns on different drawing layers. The pin screening module is configured to screen the first pin information according to pin configuration information to obtain second pin information, wherein the second pin information is used to be reserved in the second integrated circuit layout.

10. The apparatus of claim 9, wherein, The pin screening module comprises: The pin deleting unit is configured to reserve or delete pin information in the first pin information according to the pin configuration information to obtain second pin information.

11. The apparatus of claim 10, wherein, The device further comprises a pin protection module configured to protect target pin information of the first integrated circuit layout before scattering the first integrated circuit layout. The pin deleting unit is configured to reserve or delete unprotected pin information in the first pin information according to the pin configuration information to obtain second pin information.

12. The apparatus of claim 9, wherein, The device further comprises: A pin configuration information preset module configured to preset a configuration instruction and preset the pin configuration information based on the configuration instruction. Alternatively, a pin configuration information writing module configured to receive a writing request and set the pin configuration information based on the writing request.

13. The apparatus of claim 12, wherein, The pin configuration information writing module comprises: A writing interface display unit configured to display a writing interface of the pin configuration information in response to a writing request of the pin configuration information. A configuration information receiving unit configured to receive the pin configuration information through the writing interface.

14. The apparatus of claim 13, wherein, The writing interface comprises a search box configured to search pin information in a pin information database based on a keyword input into the search box to specify reservation or specified deletion, and the pin information database comprises the first pin information.

15. The apparatus of any one of claims 9 to 14, wherein, The pin configuration information is used to specify reservation or specified deletion of pin information, and the pin information comprises an identifier of a pin, a device to which the pin belongs, and a layer on which the pin is located.

16. The apparatus of any one of claims 9 to 14, wherein, Further comprising: A pattern merging module configured to merge patterns with the same attribute and intersection in the second integrated circuit layout into one pattern.

17. An electronic device, comprising: Comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of any one of claims 1-8.

18. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are executed by the processor to implement the method of any one of claims 1-8.

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