A real-time reconfigurable universal memristor simulation circuit

Abstract

The present invention discloses a real-time reconfigurable universal memristor simulation circuit. The memristor mathematical model is nonlinearly fitted using an m-term polynomial, where m is related to the amplitude and frequency of the input signal and the fitting accuracy. This allows for simple and rapid adaptation to a specified memristor model. Based on this, a system state variable generation module is constructed based on an FPGA for the system state variable, namely, magnetic flux or charge. A calculation module is used to calculate the polynomial coefficients and the system state variable in an m-stage pipeline mode in a reconfigurable manner to obtain a memristor value or a memristor value. A delay FIFO is used to delay the input signal x[n] by 3m clock cycles. An output module is used to multiply the input signal after the FIFO delay of 3m clock cycles by the memristor value or memristor value output by the calculation module to obtain an output signal, namely, a current signal or a voltage signal. By changing the polynomial coefficients, the memristor can be reconfigured in real time, thereby achieving the invention purpose of real-time reconfiguration to adapt to different memristor models. High-operating-frequency memristors can also be simulated. Simultaneously, digital circuits are used for reconstruction simulation, improving experimental accuracy.

Description

Technical Field

[0001] The present invention belongs to the technical field of memristor simulation, and more particularly, relates to a real-time reconfigurable universal memristor simulation circuit. Background Art

[0002] In 1971, Professor Cai Shaotang first proposed a theoretical model of the memristor based on the circuit completeness theorem. He considered the memristor to be the fourth fundamental two-terminal circuit element, in addition to resistors, capacitors, and inductors, describing the nonlinear relationship between charge and magnetic flux. He also identified three fundamental characteristics of the memristor: ① When stimulated by a bipolar periodic electrical signal, the device's curve in the VI plane is a pinched hysteresis loop; ② As the signal scanning frequency increases, the lobes of the pinched hysteresis loop decrease continuously; ③ As the scanning frequency approaches infinity, the pinched hysteresis loop shrinks to a single-valued function.

[0003] It wasn't until 2008, when Stan Williams' team at HP Labs first realized a physical memristor in a nanoscale thin film of titanium dioxide (TiO2), that the properties and applications of memristors garnered significant attention. At this point, Professor Cai Shaotang's memristor was no longer a theoretical mathematical model but a real-world device. Memristor models are now widely applied in fields such as neural networks, machine learning, chaos theory, secure communications, graphic encryption, non-volatile memory, and filter circuits. Unfortunately, the different raw materials used in memristor manufacturing correspond to distinct physical mechanisms, resulting in varying memristive properties. This has limited the widespread application of memristors. For example, researchers have discovered the characteristic phenomenon of pinched hysteresis loops in a variety of materials, including binary oxides, complex perovskite oxides, solid-state electrolytes, amorphous carbon materials, and organic polymers. They have proposed various physical mechanisms to explain their memristive properties, including the formation and fragmentation of conductive channels caused by oxygen vacancy migration, interface barrier modulation, the formation and fragmentation of metallic conductive channels caused by active electrode metallization reactions, the capture and release of injected carriers, and metal-insulator transition mechanisms. On the other hand, due to the high production cost of memristors, commercial memristors are not currently available. For example, the Knowm memristor has been implemented as a commercial component, but its complex structure and high cost have hindered its widespread adoption. Given the complex and diverse physical mechanisms and high production costs of memristors, the design of a real-time, reconfigurable, universal memristor simulation circuit for multiple physical models remains urgent and important, allowing for the analysis of memristor-related properties through experimental exploration.

[0004] Researchers have been conducting extensive research on improving the bandwidth (frequency) of memristor emulation circuits. Analog, hybrid digital-analog, and application-specific integrated circuit (ASIC) methods have been used to construct memristor emulation circuits and conduct verification and bandwidth testing.

[0005] Through extensive theoretical research and professional hardware debugging, simulation methods primarily utilize a variety of passive components (such as resistors, capacitors, and inductors) and active components (such as operational amplifiers, operational transconductance amplifiers (OTAs), current feedback operational amplifiers (CFOAs), differential current converters (DDCCs), and analog multipliers) for breadboard or circuit board experiments. The experimental bandwidth of memristor simulation circuits has increased from 500 Hz in the early days to 1.3 MHz today. Furthermore, memristor simulation circuits utilize positive and negative power supplies. Simulation methods often require redesigning the memristor simulation circuit for different memristor models and bandwidths, requiring significant time and effort for circuit debugging. Especially for memristor input signals in the MHz range, breadboarding is no longer feasible due to the parasitic parameters of the signal transmission lines, impedance matching, and crosstalk between signals that must be addressed. The Lissajous diagram function of the circuit board output signal can be used to display the hysteresis loop. It is worth noting that simulation methods often exhibit significant errors, primarily due to the following sources: The errors of most commercially available resistors, capacitors, and inductors are approximately 5%, 20%, and 20%, respectively. The operational amplifier's input voltage offset (Vos) and input bias current (Ib) can introduce errors into the results. The nonlinear characteristics of the active device's analog bandwidth significantly impact the frequency curves of varying signal amplitudes. Currently, no simulation methods have yet implemented memristor simulation circuits with bandwidths exceeding 10 MHz.

[0006] Because circuit design and debugging require highly specialized circuit knowledge, this is difficult for most researchers engaged in basic research. Therefore, researchers have proposed a hybrid digital-analog approach. This approach typically uses an ADC, a programmable general-purpose processor, and a DAC to implement a memristor simulation circuit. The ADC and DAC are responsible for analog-to-digital quantization of the input signal and digital-to-analog conversion of the output signal, respectively, while the programmable general-purpose processor calculates the memristor or memristor in real time based on the digital model. While the digital-analog approach is simpler and faster to implement than the analog approach, it also has the following limitations. The computational speed of the programmable general-purpose processor, the operating frequency of the ADC and DAC, and the analog bandwidth limit the hybrid approach, making it incapable of simulating memristors operating at high frequencies. Furthermore, the resolution of the ADC, DAC, and digital oscilloscope, as well as the range of the DAC output signal, limit the ability of the hybrid approach to perform high-precision hardware simulation of memristor models.

[0007] For the known memristor model, relevant scholars have proposed a dedicated integrated circuit method. In the literature, UEAyten, S.Minaei, and M. "Memristor emulator circuits using singleCBTA," AEU-Int.J.Electron.Commun., vol.82, pp.109–118, Dec. 2017, doi:10.1016 / j.aeue.2017.08.008, implements a memristor emulation circuit using 23 CMOS transistors with a ±0.9V power supply. A.Yesil, "A new grounded memristor emulator based on MOSFET-C," AEU-Int.J.Electron.Commun., vol.91, pp.143–149, Jul. 2018, doi:10.1016 / j.aeue.2018.05.004, introduces a memristor emulation circuit consisting of only seven MOSFETs and one grounded capacitor. The circuit was laid out using TSMC's Cadence Environment with 0.18μm process parameters. The layout size was only 12μm x 38μm, excluding the capacitor area. The memristor simulation after layout closely matched the theoretical analysis. Clearly, the use of an application-specific integrated circuit (ASIC) approach can significantly reduce the size of the memristor simulation circuit and improve implementation accuracy. However, the duplication of design processes and the high cost of circuit fabrication are major factors hindering the widespread adoption of this approach. The ASIC approach is only applicable to a single known model and is not suitable for studying memristor characteristics under multiple models.

[0008] In general, most existing memristor simulation circuits can only simulate the dynamic behavior of memristors at relatively low frequencies. Specifically, these circuits exhibit a narrowed hysteresis loop below a critical frequency and become linear resistors above that critical frequency. This limits their application in high-speed, high-bandwidth applications, such as high-frequency random signal generation, high-speed data transmission, and high-speed data storage. Secondly, existing memristor simulation circuits are designed for fixed models. Translating theoretical models into actual circuit output requires considerable time and effort from researchers, often requiring engineers with specialized circuit design expertise to participate in hardware debugging. None of the three existing methods achieve real-time dynamic reconfiguration based on the model, making hardware implementation of memristor simulation circuits a time-consuming, inefficient, and tedious process. Finally, inherent component errors, circuit transmission losses, and measurement instrument errors in memristor simulation circuits are crucial for high-precision circuit implementation of theoretical memristor models. However, the experimental accuracy of memristor simulation circuits has not yet received sufficient attention. Summary of the Invention

[0009] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a real-time reconfigurable universal memristor simulation circuit, which can be reconfigured in real time to adapt to memristors of different models and can simulate memristors with high operating frequencies, while improving the experimental accuracy of the memristor simulation circuit.

[0010] To achieve the above-mentioned object, the present invention provides a real-time reconfigurable universal memristor simulation circuit, which is constructed based on FPGA and includes:

[0011] The system state variable generation module includes a multiplier, an accumulator and an adder. The multiplier multiplies the input signal x[n] by the FPGA system clock period Ts to obtain Ts·x[n] and outputs it to the accumulator for accumulation to obtain the accumulated value. And output to the adder to obtain the system state variable h[n]:

[0012]

[0013] h[0] is the initial value of the system state variable, the input signal x[n] is a voltage signal or a current signal, and the system state variable h[n] is the magnetic flux or charge;

[0014] A computing module consisting of m cascaded reconfigurable computing units operating in an m-stage pipeline mode is used to implement m polynomial multiplication and accumulation operations. Each reconfigurable computing unit includes two multipliers, one adder, and one D flip-flop.

[0015] For the i+1th reconfigurable computing unit, i=0,1,2,...,m-1, its inputs are the polynomial coefficient k[i+1], the adder input s[i], the first multiplier inputs are H[i] and d[i], and the outputs are the adder output s[i+1], the multiplier output H[i+1] and the input signal delay d[i+1]. The mathematical relationship between the input and output signals is:

[0016]

[0017] Among them, the first multiplier completes the multiplication of input H[i] and d[i] and outputs H[i+1]. The second multiplier completes the multiplication of the output H[i+1] of the first multiplier and the polynomial coefficient k[i+1]. The adder completes the addition of input s[i] and the output k[i+1]·H[i+1] of the second multiplier and outputs s[i+1]. The D flip-flop delays the input d[i] by one sampling clock to obtain the input signal delay d[i+1].

[0018] For the first reconfigurable computing unit, its input d[i] is the system state variable h[n] output by the system state variable generation module, that is, the magnetic flux or charge at time n, input H[0] = 1, and input s[i] = polynomial coefficient k[0];

[0019] The number of polynomials, i.e., the order m, is determined in the following way:

[0020] According to the amplitude and frequency of the zero DC component AC signal of the input signal x[n], the maximum amplitude a is determined respectively. max and minimum frequency ω min , further determine the value range of the system state variable h[n] is

[0021] exist In the system, the McLaughlin formula is used to fit the memristor or memristor f(h[n]) with an m-order polynomial about the system state variable h[n] to obtain the fitting function g(h(n)), where the maximum fitting error ε M for:

[0022]

[0023] Assume that ε0 is the maximum acceptable fitting error, then the value of the polynomial order m should satisfy ε M ≤ε0;

[0024] Among them, the coefficients k[i], k i , i = 0, 1, 2, ..., m, and the mathematical model of the memristor to be simulated, i.e., the memristor value or memristor value f(h[n]) at time n, is expanded according to the Maclaurin formula:

[0025]

[0026] get;

[0027] The output s[m] of the m-th reconfigurable computing unit is used as the memristor or memristor value f(h[n]) and sent to the output module;

[0028] A FIFO is used to delay the input signal x[n] by m+39 clock cycles and send it to the output module;

[0029] The output module consists of a multiplier. After the input signal x[n] passes through the FIFO delay m+39 clock cycles, it is multiplied by the memristor or memristor value f(h[n]) output by the calculation module to obtain the output signal y[n]. The output signal y[n] is a current signal or a voltage signal.

[0030] The object of the present invention is achieved in this way.

[0031] The present invention discloses a real-time reconfigurable universal memristor simulation circuit. Using Weierstrass's theorem and Maclaurin's formula, the memristor mathematical model is nonlinearly fitted using an m-term polynomial, where m is related to the amplitude and frequency of the input signal and the fitting accuracy. This allows for simple and rapid adaptation to a specified memristor model by updating the polynomial order, coefficients, and sampling interval. Furthermore, a system state variable generation module is constructed based on an FPGA for the system state variable, i.e., magnetic flux or charge. A calculation module is used to reconfigure the polynomial coefficients and the system state variable in an m-stage pipelined manner to obtain a memristor or memristor value. A delay FIFO is used to delay the input signal x[n] by m+39 clock cycles. An output module is used to multiply the input signal, after the FIFO delay of m+39 clock cycles, by the memristor or memristor value output by the calculation module to obtain an output signal, i.e., a current signal or a voltage signal. By changing the polynomial coefficients, the memristor can be reconfigured in real time, thereby achieving the invention's purpose of real-time reconfiguration to adapt to different memristor models. Furthermore, the present invention can simulate high-frequency memristors by using low-frequency signal experiments to verify the memristive properties of high-frequency signals through polynomial coefficient settings. This significant advantage eliminates the need to worry about the analog bandwidth of the simulation circuit when studying memristor properties, making it particularly convenient for researchers who lack professional circuit debugging skills. Furthermore, the present invention is based on an FPGA and uses digital circuits for reconstruction simulation, improving experimental accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 are the different coefficients k of the second-order memristor model iThe qf(q) curve is drawn, where (a) is the coefficient k2≠0, k1≠0, k0≠0, f(q) unipolar, (b) is the coefficient k2≠0, k1≠0, k0≠0, f(q) bipolar, (c) is the coefficient k2≠0, k1=0. f(q) unipolar / bipolar, (d) is the coefficient k2≠0, k1≠0, k0=0, f(q) bipolar, (e) is the coefficient k2=0, k1≠0, k0≠0, f(q) bipolar, (f) is the coefficient k2=0, k1≠0, k0=0, f(q) bipolar;

[0033] Figure 2 This is the approximate variation curve of ω-l;

[0034] Figure 3 The voltage-current characteristic curves of numerical simulation experiment 1 when the coefficient matrix K=K1 are shown, where (a) is the input voltage time-domain waveform, (b) is the output current time-domain waveform, and (c) is the UI curve.

[0035] Figure 4 This is a comparison of the characteristic curves formed by different excitation frequencies and amplitudes in numerical simulation experiment 1, where (a) the input signal amplitude is 1V and (b) the input signal amplitude is 2V:

[0036] Figure 5 This is a comparison of hysteresis curves with different coefficients in numerical simulation experiment 2, where (a) is the coefficient matrix K=K2, (b) is the coefficient k0 magnified 10 times, c) is the coefficient k1 magnified 10 times, and (d) is the coefficient k2 magnified 10 times;

[0037] Figure 6 These are the hysteresis loop diagrams obtained by inputting different amplitude and frequency signals at sampling rates of 100MSa / s and 200GSa / s in numerical simulation experiment 3, wherein (a) is the hysteresis loop diagram of five frequency signals with a sampling rate of 100MSa / s and an amplitude of 0.1V, (b) is the hysteresis loop diagram of five frequency signals with a sampling rate of 100MSa / s and an amplitude of 1V, (c) is the hysteresis loop diagram of five frequency signals with a sampling rate of 100MSa / s and an amplitude of 2V, (d) is the hysteresis loop diagram of five frequency signals with a sampling rate of 200GSa / s and an amplitude of 0.1V, (e) is the hysteresis loop diagram of five frequency signals with a sampling rate of 200MSa / s and an amplitude of 1V, and (f) is the hysteresis loop diagram of five frequency signals with a sampling rate of 200MSa / s and an amplitude of 2V;

[0038] Figure 7 The hysteresis loop diagram based on oversampling, where (a) corresponds to a 500KHz sinusoidal input signal; (b) corresponds to a 1MHz sinusoidal input signal; (c) corresponds to a 2MHz sinusoidal input signal;

[0039] Figure 8 This is the simulation of the active characteristics of the memristor in numerical simulation experiment 4, where (a) is the coefficient matrix K 4.0 The hysteresis loop diagram under the pinching hysteresis, (b) is the coefficient matrix K 4.1 The hysteresis loop diagram under the pinching condition, (c) is the coefficient matrix K 4.2 The hysteresis loop diagram under the pinching hysteresis, (d) is the coefficient matrix K 4.3 The pinch hysteresis loop diagram below;

[0040] Figure 9 This is a comparison chart of the effect of changing the coefficient K on the hysteresis loop area in numerical simulation experiment 5, where (a) is the coefficient matrix K 5.0 The hysteresis loop diagram under the pinching hysteresis, (b) is the coefficient matrix K 5.1 The hysteresis loop diagram under the pinching condition, (c) is the coefficient matrix K 5.2 The hysteresis loop diagram under the pinching hysteresis, (d) is the coefficient matrix K 5.3 The pinch hysteresis loop diagram below;

[0041] Figure 10 The time domain waveforms and comparison diagrams of various parameters at 200GSa / s and 100MSa / s in numerical simulation experiment 6, where (a) corresponds to 200GSa / s, (b) corresponds to 100MSa / s, and (c) is the combination of the two;

[0042] Figure 11 This is a schematic diagram of the principle of a specific implementation of the real-time reconfigurable universal memristor simulation circuit of the present invention;

[0043] Figure 12 yes Figure 11 The schematic diagram of a specific implementation principle of the reconfigurable computing unit shown;

[0044] Figure 13 This is a simulation timing diagram of the real-time reconfigurable universal memristor simulation circuit of the present invention;

[0045] Figure 14 When K=K0, the comparison diagram of the results achieved by Matlab software and the simulation of the present invention is shown, wherein (a) is a comparison diagram of the pinch hysteresis loop, and (b) is a comparison diagram of the local error amplification. DETAILED DESCRIPTION

[0046] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.

[0047] 1. General mathematical model of memristor

[0048] Since Professor Shao-Tang Tsai derived the constitutive relations of memristors based on circuit completeness theory in 1971, many scientists have studied the mathematical model of memristors. In 2008, HP Labs observed memristive behavior in the laboratory, a discovery that advanced the mathematical model of memristors toward physical realization.

[0049] The memristor is essentially a nonlinear dynamic system. A time-invariant x-controlled memristor system is also called a generalized memristor, which is defined as:

[0050]

[0051] Where f(x(t),h) is a continuous bounded function of x(t), y(t) are the input voltage (current) and output current (voltage) signals of the generalized memristor system, respectively. f(h,m,t) represents the memristor value (memristor value), and h is the internal n-dimensional state variable. is the time derivative of the state vector. If x = U(t), then Equation (1) is called a generalized voltage-controlled memristor. If x = I(t), then Equation (1) is called a generalized current-controlled memristor.

[0052] According to Theorem 1, when f(x(t),h) can be expressed as an m-order polynomial function sequence f m When (x(t),h) is uniformly approximated, the generalized memristor model represented by formula (1) can be further expressed as follows.

[0053]

[0054] where K=(k0,k1,...,k i ,...,k m ) is a coefficient matrix, and K≠0. h(x,t) represents the magnetic flux (charge), and h(t0) represents the initial value of the magnetic flux (charge). The parameter α is the amplitude factor of y(t). When x(t) is voltage (or current), formula (2) represents a voltage-controlled memristor (or current-controlled memristor). From the perspective of mathematical models, the two types of memristors are only different in the physical units of the input variable x(t), the output variable y(t) and the system variable h(x,t). Therefore, in order to simplify the expression, the present invention takes the voltage-controlled memristor model as an example for analysis, and fixes α=1.

[0055] Formula (2) is the continuous mode expression of the universal mathematical model of memristor, but the continuous model cannot be directly processed in the universal digital processing circuit. s By quantizing formula (2), the corresponding memristor discrete model is obtained as follows:

[0056]

[0057] Among them, T s is the step time, n is the moment, and is also the length of the digital integration window. In order to express it in a consistent manner, k i Re-denoted as k[i], the other variables are the same as in formula (1). According to the definition of Riemann Integral, the discrete mathematical model of the third expression in formula (2) is the third expression in formula (3).

[0058] The definition of Riemann integral is: function f(x) is defined in the closed interval [a, b], insert n-1 points in the interval [a, b] to divide it into n small intervals [x i-1 ,x i ], i=1,2,3,...,n, any point ξ i ∈[x i-1 ,x i ], and the formula is:

[0059]

[0060] Let λ be the maximum length of all small intervals, that is, λ=max{Δx1,Δx2,...,Δx n When the segmentation becomes smaller and smaller, that is, λ→0, n→+∞, each small strip after segmentation can be regarded as a rectangle, considering the formula:

[0061]

[0062] If the value of the above formula exists, and this limit does not depend on the partition of the interval [a,b], nor on the point ξ i The limit is called the definite integral of f(x) on the interval [a,b], which is written as:

[0063]

[0064] In practical engineering applications, an analog-to-digital converter (ADC) is used to sample the adc (1 / f adc =T s ) is driven by the uniform quantization of the continuous input signal x(t). When the sampling clock f adc The higher the frequency, the more uniform the time interval T s The smaller it is. That is, the division step in the Riemann integral is getting finer. Assume that the FPGA system working clock is f FPGA When formula (3) is implemented in FPGA, if f FPGA ≥f adc, at this time, the real-time calculation of the memristor model can be realized in FPGA. FPGA <f adc When ADC is used, internal storage resources of FPGA such as FIFO or external memory such as DDR3 can be used to cache ADC quantized data first, and then implement the memristor model in hardware. According to Nyquist sampling theorem, f adc ≥2f in Therefore, the higher the ADC sampling rate, the larger the bandwidth of the input signal, and the larger the real-time data processing bandwidth in the FPGA.

[0065] 2. Universality of the universal mathematical model of memristors

[0066] Weierstrass approximation theorem: Let f(x) be a continuous function on [a, b], then there exists a polynomial function sequence {f n (x)}, so that {f n (x)} uniformly converges to f(x). The proof is as follows:

[0067] According to the definition of Bernstein polynomial, on [0,1], the error function satisfies:

[0068]

[0069] Since f(x)∈C[0,1], f(x) is bounded and uniformly continuous on [0,1]. Suppose there exists a positive number M such that |f(x)| < M on [0,1]. Therefore:

[0070]

[0071] Since f(x) is uniformly continuous on [0,1], for any ε>0, there exists δ(ε)>0, so that hour,

[0072]

[0073] Split formula (7) into two parts:

[0074]

[0075] According to the uniform continuity formula (9), we can get:

[0076]

[0077] Then using the uniform boundedness formula (8), when hour,

[0078]

[0079] Therefore, when n satisfies When , according to formula (10)-(12), we can get

[0080]

[0081] This proves Weierstrass's first theorem.

[0082] Taylor's formula can locally approximate the complex function f(x) as the sum of n-degree polynomial functions. The ability of Taylor's formula to simplify things makes it a powerful tool for analyzing and studying many mathematical problems.

[0083] Taylor's formula: If a function f(x) has an (n+1)th-order derivative on an open interval (a, b) containing x0, then for any x∈(a, b), we have:

[0084]

[0085] in It is called the nth-order Taylor polynomial, and the error term It is called the nth-order Taylor remainder, and ε is a value between x and x0.

[0086] If the n+1 derivative of the function f(x) is bounded M on N(x0), then:

[0087]

[0088] Indicates R n (x) = o((x-x0) n ), and it can also be proved that for a fixed x, when n→∞, R n (x)→0, that is, to make f(x) and P n (x) The error is reduced, then |x-x0| can be made smaller, or n can be made larger. In the nth-order Taylor formula, if x0 = 0, we can get:

[0089]

[0090] This formula is called the nth-order Taylor formula of the function f(x) at x=0, also known as the nth-order Maclaurin formula of f(x). The remaining terms are often written as o(x n )or There are two forms. The remainder expressed by n+1 order derivative is called Lagrange remainder, and the remainder is expressed by o(x n ) or o((x-x0) n ) is called the Peano remainder.

[0091] In the proposed memristor model, the amplitude a and frequency ω of the input signal are known, so the range of h(t) is fixed and bounded. Combined with Weierstrass's first theorem, f(h(t)) can be fitted with a polynomial. Taylor's formula and Maclaurin's formula give the specific implementation method of the m-order polynomial. The larger the value of the parameter m, the higher the approximation accuracy of f(h(t)), and the higher the computational complexity of f(h(t)). Therefore, when implementing in a general-purpose processor such as FPGA, it is necessary to balance the three aspects of accuracy, speed and logic resources. For the discrete memristor model, formula (3) can be used for approximation. For example, when a<<ω, the values ​​of the coefficient matrix K when using Maclaurin's formula to approximate common functions are shown in Table 1. As can be seen from Table 1, by configuring the unused coefficient matrix K={k i} can realize the polynomial approximation of the mathematical model of common function memristor.

[0092]

[0093]

[0094] Table 1

[0095] The proposed memristor model also shows good versatility compared to existing models in the literature. For example, the memristor model discovered by the HP team in 2008 is shown in formula (17).

[0096]

[0097] Where D is the thickness of the titanium dioxide film and w(t) is the thickness of the doped layer. By applying an external voltage, w(t) also changes, R on and R off The minimum value (w(t) = D) and the maximum value (w(t) = 0) of the memristor resistance should be divided. off , k1=(R on -R off ) / D, and m = 1, the proposed memristor model is the classic HP memristor model. Similarly, the coefficient matrix K and the polynomial coefficient m are configured separately. The universality of other existing models is shown in Table 2. The memristor model is compatible with existing models.

[0098]

[0099]

[0100] Table 2

[0101] 3. Universality of the memristor model of the present invention for active or passive memristors

[0102] In formula (1-2), the polarity of f(h(t)) is related to the coefficient matrix K and the value of h(t). To further illustrate the influence of various parameters on the qf(q) curve, we select a charge-controlled memristor model with m = 2 for detailed analysis, where q represents the magnetic flux. When m = 2, the mathematical expression for f(q) is:

[0103]

[0104] The coefficients k1 and k2 cannot be zero at the same time, otherwise the memristor will become a linear time-invariant resistor. Depending on the values ​​of k0, k1 and k2, the qf(q) curve has the following characteristics: Figure 1 The 24 graphics shown. Figure 1 As can be seen from the figure, the curve qf(q) can appear above, below, or intersect the horizontal axis.

[0105] If a memristor's pinch hysteresis loop is distributed only in the first and third quadrants under the action of any periodic signal with zero DC component, we call it passive. Otherwise, it is called active. The pinch hysteresis loop of an active memristor can pass through zero. Because when the pinch hysteresis loop falls in the second or fourth quadrant of the volt-ampere plane, or the fourth quadrant, x(t)y(t)≤0, the active memristor behaves like an energy source. In formula (2), the polarity of the independent variables f(q) and x(t) on the right side of the equal sign determines the polarity of the dependent variable y(t) on the left side of the equal sign. When a bipolar signal x(t) with zero DC component is input, the loop on the UI plane has three cases as shown in Table 3. First, if f(q) is positive, the loop on the UI plane passes through the first and third quadrants, and the proposed memristor is a passive memristor. Second, if f(q) is negative, the loop of the UI plane passes through quadrants 2 and 4, making the proposed memristor an active memristor. Third, if f(q) is bipolar, the loop of the UI plane passes through all quadrants, making the proposed memristor a partially active memristor. Figure 1 The memristor models corresponding to curves (1), (2), (11) and curves (3), (4), (14) belong to passive memristors and active memristors respectively. The memristor models corresponding to the other curves are all local active memristor models.

[0106]

[0107] Table 3

[0108] 4. Analysis of the nonlinear characteristics of the memristor model of the present invention

[0109] To verify the input signal bandwidth of the improved memristor mathematical model in formula (2), we use a cosine signal as input for theoretical bandwidth analysis. Assume the input signal is x(t) = acos(ωt), where a is the amplitude of the input signal and ω is the angular frequency of the input signal. Assume that the time when the signal starts to excite the system is t0, and also assume that x(t0) = 0 and h(t0) = 0. The mathematical model of h(t) is as follows:

[0110]

[0111] Among them, there are because So we can easily calculate

[0112]

[0113] Substituting formula (19) into formula (2), the expression of memristor h(t) is as follows:

[0114]

[0115] Substituting formula (20) into the first expression of formula (2), we can get the input and output signal expressions of the memristor as follows:

[0116]

[0117] In formula (22), it consists of the linear term y1(t) and the nonlinear term y2(t) with respect to x(t). Where y1(t) = k0x(t),

[0118] When k0 ≠ 0, in formula (22), as the input signal angular frequency ω decreases, the value of y2(t) gradually increases. At this point, the value of y(t) is primarily determined by the nonlinear term y2(t). Conversely, as the input signal frequency ω increases, the value of y2(t) gradually decreases to zero. At this point, the value of y(t) is primarily determined by the linear term y1(t), and y1(t) can be approximately understood as a standard linear device. For example, when the input is a voltage signal, y(t) is a standard admittance model.

[0119] Considering the actual application scenario, it is much easier to generate a higher frequency signal than to generate a higher signal amplitude. For example, a common signal source can generate a sinusoidal signal with a frequency ω as high as GHz, while the amplitude a is usually only tens of V. Therefore, in formula (19), 0≤|h(t)|<1. Function (|h(t)|0 m(m≥1) is a decreasing function of the power exponent m, so changing the absolute value of the coefficient k0 will maximize the change in f(h(t)). At the same time, when n≥1, there is also max{(|h(t)|) m}≤|h(t)|. In the coefficients k1 to k m Of the m coefficients, adjusting coefficient k1 maximizes the change in f(h(t)). In other words, in order to quickly increase or decrease the nonlinear characteristics of y2(t), in practical engineering applications, we should adjust the change in coefficient k0 or k1. Changing the other coefficients by the same amount is less likely to change the shape or area of ​​the hysteresis curve.

[0120] According to De Moivres theorem, the descending power formula holds true. When m is an even number, we have:

[0121]

[0122] When m is an odd number, we have:

[0123]

[0124] Combined with the product and difference formula of trigonometric functions:

[0125]

[0126] According to formula (23)-formula (25), the following expression is established in formula (22). When m is an even number, we have:

[0127]

[0128] When m is an odd number, we have:

[0129]

[0130] According to formula (26) and formula (27), when the input is a single-frequency signal x(t) = acos(ωt), the output signal y(t) is the sum of the fundamental wave of the input signal and each harmonic. The amplitude of the fundamental wave is ak0 / ω, and the amplitude of each harmonic is also affected by the polynomial coefficient k i (i=1,...,m), the influence of m and a / ω.

[0131] set up Then we have:

[0132]

[0133] The approximate change curve of ω-l is as follows Figure 2As shown in the figure, we can see that as the signal angular frequency ω increases from 0 to infinity, the value of l decreases, and the mathematical model of formula (2) also changes from a nonlinear model to a linear model. In other words, the proposed memristor model gradually changes from a nonlinear memristor (memconductor) model to a linear resistor model as the angular frequency ω increases. Assuming that when the ratio l is less than or equal to the threshold δ, that is, 0<l≤δ, the improved memristor has become a resistor device. The value of δ can be selected according to the actual application to meet the accuracy requirements of the system.

[0134] exist Figure 2 In the example, we set l = δ to the input signal angular frequency ω. max It is called the maximum theoretical bandwidth of the memristor. Therefore, in order to realize the hysteresis loop characteristics of the memristor, the parameter setting must meet the constraints in formula (29).

[0135]

[0136] Formula (29) improves the memory characteristics of the improved memristor model in the following ways: First, when the absolute value of k0 decreases, k i With the increase of the absolute value of (i>0), the increase of the degree m of the polynomial, the increase of the input sinusoidal signal amplitude a or the decrease of the angular frequency ω, formula (2) is more likely to satisfy the nonlinear characteristics of the memristor. Secondly, when the input sinusoidal signal angular frequency ω is known, in order to make the mathematical model of formula (2) show the characteristics of the memristor, we can increase the input signal amplitude a and increase k i (i>0) absolute value or reduced absolute value of k0.

[0137] 4. Universality of the proposed memristor model for broadband signals

[0138] According to the digital sampling principle, we have:

[0139]

[0140] where f i and f sap are the signal frequency and the sampling frequency respectively. iL and high frequency signal f iH Use sampling rate f sL and f sH ADC is quantized and the constraints are met:

[0141]

[0142] Then there is a low sampling rate quantized sequence x L [n] and high sampling rate quantized sequence x H [n] satisfies the following relationship:

[0143] x L [n] = x H [n]. (32)

[0144] Assume that the coefficient matrices corresponding to the two cases are K L and K H If the coefficient matrix K L and K H If the constraint condition (i∈[0,m]) of formula (33) is satisfied, the hysteresis loop curves formed by low-frequency sampling quantization and high-frequency sampling quantization are exactly the same. The proof is as follows:

[0145] k iL =r i ·k iH (33)

[0146] Proof: Let r·f iL =f iH , then r -1 ·T sL =T sH Where T sL and T sH They are f sL and f sH The corresponding sampling period. According to formula (3):

[0147] h L [n] = r·h H [n] (34)

[0148] where h L [n] and h H [n] are respectively f sL and f sH The corresponding magnetic flux. Further expansion of formula (3) is:

[0149] f L (h,m,n)=k 0L +k 1L ·h L [n]+...+k iL ·(h L [n]) i +k mL ·(h L [n]) m (35)

[0150] and

[0151] f H (h,m,n)=k 0H +k 1H ·h H [n]+...+kiH ·(h H [n]) i +k mH ·(h H [n]) m (36)

[0152] Substitute formulas (33)-(34) into formula (35):

[0153]

[0154] The right sides of the equal signs of formula (36) and formula (37) are equal, so we have:

[0155] f L (h L [n])=f H (h H [n]) (38)

[0156] Furthermore, according to formula (3):

[0157] y L [n]=y H [n] (4)

[0158] Therefore, according to formula (32) and formula (39), the hysteresis loop curves formed by low-frequency sampling quantization and high-frequency sampling quantization are exactly the same. Proof completed!

[0159] According to the above conclusion, if OSR=20, then the input signal f iH =10GHz and sampling rate f sH =200GSPS formed hysteresis loop curve, and the input signal f iL =5MHz and sampling rate f sL =100MSPS, the hysteresis loop curve is exactly the same. By configuring the polynomial coefficient K of the proposed memristor model, the high-frequency, high-sampling-rate mathematical model can be transferred to low-frequency, low-sampling-rate processing and hardware verification. This is of great significance for the engineering promotion and application of memristor models. The main reasons are as follows: First, GHz analog signals belong to the microwave high-frequency range. At this time, parasitic parameters in the circuit have a significant impact on the analog bandwidth and transmission of the signal circuit. The design and debugging of analog circuits are also very difficult. Unless a professional company with a rich background can complete the hardware platform implementation, most scientists engaged in theoretical research cannot conduct hardware verification in the laboratory. Second, there are currently no commercial single-chip ADCs with sampling rates reaching hundreds of GHz. Third, the rapid increase in data bandwidth caused by high sampling rates makes it difficult for back-end data processing FPGAs to achieve real-time computing. For example, an 8-bit 200GSPS sampling rate has a real-time data bandwidth of up to 200GSa / s, which is beyond the reach of existing commercial FPGAs.

[0160] 5. Improved numerical simulation of memristor model

[0161] First, Matlab was used to perform numerical simulations of the proposed universal mathematical model for memristors to verify its correctness. We designed six numerical simulation experiments, and the parameters and experimental results for each experiment are shown below.

[0162] Numerical simulation experiment 1

[0163] We set the polynomial coefficient matrix K1 = (-0.4, 4e6, -1500, -1.25e-6, -3.125e-9), m = 5, T s =10ns. Consider the cosine excitation voltage signal amplitude a = 1V and frequency f i =2MHz, the obtained time domain waveform curve is as follows Figure 3 shown. Figure 3 (a) and (b) show the time domain waveforms of the input voltage x(t) and output current y(t), respectively. Figure 3 (c) Describes the characteristic curve of the improved memristor on the UI plane, showing a typical pinch hysteresis loop.

[0164] The amplitude (1V and 2V) and frequency (1MHz, 2MHz, 2.5MHz, 5MHz and 10MHz) of the cosine signal are changed again. When the sampling rate is fixed at 100MSa / s, the simulation results are as follows: Figure 4 shown. Figure 4 (a) and Figure 4 (b) shows the comparison of the characteristic curves of different frequencies when the input signal amplitude is 1V and 2V. It is obvious that as the excitation frequency increases, the area of ​​the hysteresis loop decreases monotonically, and the slope of the hysteresis loop also gradually decreases, becoming more and more like a straight line. However, the curve of the UI plane is always fixed through the coordinate origin and tightens at the origin. In addition, from Figure 4 It can also be seen that: First, when the input signal amplitude remains unchanged, the area of ​​the hysteresis loop decreases as the frequency increases. Second, when the input signal frequency remains unchanged, the area of ​​the pinch hysteresis loop increases as the amplitude increases. Therefore, increasing (decreasing) the input signal amplitude or decreasing (increasing) the input signal frequency can quickly increase (decrease) the area of ​​the pinch hysteresis loop. In summary, the memristor model described in formula (2) can present the basic characteristics used to identify memristors.

[0165] Numerical simulation experiment 2

[0166] According to formula (29), the coefficient k in formula (2) iIt is related to the hysteresis loop and operating frequency bandwidth of the proposed memristor model. First, set the sinusoidal excitation voltage a=1V and f i =5MHz, when the coefficient matrix K2 = (1,5e6,5e6,5e6,7,100,500,0,-10,0,1), the hysteresis curve of the UI plane is drawn as follows Figure 5 (a). Then, k0, k1 and k2 are enlarged by 10 times respectively, and the hysteresis curves are drawn as follows Figure 5 (b)-(d) are shown. Figure 5 As can be seen in the figure, increasing k0 reduces the hysteresis loop to a linear function, with the linear portion of the memristor predominantly occupying a larger proportion. Increasing k1 increases the area of ​​the hysteresis loop, with the nonlinear portion of the memristor predominantly occupying a larger proportion. Increasing k2, however, leaves the hysteresis loop area virtually unchanged. This is consistent with the theoretical calculations in Section 2.

[0167] Numerical simulation experiment 3

[0168] Set the coefficient matrices to:

[0169] K 3.0 =(-0.4,4*10^6,-1500,-1.26*10^-6,-20,0,0,0,0,0,0)

[0170] K 3.1 =(-0.40,8.0*10^9,-6*10^9,-10^4,-5*10^4,508,-1.25*10^5,-6*10^7,10^4,0,-200)

[0171] The sampling rates are 100MSa / s and 200GGSa / s, and the input signal amplitudes are 0.1V, 1V, and 2V, totaling 3 groups. When the sampling frequencies are 100MSa / s and 200GSa / s, the frequencies of the simulated signals are 1MHz, 2MHz, 2.5MHz, 50MHz, 10MHz and 2GHz, 4GHz, 5GHz, 10GHz, and 20GHz, respectively. The simulation results are as follows: Figure 6 As shown in the figure, the simulation results show that when the input signal amplitude remains constant, the area of ​​the pinch hysteresis loop decreases as the frequency increases. When the input signal frequency remains constant, the area of ​​the pinch hysteresis loop increases as the amplitude increases. Therefore, increasing (decreasing) the input signal amplitude or decreasing (increasing) the input signal frequency simultaneously can quickly increase (decrease) the area of ​​the pinch hysteresis loop.

[0172] Keep the coefficient matrix K = K 2.0The hysteresis loops obtained when the sinusoidal input signals with frequencies of 500KHz, 1MHz, and 2MHz are at 10MSa / s, 20MSa / s, and 50MSa / s are as follows: Figure 7 As shown. The pinch hysteresis loop is actually realized by fitting multiple straight line segments. The more piecewise linear functions there are, the smoother the curve will be. For example, when the oversampling rate is 10 (20), one signal cycle can quantize 10 (20) discrete data. The obtained pinch hysteresis loop consists of 9 (19) straight line segments. The 9 (19) straight line segments can also be composed of a combination of 9 (19) piecewise linear functions. Compared with the discrete mathematical model and the continuous mathematical model methods, the piecewise linear function fitting method based on the Nyquist sampling theorem proposed in the present invention is simpler to implement, and the drawing of the pinch hysteresis loop can be achieved by only setting an appropriate oversampling rate. Figure 6 The curve in can also prove the above conclusion.

[0173] Numerical simulation experiment 4

[0174] The purpose of this experiment is to set appropriate parameters so that the proposed memristor model can show rich local active characteristics. The amplitude of the excitation sinusoidal voltage signal is 1V and the frequency is 10Hz. The parameters of the matrix K are set to K 4.0 =(0.9,-25,50),K 4.1 =(0.9,-35,50),K 4.2 =(-0.9,25,50) and K 4.3 =(-0.9,35,50). The hysteresis loops drawn in sequence are as follows Figure 8 (a)- Figure 8 (d). Figure 8 (a)-(b)( Figure 8 (c)-(d)) It can be seen that increasing the absolute value of the coefficient k1 switches the memristor from a passive (active) memristor to a partially active memristor. At the same time, the area of ​​the hysteresis loop also increases. Figure 8 (a) and Figure 8 (c) Changing the polarity of coefficient k0 enables switching from a passive memristor to an active memristor. In summary, changing the polarity and absolute value of the coefficient matrix K in formula (3) can easily and quickly enrich the local active characteristics of the memristor. This proves the correctness of the theoretical analysis in Section 3.

[0175] Numerical simulation experiment 5

[0176] The simulation parameters are as follows: m = 10, T s =1us, the amplitude and frequency of the input signal are 0.1V and 20KHz respectively, which are set as:

[0177] K 5.0=(10,10^5,10^5,10^5,7,100,500,0,-10^10,0,0)

[0178] K 5.1 =(10,10^6,10^5,10^5,7,100,500,0,-10^10,0,0)

[0179] K 5.2 =(10,10^5,10^6,10^5,7,100,500,0,-10^10,0,0)

[0180] K 5.3 =(10,10^5,10^5,10^6,7,100,500,0,-10^10,0,0).

[0181] and coefficient K 5.0 Compared with (such as Figure 9 (a)), the coefficient K 5.1 , K 5.2 and K 5.3 In the example, the hysteresis loops obtained by increasing k1, k2 and k3 by 10 times are as follows: Figure 9 (b), (c), and (d). Figure 9 In (a)-(d), we can clearly see that increasing the value of coefficient k1 can increase the area of ​​the pinch hysteresis loop. However, changing the coefficients k2 and k3 of the same order of magnitude has almost no effect on the area of ​​the pinch hysteresis loop, which also proves the correctness of the previous theoretical analysis.

[0182] Numerical simulation experiment 6

[0183] The simulation parameters are as follows: m=10.

[0184] The high sampling rate parameter configuration is as follows: f sH =200GSa / s, T sH =5ps, f iH =20GHz, a=1v, K 5.0 =(-0.4,8.0*10^9,-6*10^9,-10^4,-5*10^4,508,-1.25*10^5,-6*10^7,10^4,0,-200).

[0185] The low sampling rate parameter configuration is as follows: f sL =100MSa / s, T sL =10ns, f iL =1MHz, a=1v, K 5.1=(-0.4,8,-6*10^-9,-10^-23,-4*10^-5,5.08*10^-43,-1.25*10^-49,-6*10^-56,10^-68,0,-2*10^-88).

[0186] The simulated magnetic flux, memristance, hysteresis loop, input voltage and output current time domain waveforms are as follows: Figure 10 As shown. Figure 10 As we can see, all simulation data are the same except for the magnetic flux. Therefore, when the coefficient matrix K satisfies the proportional relationship of formula (33) and the oversampling ratio satisfies the proportional relationship of formula (31), the pinched hysteresis loop formed by the high-frequency signal is exactly the same as the pinched hysteresis loop formed by the low-frequency signal.

[0187] Through the numerical simulation experiments described above, we can see that the universal mathematical model of the memristor proposed in this invention can display an excellent shrinking hysteresis loop. Notably, by varying the coefficient K, the improved memristor can display shrinking hysteresis loops and appear anywhere in the coordinate region, even at higher excitation frequencies.

[0188] Figure 11 It is a schematic diagram of the principle of a specific implementation of the real-time reconfigurable universal memristor simulation circuit of the present invention.

[0189] In this embodiment, if Figure 11 As shown, the real-time reconfigurable universal memristor simulation circuit of the present invention is constructed based on FPGA, and includes a system state variable generation module 1, a calculation module 2, a FIFO 3 and an output module 4.

[0190] The system state variable generation module 1 includes a multiplier 101, an accumulator 102 and an adder 103. The multiplier 101 multiplies the input signal x[n] by the FPGA system clock period Ts to obtain Ts·x[n] and outputs it to the accumulator 102 for accumulation to obtain the accumulated value. And output to adder 103 to obtain system state variable h[n]:

[0191]

[0192] h[0] is the initial value of the system state variable, the input signal x[n] is a voltage signal or a current signal, and the system state variable h[n] is the magnetic flux or charge.

[0193] In this embodiment, a 48-bit adder is used to construct an accumulator for implementing the cumulative summation of the input signal x[n].

[0194] The computing module 2, which is composed of m cascaded reconfigurable computing units working in an m-stage pipeline mode, is used to implement m polynomial multiplication and accumulation operations, such as Figure 11 As shown, each reconfigurable computing unit includes two multipliers 2011 2012 , one adder 202 and one D flip-flop 203 .

[0195] like Figure 12 As shown, for the i+1th reconfigurable computing unit, i=0, 1, 2, ..., m-1, its input is the polynomial coefficient k[i+1], the adder 202 input is s[i], the first multiplier 2011 input is H[i] and d[i], and the output is the adder 202 output s[i+1], the second multiplier 2012 output H[i+1] and the input signal delay d[i+1]. The mathematical relationship between the input signal and the output signal is:

[0196]

[0197] Among them, the first multiplier 2011 completes the multiplication of input H[i] and d[i] and outputs H[i+1], the second multiplier 2012 completes the multiplication of the output H[i+1] of the first multiplier 2011 and the polynomial coefficient k[i+1], the adder 202 completes the addition of input s[i] and the output k[i+1]·H[i+1] of the second multiplier 2012 and outputs s[i+1], and the D flip-flop 203 delays the input d[i] by one sampling clock to obtain the input signal delay d[i+1].

[0198] For the first reconfigurable computing unit, its input d[i] is the system state variable h[n] output by the system state variable generation module, that is, the magnetic flux or charge at time n, input H[0] = 1, and input s[i] = polynomial coefficient k[0];

[0199] The number of polynomials, i.e., the order m, is determined in the following way:

[0200] According to the amplitude and frequency of the zero DC component AC signal of the input signal x[n], the maximum amplitude a is determined respectively. max and minimum frequency ω min , further determine the value range of the system state variable h[n] is

[0201] exist In the system, the McLaughlin formula is used to fit the memristor or memristor f(h[n]) with an m-order polynomial about the system state variable h[n] to obtain the fitting function g(h(n)), where the maximum fitting error ε M for:

[0202]

[0203] Assume that ε0 is the maximum acceptable fitting error, then the value of the polynomial order m should satisfy ε M ≤ε0.

[0204] Among them, the coefficients k[i], k i , i = 0, 1, 2, ..., m, and the mathematical model of the memristor to be simulated, i.e., the memristor value or memristor value f(h[n]) at time n, is expanded according to the Maclaurin formula:

[0205]

[0206] get.

[0207] The output s[m] of the m-th reconfigurable computing unit is used as the memristor or memristor f(h[n]) and sent to the output module.

[0208] FIFO3 is used to delay the input signal x[n] by 3m clock cycles and send it to the output module 4.

[0209] The output module 4 is composed of a multiplier. The input signal x[n] is delayed by 3m clock cycles in the FIFO and then multiplied by the memristor or memristor value f(h[n]) output by the calculation module to obtain the output signal y[n]. The output signal y[n] is a current signal or a voltage signal.

[0210] Functional simulation

[0211] In order to fully evaluate the performance of the proposed memristor model based on FPGA, i.e., the present invention, we conducted functional simulation experiments and compared them with existing methods.

[0212] Verilog hardware programming language, software development environment Vivado 2020.1, and functional simulation software Xsim are used for hardware functional simulation of the proposed memristor model.

[0213] First, Matlab software is used to generate a 14-bit signed digital discrete sine signal with a total of 4096 points. At the same time, the waveform sending module based on the DDS principle is implemented in the FPGA. f (The step value of the waveform ROM read address) can output a sine wave with adjustable frequency.

[0214] The coefficient matrix is:

[0215] K 1.0 =(0.4,-3.0*10^6,4.5*10^8,-10^2,1.5*10^6,50.8,-125,6,100,10,-200).

[0216] Sampling interval T s = 10ns. The FPGA simulation output data is in double-precision floating-point format to facilitate the analysis of hardware and software simulation results. The hardware simulation timing diagram is as follows: Figure 13 As shown, Figure 13 In the figure, clk, rst_n, and ce represent the 100MHz system clock, the active-low reset signal, and the module enable signal, respectively. The data dfx and dfy represent the input voltage and output current of the memristor module, respectively. A high dfx_valid (dyx_valid) indicates the output data dfx (dfy). In the figure, dfx_valid and dyx_valid are consistently high, demonstrating that the proposed memristor module can implement real-time computing in an FPGA at a speed of 12.8 Gbps.

[0217] The double-precision floating-point data output by FPGA hardware simulation is imported into Matlab, and the hysteresis loop obtained by Matlab software simulation is as follows: Figure 14 As shown in (a). As can be seen from the figure, a hysteresis loop curve consists of 40 sampling rates, that is, the oversampling factor is 40. The error local amplification of the two implementation methods is as follows Figure 14 As shown in (b), the FPGA only takes 400ns to complete one cycle of data calculation.

[0218] Next, we linearized a 10th-order nonlinear polynomial in an FPGA to conduct a fast reconfiguration experiment on six memristor models proposed in existing literature. The input parameters of the six memristor models and the frequency and amplitude of the input bipolar sinusoidal signal (fixed at 1V) are shown in Table 4.

[0219] We simulated existing memristor models in an FPGA. Each model was fed a bipolar 1V sinusoidal signal. With m fixed at 10, the polynomial coefficients, sampling rate, and input signal frequency were configured as shown in Table 4. The resulting output signal amplitude and FPGA simulation time are shown in Table 4. Table 4 shows that the output amplitude of the proposed real-time reconfigurable memristor model is dependent on the input parameters.

[0220]

[0221]

[0222] Table 4

[0223] Table 4 summarizes the time required for a single FPGA hardware implementation to compute different memristor models and input signal frequencies (ignoring the fixed delay of 390 ns). Matlab simulates the data processing flow within the FPGA, specifically converting fixed-point numbers to single-precision floating-point numbers and using single-precision floating-point numbers to calculate magnetic flux and memristance. The time required to process the same amount of data using the FPGA is shown in Table 4. As can be seen from Table 4, the real-time reconfigurable universal memristor simulation circuit of the present invention can not only simulate various existing memristor models, but also significantly reduce the computation time compared to Matlab software simulation.

[0224] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.

Claims

1. A real-time reconfigurable universal memristor simulation circuit, characterized in that: Built on FPGA, including: The system state variable generation module includes a multiplier, an accumulator and an adder. The multiplier multiplies the input signal x[n] by the FPGA system clock period Ts to obtain Ts·x[n] and outputs it to the accumulator for accumulation to obtain the accumulated value. And output to the adder to obtain the system state variable h[n]: h[0] is the initial value of the system state variable, the input signal x[n] is a voltage signal or a current signal, and the system state variable h[n] is the magnetic flux or charge; A computing module consisting of m cascaded reconfigurable computing units operating in an m-stage pipeline mode is used to implement m polynomial multiplication and accumulation operations. Each reconfigurable computing unit includes two multipliers, one adder, and one D flip-flop. For the i+1th reconfigurable computing unit, i=0, 1, 2, ..., m-1, its inputs are the polynomial coefficient k[i+1], the adder input s[i], the first multiplier inputs are H[i] and d[i], and the outputs are the adder output s[i+1], the multiplier output H[i+1] and the input signal delay d[i+1]. The mathematical relationship between the input and output signals is: Among them, the first multiplier completes the multiplication of input H[i] and d[i] and outputs H[i+1]. The second multiplier completes the multiplication of the output H[i+1] of the first multiplier and the polynomial coefficient k[i+1]. The adder completes the addition of input s[i] and the output k[i+1]·H[i+1] of the second multiplier and outputs s[i+1]. The D flip-flop delays the input d[i] by one sampling clock to obtain the input signal delay d[i+1]. For the first reconfigurable computing unit, its input d[i] is the system state variable h[n] output by the system state variable generation module, that is, the magnetic flux or charge at time n, input H[0] = 1, and input s[i] = polynomial coefficient k[0]; The number of polynomials, i.e., the order m, is determined in the following way: According to the amplitude and frequency of the zero DC component AC signal of the input signal x[n], the maximum amplitude a is determined respectively. max and minimum frequency ω min , further determine the value range of the system state variable h[n] is exist In the system, the McLaughlin formula is used to fit the memristor or memristor f(h[n]) with an m-order polynomial about the system state variable h[n] to obtain the fitting function g(h(n)), where the maximum fitting error ε M for: Assume that ε0 is the maximum acceptable fitting error, then the value of the polynomial order m should satisfy ε M ≤ε0; Among them, the coefficients k[i], k i , i = 0, 1, 2, ..., m, the mathematical model of the memristor to be simulated, i.e. the memristor value or memristor value f(h[n]) at time n, is expanded according to the Maclaurin formula: get; The output s[m] of the m-th reconfigurable computing unit is used as the memristor or memristor f(h[n]) and sent to the output module; A FIFO is used to delay the input signal x[n] by m+39 clock cycles and send it to the output module; The output module consists of a multiplier. After the input signal x[n] passes through the FIFO delay m+39 clock cycles, it is multiplied by the memristor or memristor value f(h[n]) output by the calculation module to obtain the output signal y[n]. The output signal y[n] is a current signal or a voltage signal.

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