Method of performing operations on a memory device

Abstract

A method of performing an operation on a memory device is disclosed. The method of performing an operation on a memory device includes the following steps. An erasing operation is performed on a selected word line of the memory device to lower threshold voltages of a plurality of first memory cells to be programmed and a plurality of second memory cells to be erased below a first predetermined level. A programming operation of a checkerboard pattern is performed on the selected word line such that the first memory cells are subjected to a first programming bias and the second memory cells are subjected to a second programming bias. The second programming bias is lower than the first programming bias.

Description

TECHNICAL FIELD

[0001] The present application relates to a method of performing an operation, and more particularly to a method of performing an operation on a memory device. BACKGROUND

[0002] With the development of memory technology, flash memory has been widely used in various electronic devices. Flash memory is a type of non-volatile memory which can be erased and programmed.

[0003] Generally, the programming unit of flash memory is, for example, a page of 256 Bytes, which is much smaller than the erase unit of flash memory, such as a block of 4K Bytes. The erase time is usually quite long, such as 25 milliseconds (ms). Therefore, in order to write to a page, the erase time of 25 ms or more must be waited before programming can be performed. This phenomenon causes a write delay. SUMMARY

[0004] The present application relates to a method of performing an operation on a memory device, in which only one page needs to be erased during in-place write operation on the memory device, and the same page can be directly programmed. In this process, the entire block does not need to be erased, thereby greatly improving the write delay.

[0005] According to a first aspect of the present application, a method of performing an operation on a memory device is provided. The method of performing an operation on a memory device includes the following steps. An erasing operation is performed on a selected word line of the memory device to lower the threshold voltage of a plurality of first memory cells to be programmed and a plurality of second memory cells to be erased below a first predetermined level. A programming operation of a checkerboard pattern is performed on the selected word line such that the first memory cells are applied with a first programming bias and the second memory cells are applied with a second programming bias. The second programming bias is lower than the first programming bias.

[0006] In order to better understand the above and other aspects of the present application, the following embodiments are described in detail below with reference to the accompanying drawings: BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A schematic diagram of a memory device according to an embodiment is shown.

[0008] Figure 2 A circuit diagram of a memory device is shown.

[0009] Figure 3 A flowchart illustrating a method for performing operations on a memory device according to an embodiment is shown.

[0010] Figure 4A Illustration according to an embodiment Figure 3 The voltage control status of step S110.

[0011] Figure 4B Illustration according to an embodiment Figure 3 The voltage distribution in step S110.

[0012] Figure 5A Illustration according to an embodiment Figure 3 The voltage control status of step S120.

[0013] Figure 5B Illustration according to an embodiment Figure 3 The voltage distribution in step S120.

[0014] Figure 6A Illustration according to an embodiment Figure 3 The voltage control status of step S130.

[0015] Figure 6B The illustration is based on an embodiment. Figure 3 The threshold voltage distribution in step S130.

[0016] Figure 7 The diagram illustrates the interference to neighboring memory cells during in-situ writes.

[0017] Figure 8 A flowchart illustrating a method for performing operations on a memory device according to another embodiment is shown.

[0018] Figure 9A Illustration according to an embodiment Figure 8 The voltage control status of step S110.

[0019] Figure 9B Illustration according to an embodiment Figure 8 The voltage distribution in step S110.

[0020] Figure 10A Illustration according to an embodiment Figure 8 The voltage control status of step S130'.

[0021] Figure 10B Illustration according to an embodiment Figure 8 The voltage distribution in step S130'.

[0022] Figure 11A Illustration according to an embodiment Figure 8 The voltage control status of step S120.

[0023] Figure 11B Threshold voltage distribution of step S120 according to an embodiment is illustrated. Figure 8

[0024]

Symbol explanation

[0025] 100: memory device

[0026] BL: bit line

[0027] BL1: first bit line

[0028] BL2: second bit line

[0029] CL, CL0: memory cell

[0030] CL11: first memory cell

[0031] CL12: second memory cell

[0032] CH: channel

[0033] D: drain

[0034] E: erase state

[0035] G: gate

[0036] L1: first predetermined level

[0037] L2: second predetermined level

[0038] P: program state

[0039] PG, PG1: page

[0040] S: source

[0041] S110, S120, S130: step

[0042] SL: source line

[0043] SL1: first source line

[0044] SL2: second source line

[0045] WL: word line

[0046] WL0: unselected word line

[0047] WL1: selected word line DETAILED DESCRIPTION

[0048] Reference will now be made to Figure 1 ​The diagram illustrates a memory device 100 according to one embodiment. The memory device 100 is, for example, a three-dimensional AND memory. The structure of the memory device 100 is not intended to limit the scope claimed by the invention. The memory device 100 includes a plurality of memory cells CL stacked along the Z-axis. Each memory cell CL includes a gate G, a source S, a drain D, and a channel CH. The sources S and drains D may be formed by N-type diffused polysilicon plugs. The channels CH may be formed by an ONO structure, an ONONO structure, a SONOS structure, a BE-SONOS structure, or a BE-MANOS structure.

[0049] Please refer to Figure 2 The diagram illustrates the circuit of memory device 100. Multiple memory cells CL connected to a word line WL form a page PG. The size of the page PG is, for example, 256 bytes. Multiple vertically stacked memory cells CL are connected to a bit line BL and a source line SL. The gate G of a memory cell CL is connected to the word line WL, the drain D of a memory cell CL is connected to the bit line BL, and the source S of a memory cell CL is connected to the source line SL.

[0050] This invention provides a method for performing operations on a memory device 100. The operations performed include, for example, write-in-place, in which only one page PG needs to be erased, and the same page PG can be directly programmed. Please refer to... Figure 3 The diagram illustrates a flowchart of a method for performing operations on a memory device 100 according to one embodiment. The operations performed include, for example, in-situ writing. Figure 3 In one embodiment, the method for performing an in-situ write to the memory device 100 includes steps S110 to S130. In other embodiments, the method for performing an in-situ write to the memory device 100 may include only steps S110 to S120.

[0051] Please refer to Figure 4A Its illustration is based on an embodiment Figure 3The voltage distribution of step S110 of the erase operation. In step S110, an erase operation is performed on the selected word line WL1 of the memory device 100. Step S110 of performing the erase operation on the selected word line WL1 is performed for a time period of 100 microseconds (μβ) to 1 milliseconds (ms). The plurality of first memory cells CL11 to be programmed and the plurality of second memory cells CL12 to be erased connected to the selected word line WL1 form a page PG1. Each first memory cell CL1 to be programmed is connected to a first bit line BL1 and a first source line SL1. Each second memory cell CL2 to be erased is connected to a second bit line BL2 and a second source line SL2. The unselected word lines WL0 are not subjected to the erase operation.

[0052] In this step, the same voltage of +10V is applied to the first bit line BL1, the first source line SL1, the second bit line BL2 and the second source line SL2. A negative voltage of -9V is applied to the selected word line WL1, and a positive voltage of +10V is applied to the unselected word lines WL0. Thus, the first memory cells CL11 to be programmed are subjected to a first erase bias of -19V, and the second memory cells CL12 to be erased are subjected to a second erase bias of -19V. As a result, the first memory cells CL11 and the second memory cells CL12 connected to the selected word line WL1 are erased, and the memory cells CL0 connected to the unselected word lines WL0 are inhibited.

[0053] In other embodiments, the erase bias of step S110 can be set according to the following conditions: (1) the first erase bias to which the first memory cells CL11 to be programmed and the second erase bias to which the second memory cells CL12 to be erased are both more negative than an erase threshold voltage. The erase threshold voltage is, for example, -17V. (2) the first erase bias to which the first memory cells CL11 to be programmed and the second erase bias to which the second memory cells CL12 to be erased are substantially the same. For example, the difference between the first erase bias to which the first memory cells CL11 to be programmed and the second erase bias to which the second memory cells CL12 to be erased is less than 2V. The first erase bias and the second erase bias are, for example, -19V.

[0054] Referring to Figure 4B which illustrates the voltage distribution of step S110 of the erase operation according to an embodiment. Figure 3 The voltage distribution of step S110 of the erase operation. In step S110, an erase operation is performed on the selected word line WL1 of the memory device 100. Step S110 of performing the erase operation on the selected word line WL1 is performed for a time period of 100 microseconds (μβ) to 1 milliseconds (ms). The plurality of first memory cells CL11 to be programmed and the plurality of second memory cells CL12 to be erased connected to the selected word line WL1 form a page PG1. Each first memory cell CL1 to be programmed is connected to a first bit line BL1 and a first source line SL1. Each second memory cell CL2 to be erased is connected to a second bit line BL2 and a second source line SL2. The unselected word lines WL0 are not subjected to the erase operation.

[0055] Next, refer to Figure 5A which illustrates the voltage control of step S120 according to an embodiment. Figure 3 In step S120, a programming operation of a checkerboard pattern is performed on the selected word line WL1. Step S120 of performing the programming operation on the selected word line WL1 is performed once per programming shot at a time of 10 microseconds (μβ). A voltage of +14 V is applied to the selected word line WL1, and a voltage of 0 V is applied to the unselected source lines WL0. A negative voltage of -9 V is applied to the first bit line BL1 and the first source line SL1, and a positive voltage of +2 V is applied to the second bit line BL2 and the second source line SL2. Thus, the first storage units CL11 are subjected to a first programming bias of +23 V, and the second storage units CL12 are subjected to a second programming bias of +12 V. The second programming bias is lower than the first programming bias.

[0056] In other embodiments, the programming biases of step S120 can be set according to the following conditions: (1) the first programming bias to which the first storage units CL11 to be programmed are subjected is higher than a programming threshold voltage. The programming threshold voltage is, for example, +20 V, and the first programming bias is, for example, +23 V. (2) The second programming bias to which the second storage units CL12 to be erased are subjected is lower than the programming threshold voltage. The second programming bias is, for example, +12 V. (3) The third programming bias to which the storage units CL0 connected to the unselected word lines are subjected is much lower than the programming threshold voltage. The third programming bias is, for example, +9 V to -2 V.

[0057] Next, refer to Figure 5B which illustrates the voltage distribution of step S120 according to an embodiment. Figure 3 After the programming operation of the checkerboard pattern is performed on the selected word line WL1, the threshold voltages of the first storage units CL11 to be programmed are higher than the threshold voltages of the second storage units CL12 to be erased.

[0058] Compared with Figure 4B due to the factor of program disturb, Figure 5B the distribution of the threshold voltages of the second storage units CL12 of

[0059] Next, refer to Figure 6A which illustrates the voltage control of step S120 according to an embodiment. Figure 3The voltage control in step S130. In step S130, a soft-programming operation is performed on these second memory cells CL12. In the soft-programming operation, an incremental step pulse programming (ISPP) voltage of +5.5V to +9V is applied to the selected word line WL1, and a voltage of 0V is applied to the unselected word lines WL0. These second memory cells CL12 are soft-programmed multiple times with each 5-microsecond interval. The number of programming shots is less than or equal to 8. For example, these second memory cells CL12 can be sequentially programmed eight times with voltages of +5.5V, +6V, +6.5V, +7V, +7.5V, +8V, +8.5V, and +9V.

[0060] In other embodiments, the ISPP bias voltage in step S130 can be set according to the following conditions: (1) The first ISPP bias voltage of the first memory cell CL11 to be programmed is much lower than the programming threshold voltage. The programming threshold voltage is, for example, +20V, and the first ISPP bias voltage is, for example, lower than +9V. (2) The second ISPP bias voltage of the second memory cell CL12 to be erased is slightly lower than the programming threshold voltage. The second ISPP bias voltage is, for example, +12.5V to +16V. (3) The third ISPP bias voltage of the memory cell CL0 is much lower than the programming threshold voltage. For example, the third ISPP bias voltage is, for example, +7V to 0V.

[0061] A voltage of 0V is applied to the first bit line BL1 and the first source line SL1, and a negative voltage of -7V is applied to the second bit line BL2 and the second source line SL2. Thus, the first memory cells CL11 to be programmed will be subjected to a soft programming bias voltage lower than +9V; the second memory cells CL12 to be erased will be subjected to a soft programming bias voltage of +12.5V to +16V.

[0062] Please refer to Figure 6B Its illustration is based on an embodiment. Figure 3 The threshold voltage distribution in step S130. After performing a software programming procedure on these second memory cells CL12, the threshold voltage of these second memory cells CL12 is higher than a second predetermined level L2. Therefore, the threshold voltage distribution of these second memory cells CL12 becomes more compact.

[0063] According to the above description, in-place write can be performed on the memory device 100. In the process of performing in-place write on the memory device 100, only one page PG1 needs to be erased, and the same page PG1 can be directly programmed. In this process, the entire block does not need to be erased again, thereby greatly improving the situation of write delay.

[0064] Referring to Figure 7 , a situation of interference on adjacent memory cells in the process of in-place write is illustrated. As shown in the left side of Figure 7 , a first memory cell CL11 is in an erased state E, and a second memory cell CL12 is in a programmed state P. After performing in-place write, as shown in the right side of Figure 7 , the first memory cell CL11 is changed to the programmed state P, and the second memory cell CL12 is changed to the erased state E. Comparing the left side of Figure 7 with the right side, it can be seen that the memory cells CL0 connected to the unselected word line WL0 are not changed. That is, in-place write performed on the selected word line WL1 does not cause interference on the adjacent unselected word line WL0.

[0065] Referring to Figure 8 , a flowchart of a method of performing an operation on the memory device 100 according to an embodiment is illustrated. The operation performed is, for example, in-place write. In Figure 8 , the method of performing in-place write on the memory device 100 includes steps S110, S130', and S120.

[0066] Referring to Figure 9A , a voltage control situation of step S110 of Figure 8 according to an embodiment is illustrated. In step S110, an erasing operation is performed on one selected word line WL1 of the memory device 100. Step S110 of performing the erasing operation on the selected word line WL1 is performed for a time period of 100 microseconds (μs) to 1 milliseconds (ms). A plurality of first memory cells CL11 to be programmed and a plurality of second memory cells CL12 to be erased connected to the selected word line WL1 form a page PG1. Each first memory cell CL1 to be programmed is connected to a first bit line BL1 and a first source line SL1. Each second memory cell CL2 to be programmed is connected to a second bit line BL2 and a second source line SL2. A plurality of unselected word lines WL0 are not subjected to the erasing operation.

[0067] In this step, the same voltage of +10V is applied to the first bit line BL1, the first source line SL1, the second bit line BL2, and the second source line SL2. A negative voltage of -9V is applied to the selected word line WL1, and a positive voltage of +10V is applied to the unselected word lines WL0. Thus, the first memory cells CL11 to be programmed are subjected to a first erase bias of -19V, and the second memory cells CL12 to be erased are subjected to a second erase bias of -19V. As a result, the first memory cells CL11 and the second memory cells CL12 connected to the selected word line WL1 are erased, and the memory cells CL0 connected to the unselected word lines WL0 are inhibited.

[0068] In other embodiments, the erase bias of step S110 can be set according to the following conditions: (1) the first erase bias to which the first memory cells CL11 to be programmed is subjected and the second erase bias to which the second memory cells CL12 to be erased are both higher than an erase threshold voltage. The erase threshold voltage is, for example, -17V. (2) the first erase bias to which the first memory cells CL11 to be programmed is subjected and the second erase bias to which the second memory cells CL12 to be erased are substantially the same. For example, the difference between the first erase bias to which the first memory cells CL11 to be programmed is subjected and the second erase bias to which the second memory cells CL12 to be erased is lower than 2V. The first erase bias and the second erase bias are, for example, -19V.

[0069] Referring to Figure 9B , a voltage distribution of step S110 of Figure 8 is shown according to an embodiment. After performing the erase procedure on the selected word line WL1, the threshold voltages of the first memory cells CL11 to be programmed and the second memory cells CL12 to be erased connected to the selected word line WL1 are lower than a first predetermined level L1.

[0070] Next, referring to Figure 10A , a voltage distribution of step S110 of Figure 8The voltage control in step S130'. In step S130', a soft-programming operation is performed on the first memory cells CL11 and the second memory cells CL12. In the soft-programming operation, an incremental step pulse programming (ISPP) voltage of +5.5V to +9V is applied to the selected word line WL1, and a voltage of 0V is applied to the unselected word lines WL0. The first memory cells CL11 and the second memory cells CL12 are soft-programmed multiple times with each time interval of 5 microseconds (μs). The number of programming shots is less than or equal to 8. For example, the first memory cells CL11 and the second memory cells CL12 can be sequentially programmed eight times with voltages of +5.5V, +6V, +6.5V, +7V, +7.5V, +8V, +8.5V, and +9V.

[0071] In other embodiments, the ISPP bias voltage in step S130' can be set according to the following conditions: (1) The first ISPP bias voltage of the first memory cell CL11 to be programmed and the second ISPP bias voltage of the second memory cell CL12 to be erased are slightly lower than the programming threshold voltage. The programming threshold voltage is, for example, +20V, and the first ISPP bias voltage and the second ISPP bias voltage are, for example, +12.5V to +16V. (2) The third ISPP bias voltage of the memory cell CL0 is much lower than the programming threshold voltage. For example, the third ISPP bias voltage is, for example, +7V to 0V.

[0072] A negative voltage of -7V is applied to the first bit line BL1, the first source line SL1, the second bit line BL2, and the second source line SL2. Therefore, the first memory cells CL11 to be programmed and the second memory cells CL12 to be erased are subjected to a soft programming bias voltage of +12.5V to +16V.

[0073] Please refer to Figure 10B Its illustration is based on an embodiment. Figure 8 The threshold voltage distribution in step S130'. After performing a software programming procedure on these first memory cells CL11 and these second memory cells CL12, the threshold voltages of these first memory cells CL11 and these second memory cells CL12 are higher than a second predetermined level L2. Therefore, the threshold voltage distribution of these first memory cells CL11 and these second memory cells CL12 becomes more compact.

[0074] Next, please refer to Figure 11A Its illustration is based on an embodiment Figure 8The voltage distribution of step S120 is shown in FIG. 12. After the checkerboard pattern programming operation is performed on the selected word line WL1, the threshold voltages of the first memory cells CL11 to be programmed are higher than the threshold voltages of the second memory cells CL12 to be erased.

[0075] In other embodiments, the programming bias of step S120 can be set according to the following conditions: (1) the first programming bias applied to the first memory cells CL11 to be programmed is higher than a programming threshold voltage. The programming threshold voltage is, for example, +20 V, and the first programming bias is, for example, +23 V. (2) the second programming bias applied to the second memory cells CL12 to be erased is lower than the programming threshold voltage. The second programming bias is, for example, +12 V. (3) the third programming bias applied to the memory cells CL0 connected to the unselected word line is much lower than the programming threshold voltage. The third programming bias is, for example, +9 V to -2 V.

[0076] Please refer to Figure 11B which shows the voltage distribution of step S120 according to an embodiment. Figure 8 After the checkerboard pattern programming operation is performed on the selected word line WL1, the threshold voltages of the first memory cells CL11 to be programmed are higher than the threshold voltages of the second memory cells CL12 to be erased.

[0077] Compared with Figure 10B Due to the programming interference factor, Figure 11B The threshold voltages of the second memory cells CL12 are shifted to the right a little.

[0078] According to the above description, in-place writing can be performed on the memory device 100. In the process of performing in-place writing on the memory device 100, only one page PG1 needs to be erased, and the same page PG1 can be directly programmed. In this process, the entire block does not need to be erased again, thereby greatly improving the write delay.

[0079] So far, the embodiments of the present application have been described in detail with reference to the accompanying drawings.

[0080] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application, and it should be understood that the above-described specific embodiments are merely examples of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of performing an operation on a memory device, wherein, Comprising: performing an erase procedure on a selected word line of the memory device to lower threshold voltages of a plurality of first memory cells to be programmed and a plurality of second memory cells to be erased below a first predetermined level; and performing a program procedure on the selected word line after performing the erase procedure on the selected word line such that the first memory cells are subjected to a first program bias and the second memory cells are subjected to a second program bias, the second program bias being lower than the first program bias.

2. The method of claim 1, wherein, In the step of performing the erase procedure on the selected word line, a first erase bias to which the first memory cells are subjected and a second erase bias to which the second memory cells are subjected are both more negative than an erase threshold voltage.

3. The method of claim 2, wherein, In the step of performing the erase procedure on the selected word line, the first erase bias to which the first memory cells are subjected and the second erase bias to which the second memory cells are subjected are substantially the same.

4. The method of claim 1, wherein, In the step of performing the program procedure on the selected word line, the first program bias to which the first memory cells are subjected is higher than a program threshold voltage, and the second program bias to which the second memory cells are subjected is lower than the program threshold voltage.

5. The method of claim 4, wherein, In the step of performing the program procedure on the selected word line, a third program bias to which memory cells connected to unselected word lines are subjected is lower than the program threshold voltage.

6. The method of claim 1, wherein, Further comprising: performing a soft program procedure on the second memory cells to raise threshold voltages of the second memory cells above a second predetermined level.

7. The method of claim 6, wherein, The second predetermined level is lower than the first predetermined level.

8. The method of claim 1, wherein, Further comprising: performing a soft program procedure on the first memory cells and the second memory cells to raise threshold voltages of the first memory cells and the second memory cells above a second predetermined level.

9. The method of claim 8, wherein, In the step of performing the soft program procedure on the first memory cells and the second memory cells, a first step-up pulse program bias to which the first memory cells are subjected and a second step-up pulse program bias to which the second memory cells are subjected are lower than a program threshold voltage.

10. The method of claim 9, wherein, In the step of performing the soft program procedure on the first memory cells and the second memory cells, the first step-up pulse program bias and the second step-up pulse program bias are substantially the same.

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