Method of manufacturing a semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: forming a first gate dielectric layer on a first region and a second region in a peripheral region of a substrate, and forming a first conductor layer and a first hard mask layer on the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first mask layer; performing a wet etching process using the first hard mask layer as a mask to remove the first conductor layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductor layer; forming a first gate dielectric layer in the second region; and forming a first gate conductor layer in the first region and a second gate conductor layer in the second region.

Description

Technical Field

[0001] The present invention relates to a manufacturing method of an integrated circuit device, and more particularly to a manufacturing method of a semiconductor device. Background Art

[0002] During the manufacturing process of semiconductor devices, multiple etching processes are usually involved. However, if the etching selectivity of the etchant between layers is insufficient, etching damage often occurs, resulting in electrical problems of the devices. Summary of the Invention

[0003] The present invention aims at a manufacturing method of a semiconductor device that can reduce or avoid damage to the active region of the device during the etching process.

[0004] According to an embodiment of the present invention, a manufacturing method of a semiconductor device includes: providing a substrate, the substrate including a cell region and a peripheral region, the peripheral region including a first region and a second region; forming a tunneling oxide layer, a floating conductor layer, and a hard mask stack layer in the cell region and the peripheral region; using the hard mask stack layer as a mask to remove the floating conductor layer and the tunneling oxide layer in the first region and the second region; forming a first gate dielectric layer on the substrate in the first region and the second region of the peripheral region, and forming a first conductor layer and a first hard mask layer in the cell region and the first region and the second region of the peripheral region; removing the first hard mask layer outside the first region; using the first hard mask layer as a mask to remove the first conductor layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductor layer; and forming a first gate conductor layer in the first region.

[0005] According to an embodiment of the present invention, a manufacturing method of a semiconductor device includes: providing a substrate, the substrate including a cell region and a peripheral region, the peripheral region including a first region and a second region; forming a first gate dielectric layer on the substrate in the first region and the second region of the peripheral region, and forming a first conductor layer and a first hard mask layer in the cell region and the first region and the second region of the peripheral region; forming a first mask layer on the first hard mask layer in the first region; using the first mask layer as a mask to remove the first hard mask layer outside the first region; removing the first mask layer; using the first hard mask layer as a mask to perform a wet etching process to remove the first conductor layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductor layer; forming a second gate dielectric layer in the second region; and forming a first gate conductor layer in the first region and a second gate conductor layer in the second region.

[0006] Based on the above, in the embodiments of the present invention, first form a thin gate dielectric layer of transistors with a smaller threshold voltage in each region of the peripheral circuit region, and then remove the thin gate dielectric layer on the region of the transistors with a larger threshold voltage. Since the thickness of the gate dielectric layer of the transistors with a smaller threshold voltage is thinner, the time of the wet etching process for removing the thin gate dielectric layer is shorter, and it is less likely to cause electrical problems of the device. In addition, in the embodiments of the present invention, the conductor layer on the region of the transistors with a larger threshold voltage is removed by a wet etching process, so that the active region of the device can be avoided from being damaged by etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1N is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0008] Figure 2 An intermediate flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0009] Now, reference will be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0010] Please refer to Figure 1A , and provide a substrate 100. The substrate 100 can be a semiconductor or a semiconductor compound, such as an N-type or P-type silicon substrate, a III-V semiconductor substrate, or a germanium silicide. The substrate 100 can also be a silicon on insulator (SOI). The substrate 100 includes a cell region R1 and a peripheral region R2. The peripheral region R2 includes regions A1, A2, and A3 for forming transistors with different threshold voltages. The threshold voltage of the transistors in region A2 is higher than that of the transistors in region A1 and lower than that of the transistors in region A3. For example, the transistors in region A2 have a low threshold voltage; the transistors in region A1 have an ultra-low threshold voltage; the transistors in region A3 have a high threshold voltage. In some embodiments, the threshold voltage of the transistors in region A1 is less than or equal to 1.8 volts; the threshold voltage of the transistors in region A2 is about 3 volts; the threshold voltage of the transistors in region A3 is about 5 volts to Vpp.

[0011] Form a tunneling oxide layer 102 and a conductor layer 104 on the substrate 100. The material of the tunneling oxide layer 102 is, for example, silicon oxide. The conductor layer 104 is subsequently used as a floating gate and can thus also be referred to as a floating conductor layer. The material of the conductor layer 104 is, for example, doped polysilicon. The thickness of the tunneling oxide layer 102 is, for example, 8 nm to 11 nm. The thickness of the conductor layer 114 is, for example, 50 nm to 90 nm.

[0012] Next, an isolation structure 101 is formed in the substrate 100 to define a plurality of active regions in the cell region R1 and regions A1, A2, and A3 of the peripheral region R2. The isolation structure 101 may include, for example, a spin-on glass layer 101a and a high-density plasma oxide silicon layer 101b.

[0013] Please refer to Figure 1B , a hard mask layer 106 is formed on the substrate 100 to cover the conductor layer 104 in the cell region R1 and the isolation structure 101. In one embodiment, the hard mask layer 106 includes a silicon oxide layer 108 and a silicon nitride layer 110, and thus can be referred to as a hard mask stack layer. The hard mask layer 106 can be formed by processes of deposition and photolithographic etching.

[0014] Please refer to Figure 1C , using the hard mask layer 106 as a mask, the conductor layer 104 and the silicon oxide layer 102 in the peripheral region R2 are removed to expose the surface of the substrate 100 in regions A1, A2, and A3. The conductor layer 104 can be removed by a reactive ion etching process. The silicon oxide layer 102 can be removed by a wet etching process (for example, using diluted hydrofluoric acid as an etchant). In some embodiments, the high-density plasma oxide silicon layer 101b of the isolation structure 101 in the peripheral region R2 is also removed during the process of removing the silicon oxide layer 108.

[0015] Please refer to Figure 1D , a gate dielectric layer 112 is formed on the substrate 100 in the peripheral region R2, and then a conductor layer 114 and a hard mask layer 116 are formed on the hard mask layer 106 in the cell region R1 and the gate dielectric layer 112 in the peripheral region R2. The material of the gate dielectric layer 112 is, for example, silicon oxide, and the forming method is, for example, a thermal oxidation process. Through the thermal oxidation process, the exposed substrate 100 in the peripheral region R2 can be oxidized to form silicon oxide, while the silicon nitride layer 110 in the cell region R1 cannot be oxidized, so no silicon oxide layer is formed on the silicon nitride layer 110. The material of the conductor layer 114 is, for example, doped polysilicon. The material of the hard mask layer 116 is, for example, silicon nitride. The forming methods of the conductor layer 114 and the hard mask layer 116 are, for example, chemical vapor deposition methods. The thickness of the gate dielectric layer 112 is, for example, less than the thickness of the tunneling oxide layer 102. The thickness of the gate dielectric layer 112 is, for example, 1 nm to 3 nm. The thickness of the conductor layer 114 is, for example, 10 nm to 20 nm. The thickness of the hard mask layer 116 is, for example, 10 nm to 20 nm.

[0016] After that, through a photolithography process, a mask layer (for example, a patterned photoresist layer) 120 is formed on the substrate 100 to cover the hard mask layer 116 in region A1 of the peripheral region R2.

[0017] Please refer to Figure 1EUsing the mask layer 120 of region A1 in the peripheral region R2 as a mask, an etching process (such as a reactive ion etching process) is performed to remove the hard mask layer 116 outside region A1 in the peripheral region R2.

[0018] Please refer to Figure 1F Remove the mask layer 120. Thereafter, using the hard mask layer 116 of region A1 in the peripheral region R2 as a mask, an etching process is performed to remove the conductor layer 114 and the gate dielectric layer 112 outside region A1 in the peripheral region R2, exposing the surface of the hard mask layer 106 in the cell region R1 and the substrate 100 in regions A2 and A3 of the peripheral region R2.

[0019] Please refer to Figure 1F And Figure 2 The method for removing the conductor layer 114 is, for example, to perform a wet etching process (step S10) using an etchant with a high etching selectivity. The etchant can be a solution containing tetra-methyl ammonium hydroxide (TMAH), such as the commercial cleaning formulation Rezi38 manufactured by J.T. Baker of Mallinckrodt Baker, Inc. The gate dielectric layer 112 can be removed by a wet etching process (such as a diluted hydrofluoric acid solution, step S12). Since the thickness of the gate dielectric layer 112 is very thin, the amount of the gate dielectric layer 112 to be removed is small, the required wet etching process is short, and the etchant has a high etching selectivity, so the active region of the device can be prevented from being etched and damaged.

[0020] Please refer to Figure 1G A gate dielectric layer 122 is formed on the substrate 100 in regions A2 and A3 of the peripheral region R2, and then a conductor layer 124 and a hard mask layer 126 are formed on the hard mask layer 106 in the cell region R1, on the hard mask layer 116 in region A1 of the peripheral region R2, and on the gate dielectric layer 122 in regions A2 and A3 of the peripheral region R2. The material of the gate dielectric layer 122 is, for example, silicon oxide, and the forming method is, for example, a thermal oxidation process. Through the thermal oxidation process, the exposed substrate 100 in regions A2 and A3 of the peripheral region R2 can be oxidized to form silicon oxide, while the silicon nitride layer 110 in the cell region R1 and the hard mask layer 116 in region A1 of the peripheral region R2 cannot be oxidized, so no silicon oxide layer is formed on the silicon nitride layer 110 and the hard mask layer 116. The material of the conductor layer 124 is, for example, doped polysilicon. The material of the hard mask layer 126 is, for example, silicon nitride. The forming methods of the conductor layer 124 and the hard mask layer 126 are, for example, chemical vapor deposition methods. The thickness of the gate dielectric layer 122 is, for example, 5 nanometers (nm) to 7 nm. The thickness of the conductor layer 124 is, for example, 10 nm to 20 nm. The thickness of the hard mask layer 126 is, for example, 10 nm to 20 nm.

[0021] Thereafter, a mask layer (e.g., a patterned photoresist layer) 130 is formed on the substrate 100 to cover the hard mask layer 126 in the region A2 of the peripheral region R2.

[0022] Please refer to Figure 1H , using the mask layer 130 in the region A2 of the peripheral region R2 as a mask, an etching process (e.g., a reactive ion etching process) is performed to remove the hard mask layer 126 outside the region A2 of the peripheral region R2.

[0023] Please refer to Figure 1I and Figure 2 , the mask layer 130 is removed. Thereafter, using the hard mask layer 126 in the region A2 as a mask, an etching process (steps S10 and S12) is performed to remove the conductor layer 124 and the gate dielectric layer 122 outside the region A2 of the peripheral region R2, exposing the surface of the hard mask layer 106 in the cell region R1, the hard mask layer 116 in the region A1 of the peripheral region R2, and the substrate 100 in the region A3.

[0024] The method of removing the conductor layer 124 is, for example, to perform a wet etching process using an etchant with a high etching selectivity. The etchant can be a solution containing tetramethylammonium hydroxide, such as the commercial cleaning formulation Rezi38 manufactured by J.T. Baker of Mallinckrodt Baker, Inc. The gate dielectric layer 122 can be removed by a wet etching process (e.g., a diluted hydrofluoric acid solution). Since the thickness of the gate dielectric layer 122 is very thin, the amount of the gate dielectric layer 122 to be removed is small, the required wet etching process is short, and the etchant has a high etching selectivity, so the active region of the device can be prevented from being etched and damaged.

[0025] Please refer to Figure 1J, a gate dielectric layer 132 is formed on the substrate 100 in region A3 of the peripheral region R2. Then, a conductor layer 134 and a hard mask layer 136 are formed on the hard mask layer 106 in the cell region R1, on the hard mask layer 116 in region A1 of the peripheral region R2, on the hard mask layer 126 in region A2 of the peripheral region R2, and on the gate dielectric layer 132 in region A3 of the peripheral region R2. The material of the gate dielectric layer 132 is, for example, silicon oxide, and the forming method is, for example, a thermal oxidation process. Through the thermal oxidation process, the exposed substrate 100 in region A3 of the peripheral region R2 can be oxidized to form silicon oxide, while the silicon nitride layer 110 in the cell region R1, the hard mask layer 116 in region A1 of the peripheral region R2, and the hard mask layer 126 in region A2 cannot be oxidized. Therefore, no silicon oxide layer is formed on the silicon nitride layer 110 and the hard mask layers 116, 126. The material of the conductor layer 134 is, for example, doped polysilicon. The material of the hard mask layer 136 is, for example, silicon nitride. The forming methods of the conductor layer 134 and the hard mask layer 136 are, for example, chemical vapor deposition. The thickness of the gate dielectric layer 132 is, for example, 13 nm to 17 nm. The thickness of the conductor layer 134 is, for example, 10 nm to 20 nm. The thickness of the hard mask layer 136 is, for example, 10 nm to 20 nm.

[0026] After that, a mask layer (such as a patterned photoresist layer) 140 is formed on the substrate 100 to cover the hard mask layer 136 in the cell region R1 and region A3 of the peripheral region R2.

[0027] Please refer to Figure 1K , using the mask layer 140 in the cell region R1 and region A3 of the peripheral region R2 as a mask, an etching process (such as a reactive ion etching process) is performed to remove the hard mask layer 136 and the conductor layer 134 outside the cell region R1 and region A3 of the peripheral region R2. Then, the mask layer 140 is removed.

[0028] Please refer to Figure 1L , an etching process, such as a reactive ion etching process, is performed to remove the hard mask layers 116, 126, 136 to expose the hard mask layer 106 in the cell region R1 and the conductor layers 114, 124, 134 in the peripheral region R2.

[0029] Please refer to Figure 1M , then, a conductor layer 144 is formed on the substrate 100 to cover the hard mask layer 106 in the cell region R1 and the gate dielectric layers 112, 122, 132 in the peripheral region R2. The material of the conductor layer 144 is, for example, doped polysilicon. The conductor layer 144 serves as a gate and can thus be also called a gate conductor layer.

[0030] Please refer to Figure 1N, the conductor layer 144 and the hard mask layer 106 in the cell region R1 are removed. Then, a part of the isolation structure 101b in the cell region R1 is removed so that the top surface of the remaining isolation structure 101b is lower than the top surface of the conductor layer 104. After that, an inter-gate dielectric layer 152 is formed in the cell region R1. The inter-gate dielectric layer 152 is, for example, silicon oxide, silicon nitride, or a combination thereof. In one embodiment, the inter-gate dielectric layer 152 includes a silicon oxide / silicon nitride / silicon oxide stacked layer. After that, a conductor layer 154 is formed on the inter-gate dielectric layer 152. The conductor layer 154 serves as a control gate, and its material is, for example, polysilicon. The conductor layer 154 is formed, for example, by forming a conductor material layer in the cell region R1 and the peripheral region R2 of the substrate 100, and then patterning the conductor material layer through photolithography and etching processes.

[0031] In summary, in the embodiments of the present invention, a gate dielectric layer with uniform thickness can be formed, avoiding the problem of thinning of the gate dielectric layer at the corners of the active regions of the isolation structure, so that problems such as leakage current and current double hump can be avoided. In addition, in the embodiments of the present invention, a thin gate dielectric layer of a transistor with a smaller threshold voltage is first formed in each region of the peripheral circuit region, and then the thin gate dielectric layer on the region of the transistor with a larger threshold voltage is removed. Since the thickness of the gate dielectric layer of the transistor with a smaller threshold voltage is thinner, the time of the wet etching process for removing the thin gate dielectric layer is shorter, and it is less likely to cause the above problems such as leakage current and current double hump. In addition, in the embodiments of the present invention, the conductor layer on the region of the transistor with a larger threshold voltage is removed by a wet etching process with a high etching selectivity, so that the active region of the device can be prevented from being damaged by etching.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate, the substrate including a cell region and a peripheral region, the peripheral region including a first region and a second region, wherein the transistor threshold voltage of the first region is less than the transistor threshold voltage in the second region; Forming a tunneling oxide layer and a floating conductor layer in the cell region and the peripheral region; Forming a hard mask stack layer in the cell region; Using the hard mask stack layer as a mask to remove the floating conductor layer and the tunneling oxide layer in the first region and the second region; Forming a first gate dielectric layer on the substrate in the first region and the second region of the peripheral region, and forming a first conductor layer and a first hard mask layer in the cell region and the first region and the second region of the peripheral region; Removing the first hard mask layer outside the first region; Using the first hard mask layer as a mask to remove the first conductor layer and the first gate dielectric layer outside the first region; Removing the first hard mask layer and the first conductor layer; and Forming a first gate conductor layer in the first region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein using the first hard mask layer as a mask to remove the first conductor layer and the first gate dielectric layer outside the first region includes a wet etching process.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the wet etching process includes using a solution containing tetramethylammonium hydroxide as an etchant.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the first gate dielectric layer is less than the thickness of the tunneling oxide layer.

5. The method for manufacturing a semiconductor device according to claim 1, further comprising: Before forming the first gate conductor layer in the first region, Forming a second gate dielectric layer on the substrate in the second region of the peripheral region, and forming a second conductor layer and a second hard mask layer in the cell region and the first region and the second region of the peripheral region; Forming a second mask layer on the second hard mask layer in the second region; Using the second mask layer as a mask to remove the second hard mask layer outside the second region; Removing the second mask layer; Using the second hard mask layer as a mask to remove the second conductor layer and the second gate dielectric layer outside the second region; When removing the first hard mask layer and the first conductor layer, simultaneously removing the second hard mask layer and the second conductor layer; And When forming the first gate conductor layer in the first region, simultaneously forming a second gate conductor layer in the second region.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer.

7. The method for manufacturing a semiconductor device according to claim 5, further comprising: Before forming the second gate conductor layer in the second region, Forming a third gate dielectric layer on the substrate in a third region of the peripheral region, and forming a third conductor layer and a third hard mask layer in the cell region and the first region and the second region of the peripheral region; Forming a third mask layer on the third hard mask layer in the third region; Using the third mask layer as a mask, remove the third hard mask layer and the second conductor layer outside the third region; When removing the first hard mask layer and the first conductor layer, simultaneously remove the third hard mask layer and the third conductor layer; And When forming the first gate conductor layer in the first region, simultaneously form the second gate conductor layer in the third region.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the thickness of the third gate dielectric layer is greater than the thickness of the second gate dielectric layer.

9. The method of manufacturing a semiconductor device according to claim 7, further comprising: Removing the hard mask stack layer; Forming an inter-gate dielectric layer on the floating conductor layer in the cell region; And Forming a control conductor layer on the inter-gate dielectric layer.

10. A method of manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate including a cell region and a peripheral region, the peripheral region including a first region and a second region, wherein the transistor threshold voltage of the first region is less than the transistor threshold voltage in the second region; Forming a tunneling oxide layer and a floating conductor layer in the cell region and the peripheral region; Forming a hard mask stack layer in the cell region; Using the hard mask stack layer as a mask, remove the floating conductor layer and the tunneling oxide layer in the first region and the second region; Forming a first gate dielectric layer on the substrate in the first region and the second region of the peripheral region, and forming a first conductor layer and a first hard mask layer in the cell region and the first region and the second region of the peripheral region; Forming a first mask layer on the first hard mask layer in the first region; Using the first mask layer as a mask, remove the first hard mask layer outside the first region; Removing the first mask layer; Using the first hard mask layer as a mask, perform a wet etching process to remove the first conductor layer and the first gate dielectric layer outside the first region; Removing the first hard mask layer and the first conductor layer; Forming a second gate dielectric layer in the second region; and Forming a first gate conductor layer in the first region and a second gate conductor layer in the second region.

11. The method of manufacturing a semiconductor device according to claim 10, wherein removing the first conductor layer outside the first region includes using a solution containing tetramethylammonium hydroxide as an etchant.

12. The method of manufacturing a semiconductor device according to claim 10, wherein the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer.

13. The method of manufacturing a semiconductor device according to claim 10, further comprising forming a third gate dielectric layer in a third region of the peripheral region of the substrate; and When forming the first gate conductor layer in the first region and the second gate conductor layer in the second region, simultaneously form a third gate conductor layer in the third region.

14. The method of manufacturing a semiconductor device according to claim 13, wherein the thickness of the third gate dielectric layer is greater than the thickness of the second gate dielectric layer.

Images