Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a core layer on a patterned material layer, forming a first sidewall on the sidewalls of the core layer, then removing the core layer, forming a second sidewall on the sidewalls of the first sidewall, then removing the first sidewall, using the second sidewall as a mask to pattern the patterned material layer, the patterned material layer in a first region forms a first target pattern, and the patterned material layer in a second region forms a second target pattern, wherein the sidewall adjustment process is used to adjust the line width and quantity of the second target pattern, including: in the step of forming the first sidewall, in the second region, making the first sidewalls located on the opposite sidewalls of the core layer contact each other; in the step of forming the second sidewall, in the second region, making the second sidewalls located on the opposite sidewalls of a part of the first sidewalls contact each other; after removing the first sidewall and before patterning the patterned material layer, removing the second sidewall located in the first region. The design freedom of the pitch and quantity of the second target pattern is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art

[0002] Photolithography technology is a commonly used patterning method and is the most critical production technology in semiconductor manufacturing processes. As the critical dimension (CD) of patterns continues to shrink, self-aligned double patterning (SADP) can no longer meet the current process requirements, and the self-aligned quadruple patterning (SAQP) method has emerged as the times require.

[0003] However, traditional self-aligned quadruple patterning methods have some limitations. In the same area, the line width dimensions of the target patterns formed must be uniform, and the pitch between two adjacent target patterns in the formed target patterns must also be uniform. Therefore, it is impossible to form target patterns with non-uniform line width dimensions and non-uniform pitch. At the same time, traditional self-aligned quadruple patterning methods can only form an odd number of target patterns and cannot form an even number of target patterns, which also poses great limitations on the production of various types of devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which improves the design freedom of the pitch and quantity of the second target pattern.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate on which a patterned material layer is formed, the substrate including alternately arranged first regions and second regions, the substrate further including a spacer region located between adjacent first regions and second regions, the first region being configured to form a first target pattern, the second region being configured to form a plurality of second target patterns, and along the arrangement direction of the first regions and second regions, the line width of the first target pattern being greater than the line width of the second target pattern; forming discrete and parallel core layers on the patterned material layer; forming first sidewalls on the sidewalls of the core layers; after forming the first sidewalls, removing the core layers; after removing the core layers, forming second sidewalls on the sidewalls of the first sidewalls; after forming the second sidewalls, removing the first sidewalls; after removing the first sidewalls, patterning the patterned material layer with the second sidewalls as a mask pattern to form a first target pattern in the patterned material layer of the first region and a second target pattern in the patterned material layer of the second region; wherein, the forming method further includes performing a sidewall adjustment process for adjusting one or both of the pitch and the number of the second target patterns, and the sidewall adjustment process includes one or more of the following sidewall treatment methods, and the sidewall treatment methods include: in the step of forming the first sidewalls, in the second region, making the first sidewalls on the opposite sidewalls of the core layers contact each other; in the step of forming the second sidewalls, in the second region, making the second sidewalls on the opposite sidewalls of some of the first sidewalls contact each other; before patterning the patterned material layer with the second sidewalls as a mask pattern after removing the first sidewalls, removing the second sidewalls located in the first region.

[0006] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0007] The forming method provided by the embodiment of the present invention further includes performing sidewall adjustment processing for adjusting one or both of the pitch and the number of the second target patterns. The sidewall processing method includes: in the step of forming the first sidewall, in the second region, making the first sidewalls on the opposite sidewalls of the core layer contact with each other; in the step of forming the second sidewall, in the second region, making the second sidewalls on the opposite sidewalls of some of the first sidewalls contact with each other; after removing the first sidewall, before patterning the graphic material layer with the second sidewall as a mask, removing the second sidewall in the first region; in the embodiment of the present invention, by making the first sidewalls on the opposite sidewalls of the core layer contact with each other, the line width of the formed second target pattern can be changed to form second target patterns with different line width dimensions that meet the requirements. By one or both of the adjustment methods of making the second sidewalls on the opposite sidewalls of some of the first sidewalls contact with each other and removing the second sidewall in the first region, the number of the formed second target patterns can be changed to obtain an even number of the second target patterns. Therefore, in the embodiment of the present invention, through the sidewall processing method, by selecting one or more sidewall processing methods, second target patterns with different pitches and / or an even number can be obtained, meeting different types of process requirements and improving the design freedom of the pitch and the number of the second target patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. is a schematic diagram of the relative positional relationship among a core layer, a first sidewall, a second sidewall, a first target pattern, and a second target pattern in a forming method of a semiconductor structure;

[0009] Figures 2 to 9 FIG. is a schematic diagram corresponding to the first embodiment of the forming method of the semiconductor structure of the present invention;

[0010] Figure 10 FIG. is a schematic diagram of the relative positional relationship among a core layer, a first sidewall, a second sidewall, a first target pattern, and a second target pattern in the second embodiment of the forming method of the semiconductor structure of the present invention;

[0011] Figure 11 FIG. is a schematic diagram of the relative positional relationship among a core layer, a first sidewall, a second sidewall, a first target pattern, and a second target pattern in the third embodiment of the forming method of the semiconductor structure of the present invention;

[0012] Figure 12 FIG. is a schematic diagram of the relative positional relationship among a core layer, a first sidewall, a second sidewall, a first target pattern, and a second target pattern in the fourth embodiment of the forming method of the semiconductor structure of the present invention;

[0013] Figure 13It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the fifth embodiment of the method for forming a semiconductor structure according to the present invention;

[0014] Figure 14 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the sixth embodiment of the method for forming a semiconductor structure according to the present invention;

[0015] Figure 15 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the seventh embodiment of the method for forming a semiconductor structure according to the present invention;

[0016] Figure 16 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the eighth embodiment of the method for forming a semiconductor structure according to the present invention. Detailed implementation manners

[0017] Currently, the design freedom of the pitch and the number of target patterns of semiconductor structures needs to be improved. The reasons why the design freedom of the pitch and the number of target patterns needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0018] Figure 1 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in a method for forming a semiconductor structure.

[0019] Reference Figure 1, a substrate (not shown) is provided, and a pattern material layer (not shown) is formed on the substrate. The substrate includes alternately arranged first regions 10A and second regions 10B, and the substrate further includes a spacer 10C located between adjacent first regions 10A and second regions 10B. The first region 10A is used to form a first target pattern 31, and the second region 10B is used to form a plurality of second target patterns 32. Along the arrangement direction of the first region 10A and the second region 10B, the line width of the first target pattern 31 is greater than the line width of the second target pattern 32; discrete and parallel core layers 11 are formed on the pattern material layers of the first region 10A and the second region 10B, and the core layer 11 of the first region 10A further extends to cover the adjacent spacer 10C; a first sidewall 21 is formed on the sidewall of the core layer 11; after forming the first sidewall 21, the core layer 11 is removed; after removing the core layer 11, a second sidewall 22 is formed on the sidewall of the first sidewall 21; after forming the second sidewall 22, the first sidewall 21 is removed; after removing the first sidewall 21, the pattern material layer is patterned using the second sidewall 22 as a mask pattern to form a target pattern (not labeled), and the target pattern includes the first target pattern 31 formed in the pattern material layer of the first region 10A and the second target pattern 32 formed in the pattern material layer of the second region 10B.

[0020] Since the first sidewall 21 is formed in the same step, the line width dimensions of the first sidewall 21 are uniform, and the first sidewall 21 is used to define the line width of the target pattern. Therefore, the line width dimensions of the second target patterns 32 corresponding to the first sidewall 21 are uniform. Also, since the second sidewall 22 is formed in the same step, the line width dimensions of the second sidewall 22 are uniform, so the pitch between the second target patterns 32 corresponding to the second sidewall 22 is uniform. At the same time, the second sidewall 22 is formed on the opposite sidewall of the first sidewall 21, so one first sidewall 21 corresponds to the formation of two second sidewalls 22, which makes the number of the second sidewalls 22 in the region between adjacent first regions 10A an even number. The first sidewall 21 is used to define the space between adjacent target patterns. When patterning the pattern material layer using an even number of the second sidewalls 22 as a mask pattern, only an odd number of second target patterns 32 can be formed. Therefore, currently, only the second target patterns 32 with uniform line width dimensions and spacing dimensions and an odd number of patterns can be formed, which cannot meet more process requirements.

[0021] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a pattern material layer is formed, the substrate including alternately arranged first regions and second regions, the substrate further including a spacer located between adjacent first regions and second regions, the first region being configured to form a first target pattern, the second region being configured to form a plurality of second target patterns, along the arrangement direction of the first regions and second regions, the line width of the first target pattern being greater than the line width of the second target pattern; forming discrete and parallel core layers on the pattern material layer; forming first sidewalls on the sidewalls of the core layers; after forming the first sidewalls, removing the core layers; after removing the core layers, forming second sidewalls on the sidewalls of the first sidewalls; after forming the second sidewalls, removing the first sidewalls; after removing the first sidewalls, patterning the pattern material layer with the second sidewalls as a mask pattern, forming a first target pattern in the pattern material layer of the first region and forming second target patterns in the pattern material layer of the second region; wherein, the forming method further includes performing sidewall adjustment processing for adjusting one or both of the pitch and the number of the second target patterns, the sidewall adjustment processing including one or more of the following sidewall processing manners, the sidewall processing manners including: in the step of forming the first sidewalls, in the second region, making the first sidewalls on the opposite sidewalls of the core layer contact with each other; in the step of forming the second sidewalls, in the second region, making the second sidewalls on the opposite sidewalls of some of the first sidewalls contact with each other; before patterning the pattern material layer with the second sidewalls as a mask pattern after removing the first sidewalls, removing the second sidewalls located in the first region.

[0022] The forming method provided by the embodiment of the present invention further includes performing sidewall adjustment processing for adjusting one or both of the pitch and the number of the second target patterns. The sidewall processing method includes: in the step of forming the first sidewall, in the second region, making the first sidewalls on the opposite sidewalls of the core layer contact with each other; in the step of forming the second sidewall, in the second region, making the second sidewalls on the opposite sidewalls of a part of the first sidewalls contact with each other; after removing the first sidewall, before patterning the graphic material layer with the second sidewall as a mask pattern, removing the second sidewall in the first region. In the embodiment of the present invention, by making the first sidewalls on the opposite sidewalls of the core layer contact with each other, the line width of the formed second target pattern can be changed, and second target patterns with different line width dimensions meeting the requirements can be formed. By one or both of the adjustment methods of making the second sidewalls on the opposite sidewalls of a part of the first sidewalls contact with each other and removing the second sidewall in the first region, the number of the formed second target patterns can be changed, and an even number of the second target patterns can be obtained. Therefore, in the embodiment of the present invention, through the sidewall processing method, by selecting one or more sidewall processing methods, second target patterns with different pitches and / or an even number can be obtained, meeting different types of process requirements and improving the design freedom of the pitch and the number of the second target patterns.

[0023] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be made with reference to the accompanying drawings.

[0024] Figures 2 to 9 It is a schematic diagram corresponding to the first embodiment of the forming method of the semiconductor structure of the present invention.

[0025] Reference Figure 2 , Figure 2 is a cross-sectional view, providing a substrate (not shown in the figure), on which a graphic material layer 100 is formed. The substrate includes an alternately arranged first region 100A and a second region 100B, and the substrate further includes a spacer 100C located between adjacent first region 100A and second region 100B. The first region 100A is used to form a first target pattern, and the second region 100B is used to form a plurality of second target patterns. Along the arrangement direction of the first region 100A and the second region 100B, the line width of the first target pattern is greater than the line width of the second target pattern.

[0026] The substrate includes a substrate, and the substrate provides a process platform for subsequent processes.

[0027] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium. The substrate can also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0028] In this embodiment, the base may further include other structures, such as gate structures, doped regions, shallow trench isolation structures, etc.

[0029] In this embodiment, the forming method is used to form the interconnect grooves. Therefore, the patterned material layer 100 formed on the base includes a dielectric layer. The dielectric layer provides a platform basis for forming the interconnect grooves. The first target pattern and the second target pattern are both interconnect grooves formed in the dielectric layer. Specifically, the dielectric layer is an inter-metal dielectric layer.

[0030] In other embodiments, the forming method can also be used to form other types of patterns. For example, it is used to form a substrate and fins protruding from the substrate. That is, the target pattern formed is a fin. The patterned material layer may further include a fin material layer, and the base is the substrate.

[0031] It should be noted that other film layers at the bottom of the patterned material layer 100 are not shown in this embodiment.

[0032] Continue to refer to Figure 2 , and discrete and parallel core layers 110 are formed on the patterned material layer 100.

[0033] Subsequently, a first sidewall is formed on the sidewalls of the core layer 110. The core layer 110 plays a supporting role for the subsequent formation of the first sidewall. The line width of the core layer 110 and the spacing between adjacent core layers 110 are also used to define the spacing between adjacent first sidewalls.

[0034] Specifically, the steps of forming the core layer 110 include: forming a first sub-core layer 111 on the patterned material layer 100 in the first region 100A, and forming a second sub-core layer 112 on the patterned material layer 100 in the second region 100B. The first sub-core layer 111 and the second sub-core layer 112 constitute the core layer 110. Among them, along the arrangement direction of the first region 100A and the second region 100B, the first sub-core layer 111 extends to the same side and covers the adjacent spacer region 100C.

[0035] In the self-aligned quadruple patterning process, a first spacer is formed on the sidewalls of the core layer 110 subsequently. After removing the core layer 110, a second spacer is formed on the sidewalls of the first spacer. Therefore, four second spacers are correspondingly formed for one core layer 110. The second spacers are used to define the spacing between adjacent target patterns, and an additional target pattern is formed in the region between two adjacent core layers 110. The second spacers are used to define the spacing between adjacent target patterns, and an additional target pattern is formed in the region between two adjacent core layers 110. Therefore, if the number of core layers 110 is n, the total number of formed target patterns is 4*n - 1, that is to say, the total number of target patterns is odd. Therefore, in this embodiment, the first sub-core layer 111 extends to the same side and covers the adjacent spacer region 100C, then the first spacer on one side of the first sub-core layer 111 will be formed in the first region 100A, and the second spacer is formed on the sidewalls of the first spacer subsequently. This makes the second spacers on both sides of the first spacer be formed in the spacer region 100C and the first region 100A respectively, so as to isolate the first target pattern and the second target pattern. Subsequently, the second spacer located in the first region 100A is removed, changing the number of the second spacers, so that the two originally discrete target patterns become a first target pattern with a larger line width. Therefore, compared with the conventional self-aligned quadruple patterning process, each time the second spacer in the first region 100A is removed, one target pattern can be reduced, thereby changing the number of the second target patterns, so that the number of the second target patterns between adjacent first target patterns is an even number.

[0036] In this embodiment, in the step of forming the core layer 110 according to the target number of the second target patterns between adjacent first target patterns, the first sub-core layer 111 is formed in part of the first region 100A. Along the arrangement direction of the first region 100A and the second region 100B, the first sub-core layer 111 and the second sub-core layer 112 closest to the spacer region 100C extend to the same side and cover the adjacent spacer region 100C.

[0037] The first sub-core layer 111 is formed in a part of the first region 100A, and the core layer 110 is not formed in the remaining part of the first region 100A. Then, the spacer 100C adjacent to the remaining part of the first region 100A is extended and covered by the second sub-core layer 112 closest to the spacer 100C on the same side, so that a part of the first sidewall is formed in the first region 100A, and further a part of the second sidewall is formed in the first region 100A. Therefore, the second sidewall located in the first region 100A is removed later, the number of the second sidewalls is changed, and then a first target pattern with a larger line width is formed in the first region 100A, and at the same time, the number of the second target patterns is changed.

[0038] The material of the core layer 110 includes amorphous silicon, silicon nitride, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride or silicon carbon oxynitride. In this embodiment, the material of the core layer 110 is amorphous silicon.

[0039] In this embodiment, the line width of the first target pattern is a first preset line width d1 (as Figure 4 shown), the line width of the second target pattern is a second preset line width d2 (as Figure 4 shown), the interval between adjacent second target patterns 102 is a first preset interval p1 (as Figure 4 shown). In the step of forming the core layer 110, the line width d3 (as Figure 4 shown) of the second sub-core layer 112 is the sum of the second preset line width d2 and twice the first preset interval p1, and the interval p2 between adjacent core layers 110 is the sum of three times the second preset line width d2 and twice the first preset interval p1.

[0040] As Figure 9 shown, in the subsequent manufacturing process, taking the two discrete first sidewalls formed on both sides of the second sub-core layer 112 as a first sidewall group, after two discrete second sidewalls are formed on the sidewalls of the first sidewall, a pair of second sidewalls formed on the sidewalls opposite to the first sidewall in the first sidewall group are used as a second sidewall group. The second sidewall group is located in the region corresponding to the second sub-core layer 112. Then, using the second sidewall as a mask to pattern the graphic material layer 100, the region where part of the second target pattern is located is the region between the two second sidewalls in the second sidewall group. Therefore, the line width d3 of the second sub-core layer 112 is the sum of the second preset line width d2 and twice the first preset interval p1.

[0041] Refer to Figure 3 and Figure 4 , Figure 3 is a cross-sectional view, Figure 4 isFigure 3 Schematic diagram of the relative position relationship between the core layer and the first sidewall. A first sidewall 121 is formed on the sidewall of the core layer 110.

[0042] Wherein, Figure 4 In the figure, the positions of the subsequent first target pattern 101 and second target pattern 102 are marked with a dashed box.

[0043] The first sidewall 121 in the second region 100B is used to define the line width dimension of the second target pattern layer and serves as a support for the subsequent formation of the second sidewall. The line width of the first sidewall 121 and the spacing between adjacent first sidewalls 121 are also used to define the spacing between subsequent adjacent second sidewalls.

[0044] In this embodiment, the step of forming the first sidewall 121 includes: forming a first sidewall material layer (not shown in the figure) that conformally covers the top and sidewalls of the core layer 110 and the top of the pattern material layer 100, removing the first sidewall material layer located on the top of the core layer 110 and the top of the pattern material layer 100, and retaining the first sidewall material layer located on the sidewall of the core layer 110 as the first sidewall 121.

[0045] In this embodiment, using the atomic layer deposition process to form the first sidewall material layer is beneficial to improving the conformal coverage ability of the first sidewall material layer, is also beneficial to improving the thickness uniformity of the first sidewall material layer, and reduces the difficulty of precisely controlling the thickness of the first sidewall material layer, thereby correspondingly improving the line width uniformity of the first sidewall 121.

[0046] In this embodiment, an anisotropic dry etching process is used to remove the first sidewall material layer located on the top of the core layer 110 and the top of the pattern material layer. The anisotropic dry etching process has the characteristics of anisotropic etching, so that without a mask, the first sidewall material layer on the top of the core layer 110 and the top of the pattern material layer can be removed, while the first sidewall material layer on the sidewall of the core layer 110 is retained.

[0047] In this embodiment, in the step of forming the first sidewall 121, the first sidewall 121 is respectively formed in the first region 100A and the second region 100B.

[0048] Subsequently, a second sidewall needs to be formed on the sidewall of the first sidewall 121. Therefore, part of the second sidewall will be formed in the first region 100A, and the second sidewall in the first region 100A will be removed subsequently. Therefore, the number of the second sidewalls can be changed, and further the number of the second target patterns can be changed.

[0049] The material of the first sidewall 121 includes titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the first sidewall 121 is titanium oxide. Subsequently, after removing the core layer 110 and retaining the first sidewall 121, the titanium oxide material has a large etching selectivity with respect to the amorphous silicon material, which is beneficial for the first sidewall 121 to be retained in the subsequent step of removing the first core layer 110.

[0050] In this embodiment, in the step of forming the first sidewall 121, the line width of the first sidewall 121 is equal to the second preset line width d2.

[0051] As Figure 9 shown, in the subsequent manufacturing process, after forming a second sidewall on the sidewall of the first sidewall 121 and then removing the first sidewall 121, the interval dimension between the adjacent second sidewalls is equal to the line width dimension of the first sidewall 121. Then, using the second sidewall as an etching mask to pattern the graphic material layer, the interval dimension between the adjacent second sidewalls is equal to the line width dimension of the second target graphic. Therefore, the line width of the first sidewall 121 is equal to the second preset line width d2.

[0052] In this embodiment, after forming the first sidewall 121, the core layer 110 is removed.

[0053] Removing the core layer 110 exposes the sidewall of the first sidewall 121 in contact with the core layer 110, enabling the subsequent formation of second sidewalls on the two sidewall surfaces of the first sidewall 121.

[0054] In this embodiment, the core layer 110 is removed by a wet etching process. The wet etching process has a relatively low cost, simple operation steps, and can also achieve a large etching selectivity ratio.

[0055] Refer to Figure 5 and Figure 6 , Figure 5 is a cross-sectional view, Figure 6 is Figure 5 a schematic diagram of the relative positional relationship between the first sidewall and the second sidewall in . After removing the core layer 110, a second sidewall 122 is formed on the sidewall of the first sidewall 121.

[0056] Among them, Figure 5 the positions of the subsequent first target graphic 101 and second target graphic 102 are marked with a dashed box in .

[0057] The second sidewall 122 serves as an etching mask for the subsequent formation of the first target graphic 101 and the second target graphic 102.

[0058] In this embodiment, the steps of forming the second sidewall 122 include: forming a second sidewall material layer (not shown in the figure) that conformally covers the top and sidewalls of the first sidewall 121 and the top of the pattern material layer, removing the second sidewall material layer located on the top of the first sidewall 121 and the top of the pattern material layer, and retaining the second sidewall material layer located on the sidewalls of the first sidewall 121 as the second sidewall 122.

[0059] In this embodiment, an atomic layer deposition process is used to form the second sidewall material layer, which is beneficial to improving the conformal coverage ability of the second sidewall material layer, is also beneficial to improving the thickness uniformity of the second sidewall material layer, and reduces the difficulty of precisely controlling the thickness of the second sidewall material layer.

[0060] In this embodiment, an anisotropic dry etching process is used to remove the second sidewall material layer located on the top of the first sidewall 121 and the top of the pattern material layer. The anisotropic dry etching process has the characteristics of anisotropic etching, so that the second sidewall material layer on the top of the first sidewall 121 and the top of the pattern material layer can be removed without a mask, and at the same time, the second sidewall material layer on the sidewalls of the first sidewall 121 is retained.

[0061] In this embodiment, in the steps of forming the second sidewall 122, the second sidewall 122 is respectively formed in the first region 100A, the second region 100B, and the spacer region 100C, and the number of the second sidewalls 122 in the second region 100B is an odd number.

[0062] The number of the second sidewalls 122 in the second region 100B is an odd number, and the second sidewall 122 is also formed in the spacer region 100C. Then, the number of the second sidewalls 122 in the second region 100B and the adjacent two spacer regions 100C is still an odd number. The interval between the second sidewalls 122 in the second region 100B and the adjacent two spacer regions 100C is an even number. When patterning the pattern material layer with the second sidewall 122 as the mask pattern, in the second region 100B, the formed second target pattern corresponds to the interval between the second sidewalls 122. Therefore, the number of the formed second target patterns in the second region 100B is an even number, achieving the effect of changing the number of the second target patterns.

[0063] The material of the second sidewall 122 includes titanium oxide, titanium nitride, silicon nitride, aluminum oxide, or silicon oxide. Subsequently, the first sidewall 121 needs to be removed while the second sidewall 122 is retained. Therefore, in this embodiment, the material of the second sidewall 122 is different from that of the first sidewall 121, which is beneficial to improving the etching selectivity between the first sidewall 121 and the second sidewall 122, and further retaining the second sidewall 122 in the step of removing the first sidewall 121.

[0064] In this embodiment, after the second sidewall 122 is formed, the first sidewall 121 is removed.

[0065] Removing the first sidewall 121 prepares for subsequent etching of the graphic material layer using the second sidewall 122 as an etching mask.

[0066] In this embodiment, a wet etching process is used to remove the first sidewall 121. The wet etching process has a relatively low cost, simple operating steps, and can also achieve a large etching selectivity.

[0067] Reference Figure 7 , Figure 7 is a cross-sectional view. The forming method further includes performing a sidewall adjustment process for adjusting the number of the second target graphics so that the number of the second target graphics between adjacent first target graphics is an even number. The sidewall adjustment process includes the following sidewall processing methods, and the sidewall processing method includes: after removing the first sidewall 121 and before patterning the graphic material layer using the second sidewall 122 as a mask, removing the second sidewall 122 located in the first region 100A (as shown by the dashed circles in Figure 5 and Figure 6 ).

[0068] One first sidewall 121 corresponds to the formation of two second sidewalls 122. Since the first sub-core layer 111 extends to the same side and covers the adjacent spacer regions 100C, the first sidewall 121 on one side of the first sub-core layer 111 is formed in the first region 100A, and the first sidewall 121 on the other side is formed in the second region 100B. Correspondingly, after the second sidewalls 122 are formed on the sidewalls of the first sidewall 121, two second sidewalls 122 will be correspondingly formed at the position where the first sub-core layer 111 is located. One of the second sidewalls 122 is located in the first region 100A, and the other second sidewall 122 is located in the second region 100B. The number of the second sidewalls 122 in the second region 100B is an odd number, which can achieve the effect that the number of the formed second target graphics is an even number.

[0069] In this embodiment, along the arrangement direction of the first region 100A and the second region 100B, the first sub-core layer 111 and the second sub-core layer 112 closest to the spacer region 100C extend to the same side and cover the adjacent spacer region 100C. Therefore, in the second sidewall 122 formed at the position where the second sub-core layer 112 closest to the spacer region 100C is located, one of the second sidewalls 122 is located in the spacer region 100C, and in the second sidewall 122 formed at the position where the first sub-core layer 111 is located, one of the second sidewalls 122 is also located in the spacer region 100C. Therefore, the number of second sidewalls 122 in the region between the adjacent spacer regions 100C (i.e., in the second region 100B) is still an odd number.

[0070] With reference to Figure 8 and Figure 9 , Figure 8 is a cross-sectional view, Figure 9 which is Figure 8 a schematic diagram of the relative positional relationship between the first target pattern and the second target pattern in

[0071] After removing the first sidewall 121, the pattern material layer 100 is patterned using the second sidewall 122 as a mask, a first target pattern 101 is formed in the pattern material layer 100 of the first region 100A, and a second target pattern 102 is formed in the pattern material layer of the second region 100B.

[0072] In this embodiment, the anisotropic dry etching is used to pattern the pattern material layer. The anisotropic dry etching has good directionality, can obtain a quite accurate pattern conversion, is beneficial to improving the topography quality and dimensional accuracy of the target pattern, and reduces the damage to the pattern material layer between the target patterns while forming the target pattern.

[0073] In this embodiment, after patterning the pattern material layer using the second sidewall 122 as a mask, it further includes: forming a metal interconnect line (not shown in the figure) in the interconnect groove.

[0074] The metal interconnect line is used to realize the electrical connection between different devices.

[0075] In this embodiment, the material of the metal interconnect line includes copper.

[0076] It should be noted that in the actual process, according to actual requirements, the sidewall adjustment process is used to adjust one or both of the pitch and the number of the second target patterns 102. The sidewall adjustment process includes one or more of the following sidewall processing methods, and the sidewall processing methods include: in the step of forming the first sidewall 121, in the second region 100B, making the first sidewalls 121 on the opposite sidewalls of the core layer 110 contact each other; in the step of forming the second sidewall 122, in the second region 100B, making the second sidewalls 122 on the opposite sidewalls of a part of the first sidewalls 121 contact each other; after removing the first sidewall 121, before patterning the graphic material layer with the second sidewall 122 as a mask pattern, removing the second sidewall 122 in the first region 100A.

[0077] Among them, by making the first sidewalls 121 on the opposite sidewalls of the core layer 110 contact each other, the line width of the formed second target pattern 102 can be changed, and the second target pattern 102 with different line width sizes meeting the requirements can be formed. By one or both of the adjustment methods of making the second sidewalls 122 on the opposite sidewalls of a part of the first sidewalls 121 contact each other and removing the second sidewall 122 in the first region 100A, the number of the formed second target patterns 102 can be changed, and an even number of the second target patterns 102 can be obtained. Therefore, in the embodiments of the present invention, through the sidewall processing method, by selecting one or more sidewall processing methods, the second target pattern 102 with different pitches and / or an even number can be obtained, meeting different types of process requirements and improving the design freedom of the pitch and the number of the second target pattern 102.

[0078] In this embodiment, only the example of removing the second sidewall 122 in the first region 100A is used for illustration, so as to adjust the number of the second target patterns 102 through the sidewall adjustment process, and make the number of the second target patterns 102 between adjacent first target patterns 101 an even number.

[0079] It should also be noted that in other embodiments, the formed first target pattern and second target pattern can also be fins. Therefore, through the forming method described in this embodiment, fins with different pitches and numbers can be formed in the second region to meet the performance requirements of different devices.

[0080] Figure 10 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the second embodiment of the forming method of the semiconductor structure of the present invention.

[0081] The similarities between this embodiment and the foregoing embodiments will not be described herein again. The differences between this embodiment and the foregoing embodiments are as follows: The sidewall adjustment process adopted includes a sidewall treatment method, and the sidewall treatment method includes: in the step of forming the second sidewall 232, in the second region 200B, making the second sidewalls 232 located on the opposite sidewalls of a part of the first sidewall 231 contact each other.

[0082] In this embodiment, the sidewall adjustment process is used to adjust the number of the second target patterns 202 so that the number of the second target patterns 202 between adjacent first target patterns 201 is an even number.

[0083] Referring to Figure 10 , the step of forming the core layer 210 includes: forming a first sub-core layer 211 on the pattern material layer in a part of the first region 200A, and forming a second sub-core layer 212 on the pattern material layer in the second region 200B. The first sub-core layer 211 and the second sub-core layer 212 constitute the core layer 210. Among them, there are two second sub-core layers 212 spaced between two adjacent first sub-core layers 211, and along the arrangement direction of the first region 200A and the second region 200B, the first sub-core layer 211 extends to both sides and covers the adjacent spacer regions 200C.

[0084] During the formation of the second sidewall 232, partial contact between adjacent second sidewalls 232 is required. Therefore, the first sub-core layer 211 extends to both sides and covers the adjacent spacer regions 200C. The first sidewall 231 formed on the sidewall of the first sub-core layer 211 is formed in the second region 200B. Among the second sidewalls 232 formed on the sidewall of the first sidewall 231, one second sidewall 232 is formed in the second region 200B, and the other second sidewall 232 is formed in the spacer region 100C. The second sub-core layer 212 is located in the second region 200B, and there are two second sub-core layers 212 spaced between two adjacent first sub-core layers 211. That is, along the arrangement direction of the first region 200A and the second region 200B, in two adjacent first regions 100A, when a first sub-core layer 211 is formed in one of the first regions 200A, no first sub-core layer 211 is formed in the adjacent other first region 200A. Then, the second sidewall 232 formed relying on the second sub-core layer 212 is also formed in the second region 200B. Therefore, relying on the first sidewalls formed on the opposite sidewalls of the first sub-core layer 211 and the second sub-core layer 212, the second sidewalls 232 formed in the region between adjacent first sub-core layers 211 and second sub-core layers 212 can achieve the effect of contact, thus achieving the effect of reducing one second sidewall 232, and further making the number of second sidewalls 232 in the second region 100B odd.

[0085] Continue to refer to Figure 10 , in the step of providing the substrate, the line width of the second target pattern 202 is the second preset line width d2, and the interval between adjacent second target patterns 202 is the first preset interval p1.

[0086] In this embodiment, in the step of forming the core layer 210, in the second region 200B, the line width d3 of the second core layer 212 is the sum of the preset line width d2 and twice the preset interval p1.

[0087] In subsequent manufacturing processes, a pair of first sidewalls 231 formed on both sides of the second core layer 212 serve as a first sidewall group. After two second sidewalls 232 are formed on the sidewalls of the first sidewall 231, the second sidewalls 232 formed on the opposite sidewalls of the first sidewall 231 in the first sidewall group serve as a second sidewall group. The interval between the second sidewalls 232 in the second sidewall group corresponds to the second target pattern 202, and the position where the interval between the second sidewall group and the second sidewalls 232 in the second sidewall group is located coincides with the position where the second core layer 212 is located. Then, the line width d3 of the second core layer 212 is the sum of the preset line width d2 and twice the preset interval p1.

[0088] For the specific description of forming the core layer 210, reference may be made to the corresponding description in the foregoing embodiments, which will not be elaborated herein.

[0089] In this embodiment, in the step of forming the first sidewall 231, the first sidewall 231 on the sidewall of the first sub-core layer 211 has a first outer sidewall 233 facing away from the first sub-core layer 211, and the sidewall 231 on the sidewall of the second sub-core layer 212 has a second outer sidewall 234 facing away from the second sub-core layer 212.

[0090] In this embodiment, in the step of forming the first sidewall 231, the line width of the first sidewall 231 is equal to the second preset line width d2, and the distance between the first outer sidewall 233 and the second outer sidewall 234 is equal to the first preset interval p1.

[0091] Since a pair of second sidewalls 232 formed on the sidewall of the first sidewall 231 serve as a second sidewall group, the interval size between the second sidewalls 232 in the second sidewall group is equal to the line width of the first sidewall 231. Using the second sidewall 232 as a mask to pattern the graphic material layer, the interval between the second sidewalls 232 in the second sidewall group correspondingly forms the second target graphic 202. Therefore, the line width of the first sidewall 231 is equal to the line width of the second target graphic 202 (i.e., the second preset line width d2).

[0092] A second sidewall 232 is formed between the first outer sidewall 233 and the second outer sidewall 234. Then the distance between the first outer sidewall 233 and the second outer sidewall 234 is equal to the line width of the second sidewall 232. Using the second sidewall 232 as a mask to pattern the graphic material layer, the second sidewall 232 correspondingly forms the interval of the second target graphic 202 (i.e., the first preset interval p1). Then the line width of the second sidewall 232 is equal to the first preset interval p1. Therefore, the distance between the first outer sidewall 233 and the second outer sidewall 234 is equal to the first preset interval p1.

[0093] In this embodiment, the contacting second sidewalls 232 serve as the first type of second sidewalls, and the remaining independent second sidewalls 232 serve as the second type of second sidewalls. The distance between the first outer sidewall 233 and the second outer sidewall 234 is equal to half of the line width of the second type of second sidewalls, so that the line widths of the first type of second sidewalls and the second type of second sidewalls are equal.

[0094] In this embodiment, in the step of forming the second sidewall 232, in the second region 200B, the second sidewalls 232 on the opposite first outer sidewall 233 and second outer sidewall 234 are in contact.

[0095] In the traditional SAQP process, since the second sidewall is formed on the sidewall of the first sidewall, the number of the second sidewalls should be an even number. However, in this embodiment, the second sidewalls 232 on the opposite first outer sidewall 233 and second outer sidewall 234 are in contact, so that the number of the formed second sidewalls 232 is reduced by one, and the number of the second sidewalls 232 becomes an odd number. Therefore, taking the second sidewalls 232 as a mask, the number of the second target patterns 202 formed in the spaced area between the second sidewalls 232 is an even number, achieving the process effect of changing the number of the second target patterns 202.

[0096] It should be noted that in the actual process, by adjusting the distance between the first outer sidewall 233 and the second outer sidewall 234, the line width of the first type of second sidewall can be adjusted. Among them, in order to make the second sidewalls 232 between the first outer sidewall 233 and the second outer sidewall 234 in contact, the distance between the first outer sidewall 233 and the second outer sidewall 234 needs to be less than or equal to half of the line width of the second type of second sidewall.

[0097] For the specific description of the forming method in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, which will not be elaborated herein.

[0098] Figure 11 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the third embodiment of the forming method of the semiconductor structure of the present invention.

[0099] The same parts of this embodiment and the foregoing embodiment will not be elaborated herein. The difference between this embodiment and the foregoing embodiment lies in that the sidewall adjustment process adopted includes a sidewall treatment method, and the sidewall treatment method includes: in the step of forming the first sidewall 321, in the second region 300B, making the second sidewalls 322 on the opposite sidewalls of part of the first sidewall 321 in contact.

[0100] In this embodiment, the sidewall adjustment process is used to adjust the line width of the second target pattern 302, so that the second target patterns 302 between adjacent first target patterns 301 have different line widths.

[0101] Reference Figure 11 , the step of forming the core layer 310 includes: forming the core layer 310 on the pattern material layer in the first region 300A and the second region 300B, and along the arrangement direction of the first region 300A and the second region 300B, the core layer 310 in the first region 300A extends to both sides and covers the adjacent spaced areas 300C.

[0102] A pair of first sidewalls 321 formed on the sidewalls of the core layer 310 in the first region 300A serves as the first sidewall group. A pair of second sidewalls 322 formed on the opposite sidewalls of the first sidewalls 321 in the first sidewall group serves as the second sidewall group. The region where the second sidewalls 322 in the second sidewall group are located is within the region where the core layer 310 is located. Therefore, by extending the core layer 310 in the first region 300A to both sides and covering the adjacent spacer regions 300C, in the second sidewall group correspondingly formed by the core layer 310 in the first region 300A, the second sidewalls 322 respectively form the spacer regions 300C on both sides of the first region 300A.

[0103] In this embodiment, in the step of forming the core layer 310, the spacing between adjacent core layers 310 is the second preset spacing p2, and the line width of the core layer 310 in the second region 300B is the third preset line width d3; in the step of forming the second sidewall 322, the line width of the second sidewall 322 is the fourth preset line width d4, where the difference between the third preset line width d3 and twice the fourth preset line width d4 is not equal to the second preset spacing p2.

[0104] It should be noted that a first sidewall 321 will be formed on the sidewalls of the core layer 310 subsequently, and the first sidewalls 321 on the opposite sidewalls of adjacent core layers 310 are in contact. Therefore, the line width of the first sidewall 321 refers to the total line width of the contacting first sidewalls 321. That is to say, taking the contacting first sidewalls 321 as the first type of first sidewalls, the line width of the first sidewall 321 refers to the line width of the first type of first sidewalls.

[0105] Therefore, the spacing between adjacent core layers 310 is equal to the line width of the first sidewall 321, the line width of the first sidewall 321 is equal to the line width of part of the second target pattern 302, that is, the line width of part of the second target pattern 302 is equal to the second preset spacing p2, and the difference between the third preset line width d3 and twice the fourth preset line width d4 is the line width of the remaining second target pattern 302. The difference between the third preset line width d3 and twice the fourth preset line width d4 is not equal to the second preset spacing p2, so that the line width dimensions of the second target pattern 302 are not uniform, achieving the effect of adjusting the line width of the second target pattern 302.

[0106] In this embodiment, in the step of forming the first sidewall 321, the first sidewalls 321 on the opposite sidewalls of adjacent core layers 310 are in contact.

[0107] If it is in contact with the first sidewall 321 located on the opposite sidewalls of the adjacent core layer 310, then by adjusting the interval between the adjacent core layers 310 (i.e., the second preset interval p2), the total line width of the first sidewalls 321 in contact on the opposite sidewalls of the adjacent core layers 310 can be adjusted. That is, the line width of the first type of first sidewalls is adjustable. Subsequently, a second sidewall 322 is formed on the sidewalls of the in-contact first sidewalls 321. After patterning the graphic material layer using the second sidewall 322 as a mask, the line width of the second target pattern 302 corresponding to the formed line width of the first type of first sidewalls is adjustable. Therefore, the line width dimension of the second target pattern 302 can be adjusted, and it is easy to make the second target patterns 302 between the adjacent first target patterns 301 have different line widths.

[0108] For the specific description of the formation method described in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be elaborated here.

[0109] Figure 12 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the fourth embodiment of the formation method of the semiconductor structure of the present invention.

[0110] The similarities between this embodiment and the third embodiment will not be elaborated here. The difference between this embodiment and the foregoing embodiments is that the semiconductor structure is a SRAM.

[0111] Reference Figure 12 , in the step of providing the substrate, the substrate includes a plurality of SRAM cell regions. In the SRAM cell region, the number of the first regions 400A is one, and the second regions 400B are located on both sides of the first region 400A. Along the arrangement direction of the first region 400A and the second regions 400B, the second region 400B includes a first sub-region 400A1 and a second sub-region 400A2. The second sub-region 400A2 is located between the first sub-region 400A1 and the first region 400A1. The first target pattern 401 is used to form a power line, and the second target pattern 402 in the first sub-region 400A1 is used to form a ground line and a word line. The second target pattern 402 in the second sub-region 400A2 is used to form a bit line.

[0112] The SRAM structure includes a power line, a ground line, a word line, and a bit line. The ground line and the word line are in the same region and are located on both sides of the power line. The bit line is located between the power line and the ground line and word line region and is located on both sides of the power line.

[0113] In this embodiment, in the step of forming the core layer 410, in the second region 400B, the core layer 410 exposes the pattern material layer of the second sub-region 400A2.

[0114] In the second region 400B, the core layer 410 exposes the pattern material layer of the second sub-region 400A2, thereby providing a spatial position for forming the first sidewall 421 in the second region 400B, so that the second target patterns 402 can be respectively formed in the first sub-region 400A1 and the second sub-region 400A2.

[0115] In this embodiment, in the step of forming the core layer 410, the interval between adjacent core layers 410 is a second preset interval p2, and the line width of the core layer 410 located in the second region 400B is a third preset line width d3; in the step of forming the second sidewall 422, the line width of the second sidewall 422 is a fourth preset line width d4, wherein the difference between the third preset line width d3 and twice the fourth preset line width d4 is not equal to the second preset interval p2.

[0116] It should be noted that the first sidewall 421 will be formed on the sidewalls of the core layer 410 subsequently, and the first sidewalls 421 on the opposite sidewalls of adjacent core layers 410 are in contact with each other. Therefore, the line width of the first sidewall 421 refers to the total line width of the contacting first sidewalls 421. That is to say, taking the contacting first sidewalls 421 as the first type of first sidewalls, the line width of the first sidewall 421 refers to the line width of the first type of first sidewalls.

[0117] Therefore, the interval between adjacent core layers 410 is equal to the line width of the first sidewall 421, the line width of the first sidewall 421 is equal to the line width of part of the second target pattern 402, that is, the line width of part of the second target pattern 402 is equal to the second preset interval p2, and the difference between the third preset line width d3 and twice the fourth preset line width d4 is the line width of the remaining second target pattern 402. The difference between the third preset line width d3 and twice the fourth preset line width d4 is not equal to the second preset interval p2, so that the line width dimensions of the second target pattern 402 are not uniform, achieving the effect of adjusting the line width of the second target pattern 402.

[0118] It should be noted that in the actual process, before patterning the pattern material layer, part of the region of the first sub-region 400A1 will also be blocked by a blocking structure, so that discrete second target patterns 402 can be obtained in the direction perpendicular to the arrangement direction of the first region 400A and the second region 400B, and are respectively used to form ground wires and word lines.

[0119] For a detailed description of the formation method described in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, which will not be elaborated herein.

[0120] Figure 13 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the fifth embodiment of the method for forming a semiconductor structure of the present invention.

[0121] The similarities between this embodiment and the foregoing embodiments will not be elaborated herein. The differences between this embodiment and the foregoing embodiments are as follows: The sidewall adjustment process adopted includes a sidewall treatment method, and the sidewall treatment method includes: in the step of forming the first sidewall 521, in the second region 500B, making the first sidewalls 521 on the opposite sidewalls of the core layer 510 contact each other; after removing the first sidewall 521, before patterning the graphic material layer with the second sidewall 522 as a mask, removing the second sidewall 522 in the first region 500A.

[0122] In this embodiment, the sidewall adjustment process is used to adjust the line width of the second target pattern 502, so that the second target patterns 502 between adjacent first target patterns 501 have different line widths.

[0123] Reference Figure 13 , the step of forming the core layer 510 includes: forming the core layer 510 on the graphic material layer in the second region 500B, and along the arrangement direction of the first region 500A and the second region 500B, the core layer 510 closest to the spacer region 500C also extends to cover the spacer region 500C.

[0124] The core layer 510 closest to the spacer region 500C also extends to cover the spacer region 500C, so that the first sidewall 521 on the sidewall of the core layer 510 closest to the spacer region 500C can be formed in the first region 500A. Therefore, by subsequently removing the second sidewall 522 in the first region 500A, a first target pattern 501 with a larger line width can be obtained.

[0125] In this embodiment, in the step of forming the core layer 510, the interval between adjacent core layers 510 is the second preset interval p2, and the line width of the core layer 510 in the second region 500B is the third preset line width d3; in the step of forming the second sidewall 522, the line width of the second sidewall 522 is the fourth preset line width d4, where the difference between the third preset line width d3 and twice the fourth preset line width d4 is not equal to the second preset interval p2.

[0126] It should be noted that a first sidewall 521 will be formed on the sidewall of the core layer 510 subsequently, and the first sidewalls 521 located on the opposite sidewalls of adjacent core layers 310 are in contact with each other. Therefore, the line width of the first sidewall 521 refers to the total line width of the contacting first sidewalls 521. That is to say, taking the contacting first sidewalls 521 as the first type of first sidewalls, the line width of the first sidewall 521 refers to the line width of the first type of first sidewalls.

[0127] Therefore, the interval between adjacent core layers 510 is equal to the line width of the first sidewall 521. The line width of the first sidewall 521 is equal to the line width of part of the second target pattern 502, that is, the line width of part of the second target pattern 502 is equal to the second preset interval p2. The difference between the third preset line width d3 and twice the fourth preset line width d4 is the line width of the remaining second target pattern 502. The difference between the third preset line width d3 and twice the fourth preset line width d4 is not equal to the second preset interval p2, so that the line width dimensions of the second target pattern 502 are not uniform, achieving the effect of adjusting the line width of the second target pattern 502.

[0128] In this embodiment, in the step of forming the first sidewall 521, in the second region 500B, the first sidewalls 521 located on the opposite sidewalls of adjacent core layers 510 are in contact with each other.

[0129] In this embodiment, taking the contacting first sidewalls 521 as the first type of first sidewalls and the remaining independent first sidewalls 521 as the second type of first sidewalls. Since the first sidewalls 521 located on the opposite sidewalls of adjacent core layers 510 are in contact with each other, by adjusting the interval between adjacent core layers 510, the total line width of the contacting first sidewalls 521 located on the opposite sidewalls of adjacent core layers 510 can be adjusted, that is, the line width of the first type of first sidewalls is adjustable. Subsequently, a second sidewall 522 is formed on the sidewall of the contacting first sidewalls 521, and then the graphic material layer is patterned with the second sidewall 522 as a mask pattern. Then, the line width of the second target pattern 502 corresponding to the line width of the first type of first sidewalls is adjustable. Therefore, the line width dimensions of the second target pattern 502 can be adjusted, and it is easy to make the second target patterns 502 between adjacent first target patterns 501 have different line widths.

[0130] In this embodiment, after removing the first sidewall 521 and before patterning the graphic material layer with the second sidewall 522 as a mask, it further includes: removing the second sidewall 522 located in the first region (as Figure 6 shown).

[0131] Remove the second sidewall 522 located in the first region to ensure the requirement for a relatively large line width of the first target pattern 501.

[0132] For the specific description of the formation method in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be elaborated herein.

[0133] Figure 14 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the sixth embodiment of the method for forming a semiconductor structure according to the present invention.

[0134] The similarities between this embodiment and the foregoing embodiments will not be elaborated herein. The differences between this embodiment and the foregoing embodiments are as follows: The sidewall adjustment process adopted includes a sidewall treatment method, and the sidewall treatment method includes: in the step of forming the first sidewall 621, in the second region 600B, the first sidewalls 621 on the opposite sidewalls of the core layer 610 are made to contact each other; in the step of forming the second sidewall 622, in the second region 600B, the second sidewalls 622 on the opposite sidewalls of a part of the first sidewalls 621 are made to contact each other.

[0135] In this embodiment, the sidewall adjustment process is used to adjust the line width and quantity of the second target pattern 602, so that the quantity of the second target patterns 602 between adjacent first target patterns 601 is an even number, and the second target patterns 602 between adjacent first target patterns 601 have different line widths.

[0136] Reference Figure 14 , the step of forming the core layer 610 includes: forming the core layer 610 on the pattern material layer in the first region 600A and the second region 600B, and along the arrangement direction of the first region 600A and the second region 600B, the core layer 610 in the first region 600A extends to both sides and covers the adjacent spacer regions 600C.

[0137] A pair of first sidewalls 621 formed on the sidewalls of the core layer 610 in the first region 300A serve as a first sidewall group, and a pair of second sidewalls 622 formed on the opposite sidewalls of the first sidewalls 621 in the first sidewall group serve as a second sidewall group. The region where the second sidewalls 622 in the second sidewall group are located is within the region where the core layer 610 is located. Therefore, by making the core layer 610 in the first region 600A extend to both sides and cover the adjacent spacer regions 600C, the second sidewalls 622 in the second sidewall group corresponding to the core layer 610 in the first region 600A respectively form the spacer regions 600C on both sides of the first region 600A.

[0138] In this embodiment, in the step of forming the core layer 610, the interval between adjacent core layers 610 is a second preset interval p2, and the line width of the core layer 610 located in the second region 600B is a third preset line width d3; in the step of forming the second sidewall 622, the line width of the second sidewall 622 is a fourth preset line width d4, where the difference between the third preset line width d3 and twice the fourth preset line width d4 is not equal to the second preset interval p2.

[0139] It should be noted that a first sidewall 621 will be formed on the sidewalls of the core layer 610 later, and the first sidewalls 621 located on the opposite sidewalls of adjacent core layers 610 are in contact with each other. Therefore, the line width of the first sidewall 621 refers to the total line width of the in-contact first sidewalls 621. That is to say, taking the in-contact first sidewalls 621 as the first type of first sidewalls, the line width of the first sidewall 621 refers to the line width of the first type of first sidewalls.

[0140] Therefore, the interval between adjacent core layers 610 is equal to the line width of the first sidewall 621, the line width of the first sidewall 621 is equal to the line width of a part of the second target pattern 602, that is, the line width of a part of the second target pattern 602 is equal to the second preset interval p2, and the difference between the third preset line width d3 and twice the fourth preset line width d4 is the line width of the remaining second target pattern 602. The difference between the third preset line width d3 and twice the fourth preset line width d4 is not equal to the second preset interval p2, so that the line width dimensions of the second target pattern 602 are not uniform, achieving the effect of adjusting the line width of the second target pattern 602.

[0141] In this embodiment, in the step of forming the first sidewall 621, in the second region 600B, the first sidewalls 621 located on the opposite sidewalls of the core layer 610 are in contact with each other.

[0142] If the first sidewalls 621 located on the opposite sidewalls of adjacent core layers 610 are in contact with each other, then by adjusting the interval between adjacent core layers 610 (i.e., the second preset interval p2), the total line width of the first sidewalls 621 located on the opposite sidewalls of adjacent core layers 610 and in contact with each other can be adjusted, that is, the line width of the first type of first sidewalls is adjustable. Later, a second sidewall 622 is formed on the sidewalls of the in-contact first sidewalls 621, and after patterning the graphic material layer with the second sidewall 622 as a mask, the line width of the second target pattern 602 corresponding to the line width of the first type of first sidewalls is adjustable. Therefore, the line width dimensions of the second target pattern 602 can be adjusted, making it easy for the second target patterns 602 between adjacent first target patterns 601 to have different line widths.

[0143] In this embodiment, in the step of forming the second sidewall 622, in the second region 600B, the second sidewalls 622 located on the opposite sidewalls of a part of the first sidewall 621 are in contact with each other, and the number of the second sidewalls 622 is an odd number.

[0144] By bringing a part of the second sidewalls 622 into contact with each other, the number of the second sidewalls 622 can be adjusted. In this embodiment, in the second region 600B, when the number of the second sidewalls 622 is adjusted to be an odd number, the number of intervals between the second sidewalls 622 is an even number. When patterning the graphic material layer with the second sidewalls 622 as a mask pattern, the formed second target patterns 602 correspond to the intervals between the second sidewalls 622. Therefore, in the second region 600B, the number of the formed second target patterns 602 is an even number, achieving the effect of changing the number of the second target patterns 602.

[0145] In summary, this embodiment achieves the effect of adjusting the line width and the number of the second target patterns 602.

[0146] For the specific description of the forming method described in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be elaborated herein.

[0147] Figure 15 It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the seventh embodiment of the forming method of the semiconductor structure of the present invention.

[0148] The same parts of this embodiment and the foregoing embodiments will not be elaborated herein. The differences between this embodiment and the foregoing embodiments are as follows: The sidewall adjustment process adopted includes a sidewall treatment method, and the sidewall treatment method includes: in the step of forming the second sidewall 722, in the second region 700B, bringing the second sidewalls 722 located on the opposite sidewalls of a part of the first sidewall 721 into contact with each other; after removing the first sidewall 721 and before patterning the graphic material layer with the second sidewalls 722 as a mask pattern, removing the second sidewalls 722 located in the first region 700A.

[0149] The sidewall adjustment process is used to adjust the number of the second target patterns 702 so that the number of the second target patterns 702 between adjacent first target patterns 701 is an even number.

[0150] Reference Figure 15, the steps of forming the core layer 710 include: forming a first sub-core layer 711 on the graphic material layer in a part of the spacer region 700C, and forming a second sub-core layer 712 on the graphic material layer in the second region 700B. The first sub-core layer 711 and the second sub-core layer 712 constitute the core layer 710. Along the arrangement direction of the first region 700A and the second region 700B, the first sub-core layer 711 and the second sub-core layer 712 are alternately arranged, and the second sub-core layer 712 extends to the same side and covers the remaining adjacent spacer regions 700C.

[0151] A pair of first sidewalls 721 are formed on the sidewalls of the first sub-core layer 711 on the graphic material layer in a part of the spacer region 700C as a first sidewall group. A pair of second sidewalls 722 formed on the opposite sidewalls of the first sidewall 721 in the first sidewall group are used as a second sidewall group. Then, the second sidewall group is located in the isolation region 700C so that subsequent parts of the second sidewalls 722 are in contact.

[0152] Meanwhile, the first sub-core layer 711 covers the isolation region 700C, and the second sub-core layer 712 extends to the same side and covers the remaining adjacent spacer regions 700C. Then, the first sidewall 721 formed on the sidewall of the core layer 710 is formed in the first region 700A and the second region 700B. Furthermore, the second sidewall 722 formed on the sidewall of the first sidewall 721 is formed in the first region 700A and the second region 700B. Therefore, the second sidewall 722 located in the first region 700A is removed subsequently, the number of the second sidewalls 722 is changed, and thus a first target pattern 701 with a larger line width is formed in the first region 700A, and the number of the second target patterns 702 is changed at the same time.

[0153] In this embodiment, in the step of forming the first sidewall 721, the first sidewall 721 on the sidewall of the first sub-core layer 711 has an inner sidewall facing the first sub-core layer 711; in the step of forming the second sidewall 722, the second sidewalls 722 on the opposite inner sidewalls are in contact.

[0154] By making the second sidewalls 722 on the opposite inner sidewalls in contact, the number of the second sidewalls 722 can be reduced. Accordingly, the number of the second sidewalls 722 is adjusted, so as to adjust the number of intervals between the second sidewalls 722, and further adjust the number of the second target patterns 702 corresponding to the intervals.

[0155] For the specific description of the forming method in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be elaborated here.

[0156] Figure 16It is a schematic diagram of the relative positional relationship among the core layer, the first sidewall, the second sidewall, the first target pattern, and the second target pattern in the eighth embodiment of the method for forming a semiconductor structure according to the present invention.

[0157] The same parts of this embodiment and the foregoing embodiments will not be described herein again. The difference between this embodiment and the foregoing embodiments lies in that the sidewall adjustment process adopted includes a sidewall treatment method, and the sidewall treatment method includes: in the step of forming the first sidewall 821, in the second region 800B, the first sidewalls 821 located on the opposite sidewalls of the core layer 810 are brought into contact; in the step of forming the second sidewall 822, in the second region 800B, the second sidewalls 822 located on the opposite sidewalls of a part of the first sidewalls 821 are brought into contact; after removing the first sidewall 821 and before patterning the graphic material layer with the second sidewall 822 as a mask, the second sidewall 822 located in the first region 800A is removed.

[0158] In this embodiment, the sidewall adjustment process is used to adjust the number of the second target patterns 802 so that the number of the second target patterns 802 between adjacent first target patterns 801 is an even number.

[0159] Reference Figure 16 , the step of forming the core layer 810 includes: forming the core layer 810 on the graphic material layer in the second region 800B, and along the arrangement direction of the first region 800A and the second region 800B, the core layer 810 closest to the spacer 800C extends to cover the spacer 800C, and the number of the core layers 810 in the second region 800B is an odd number.

[0160] The core layer 810 closest to the spacer 800C extends to cover the spacer 800C. Then, a first sidewall 821 is formed on the side of the core layer 810 covering the spacer 800C, and then two second sidewalls 822 are formed according to this first sidewall 821, which are respectively located in the spacer 800C and the first region 800A. The second sidewall 822 located in the spacer 800C is used to define the spacer 800C in the graphic material layer, and the second sidewall 822 located in the first region 800A is removed later to adjust the number of the second target patterns 802.

[0161] Moreover, the number of the core layers 810 in the second region 800B is odd, so the gaps between the core layers 810 are even. In subsequent manufacturing processes, in the second region 800B, the first sidewalls 821 on the opposite sidewalls of the core layer 810 are in contact with each other, and the first sidewalls 821 on the opposite sidewalls of the core layer 810 are in contact with each other. Moreover, in the second region 800B, the first sidewalls 821 are formed in the gaps between the core layers 810, so the number of the first sidewalls 821 is even, and thus the gaps between the first sidewalls 821 are odd. Also, the second sidewalls 822 are formed in the gaps between the first sidewalls 821, so the number of the second sidewalls 822 is odd, and thus the gaps between the second sidewalls 822 are even. Moreover, the second target patterns 802 are formed in the gaps between the second sidewalls 822, so the number of the second target patterns 802 is even.

[0162] In this embodiment, in the step of forming the first sidewalls 821, in the second region 800B, the first sidewalls 821 on the opposite sidewalls of the core layer 810 are in contact with each other.

[0163] In the second region 800B, the first sidewalls 821 on the opposite sidewalls of the core layer 810 are in contact with each other. Then, by adjusting the intervals between adjacent core layers 810, the line widths of the first sidewalls 821 in contact with each other on the opposite sidewalls of adjacent core layers 810 can be adjusted, that is, the line widths of the first sidewalls 821 are adjustable. Subsequently, second sidewalls 822 are formed on the sidewalls of the contacting first sidewalls 821. After patterning the graphic material layer with the second sidewalls 822 as a mask, the line widths of the second target patterns 802 corresponding to the formed line widths of the first sidewalls 821 are adjustable. Therefore, the line width dimensions of the second target patterns 802 can be adjusted, and it is easy to make the second target patterns 802 between adjacent first target patterns 801 have different line widths.

[0164] In this embodiment, in the step of forming the second sidewalls 822, in the second region 800B, the second sidewalls 822 on the opposite sidewalls of the first sidewalls 821 are in contact with each other.

[0165] By making the second sidewalls 822 on the opposite sidewalls of some of the first sidewalls 821 in contact with each other, the number of the second sidewalls 822 is reduced. Accordingly, the number of the second sidewalls 822 is adjusted, so as to adjust the number of the intervals between the second sidewalls 822, and further adjust the number of the second target patterns 802 corresponding to the intervals.

[0166] For the specific description of the forming method in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be elaborated herein.

[0167] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate on which a pattern material layer is formed. The substrate includes alternately arranged first regions and second regions, and the substrate further includes a spacer located between adjacent first and second regions. The first region is for forming a first target pattern, and the second region is for forming a plurality of second target patterns. Along the arrangement direction of the first and second regions, the line width of the first target pattern is greater than that of the second target pattern. Forming a discrete and parallel arrangement of core layers on the pattern material layer. Forming a first sidewall on the sidewalls of the core layers. After forming the first sidewall, removing the core layers. After removing the core layers, forming a second sidewall on the sidewalls of the first sidewall. After forming the second sidewall, removing the first sidewall. After removing the first sidewall, patterning the pattern material layer using the second sidewall as a mask, forming a first target pattern in the pattern material layer of the first region, and forming a second target pattern in the pattern material layer of the second region. Wherein, the forming method further includes performing sidewall adjustment processing for adjusting one or both of the pitch and the number of the second target patterns. The sidewall adjustment processing includes one or more of the following sidewall processing methods, and the sidewall processing methods include: in the step of forming the first sidewall, in the second region, making the first sidewalls on the opposite sidewalls of the core layer contact each other; in the step of forming the second sidewall, in the second region, making the second sidewalls on the opposite sidewalls of part of the first sidewalls contact each other; before patterning the pattern material layer using the second sidewall as a mask after removing the first sidewall, removing the second sidewall located in the first region.

2. The method for forming a semiconductor structure according to claim 1, wherein The sidewall adjustment processing is used to adjust the number of the second target patterns so that the number of the second target patterns between adjacent first target patterns is an even number. The step of forming the core layers includes: forming a first sub-core layer on the pattern material layer in the first region and forming a second sub-core layer on the pattern material layer in the second region. The first sub-core layer and the second sub-core layer constitute the core layer. Wherein, along the arrangement direction of the first and second regions, the first sub-core layer extends to the same side and covers the adjacent spacer. In the step of forming the first sidewall, the first sidewall is respectively formed in the first region and the second region. In the step of forming the second sidewall, the second sidewall is respectively formed in the first region, the second region, and the spacer, and the number of the second sidewalls in the second region is an odd number. Before patterning the pattern material layer using the second sidewall as a mask after removing the first sidewall, it further includes: removing the second sidewall located in the first region.

3. The method for forming a semiconductor structure according to claim 2, wherein In the step of forming the core layer, a first sub-core layer is formed in part of the first region. Along the arrangement direction of the first region and the second region, the first sub-core layer and the second sub-core layer closest to the spacer extend to the same side and cover the adjacent spacer.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, Taking the line width of the first target pattern as the first preset line width, the line width of the second target pattern as the second preset line width, and the spacing between adjacent second target patterns as the first preset spacing. In the step of forming the core layer, the line width of the second sub-core layer is the sum of the second preset line width and twice the first preset spacing, and the spacing between adjacent core layers is the sum of three times the second preset line width and twice the first preset spacing. In the step of forming the first sidewall, the line width of the first sidewall is equal to the second preset line width.

5. The method for forming a semiconductor structure according to claim 1, wherein The sidewall adjustment process is used to adjust the number of the second target patterns so that the number of the second target patterns between adjacent first target patterns is an even number. The step of forming the core layer includes: forming a first sub-core layer on the pattern material layer in part of the first region, and forming a second sub-core layer on the pattern material layer in the second region. The first sub-core layer and the second sub-core layer constitute the core layer. Wherein, there are two second sub-core layers spaced between adjacent first sub-core layers, and along the arrangement direction of the first region and the second region, the first sub-core layer extends to both sides and covers the spacer. In the step of forming the first sidewall, the first sidewall located on the sidewall of the first sub-core layer has a first outer sidewall facing away from the first sub-core layer, and the first sidewall located on the sidewall of the second sub-core layer has a second outer sidewall facing away from the second sub-core layer. In the step of forming the second sidewall, in the second region, the second sidewalls located on the opposite first outer sidewall and second outer sidewall are in contact.

6. The method for forming a semiconductor structure according to claim 5, wherein, In the step of providing the substrate, the line width of the second target pattern is the second preset line width, and the spacing between adjacent second target patterns is the first preset spacing. In the step of forming the core layer, in the second region, the line width of the core layer is the sum of the second preset line width and twice the first preset spacing. In the step of forming the first sidewall, the line width of the first sidewall is equal to the second preset line width, and the distance between the first outer sidewall and the second outer sidewall is equal to the first preset spacing.

7. The method for forming a semiconductor structure according to claim 1, wherein, The sidewall adjustment process is used to adjust the line width of the second target pattern so that the second target patterns between adjacent first target patterns have different line widths. The step of forming the core layer includes: forming a core layer on the pattern material layer in the first region and the second region. Along the arrangement direction of the first region and the second region, the core layer located in the first region extends to both sides and covers the adjacent spacer. In the step of forming the first sidewall, the first sidewalls located on the opposite sidewalls of adjacent core layers are in contact.

8. The method for forming a semiconductor structure according to claim 7, wherein The semiconductor structure is SRAM. In the step of providing the substrate, the substrate includes a plurality of SRAM cell regions. In the SRAM cell region, the number of the first regions is one, and the second regions are located on both sides of the first region. Along the arrangement direction of the first region and the second regions, the second region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the first region. The first target pattern is used to form a power line, the second target pattern in the first sub-region is used to form a ground line and a word line, and the second target pattern in the second sub-region is used to form a bit line; In the step of forming the core layer, in the second region, the core layer exposes the pattern material layer of the second sub-region.

9. The method for forming a semiconductor structure according to claim 1, wherein, The sidewall adjustment process is used to adjust the line width of the second target pattern, so that the second target patterns between adjacent first target patterns have different line widths; The step of forming the core layer includes: forming a core layer on the pattern material layer in the second region, and along the arrangement direction of the first region and the second regions, the core layer closest to the spacer also extends to cover the spacer; In the step of forming the first sidewall, in the second region, the first sidewalls located on the opposite sidewalls of the adjacent core layers are in contact; After removing the first sidewall and before patterning the pattern material layer with the second sidewall as a mask pattern, it further includes: removing the second sidewall located in the first region.

10. The method for forming a semiconductor structure according to claim 1, wherein, The sidewall adjustment process is used to adjust the line width and the number of the second target patterns, so that the number of the second target patterns between adjacent first target patterns is an even number, and the second target patterns between adjacent first target patterns have different line widths; The step of forming the core layer includes: forming a core layer on the pattern material layer in the first region and the second regions, and along the arrangement direction of the first region and the second regions, the core layer located in the first region extends to both sides and covers the adjacent spacers; In the step of forming the first sidewall, in the second region, the first sidewalls located on the opposite sidewalls of the core layer are in contact; In the step of forming the second sidewall, in the second region, the second sidewalls located on the opposite sidewalls of some of the first sidewalls are in contact, and the number of the second sidewalls is an odd number.

11. The method for forming a semiconductor structure according to any one of claims 7 to 10, characterized in that, In the step of forming the core layer, the interval between adjacent core layers is a second preset interval, and the line width of the core layer located in the second region is a third preset line width; In the step of forming the second sidewall, the line width of the second sidewall is a fourth preset line width, wherein the difference between the third preset line width and twice the fourth preset line width is not equal to the second preset interval.

12. The method for forming a semiconductor structure according to claim 1, wherein, The sidewall adjustment process is used to adjust the number of the second target patterns, so that the number of the second target patterns between adjacent first target patterns is an even number; The steps of forming the core layer include: forming a first sub-core layer on the graphic material layer in part of the spacer region, and forming a second sub-core layer on the graphic material layer in the second region, wherein the first sub-core layer and the second sub-core layer constitute the core layer. Along the arrangement direction of the first region and the second region, the first sub-core layer and the second sub-core layer are arranged alternately, and the second sub-core layer extends to the same side and covers the remaining adjacent spacer regions; In the step of forming the first sidewall, the first sidewall located on the sidewall of the first sub-core layer has an inner sidewall facing the first sub-core layer; In the step of forming the second sidewall, the second sidewalls located on the opposite inner sidewalls are in contact with each other.

13. The method for forming a semiconductor structure according to claim 1, wherein, The sidewall adjustment process is used to adjust the number of the second target patterns so that the number of the second target patterns between adjacent first target patterns is an even number; The steps of forming the core layer include: forming a core layer on the graphic material layer in the second region, and along the arrangement direction of the first region and the second region, the core layer closest to the spacer region extends to cover the spacer region, and the number of core layers in the second region is an odd number; In the step of forming the first sidewall, in the second region, the first sidewalls located on the opposite sidewalls of the core layer are in contact with each other; In the step of forming the second sidewall, in the second region, the second sidewalls located on the opposite sidewalls of the first sidewall are in contact with each other.

14. The method for forming a semiconductor structure as claimed in claim 1, wherein, In the step of providing the substrate, the graphic material layer includes a dielectric layer, and both the first target pattern and the second target pattern are interconnect grooves formed in the dielectric layer; After patterning the graphic material layer with the second sidewall as a mask pattern, it further includes: forming metal interconnections in the interconnect grooves.

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