Memory and method of making the same

Abstract

The embodiments of the present disclosure disclose a memory and a manufacturing method thereof. The memory comprises: a first semiconductor structure and a second semiconductor structure which are stacked; and a first bonding structure comprising: a first conductive wire located between the first semiconductor structure and the second semiconductor structure and extending along a first direction; wherein the first conductive wire is electrically connected with the first semiconductor structure and the second semiconductor structure respectively; and the first direction is parallel to a horizontal plane.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a memory and a manufacturing method thereof. BACKGROUND

[0002] By improving process technology, circuit design, programming algorithm and manufacturing process, planar memory cells are scaled to smaller sizes. However, as the feature size of the memory cells approaches the lower limit, planar process and manufacturing technology become challenging and costly. Therefore, the storage density of planar memory cells approaches the upper limit.

[0003] Three-dimensional (3D) memory structures can solve the density limitation in planar memory cells, and by bonding a wafer with peripheral circuits and a wafer with memory cell arrays, the integration and bit density of the memory can be improved. At the bonding interface of the peripheral circuit wafer and the memory cell array wafer, a metal interconnection (via) is usually used for bonding, and the bonded metal interconnection is only used for connection, with low utilization. SUMMARY

[0004] According to a first aspect of embodiments of the present disclosure, a memory is provided, comprising:

[0005] a first semiconductor structure and a second semiconductor structure stacked;

[0006] a first bonding structure comprising: a first conductive line located between the first semiconductor structure and the second semiconductor structure and extending along a first direction; wherein the first conductive line is electrically connected to the first semiconductor structure and the second semiconductor structure respectively; and the first direction is parallel to a horizontal plane.

[0007] According to a second aspect of embodiments of the present disclosure, a manufacturing method of a memory is provided, comprising:

[0008] forming a first semiconductor structure;

[0009] forming a first conductive line extending along a first direction on the first semiconductor structure; wherein the first conductive line is electrically connected to the first semiconductor structure; and the first direction is parallel to a horizontal plane;

[0010] forming a second semiconductor structure;

[0011] aligning and bonding the first semiconductor structure and the second semiconductor structure, the first conductive line being electrically connected to the second semiconductor structure; wherein the first conductive line is located between the first semiconductor structure and the second semiconductor structure.

[0012] In the embodiments of the present disclosure, by setting the first bonding structure, since the first bonding structure includes the first conductive wire, and the first conductive wire is electrically connected with the first semiconductor structure and the second semiconductor structure respectively, the first semiconductor structure and the second semiconductor structure can be electrically connected through the first bonding structure to realize the interaction of electrical signals.

[0013] Since the first conductive wire extends along the first direction, the first semiconductor structure and the second semiconductor structure are bonded through the conductive wire, at the bonding position, a part of the bonding structure (i.e. the first bonding structure) can be used for connection, and the other part of the bonding structure (other bonding structures except the first bonding structure) can be used for other purposes, which is beneficial to improve the utilization rate of the bonding structure at the bonding position. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a schematic diagram of a manufacturing method of a memory according to an exemplary embodiment;

[0015] Figure 2 is a structural schematic diagram of a memory according to an embodiment of the present disclosure Figure 1 ;

[0016] Figure 3 is a structural schematic diagram of a memory according to an embodiment of the present disclosure Figure 2 ;

[0017] Figure 4 is a structural schematic diagram of a memory according to an embodiment of the present disclosure Figure 3 ;

[0018] Figure 4 is a structural schematic diagram of a memory according to an embodiment of the present disclosure Figure 6 ;

[0019] Figure 5 is a structural schematic diagram of a memory according to an embodiment of the present disclosure Figure 7 ;

[0020] Figure 1 is a flowchart of a manufacturing method of a memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The technical solutions of the present disclosure will be further described in detail below in combination with the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0022] The present disclosure will be described in more detail with reference to the drawings in the following paragraphs. The advantages and features of the present disclosure will become apparent from the following description with reference to the drawings. It is to be noted that the drawings are in extremely simplified form and are not drawn to precise scale, and are merely used to facilitate, clarify and aid in the understanding of the embodiments of the present disclosure.

[0023] It can be understood that the meaning of "on", "above" and "upper" of the present disclosure should be interpreted in the broadest way, so that the meaning of "on" not only means the meaning of "on" something with no intervening features or layers therebetween (i.e. directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0024] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily have to describe a particular order or sequence.

[0025] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope less than the scope of the underlying or overlying structure. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0026] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0027] Figure 1 is a schematic diagram of a method of manufacturing a memory 30 according to an example embodiment. Referring to Figure 2 the method of manufacturing includes at least the following steps:

[0028] Step 1: Form a first semiconductor structure 10; wherein the first semiconductor structure 10 includes a peripheral circuit and a first interconnection structure; the first interconnection structure includes a bottom metal 11 and a bottom via 12; the bottom via 12 is electrically connected to the peripheral circuit (not shown in the figure) through the bottom metal 11.

[0029] The first semiconductor structure 10 includes a wafer carrying a plurality of dies or a single die. For example, a wafer provided with a peripheral circuit or a die provided with a peripheral circuit.

[0030] Step two: forming a second semiconductor structure 20; wherein the second semiconductor structure 20 comprises a memory cell array and a second interconnection structure; the second interconnection structure comprises a top metal 21 and a top via 22; the top via 22 is electrically connected with the memory cell array (not shown in the figure) through the top metal 21.

[0031] The second semiconductor structure 20 comprises a wafer carrying a plurality of dies or a single die. For example, a wafer provided with a memory cell array or a die provided with a memory cell array.

[0032] Step two: bonding the first semiconductor structure 10 and the second semiconductor structure 20 so that the lower interconnection via 12 and the top via 22 are in contact.

[0033] By performing the above steps one to three, a three-dimensional memory 30 can be formed. The memory 30 comprises the bonded first semiconductor structure 10 and the second semiconductor structure 20. For example, a bonded wafer and wafer, a bonded wafer and die, or a bonded die and die.

[0034] As the number of memory cell array stack layers in the second semiconductor structure 20 increases, more circuit elements (such as resistors or capacitors, etc.) are required in the peripheral circuit in the first semiconductor structure 10 to meet the operation requirements of the memory cell array. For example, more capacitors are required in the back-end-of-line process of the memory 30.

[0035] However, at the bonding position of the first semiconductor structure 10 and the second semiconductor structure 20, the bonded lower interconnection via 12 and the top via 22 are only used as connections, and it is difficult to use them for other purposes, such as electrode plates of capacitors, alignment marks, or sealing structures, etc., resulting in low utilization of the lower interconnection via 12 and the top via 22.

[0036] In addition, providing more circuit elements in the first semiconductor structure 10 will increase the difficulty of routing of the memory 30, and even require additional substrate area to provide these circuit elements, resulting in an increase in the planar size of the first semiconductor structure 10, and further resulting in an increase in the planar size of the three-dimensional memory 30, limiting the improvement of the integration of the three-dimensional memory 30.

[0037] Therefore, the embodiments of the present disclosure provide a memory.

[0038] Figure 2 is a structural schematic diagram of a memory 100 according to an embodiment of the present disclosure. Referring to Figure 2 As shown in the figure, the memory 100 comprises:

[0039] a stacked first semiconductor structure and a second semiconductor structure;

[0040] The first bonding structure 110 comprises: a first conductive line 111 located between the first semiconductor structure and the second semiconductor structure and extending along a first direction y; wherein the first conductive line 111 is electrically connected with the first semiconductor structure and the second semiconductor structure respectively; and the first direction y is parallel to a horizontal plane.

[0041] In an example, the first semiconductor structure comprises the peripheral circuit 101, and the second semiconductor structure comprises a memory cell array. In another example, the first semiconductor structure comprises the memory cell array, and the second semiconductor structure comprises the peripheral circuit 101. For ease of description, the following will be described by taking the first semiconductor structure comprising the peripheral circuit 101 and the second semiconductor structure comprising the memory cell array as an example, but the present disclosure is not limited thereto.

[0042] The peripheral circuit 101 comprises a plurality of transistors, for example, P-type transistors or N-type transistors. Each transistor comprises a source, a channel, a drain and a gate.

[0043] In an example, the source and the drain of the transistor are arranged side by side along the first direction y, the channel is located between the source and the drain, and the gate is located above the channel. In another example, the source and the drain of the transistor are arranged side by side along the second direction x, the channel is located between the source and the drain, and the gate is located above the channel. In another example, the source and the drain of the transistor are arranged side by side along the third direction z, the channel is located between the source and the drain, and the gate is located on the sidewall of the channel.

[0044] In the present disclosure, the first direction is denoted by “y”, the second direction is denoted by “x”, and the third direction is denoted by “z”. The first direction and the second direction are parallel to a horizontal plane, and the third direction is perpendicular to the horizontal plane, which will not be described again hereinafter.

[0045] In some embodiments, the first semiconductor structure further comprises: a first conductive structure located between the peripheral circuit 101 and the first conductive line 111, for electrically connecting the peripheral circuit 101 and the first conductive line 111.

[0046] In an example, the first conductive line 111 is electrically connected with the source of the transistor through the first conductive structure. In another example, the first conductive line 111 is electrically connected with the drain of the transistor through the first conductive structure. In another example, the first conductive line 111 is electrically connected with the gate of the transistor through the first conductive structure.

[0047] In some embodiments, the second semiconductor structure further comprises: a second conductive structure located between the first conductive line 111 and a memory cell array (not shown in the figure), for electrically connecting the first conductive line 111 and the memory cell array. For example, the memory cell array comprises a memory string, and the second conductive structure is used for electrically connecting the first conductive line 111 and the memory string.

[0048] Although in the present example, the memory 100 comprises the peripheral circuit 101, the first conductive structure, the first conductive line 111, the second conductive structure and the memory cell array which are sequentially stacked along the positive direction of the z-axis, in other examples, the memory comprises the memory cell array, the second conductive structure, the first conductive line 111, the first conductive structure and the peripheral circuit 101 which are sequentially stacked along the positive direction of the z-axis.

[0049] The first conductive line 111 extends along the first direction y, and the projection of the first conductive line 111 on the xy plane comprises a polygon. For example, a rectangle, a square, a rhombus, a “cross” shape, a “T” shape or a “L” shape, etc.

[0050] The constituent material of the first conductive line 111 comprises a conductive material, for example, any one of tungsten, copper, aluminum, platinum, nickel, titanium, titanium nitride, tantalum nitride or tungsten nitride or a combination thereof.

[0051] In the embodiments of the present disclosure, by arranging the first bonding structure, since the first bonding structure comprises the first conductive line and the first conductive line is electrically connected with the first semiconductor structure and the second semiconductor structure respectively, the first semiconductor structure and the second semiconductor structure can be electrically connected through the first bonding structure to realize the interaction of electrical signals.

[0052] Since the first conductive line extends along the first direction, the first semiconductor structure and the second semiconductor structure are bonded through the conductive line, at the bonding position, a part of the bonding structure (i.e. the first bonding structure) can be used for connection, and the other part of the bonding structure (other bonding structures except the first bonding structure) can be used for other purposes, which is conducive to improving the utilization rate of the bonding structure at the bonding position.

[0053] In some embodiments, referring to Figure 2 As shown in the figure, the first bonding structure 110 further comprises:

[0054] The second conductive line 112 is located between the first conductive line 111 and the second semiconductor structure and extends along the first direction y; wherein the side of the second conductive line 112 which is relatively close to the first conductive line 111 is in contact with the first conductive line, and the side of the second conductive line 112 which is relatively far away from the first conductive line 111 is electrically connected with the second semiconductor structure.

[0055] In some embodiments, the second conductive structure is located between the second conductive line 112 and the second semiconductor structure and is used to electrically connect the second conductive line 112 and the second semiconductor structure. For example, the second conductive structure is used to electrically connect the second conductive line 112 and the memory cell array.

[0056] Although in the present example, the memory 100 comprises the peripheral circuit 101, the first conductive structure, the first conductive line 111, the second conductive line 112, the second conductive structure and the memory cell array which are sequentially stacked along the positive direction of the z-axis, in other examples, the memory comprises the memory cell array, the second conductive structure, the second conductive line 112, the first conductive line 111, the first conductive structure and the peripheral circuit 101 which are sequentially stacked along the positive direction of the z-axis.

[0057] The second conductive line 112 extends along the first direction y, and the contact between the second conductive line 112 and the first conductive line 111 comprises that the second conductive line 112 is in full contact or partial contact with the first conductive line 111.

[0058] In some embodiments, the projection of the second conductive line 112 on the xy plane comprises a polygon. For example, a rectangle, a square, a diamond, a "cross" shape, a "T" shape or a "L" shape, etc.

[0059] In some embodiments, the memory 100 comprises a plurality of first bonding structures 110 arranged in an array. Two adjacent first bonding structures 110 are electrically insulated. For example, the plurality of first bonding structures 110 are arranged side by side along the second direction x, and / or the plurality of first bonding structures 110 are arranged side by side along the first direction y.

[0060] The constituent material of the second conductive line 112 comprises a conductive material, for example, any one of tungsten, copper, aluminum, platinum, nickel, titanium, titanium nitride, tantalum nitride or tungsten nitride or a combination thereof. The constituent material of the first conductive line 111 and the second conductive line 112 can be the same or different.

[0061] In the embodiments of the present disclosure, by arranging the second conductive line in contact with the first conductive line, since the first conductive line and the second conductive line both extend along the first direction, the first semiconductor structure and the second semiconductor structure are bonded by two conductive lines, at the bonding position, a part of the bonded conductive line can be used for connection, and another part of the bonded conductive line (other conductive lines in addition to the first conductive line and the second conductive line) can be used for other purposes, which is conducive to improving the utilization rate of the bonding structure at the bonding position.

[0062] In some embodiments, the memory 100 comprises: a first region 100a and a second region 100b arranged side by side along the second direction x; wherein the first bonding structure 110 is located in the first region 100a; the second direction x is parallel to the horizontal plane, and the second direction x intersects the first direction y;

[0063] The memory 100 further comprises: a plurality of second bonding structures 120 located in the second region 100b and arranged side by side along the second direction x;

[0064] The electrically insulating dielectric structure is located between the two adjacent second bonding structures 120; wherein one of the two adjacent second bonding structures is electrically connected with the first semiconductor structure or the second semiconductor structure, and the other of the two adjacent second bonding structures is electrically connected with the ground terminal;

[0065] The second bonding structure 120 includes:

[0066] The third conductive line 121 extends along the first direction y;

[0067] The fourth conductive line 122 is located between the third conductive line 121 and the second semiconductor structure and extends along the first direction y, and the fourth conductive line 122 is in contact with the third conductive line 121.

[0068] Referring to Figure 2 As shown in the figure, the two second bonding structures 120 are arranged side by side along the second direction x and can serve as two electrode plates of a capacitor, and the electrically insulating dielectric structure (not shown in the figure) located between the two second bonding structures 120 can serve as a dielectric layer of the capacitor, so that the two second bonding structures 120 and the dielectric structure located between the two second bonding structures 120 can constitute a capacitor.

[0069] In an example, one of the two adjacent second bonding structures 120 is electrically connected with the memory cell array, and the other of the two adjacent second bonding structures 120 is electrically connected with the ground terminal (not shown in the figure). The capacitor composed of the two adjacent second bonding structures 120 and the dielectric structure located between the two adjacent second bonding structures 120 is electrically connected with the memory cell array, which is conducive to meeting the power supply requirements of the memory cell array, for example, ensuring the stability of the input electrical signal (e.g., voltage or current) of the memory cell array.

[0070] In an example, referring to Figure 3 As shown in the figure, one of the two adjacent second bonding structures 120 is electrically connected with the peripheral circuit, and the other of the two adjacent second bonding structures 120 is electrically connected with the ground terminal. The capacitor composed of the two adjacent second bonding structures 120 and the dielectric structure located between the two adjacent second bonding structures 120 is electrically connected with the peripheral circuit, which is conducive to ensuring the stability of the output electrical signal (e.g., voltage or current) of the peripheral circuit and avoiding the intensity of the electrical signal being too large to cause damage to the memory cell array.

[0071] Here, the two second bonding structures 120 arranged side by side along the second direction x are taken as an example for description, and the number of the second bonding structures 120 arranged side by side along the second direction x is not limited to two, but can also be three, four or even more.

[0072] The third conductive line 121 and the fourth conductive line 122 both extend along the first direction y, and the contact between the third conductive line 121 and the fourth conductive line 122 includes that the third conductive line 121 is in full contact or partial contact with the fourth conductive line 122.

[0073] In some embodiments, the third conductive line 121 is in the same horizontal plane as the first conductive line 111, and / or the fourth conductive line 122 is in the same horizontal plane as the second conductive line 112.

[0074] When the third conductive line 121 is in the same horizontal plane as the first conductive line 111, the wiring window of the third conductive line 121 and the first conductive line 111 can be increased, and the wiring difficulty of the third conductive line 121 and the first conductive line 111 can be reduced. When the fourth conductive line 122 is in the same horizontal plane as the second conductive line 112, the wiring window of the fourth conductive line 122 and the second conductive line 112 can be increased, and the wiring difficulty of the fourth conductive line 122 and the second conductive line 112 can be reduced. In this way, it is beneficial to reduce the wiring difficulty in the memory and reduce the difficulty of the wiring manufacturing process in the memory.

[0075] In other embodiments, the third conductive line 121 and the first conductive line 111 can also be in different horizontal planes, and the fourth conductive line 122 and the second conductive line 112 can also be in different horizontal planes, which are not limited in the present disclosure.

[0076] The constituent material of the third conductive line 121 and the fourth conductive line 122 includes a conductive material, for example, any one of tungsten, copper, aluminum, platinum, nickel, titanium, titanium nitride, tantalum nitride, or tungsten nitride, or a combination thereof. The constituent material of the third conductive line 121 and the fourth conductive line 122 can be the same or different.

[0077] The constituent material of the dielectric structure includes an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0078] The included angle between the first direction y and the second direction x includes an acute angle, a right angle, or an obtuse angle. Preferably, the included angle between the first direction y and the second direction x is a right angle, that is, the first direction y and the second direction x are perpendicular.

[0079] In the embodiments of the present disclosure, by arranging the second bonding structure in the second region of the memory, since the second bonding structure includes the third conductive line and the fourth conductive line in contact, the third conductive line and the fourth conductive line extend along the first direction, that is, the second bonding structure extends along the first direction. The extended second bonding structure can be used as an electrode plate of a capacitor, which increases the application scenarios of the bonding structure and is beneficial to improve the utilization rate of the bonding structure.

[0080] By setting multiple second bonding structures and a medium structure between two adjacent second bonding structures, at least one capacitor can be formed. By using part of the bonding structure at the bonding interface as a capacitor, the occupation of the peripheral circuit substrate area can be reduced, the layout of the memory can be optimized, and the integration of the memory can be improved.

[0081] In addition, since one electrode plate of the capacitor (i.e., one of the two adjacent second bonding structures) is electrically connected to the first semiconductor structure or the second semiconductor structure, and the other electrode plate (i.e., the other of the two adjacent second bonding structures) is electrically connected to the ground terminal, the stability of the power supply of the memory can be ensured.

[0082] Further, since the first semiconductor structure and the second semiconductor structure are respectively located on the upper and lower sides of the second bonding structure, the winding can be separated from the upper and lower sides of the second bonding structure, which can reduce the winding difficulty of the electrical connection between the capacitor and the first semiconductor structure or the capacitor and the second semiconductor structure, and can reduce the probability of short circuit in the memory.

[0083] In some embodiments, referring to Figure 3 The first semiconductor structure further includes: multiple first contact pillars 151 arranged side by side along the first direction y and located between the peripheral circuit 101 and the first conductive line 111; one end of the first contact pillar 151 is electrically connected to the peripheral circuit 101; the other end of the first contact pillar 151 is electrically connected to the first conductive line 111.

[0084] The second semiconductor structure further includes: multiple second contact pillars 161 arranged side by side along the first direction y and located between the second conductive line 112 and the memory cell array; one end of the multiple second contact pillars 161 is electrically connected to the second conductive line 112; the other end of the second contact pillar 161 is electrically connected to the memory cell array.

[0085] Referring to Figure 3 The first conductive line 111 extending along the first direction y can be electrically connected to the multiple first contact pillars 151 arranged side by side along the first direction y, and the second conductive line 112 extending along the first direction y can be electrically connected to the multiple second contact pillars 161 arranged side by side along the first direction y. In this way, the wiring difficulty of the memory can be reduced.

[0086] Here, the two adjacent first contact pillars 151 are spaced apart by an insulating material (e.g., silicon oxide or silicon nitride), and the number of the first contact pillars 151 connected to the first conductive line 111 can be Figure 3 as shown in FIG. 1B, which can also be other numbers, such as 2, 3, 5, or even more.

[0087] Similarly, the number of the second contact pillars 161 connected to the second conductive line 112 can be 4 as shown in FIG. 1, or other numbers, such as 2, 3, 5 or even more. Figure 4 The number of the second contact pillars 161 connected to the second conductive line 112 can be 4 as shown in FIG. 1, or other numbers, such as 2, 3, 5 or even more.

[0088] In some embodiments, the number of the first contact pillars 151 connected to the first conductive line 111 is the same as the number of the second contact pillars 161 connected to the second conductive line 112. For example, 4 first contact pillars 151 are connected to the first conductive line 111, and 4 second contact pillars 161 are connected to the second conductive line 112.

[0089] In some embodiments, the number of the first contact pillars 151 connected to the first conductive line 111 is the same as the number of the second contact pillars 161 connected to the second conductive line 112. For example, 4 first contact pillars 151 are connected to the first conductive line 111, and 4 second contact pillars 161 are connected to the second conductive line 112.

[0090] The first conductive line 111 is electrically connected to the peripheral circuit 101 (e.g., transistors) through the first contact pillars 151 and the lower interconnection lines 152, and the second conductive line 112 is electrically connected to the memory cell array (e.g., memory string) through the second contact pillars 161 and the upper interconnection lines 162.

[0091] The constituent materials of the first contact pillars 151, the second contact pillars 161, the lower interconnection lines 152 and the upper interconnection lines 162 include conductive materials, such as any one or a combination of tungsten, copper, aluminum, platinum, nickel, titanium, titanium nitride, tantalum nitride or tungsten nitride. The constituent materials of any two of the first contact pillars 151, the second contact pillars 161, the lower interconnection lines 152 and the upper interconnection lines 162 are the same or different.

[0092] In the embodiments of the present disclosure, by arranging a plurality of first contact pillars between the peripheral circuit and the first conductive line, and a plurality of second contact pillars between the memory cell array and the second conductive line, the design of the layout in the existing memory can be compatible, and the manufacturing process of the layout in the existing memory can be compatible.

[0093] In addition, by connecting a plurality of first contact pillars to the first conductive line, and connecting a plurality of second contact pillars to the second conductive line, the difficulty of the layout in the memory can be reduced, thereby reducing the difficulty of the manufacturing process of the layout in the memory.

[0094] In some embodiments, the length of the two adjacent second bonding structures 120 in the first direction y is the same, and the ends of the two adjacent second bonding structures 120 in the first direction y are spaced.

[0095] Referring to Figure 4 Fig. 2, the length of the first second bonding structure 120-1 and the second second bonding structure 120-2 in the first direction y is the same, and the ends of the first second bonding structure 120-1 and the second second bonding structure 120-2 in the first direction y are spaced, so that a plurality of second bonding structures 120 arranged in the x direction are staggered.

[0096] In some embodiments, the memory 100 further comprises: the first metal line 125 and the second metal line 126 are arranged side by side along the first direction y, and the plurality of second bonding structures are located between the first metal line 125 and the second metal line 126; wherein the first metal line 125 is electrically connected with the 2N-1th second bonding structure; the second metal line 126 is electrically connected with the 2Nth second bonding structure; N is a positive integer greater than or equal to 1.

[0097] Here, the first metal line 125 and the second metal line 126 both extend along the second direction x. It can be understood that by sequentially numbering the plurality of second bonding structures as 1, 2, 3, 4, …, arranging the first metal line 125 to be electrically connected with the odd-numbered second bonding structures, and arranging the second metal line 126 to be electrically connected with the even-numbered second bonding structures, a "interdigital" shaped capacitor array as shown in Figure 5 Fig. 2 can be formed, so that the capacitance value of the capacitor can be increased.

[0098] In actual production, the number of second bonding structures connected by the first metal line 125 or the second metal line 126 can be reasonably set according to the demand for the capacitance value, and the present disclosure does not make further limitations here.

[0099] In some embodiments, the first conductive line 121 is located in the first dielectric layer 123, and the two adjacent first conductive lines 121 are spaced by the first dielectric layer 123; the second conductive line 122 is located in the second dielectric layer 124, and the two adjacent second conductive lines 122 are spaced by the second dielectric layer 124. It can be understood that the above-mentioned dielectric structure includes the first dielectric layer 123 and the second dielectric layer 124.

[0100] The composition material of the first metal line 125 and the second metal line 126 includes a conductive material, for example, any one or a combination of tungsten, copper, aluminum, platinum, nickel, titanium, titanium nitride, tantalum nitride, and tungsten nitride. The composition material of the first metal line 125 and the second metal line 126 is the same or different.

[0101] The constituent material of the first dielectric layer 123 and the second dielectric layer 124 includes an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, etc.

[0102] In the embodiments of the present disclosure, by setting the lengths of the two adjacent second bonding structures in the first direction to be the same and the end portions of the two adjacent second bonding structures in the first direction to have a spacing, a plurality of second bonding structures arranged in the second direction can be formed, and by reasonable wiring, a "interdigital" capacitor array can be formed, which is conducive to meeting the demand of the storage cell array for capacitors and better ensuring the stability of power supply of the storage cell array.

[0103] In some embodiments, referring to Figure 5 As shown in the figure, the memory 100 further includes: a third region 100c, which is arranged side by side with the first region 100a and the second region 100b along the second direction x; wherein the second region 100b is located between the first region 100a and the third region 100c.

[0104] The memory 100 further includes: a third bonding structure 130, which is located in the third region 100c.

[0105] The third bonding structure 130 includes:

[0106] The fifth conductive line 131 extends along the first direction y.

[0107] The sixth conductive line 132 is located between the fifth conductive line 131 and the second semiconductor structure and extends along the first direction y, and the fifth conductive line 131 is in contact with the sixth conductive line 132; wherein the projection of the fifth conductive line 131 on the third region 100c covers the projection of the sixth conductive line 132 on the third region 100c.

[0108] The first region 100a can be a core area of the memory 100, for example, an area provided with a peripheral circuit and a storage cell array, and the first bonding structure 110 is located in the first region 100a. The second region 100b can be a step area of the memory 100, for example, an area provided with a word line contact, and the second bonding structure 120 is located in the second region 100b. The third region 100c can be part of a cutting area of the memory 100, for example, an area provided with a bonding alignment mark, and the third bonding structure 130 is located in the third region 100c.

[0109] Figure 5A partial top view of the memory 100 is shown, the projection of the sixth conductive line 132 in the third region 100c is within the projection of the fifth conductive line 131 in the third region 100c. In other embodiments, the projection of the sixth conductive line 132 in the third region 100c coincides with the projection of the fifth conductive line 131 in the third region 100c. In other embodiments, the projection of the sixth conductive line 132 in the third region 100c covers the projection of the fifth conductive line 131 in the third region 100c.

[0110] In some embodiments, the fifth conductive line 131 is in the same horizontal plane as the first conductive line 111 and the third conductive line 121, and / or the sixth conductive line 132 is in the same horizontal plane as the second conductive line 112 and the fourth conductive line 122.

[0111] When the fifth conductive line 131 is in the same horizontal plane as the first conductive line 111 and the third conductive line 121, the wiring window of the fifth conductive line 131 with the first conductive line 111 and the third conductive line 121 can be increased, and the wiring difficulty of the fifth conductive line 131 with the first conductive line 111 and the third conductive line 121 can be reduced. When the sixth conductive line 132 is in the same horizontal plane as the second conductive line 112 and the fourth conductive line 122, the wiring window of the sixth conductive line 132 with the second conductive line 112 and the fourth conductive line 122 can be increased, and the wiring difficulty of the sixth conductive line 132 with the second conductive line 112 and the fourth conductive line 122 can be reduced. In this way, it is beneficial to reduce the wiring difficulty in the memory and reduce the difficulty of the wiring manufacturing process in the memory.

[0112] In other embodiments, the fifth conductive line 131 and the first conductive line 111 and the third conductive line 121 can also be in different horizontal planes, and the sixth conductive line 132 and the second conductive line 112 and the fourth conductive line 122 can also be in different horizontal planes, which is not limited by the present disclosure.

[0113] In some embodiments, the fifth conductive line 131 and the sixth conductive line 132 are used for alignment when the memory cell array wafer and the peripheral circuit wafer are bonded. That is, the third bonding structure can be used as an alignment structure of the memory 100, increasing the application scenarios of the bonding structure and being beneficial to improve the utilization rate of the bonding structure.

[0114] In some embodiments, the memory 100 includes: a plurality of third bonding structures 130 arranged side by side along the second direction x, and adjacent two third bonding structures are electrically insulated. It can be understood that by arranging a plurality of third bonding structures, it is beneficial to better align the memory cell array wafer and the peripheral circuit wafer when bonding, and improve the alignment accuracy of the bonding.

[0115] The constituent material of the fifth conductive line 131 and the sixth conductive line 132 includes a conductive material, for example, any one of tungsten, copper, aluminum, platinum, nickel, titanium, titanium nitride, tantalum nitride, or tungsten nitride, or a combination thereof.

[0116] In the embodiments of the present disclosure, by arranging the third bonding structure in the third region of the memory, the third bonding structure can be used as an alignment structure of the memory, which increases the application scenarios of the bonding structure and is beneficial to improve the utilization of the bonding structure.

[0117] Since the third bonding structure includes the contacting fifth conductive line and sixth conductive line, the fifth conductive line and the sixth conductive line extend along the first direction, which is beneficial to increase the alignment window of the bonding of the memory cell array wafer and the peripheral circuit wafer, and the projection of the fifth conductive line in the third region covers the projection of the sixth conductive line in the third region, which can ensure that the overlapping area between the fifth conductive line and the sixth conductive line is large, that is, the alignment deviation between the memory cell array wafer and the peripheral circuit wafer after bonding is small, which is beneficial to improve the alignment accuracy of the memory cell array wafer and the peripheral circuit wafer.

[0118] In addition, the fifth conductive line and the sixth conductive line extend along the same direction as the first conductive line, the second conductive line, the third conductive line, and the fourth conductive line, which is beneficial to reduce the difficulty of memory wiring.

[0119] In some embodiments, referring to FIG. 1, the memory 100 further includes a fourth region 100d arranged at least around the first region 100a; Figure 6

[0120] Referring to FIG. 1, the memory 100 further includes a fourth bonding structure 140 located in the fourth region 100d. Figure 5

[0121] The fourth bonding structure 140 includes:

[0122] The first sealing structure 141 extends along the first direction y and includes a first surface 141a and a second surface 141b; the first surface 141a is relatively close to the first semiconductor structure, and the second surface 141b is relatively far away from the first semiconductor structure; along the second direction x, the width of the second surface 141b is greater than the width of the first surface 141a.

[0123] The second sealing structure 142 is located between the first sealing structure 141 and the second semiconductor structure and extends along the first direction y, and includes a third surface 142b and a fourth surface 142a; the third surface 142b is relatively close to the first sealing structure 141, and the fourth surface 142a is relatively far away from the first sealing structure 141; along the second direction, the width of the third surface 142b is greater than the width of the fourth surface 142a; the third surface 142b is in contact with the second surface 141b.​​

[0124] The fourth region 100d can be a region in the memory 100 provided with a sealing structure. In one example, the fourth region 100d is provided around the first region 100a, in another example, the fourth region 100d is provided around the first region 100a and the second region 100b, as shown in Figure 6 .

[0125] Figure 6 A partial cross-sectional view of the memory 100 is shown, the first sealing structure 141 and the second sealing structure 142 extend along the first direction y, the first sealing structure 141 and the second sealing structure 142 contact includes: the first sealing structure 141 and the second sealing structure 142 completely contact or partially contact.

[0126] Along the second direction x, the width of the second surface 141b is greater than the width of the first surface 141a, the first sealing structure 141 can be formed as shown in Figure 6 , along the second direction x, the width of the third surface 142b is greater than the width of the fourth surface 142a, the second sealing structure 142 can be formed as shown in Figure 3 , by setting the width of the bonding contact surface of the first sealing structure 141 and the second sealing structure 142 to be larger, it is beneficial to better align the first sealing structure 141 and the second sealing structure 142 when bonding, and improve the sealing performance of the fourth bonding structure.

[0127] In other embodiments, along the second direction x, the width of the second surface 141b can be less than or equal to the width of the first surface 141a; the width of the third surface 142b can be less than or equal to the width of the fourth surface 142a.

[0128] In some embodiments, the first sealing structure 141 is located in the same horizontal plane as the first conductive wire 111, the third conductive wire 121 and the fifth conductive wire 131, and / or the second sealing structure 142 is located in the same horizontal plane as the second conductive wire 112, the fourth conductive wire 122 and the sixth conductive wire 132.

[0129] When the first sealing structure 141 is located at the same horizontal plane as the first conductive line 111, the third conductive line 121 and the fifth conductive line 131, the wiring window of the first sealing structure 141 and the first conductive line 111, the third conductive line 121 and the fifth conductive line 131 can be increased, and the wiring difficulty of the first sealing structure 141 and the first conductive line 111, the third conductive line 121 and the fifth conductive line 131 can be reduced. When the second sealing structure 142 is located at the same horizontal plane as the second conductive line 112, the fourth conductive line 122 and the sixth conductive line 132, the wiring window of the second sealing structure 142 and the second conductive line 112, the fourth conductive line 122 and the sixth conductive line 132 can be increased, and the wiring difficulty of the second sealing structure 142 and the second conductive line 112, the fourth conductive line 122 and the sixth conductive line 132 can be reduced. In this way, the wiring difficulty in the memory and the difficulty of the wiring manufacturing process in the memory can be reduced.

[0130] In other embodiments, the first sealing structure 141 and the first conductive line 111, the third conductive line 121 and the fifth conductive line 131 can also be located at different horizontal planes, and the second sealing structure 142 and the second conductive line 112, the fourth conductive line 122 and the sixth conductive line 132 can also be located at different horizontal planes.

[0131] In some embodiments, the memory 100 further comprises: a third sealing structure 143 located in the fourth region 100d and extending along the first direction y; wherein the first sealing structure 141 is located between the third sealing structure 143 and the second sealing structure 142.

[0132] A fourth sealing structure 144 is located in the fourth region 100d and extends along the first direction y; wherein the second sealing structure 142 is located between the first sealing structure 141 and the fourth sealing structure 144.

[0133] It can be understood that the third sealing structure 143, the first sealing structure 141, the second sealing structure 142 and the fourth sealing structure 144 arranged in sequence along the z direction can well seal the memory cell array and the peripheral circuit, and reduce the probability of damage to the peripheral circuit and the memory cell array.

[0134] The composition material of the first sealing structure and the second sealing structure includes metal or dielectric material, for example, tungsten, copper, aluminum, platinum, nickel, titanium, titanium nitride, tantalum nitride, tungsten nitride, silicon oxide, silicon nitride or silicon oxynitride, etc.

[0135] In the embodiments of the present disclosure, by arranging the fourth bonding structure in the fourth region, the fourth bonding structure can be used as a sealing structure of the memory, which increases the application scenarios of the bonding structure and is beneficial to improve the utilization rate of the bonding structure.

[0136] Since the fourth bonding structure comprises the contacted first sealing structure and the second sealing structure, the first sealing structure and the second sealing structure extend along the first direction, and along the second direction, the width of the second surface of the first sealing structure is greater than the width of the first surface of the first sealing structure, and the width of the third surface of the second sealing structure is greater than the width of the fourth surface of the second sealing structure, which is conducive to increasing the alignment accuracy of the first sealing structure and the second sealing structure.

[0137] In addition, the first sealing structure and the second sealing structure extend in the same direction as the first conductive wire and the second conductive wire, which is conducive to reducing the difficulty of memory wiring.

[0138] In some embodiments, the memory 100 comprises: a plurality of first bonding structures 110 arranged side by side along a first direction y; wherein along the first direction y, the length of the first conductive wire 111 is greater than or equal to a first preset value; and / or, along the first direction y, the length of the second conductive wire 112 is greater than or equal to a second preset value.

[0139] It should be noted that if the size of the first conductive wire / second conductive wire is too small, it will affect the transmission (for example, delay) of the electrical signal between the peripheral circuit and the memory cell array, and the alignment window is reduced when the first conductive wire and the second conductive wire are bonded. Here, by setting the length of the first conductive wire to be greater than or equal to the first preset value; and / or, the length of the second conductive wire is greater than or equal to the second preset value, while ensuring the transmission of the electrical signal between the peripheral circuit and the memory cell array, the alignment accuracy of the first conductive wire and the second conductive wire when bonded is higher.

[0140] In a specific example, along the first direction y, the length of the first conductive wire 111 is greater than or equal to 300 nanometers; and / or, along the first direction y, the length of the second conductive wire 112 is greater than or equal to 300 nanometers. It should be understood that in this example, the first preset value can be 300 nanometers, and the second preset value can be 300 nanometers, that is, the first preset value and the second preset value are the same. In other examples, the first preset value and the second preset value can be different. In actual production, the above-mentioned first preset value and the second preset value can be selected according to actual conditions.

[0141] In the embodiments of the present disclosure, by setting the length of the first conductive wire / second conductive wire along the first direction to be greater than or equal to 300 nanometers, it is conducive to ensuring good electrical connection between the peripheral circuit and the memory cell array, and can increase the alignment window of the first conductive wire and the second conductive wire when bonded, which is conducive to improving the alignment accuracy of the first conductive wire and the second conductive wire when bonded.

[0142] In some embodiments, the spacing between two adjacent first conductive wires 111 is greater than or equal to a third preset value; and / or, the spacing between two adjacent second conductive wires 112 is greater than or equal to a fourth preset value.

[0143] It should be noted that when the plurality of first bonding structures are arranged side by side along the first direction, the spacing between two adjacent first bonding structures is too small, which may cause a risk of short circuit. Here, by setting the spacing between the two adjacent first conductive wires 111 to be greater than or equal to a third preset value; and / or, the spacing between the two adjacent second conductive wires 112 is greater than or equal to a fourth preset value, the probability of short circuit between the two adjacent first conductive wires 111 and / or the two adjacent second conductive wires 112 is reduced.

[0144] In a specific example, the spacing between the two adjacent first conductive wires 111 is greater than or equal to 300 nanometers; and / or, the spacing between the two adjacent second conductive wires 112 is greater than or equal to 300 nanometers. It should be understood that in this example, the third preset value can be 300 nanometers, and the fourth preset value can be 300 nanometers, that is, the third preset value and the fourth preset value are the same. In other examples, the third preset value and the fourth preset value can be different. In actual production, the third preset value and the fourth preset value can be selected according to actual conditions.

[0145] In the embodiments of the present disclosure, by setting the spacing between the two adjacent first conductive wires / the two adjacent second conductive wires to be greater than or equal to 300 nanometers, the probability of short circuit of the memory is reduced.

[0146] In some embodiments, the sum of the projection areas of the plurality of first bonding structures 110 in the first region 100a is less than 10% of the first region 100a. When the projection area of the plurality of first bonding structures in the first region is too large (for example, greater than or equal to 10%), bubbles are prone to occur at the bonding interface of the first bonding structure 110 (that is, the contact surface of the first conductive wire and the second conductive wire), resulting in a decrease in the bonding quality of the first bonding structure 110.

[0147] In the embodiments of the present disclosure, by setting the sum of the projection areas of the plurality of first bonding structures in the first region to be less than 10% of the first region, the density distribution of the plurality of first bonding structures at the bonding interface can be controlled, the probability of bubbles occurring at the bonding interface of the first bonding structure is reduced, and the quality of the first bonding structure is improved.

[0148] In some embodiments, the first bonding structure 110 further includes: a conductive column located between the first conductive wire 111 and the second semiconductor structure and extending along a third direction z; wherein the side of the conductive column relatively close to the first conductive wire 111 is in contact with the first conductive wire 111, and the side of the conductive column relatively far away from the first conductive wire 111 is electrically connected with the second semiconductor structure; the third direction z is perpendicular to the horizontal plane.

[0149] The conductive column extends along the third direction z, and the contact between the conductive column and the first conductive line 111 includes complete contact or partial contact between the conductive column and the first conductive line 111. The composition material of the conductive column includes a conductive material, for example, any one of tungsten, copper, aluminum, platinum, nickel, titanium, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof. The composition materials of the conductive column and the first conductive line 111 can be the same or different.

[0150] In some embodiments, the projection of the conductive column on the xy plane includes a circle, an ellipse, or the like.

[0151] With Figure 7 Unlike the second conductive line 112 shown in the figure, in this example, the first conductive line 111 is bonded with a conductive column extending along the third direction z, that is, the first semiconductor structure (for example, the peripheral circuit) and the second semiconductor structure (for example, the memory cell array) can also be bonded in the manner of one conductive line (extending along the first direction) and one conductive column (extending along the third direction).

[0152] In some embodiments, the memory 100 includes a three-dimensional memory.

[0153] In some embodiments, the three-dimensional memory includes a 3D NAND memory.

[0154] Figure 2 is a flowchart of a manufacturing method of a memory according to an embodiment of the present disclosure, and the manufacturing method at least includes the following steps:

[0155] S100: forming a first semiconductor structure;

[0156] S200: forming a first conductive line extending along a first direction on the first semiconductor structure; wherein the first conductive line is electrically connected with the first semiconductor structure; and the first direction is parallel to a horizontal plane.

[0157] S300: forming a second semiconductor structure;

[0158] S400: aligning and bonding the first semiconductor structure and the second semiconductor structure, and the first conductive line is electrically connected with the second semiconductor structure; wherein the first conductive line is located between the first semiconductor structure and the second semiconductor structure.

[0159] In step S100, the first semiconductor structure may include a first substrate and peripheral circuitry (not shown in the figure), which includes multiple transistors, such as P-type transistors or N-type transistors. Each transistor includes a source, a drain, and a gate. The first substrate may be doped using ion implantation or ion diffusion processes to form multiple doped regions. For example, the first doped region serves as the source of the transistor, the second doped region serves as the drain of the transistor, and the first substrate located between the first and second doped regions serves as the channel of the transistor. The gate of the transistor is formed on the channel using a thin-film deposition process. Here, the first semiconductor structure includes a first substrate and peripheral circuitry. Optionally, after bonding the first semiconductor structure and the second semiconductor structure, the first substrate may be thinned or removed.

[0160] In step S200, a first dielectric material layer can be formed on the peripheral circuit using a thin-film deposition process. A first trench extending along a first direction is formed in the first dielectric material layer by photolithography and etching processes. The first trench is located in a first region, and a conductive material is used to fill the first trench to form a... Figure 3 or Figure 2 The first conductive line 111 is shown.

[0161] In step S300, the second semiconductor structure may include a second substrate and a memory cell array. The memory cell array can be formed on the second substrate through processes such as thin film deposition, photolithography, and etching. The memory cell array includes alternately stacked insulating layers (e.g., silicon oxide) and conductive layers (e.g., tungsten metal), as well as multiple memory strings penetrating the insulating and conductive layers. Here, the second semiconductor structure includes a second substrate and a memory cell array. Optionally, after bonding the first semiconductor structure and the second semiconductor structure, the second substrate may be thinned or removed.

[0162] In step S400, the first semiconductor structure and the second semiconductor structure are aligned and bonded using a bonding process, and the first conductive line is electrically connected to the second semiconductor structure after bonding.

[0163] In this embodiment of the present disclosure, a first conductive line extending in a first direction is formed on a first semiconductor structure and electrically connected to the first semiconductor structure. The first semiconductor structure and the second semiconductor structure are aligned and bonded, so that the first conductive line and the second semiconductor structure are electrically connected. The first semiconductor structure and the second semiconductor structure can be electrically connected through the first conductive line and the second conductive line to realize the interaction of electrical signals.

[0164] Since the first conductive lines extend along the first direction, the first semiconductor structure and the second semiconductor structure are bonded by the conductive lines, at the bonding position, a part of the bonding structure (i.e. the bonded first conductive lines) can be used as connection, and another part of the bonding structure (other than the bonded first conductive lines) can be used as other use, which is conducive to improving the utilization of the bonding structure at the bonding position.

[0165] In some embodiments, before bonding the first semiconductor structure and the second semiconductor structure, the above manufacturing method further comprises:

[0166] forming a second conductive line extending along the first direction on the second semiconductor structure; wherein the second conductive line is electrically connected with the second semiconductor structure;

[0167] The above aligning and bonding the first semiconductor structure and the second semiconductor structure comprises:

[0168] aligning and bonding the first conductive line and the second conductive line, the first conductive line being in contact with the second conductive line; wherein the second conductive line is between the first conductive line and the second semiconductor structure.

[0169] Exemplarily, before bonding the first semiconductor structure and the second semiconductor structure, a second dielectric material layer can be formed on the memory cell array by a thin film deposition process, a second trench extending along the first direction can be formed in the second dielectric material layer by a photolithography and etching process, the second trench is located in the first region, and the second conductive line 112 as shown in Figure 3 or Figure 2 can be formed by filling the second trench with a conductive material. By aligning and bonding the first conductive line and the second conductive line, the first conductive line is in contact with the second conductive line, since the first conductive line and the second conductive line both extend along the first direction, the first semiconductor structure and the second semiconductor structure are bonded by two conductive lines, at the bonding position, a part of the bonded conductive lines can be used as connection, and another part of the bonded conductive lines (other than the first conductive line and the second conductive line) can be used as other use, which is conducive to improving the utilization of the bonding structure at the bonding position.

[0170] In some embodiments, the memory comprises: a first region and a second region arranged side by side along a second direction; wherein the first conductive line and the second conductive line are located in the first region; the second direction is parallel to the horizontal plane, and the second direction intersects the first direction;

[0171] After forming the first semiconductor structure, and before bonding the first conductive line and the second conductive line, the above manufacturing method further comprises:

[0172] forming a plurality of third conductive lines arranged side by side along the second direction on the first semiconductor structure, wherein the third conductive lines are located in the second region and extend along the first direction;

[0173] forming a first dielectric layer between two adjacent third conductive lines;

[0174] after forming the second semiconductor structure and before bonding the first conductive lines and the second conductive lines, the method further comprises:

[0175] forming a plurality of fourth conductive lines arranged side by side along the second direction on the second semiconductor structure, wherein the fourth conductive lines are located in the second region and extend along the first direction;

[0176] forming a second dielectric layer between two adjacent fourth conductive lines;

[0177] aligning and bonding the third conductive lines and the fourth conductive lines while aligning and bonding the first conductive lines and the second conductive lines, the third conductive lines being in contact with the fourth conductive lines;

[0178] aligning and bonding the first dielectric layer and the second dielectric layer, the first dielectric layer being in contact with the second dielectric layer.

[0179] In an example, a plurality of third trenches arranged side by side along the second direction are formed in the first dielectric material layer by a lithography and etching process, the third trenches are located in the second region, the third trenches extend along the first direction, the third trenches are filled with a conductive material to form the third conductive lines 121 as shown in FIG. 1C or FIG. 1D, the first dielectric material layer between two adjacent third trenches is the first dielectric layer. Figure 4 or Figure 2 In an example, the third trenches are arranged side by side along the second direction with the first trenches, the third trenches and the first trenches can be formed simultaneously by etching or can be formed separately by etching. The first conductive lines and the third conductive lines are arranged side by side along the second direction, the first conductive lines and the third conductive lines can be formed simultaneously by filling or can be formed separately by filling.

[0180] In an example, a plurality of fourth trenches arranged side by side along the second direction are formed in the second dielectric material layer by a lithography and etching process, the fourth trenches are located in the second region, the fourth trenches extend along the first direction, the fourth trenches are filled with a conductive material to form the fourth conductive lines 122 as shown in FIG. 2C or FIG. 2D, the second dielectric material layer between two adjacent fourth trenches is the second dielectric layer.

[0181] In an example, the third trenches are arranged side by side along the second direction with the first trenches, the third trenches and the first trenches can be formed simultaneously by etching or can be formed separately by etching. The first conductive lines and the third conductive lines are arranged side by side along the second direction, the first conductive lines and the third conductive lines can be formed simultaneously by filling or can be formed separately by filling. Figure 4 or Figure 5 In an example, the third trenches are arranged side by side along the second direction with the first trenches, the third trenches and the first trenches can be formed simultaneously by etching or can be formed separately by etching. The first conductive lines and the third conductive lines are arranged side by side along the second direction, the first conductive lines and the third conductive lines can be formed simultaneously by filling or can be formed separately by filling.

[0182] In an example, the fourth groove is arranged in parallel with the second groove along the second direction, and the fourth groove and the second groove can be formed simultaneously or separately.

[0183] In an example, the first substrate or the second substrate is inverted so that the first conductive line is aligned with the second conductive line and the third conductive line is aligned with the fourth conductive line. The first substrate and the second substrate are bonded so that the first conductive line is in contact with the second conductive line and the third conductive line is in contact with the fourth conductive line.

[0184] In the embodiments of the present disclosure, the third conductive line extending along the first direction is formed in the second region of the first substrate, the fourth conductive line extending along the first direction is formed in the second region of the second substrate, and the third conductive line and the fourth conductive line are aligned and bonded at the same time as the first conductive line and the second conductive line are aligned and bonded, so that the third conductive line and the fourth conductive line are in contact. The third conductive line and the fourth conductive line extending along the first direction can be used as electrode plates of a capacitor. The first dielectric layer and the second dielectric layer are aligned and bonded at the same time as the first conductive line and the second conductive line are aligned and bonded, so that the first dielectric layer and the second dielectric layer are in contact. The first dielectric layer and the second dielectric layer in contact can be used as a dielectric structure of a capacitor, which increases the application scenarios of the bonded structure and is conducive to improving the utilization rate of the bonded structure.

[0185] In some embodiments, the memory further includes: a third region arranged in parallel with the first region and the second region along the second direction; and wherein the second region is located between the first region and the third region.

[0186] After the first semiconductor structure is formed and before the first conductive line and the second conductive line are bonded, the above manufacturing method further includes:

[0187] The fifth conductive line extending along the first direction is formed on the first semiconductor structure; and wherein the fifth conductive line is located in the third region.

[0188] After the second semiconductor structure is formed and before the first conductive line and the second conductive line are bonded, the above manufacturing method further includes:

[0189] The sixth conductive line extending along the first direction is formed on the second semiconductor structure; and wherein the sixth conductive line is located in the third region.

[0190] The above aligning and bonding the first conductive line and the second conductive line includes:

[0191] The second semiconductor structure is inverted, and the fifth conductive line and the sixth conductive line are aligned; and wherein the projection of the fifth conductive line in the third region covers the projection of the sixth conductive line in the third region.

[0192] bonding the first conductive line and the second conductive line.

[0193] In an example, the fifth trench is formed in the first dielectric material layer along the first direction by a photolithography and etching process, the fifth trench is located in the third region, and the fifth trench is filled with a conductive material to form the fifth conductive line 131 as shown. Figure 5

[0194] In an example, the fifth trench is arranged along the second direction in parallel with the first trench and the third trench, the fifth trench can be etched simultaneously with the first trench and the third trench, or the fifth trench can be etched separately from the first trench and the third trench. The first conductive line, the third conductive line, and the fifth conductive line are arranged along the second direction in parallel, the first conductive line, the third conductive line, and the fifth conductive line can be filled simultaneously, or the first conductive line, the third conductive line, and the fifth conductive line can be filled separately.

[0195] In an example, the sixth trench is formed in the second dielectric material layer along the first direction by a photolithography and etching process, the sixth trench is located in the third region, and the sixth trench is filled with a conductive material to form the sixth conductive line 132 as shown. Figure 6

[0196] In an example, the sixth trench is arranged along the second direction in parallel with the second trench and the fourth trench, the sixth trench can be etched simultaneously with the second trench and the fourth trench, or the sixth trench can be etched separately from the second trench and the fourth trench. The sixth conductive line is arranged along the second direction in parallel with the second conductive line and the fourth conductive line, the sixth conductive line can be filled simultaneously with the second conductive line and the fourth conductive line, or the sixth conductive line can be filled separately from the second conductive line and the fourth conductive line.

[0197] In an example, the first substrate or the second substrate is inverted so that the fifth conductive line and the sixth conductive line are aligned, and the fifth conductive line and the sixth conductive line are used as alignment marks for bonding.

[0198] In the embodiments of the present disclosure, the fifth conductive line is formed in the third region of the first substrate along the first direction, and the sixth conductive line is formed in the third region of the second substrate along the first direction. When the first substrate and the second substrate are bonded, the fifth conductive line and the sixth conductive line can be used as alignment marks for bonding, which increases the application scenarios of the bonded structure and is conducive to improving the utilization rate of the bonded structure.

[0199] In some embodiments, the memory further includes a fourth region arranged at least around the first region.

[0200] After the first semiconductor structure is formed and before the first conductive line and the second conductive line are bonded, the above manufacturing method further includes:

[0201] ​​forming a first encapsulation structure extending along the first direction on the first semiconductor structure; wherein the first encapsulation structure is located in the fourth region; the first encapsulation structure comprises a first surface and a second surface; the first surface is relatively close to the first semiconductor structure, and the second surface is relatively far away from the first semiconductor structure; along the second direction, a width of the second surface is greater than a width of the first surface;

[0202] after forming the second semiconductor structure, and before bonding the first conductive wire and the second conductive wire, the above manufacturing method further comprises:

[0203] forming a second encapsulation structure extending along the first direction on the second semiconductor structure; wherein the second encapsulation structure is located in the fourth region; the second encapsulation structure comprises a third surface and a fourth surface; the third surface is relatively far away from the second semiconductor structure, and the fourth surface is relatively close to the second semiconductor structure; along the second direction, a width of the third surface is greater than a width of the fourth surface;

[0204] simultaneously aligning and bonding the first encapsulation structure and the second encapsulation structure, and the second surface and the third surface are in contact.

[0205] In an example, at least a first encapsulation trench surrounding the first conductive wire is formed in the first dielectric material layer by a photolithography and etching process, the first encapsulation trench is located in the fourth region, and the first encapsulation trench is filled with an encapsulation material to form the first encapsulation structure 141 as shown in Figure 6 .

[0206] In an example, along the second direction, a top width of the first encapsulation trench is greater than a bottom width of the first encapsulation trench. The top of the first encapsulation trench is relatively far away from the first semiconductor structure, and the bottom of the first encapsulation trench is relatively close to the first semiconductor structure.

[0207] In an example, at least a second encapsulation trench surrounding the second conductive wire is formed in the second dielectric material layer by a photolithography and etching process, the second encapsulation trench is located in the fourth region, and the second encapsulation trench is filled with a conductive material to form the second encapsulation structure 142 as shown in Figure 3 .

[0208] In an example, along the second direction, a top width of the second encapsulation trench is greater than a bottom width of the second encapsulation trench. The top of the second encapsulation trench is relatively far away from the second semiconductor structure, and the bottom of the first encapsulation trench is relatively close to the second semiconductor structure.

[0209] In an example, the first substrate or the second substrate is inverted so that the first encapsulation structure and the second encapsulation structure are in contact, and the first encapsulation structure and the second encapsulation structure are used as encapsulation structures of the memory.

[0210] In the embodiments of the present disclosure, by forming the first sealing structure surrounding the first conductive line in the fourth region of the first substrate and forming the second sealing structure surrounding the second conductive line in the fourth region of the second substrate, after bonding the first substrate and the second substrate, the first sealing structure and the second sealing structure can be used as the sealing structure of the memory, which increases the application scenarios of the bonded structure and is beneficial to improve the utilization rate of the bonded structure.

[0211] In some embodiments, the first semiconductor structure includes a peripheral circuit and a plurality of first contact pillars; the second semiconductor structure includes a memory cell array and a plurality of second contact pillars; the step S100 includes:

[0212] forming a first insulating layer covering the peripheral circuit;

[0213] forming a plurality of first contact pillars in the first insulating layer and electrically connected to the peripheral circuit; wherein the plurality of first contact pillars are arranged side by side along a first direction;

[0214] the step S200 includes:

[0215] forming a first dielectric material layer covering the first insulating layer and the plurality of first contact pillars;

[0216] forming a first trench penetrating through the first dielectric material layer; wherein the first trench extends along the first direction, and the bottom of the first trench exposes the plurality of first contact pillars;

[0217] filling a conductive material into the first trench to form a first conductive line;

[0218] the step S300 includes:

[0219] forming a second insulating layer covering the memory cell array;

[0220] forming a plurality of second contact pillars in the second insulating layer and electrically connected to the memory cell array; wherein the plurality of second contact pillars are arranged side by side along the first direction;

[0221] the step of forming a second conductive line extending along the first direction on the second semiconductor structure includes:

[0222] forming a second dielectric material layer covering the second insulating layer and the plurality of second contact pillars;

[0223] forming a second trench penetrating through the second dielectric material layer; wherein the second trench extends along the first direction, and the bottom of the second trench exposes the plurality of second contact pillars;

[0224] filling a conductive material into the second trench to form a second conductive line.

[0225] In an example, before forming the first dielectric material layer, a first insulating layer covering the peripheral circuit is formed, a plurality of first contact holes are formed in the first insulating layer by a photolithography and etching process, the bottom of the first contact hole exposes the peripheral circuit (for example, the source, drain or gate of a transistor), the first contact hole is filled with a conductive material to form a first contact pillar 151 as shown in Figure 3

[0226] In an example, before forming the second dielectric layer material, a second insulating layer covering the memory cell array is formed, a plurality of second contact holes are formed in the second insulating layer by a photolithography and etching process, the bottom of the second contact hole exposes the memory cell array (for example, a memory string), the second contact hole is filled with a conductive material to form a second contact pillar 161 as shown in ​

[0227] In some embodiments, before bonding the first semiconductor structure and the second semiconductor structure, the above manufacturing method further comprises:

[0228] forming a conductive pillar extending along a third direction on the second semiconductor structure; wherein the conductive pillar is electrically connected with the second semiconductor structure; the third direction is perpendicular to the horizontal plane;

[0229] The above aligning and bonding the first semiconductor structure and the second semiconductor structure comprises:

[0230] aligning and bonding the first conductive wire and the conductive pillar, the first conductive wire is in contact with the conductive pillar; wherein the conductive pillar is located between the first conductive wire and the second semiconductor structure.

[0231] Exemplarily, before bonding the first semiconductor structure and the second semiconductor structure, a second dielectric material layer can be formed on the memory cell array by a thin film deposition process, a connecting hole extending along a third direction is formed in the second dielectric material layer by a photolithography and etching process on the second dielectric material layer, the connecting hole is located in the first region, and the connecting hole is filled with a conductive material to form a conductive pillar.

[0232] By aligning and bonding the first conductive wire and the conductive pillar, the first conductive wire is in contact with the conductive pillar, and the first semiconductor structure and the second semiconductor structure are bonded by one conductive wire (extending in the first direction) and one conductive pillar (extending along the third direction).

[0233] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.​​

Claims

1. A memory, characterized in that, include: Stacked first and second semiconductor structures; The first bonding structure is located in the first region of the memory; The first bonding structure includes: a first conductive line and a second conductive line; wherein, the first conductive line is located between the first semiconductor structure and the second semiconductor structure and extends along a first direction, the first conductive line is electrically connected to the first semiconductor structure and the second semiconductor structure respectively, and the first direction is parallel to a horizontal plane; the second conductive line is located between the first conductive line and the second semiconductor structure and extends along the first direction, the side of the second conductive line relatively closer to the first conductive line is in contact with the first conductive line, and the side of the second conductive line relatively farther from the first conductive line is electrically connected to the second semiconductor structure; Multiple second bonding structures are located in a second region of the memory and arranged side-by-side along a second direction; the second bonding structures serve as electrode plates for capacitors; the second bonding structures include a third conductive line and a fourth conductive line; wherein the third conductive line extends along a first direction; the fourth conductive line is located between the third conductive line and the second semiconductor structure and extends along the first direction, and the fourth conductive line is in contact with the third conductive line; the second region and the first region are arranged side-by-side along the second direction, the second direction is parallel to the horizontal plane, and the second direction intersects the first direction.

2. The memory according to claim 1, characterized in that, The memory also includes: An electrically insulating dielectric structure is located between two adjacent second bonding structures; wherein one of the two adjacent second bonding structures is electrically connected to the first semiconductor structure or the second semiconductor structure, and the other of the two adjacent second bonding structures is electrically connected to a ground terminal.

3. The memory according to claim 2, characterized in that, The two adjacent second bonding structures have the same length in the first direction, and the two adjacent second bonding structures have a gap at their ends in the first direction.

4. The memory according to claim 2, characterized in that, The memory further includes: a third region, arranged side-by-side with the first region and the second region along the second direction; wherein the second region is located between the first region and the third region; The memory further includes: a third bonding structure located in the third region; The third bonding structure includes: The fifth conductive line extends along the first direction; A sixth conductive line is located between the fifth conductive line and the second semiconductor structure and extends along the first direction, wherein the fifth conductive line is in contact with the sixth conductive line; wherein the projection of the fifth conductive line in the third region covers the projection of the sixth conductive line in the third region.

5. The memory according to claim 2, characterized in that, The memory further includes: a fourth region, which is disposed at least around the first region; The memory further includes: a fourth bonding structure located in the fourth region; The fourth bonding structure includes: A first sealing structure, extending along the first direction, includes: a first surface and a second surface; wherein the first surface is relatively close to the first semiconductor structure, and the second surface is relatively far from the first semiconductor structure; along the second direction, the width of the second surface is greater than the width of the first surface; A second sealing structure, located between the first sealing structure and the second semiconductor structure and extending along the first direction, includes a third surface and a fourth surface; wherein the third surface is relatively close to the first sealing structure, and the fourth surface is relatively far from the first sealing structure; along the second direction, the width of the third surface is greater than the width of the fourth surface; the third surface is in contact with the second surface.

6. The memory according to claim 2, characterized in that, The memory includes: a plurality of the first bonding structures, arranged side by side along the first direction; wherein... Along the first direction, the length of the first conductive line is greater than or equal to 300 nanometers; And / or, Along the first direction, the length of the second conductive line is greater than or equal to 300 nanometers.

7. The memory according to claim 2, characterized in that, The memory includes: a plurality of the first bonding structures, arranged side by side along the first direction; wherein... The spacing between two adjacent first conductive lines is greater than or equal to 300 nanometers; And / or, The spacing between two adjacent second conductive lines is greater than or equal to 300 nanometers.

8. The memory according to claim 6 or 7, characterized in that, The ratio of the sum of the projected areas of the plurality of the first bonding structures in the first region to the first region is less than 10%.

9. The memory according to claim 1, characterized in that, The first semiconductor structure includes peripheral circuitry; The second semiconductor structure includes a memory cell array; The first semiconductor structure further includes: a plurality of first contact posts arranged side by side along the first direction and located between the peripheral circuit and the first conductive line; wherein one end of the plurality of first contact posts is electrically connected to the peripheral circuit; and the other end of the plurality of first contact posts is electrically connected to the first conductive line. The second semiconductor structure further includes: a plurality of second contact posts arranged in parallel along the first direction and located between the second conductive line and the memory cell array; wherein one end of the plurality of second contact posts is electrically connected to the second conductive line; and the other end of the plurality of second contact posts is electrically connected to the memory cell array.

10. The memory according to claim 1, characterized in that, The memory includes a three-dimensional memory.

11. The memory according to claim 10, characterized in that, The three-dimensional memory includes a 3DNAND memory.

12. A method for manufacturing a memory, characterized in that, include: Forming the first semiconductor structure; A first conductive line extending along a first direction is formed on the first semiconductor structure; wherein the first conductive line is electrically connected to the first semiconductor structure; the first direction is parallel to a horizontal plane; A plurality of third conductive lines are formed on the first semiconductor structure and arranged in parallel along a second direction; wherein the third conductive lines extend along the first direction; the second direction is parallel to the horizontal plane and intersects the first direction; Forming a second semiconductor structure; A second conductive line extending along the first direction is formed on the second semiconductor structure; wherein the second conductive line is electrically connected to the second semiconductor structure; A plurality of fourth conductive lines are formed on the second semiconductor structure and arranged in parallel along the second direction; wherein the fourth conductive lines extend along the first direction; Align and bond the first conductive line and the second conductive line, with the first conductive line contacting the second conductive line; wherein the contacting first conductive line and the second conductive line are located in a first region of the memory; the first conductive line is located between the first semiconductor structure and the second semiconductor structure, and the second conductive line is located between the first conductive line and the second semiconductor structure. While aligning and bonding the first conductive line and the second conductive line, the third conductive line and the fourth conductive line are aligned and bonded, and the third conductive line contacts the fourth conductive line; wherein the contacting third conductive line and the fourth conductive line are located in the second region of the memory and serve as electrode plates of a capacitor; the second region and the first region are arranged side by side along the second direction.

13. The manufacturing method according to claim 12, characterized in that, After forming the first semiconductor structure and before bonding the first conductive line and the second conductive line, the fabrication method further includes: A first dielectric layer is formed between two adjacent third conductive lines; After forming the second semiconductor structure and before bonding the first conductive line and the second conductive line, the fabrication method further includes: A second dielectric layer is formed between two adjacent fourth conductive lines; Align and bond the first dielectric layer and the second dielectric layer, and bring the first dielectric layer and the second dielectric layer into contact.

14. The manufacturing method according to claim 13, characterized in that, The memory further includes: a third region, arranged side-by-side with the first region and the second region along the second direction; wherein the second region is located between the first region and the third region; After forming the first semiconductor structure and before bonding the first conductive line and the second conductive line, the fabrication method further includes: A fifth conductive line extending along the first direction is formed on the first semiconductor structure; wherein the fifth conductive line is located in the third region; After forming the second semiconductor structure and before bonding the first conductive line and the second conductive line, the fabrication method further includes: A sixth conductive line extending along the first direction is formed on the second semiconductor structure; wherein the sixth conductive line is located in the third region; The alignment and bonding of the first conductive line and the second conductive line includes: The second semiconductor structure is inverted, and the fifth conductive line and the sixth conductive line are aligned; wherein the projection of the fifth conductive line in the third region covers the projection of the sixth conductive line in the third region; The first conductive wire and the second conductive wire are bonded together.

15. The manufacturing method according to claim 13, characterized in that, The memory further includes: a fourth region, which is disposed at least around the first region; After forming the first semiconductor structure and before bonding the first conductive line and the second conductive line, the fabrication method further includes: A first sealing structure extending along the first direction is formed on the first semiconductor structure; wherein the first sealing structure is located in the fourth region; the first sealing structure includes a first surface and a second surface; the first surface is relatively close to the first semiconductor structure, and the second surface is relatively far from the first semiconductor structure; along the second direction, the width of the second surface is greater than the width of the first surface; After forming the second semiconductor structure and before bonding the first conductive line and the second conductive line, the fabrication method further includes: A second sealing structure extending along the first direction is formed on the second semiconductor structure; wherein the second sealing structure is located in the fourth region; the second sealing structure includes a third surface and a fourth surface; the third surface is relatively far away from the second semiconductor structure, and the fourth surface is relatively close to the second semiconductor structure; along the second direction, the width of the third surface is greater than the width of the fourth surface; While aligning and bonding the first conductive line and the second conductive line, the first sealing structure and the second sealing structure are aligned and bonded, and the second surface and the third surface are in contact.

16. The manufacturing method according to claim 12, characterized in that, The first semiconductor structure includes peripheral circuitry and a plurality of first contact pillars; the second semiconductor structure includes a memory cell array and a plurality of second contact pillars. The formation of the first semiconductor structure includes: A first insulating layer is formed to cover the peripheral circuit; A plurality of first contact posts electrically connected to the peripheral circuit are formed in the first insulating layer; wherein the plurality of first contact posts are arranged side by side along the first direction; The step of forming a first conductive line extending in a first direction on the first semiconductor structure includes: A first dielectric material layer is formed covering the first insulating layer and the plurality of first contact posts; A first trench is formed that penetrates the first dielectric material layer; wherein the first trench extends along the first direction and the bottom of the first trench exposes the plurality of first contact posts; The first trench is filled with conductive material to form the first conductive line; The formation of the second semiconductor structure includes: A second insulating layer is formed to cover the memory cell array; A plurality of second contact posts electrically connected to the memory cell array are formed in the second insulating layer; wherein the plurality of second contact posts are arranged side by side along the first direction; The step of forming a second conductive line extending along the first direction on the second semiconductor structure includes: A second dielectric material layer is formed covering the second insulating layer and the plurality of second contact posts; A second trench is formed that penetrates the second dielectric material layer; wherein the second trench extends along the first direction and the bottom of the second trench exposes the plurality of second contact posts; The second trench is filled with conductive material to form the second conductive wire.

Images