One-time programmable memory structure

Abstract

The present invention provides a one-time programmable memory structure comprising a substrate, a transistor, a capacitor, and an interconnect structure. The transistor is located on the substrate. The capacitor comprises a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode on top of the first electrode. This one-time programmable memory structure can effectively prevent the generation of noise sources in the substrate.

Description

Technical Field

[0001] The present invention relates to a memory structure, and in particular to a one-time programmable (OTP) memory structure. Background Art

[0002] Current one-time programmable memories have capacitors electrically connected to transistors. However, since the bottom electrode of the capacitor is a doped region located in the substrate, the bottom electrode located in the substrate can become a noise source for adjacent devices when programming the one-time programmable memory. Summary of the Invention

[0003] The present invention provides a one-time programmable memory structure, which can effectively prevent noise sources from being generated in a substrate.

[0004] The present invention provides a one-time programmable memory structure comprising a substrate, a transistor, a capacitor, and an interconnect structure. The transistor is located on the substrate. The capacitor comprises a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode on a top surface of the first electrode.

[0005] According to an embodiment of the present invention, in the one-time programmable memory structure, the interconnection line structure may directly contact the top surface of the first electrode.

[0006] According to one embodiment of the present invention, in the one-time programmable memory structure described above, the transistor may include a gate, a gate dielectric layer, a first doped region, and a second doped region. The gate is disposed on a substrate. The gate dielectric layer is disposed between the gate and the substrate. The first doped region and the second doped region are located in the substrate on either side of the gate.

[0007] According to an embodiment of the present invention, in the one-time programmable memory structure, the first electrode and the gate may be derived from the same material layer.

[0008] According to one embodiment of the present invention, in the one-time programmable memory structure, the interconnect structure may include a first contact window, a second contact window, and a conductive line. The first contact window is electrically connected to the first doped region. The second contact window is electrically connected to the first electrode. The conductive line is electrically connected between the first contact window and the second contact window.

[0009] According to an embodiment of the present invention, in the one-time programmable memory structure, the interconnection line structure may include a contact window electrically connected between the first doped region and the first electrode.

[0010] According to an embodiment of the present invention, in the one-time programmable memory structure, the contact window can directly contact the first doped region and the first electrode.

[0011] According to an embodiment of the present invention, the one-time programmable memory structure includes a plurality of capacitors electrically connected to the same transistor.

[0012] According to an embodiment of the present invention, the one-time programmable memory structure may further include an isolation structure, the isolation structure being located in the substrate, and the first electrode being disposed on the isolation structure.

[0013] The present invention provides another one-time programmable memory structure, comprising a substrate, a transistor, a capacitor, and an interconnect structure. The transistor is located on the substrate. The capacitor comprises a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the second electrode of the capacitor. The interconnect structure is electrically connected to the second electrode on top of the second electrode.

[0014] According to another embodiment of the present invention, in the one-time programmable memory structure, the interconnection line structure may directly contact the top surface of the second electrode.

[0015] According to another embodiment of the present invention, in the one-time programmable memory structure described above, the transistor may include a gate, a gate dielectric layer, a first doped region, and a second doped region. The gate is disposed on a substrate. The gate dielectric layer is disposed between the gate and the substrate. The first doped region and the second doped region are located in the substrate on either side of the gate.

[0016] According to another embodiment of the present invention, in the one-time programmable memory structure, the first electrode and the gate may be derived from the same material layer.

[0017] According to another embodiment of the present invention, in the one-time programmable memory structure, the interconnect structure may include a first contact window, a second contact window, and a conductive line. The first contact window is electrically connected to the first doped region. The second contact window is electrically connected to the second electrode. The conductive line is electrically connected between the first contact window and the second contact window.

[0018] According to another embodiment of the present invention, in the one-time programmable memory structure, the interconnection line structure may include a contact window electrically connected between the first doped region and the second electrode.

[0019] According to another embodiment of the present invention, in the one-time programmable memory structure, the contact window can directly contact the first doped region and the second electrode.

[0020] According to another embodiment of the present invention, the one-time programmable memory structure includes a plurality of capacitors electrically connected to the same transistor.

[0021] According to another embodiment of the present invention, the one-time programmable memory structure may further include an isolation structure, the isolation structure being located in the substrate, and the first electrode being disposed on the isolation structure.

[0022] The present invention provides another one-time programmable memory structure, comprising a substrate, a transistor, a capacitor, an interconnect structure, and a resistor. The substrate comprises a memory region and a resistor region. The transistor is located on the substrate and in the memory region. The capacitor is located in the memory region and comprises a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is disposed between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode on a top surface of the first electrode. The resistor is located in the resistor region and comprises a conductor layer. The conductor layer is disposed above the substrate.

[0023] According to another embodiment of the present invention, in the one-time programmable memory structure, the conductive layer and the second electrode may be derived from the same material layer.

[0024] Based on the above, in the one-time programmable memory structure proposed in the present invention, since the first electrode and the second electrode of the capacitor are both disposed above the substrate, noise sources generated by the capacitor electrodes disposed in the substrate can be prevented.

[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A A top view of a one-time programmable memory structure according to an embodiment of the present invention;

[0027] Figure 1B To follow Figure 1A A sectional view along the section line I-I';

[0028] Figure 2A A top view of a one-time programmable memory structure according to another embodiment of the present invention;

[0029] Figure 2B To follow Figure 2AA sectional view along section line II-II';

[0030] Figure 3A A top view of a one-time programmable memory structure according to another embodiment of the present invention;

[0031] Figure 3B To follow Figure 3A A cross-sectional view along section line III-III';

[0032] Figure 4A A top view of a one-time programmable memory structure according to another embodiment of the present invention;

[0033] Figure 4B To follow Figure 4A A sectional view taken along section line IV-IV';

[0034] Figure 5A A top view of a one-time programmable memory structure according to another embodiment of the present invention;

[0035] Figure 5B To follow Figure 5A Sectional view along the V-V' section line;

[0036] Figure 6A A top view of a one-time programmable memory structure according to another embodiment of the present invention;

[0037] Figure 6B To follow Figure 6A A cross-sectional view along the section line VI-VI';

[0038] Figure 7 A cross-sectional view of a one-time programmable memory structure according to another embodiment of the present invention;

[0039] Figure 8 FIG. 4 is a cross-sectional view of a one-time programmable memory structure according to another embodiment of the present invention.

[0040] Description of Figure Numbers:

[0041] 10,20,30,40,50,60,70,80: One-time programmable memory structure

[0042] 100: Base

[0043] 102: Transistor

[0044] 104,304,604:Capacitors

[0045] 106,130,136,148,150,206,506: Interconnection structure

[0046] 108: Isolation Structure

[0047] 110: Gate

[0048] 112: Gate dielectric layer

[0049] 114,116: doped regions

[0050] 118,120: Electrode

[0051] 122: Insulation layer

[0052] 124,126,132,138,152,156,224,524: Contact window

[0053] 128,134,140,154,158: Wire

[0054] 142,144: Dielectric layer

[0055] 146: Conductor layer

[0056] 160: Virtual Electrode

[0057] 162: Virtual insulation layer

[0058] AA: Active Area

[0059] MC: Storage Unit

[0060] R: Resistor

[0061] R1: memory area

[0062] R2: resistance area DETAILED DESCRIPTION

[0063] Figure 1A FIG. 1 is a top view of a one-time programmable memory structure according to an embodiment of the present invention. Figure 1B To follow Figure 1A In addition, in Figure 1A in, omit Figure 1B To clearly describe some of the components in Figure 1A The configuration relationship between the components in.

[0064] Please refer to Figure 1A and Figure 1BThe one-time programmable memory structure 10 includes a substrate 100, a transistor 102, a capacitor 104, and an interconnect structure 106. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, the one-time programmable memory structure 100 may further include an isolation structure 108. The isolation structure 108 is located in the substrate 100, thereby defining an active area AA in the substrate 100. The isolation structure 108 may be, for example, a shallow trench isolation (STI) structure. The material of the isolation structure 108 may be, for example, silicon oxide.

[0065] Transistor 102 is disposed on substrate 100. Transistor 102 may include a gate 110, a gate dielectric layer 112, a doped region 114, and a doped region 116. Gate 110 is disposed on substrate 100. Gate dielectric layer 112 is disposed between gate 110 and substrate 100. In some embodiments, gate 110 may be made of doped polysilicon, and gate dielectric layer 112 may be made of silicon oxide, but the present invention is not limited thereto. In other embodiments, gate 110 and gate dielectric layer 112 may be formed using high-k metal gate (HKMG) technology. Doped regions 114 and 116 are disposed in substrate 100 on either side of gate 110. Doped regions 114 and 116 may serve as either a source region or a drain region, respectively. In this embodiment, doped region 114 may serve as a source region, and doped region 116 may serve as a drain region, but the present invention is not limited thereto. In some embodiments, the transistor 102 may further include components such as a spacer and a lightly doped drain (LDD) (not shown), and description thereof is omitted here.

[0066] Capacitor 104 includes an electrode 118, an electrode 120, and an insulating layer 122. Electrode 118 is disposed above substrate 100. For example, electrode 118 may be disposed on isolation structure 108. The material of electrode 118 may be, for example, doped polysilicon or metal. In some embodiments, electrode 118 and gate 110 may be derived from the same material layer. That is, electrode 118 and gate 110 may be formed from the same material layer, thereby integrating the process of transistor 102 with the process of capacitor 104, thereby reducing the process complexity of the one-time programmable memory structure 10. In addition, electrode 118 and gate 110 may be made of the same material. Electrode 120 is disposed on electrode 118. Electrode 118 is located between electrode 120 and substrate 100. The material of electrode 120 may be, for example, a high resistivity material. The material of electrode 120 may be, for example, a metal-containing material. In some embodiments, the material of electrode 120 may be, for example, a metal compound, such as titanium nitride or tantalum nitride. The insulating layer 122 is disposed between the electrode 118 and the electrode 120. The insulating layer 122 is made of, for example, silicon oxide.

[0067] The interconnect structure 106 is electrically connected between the transistor 102 and the electrode 118 of the capacitor 104. The interconnect structure 106 is electrically connected to the electrode 118 at the top surface of the electrode 118. In some embodiments, the interconnect structure 106 may directly contact the top surface of the electrode 118. For example, the interconnect structure 106 may include a contact window 124, a contact window 126, and a conductive line 128, but the present invention is not limited thereto. The contact window 124 is electrically connected to the doped region 114. The contact window 126 is electrically connected to the electrode 118. In some embodiments, the contact window 126 may directly contact the top surface of the electrode 118. The material of the contact windows 124 and 126 is, for example, a conductive material such as tungsten. The conductive line 128 is electrically connected between the contact windows 124 and 126. The material of the conductive line 128 is, for example, a conductive material such as tungsten, aluminum, or copper.

[0068] The one-time programmable memory structure may further include an interconnect structure 130. The interconnect structure 130 is electrically connected to the electrode 120. For example, the interconnect structure 130 may include a contact window 132 and a conductive line 134. The contact window 132 is electrically connected to the electrode 120. The material of the contact window 132 is, for example, a conductive material such as tungsten. The conductive line 134 is electrically connected to the contact window 132. The material of the conductive line 134 is, for example, a conductive material such as tungsten, aluminum, or copper.

[0069] In addition, the one-time programmable memory structure may further include an interconnect structure 136. The interconnect structure 136 is electrically connected to the doped region 116. For example, the interconnect structure 136 may include a contact window 138 and a conductive line 140. The contact window 138 is electrically connected to the doped region 116. The material of the contact window 138 is, for example, a conductive material such as tungsten. The conductive line 140 is electrically connected to the contact window 138. The material of the conductive line 140 is, for example, a conductive material such as tungsten, aluminum, or copper. The conductive line 134 and the conductive line 140 may serve as one of a source line and the other of a bit line, respectively. In this embodiment, the conductive line 134 may serve as a source line, and the conductive line 140 may serve as a bit line, but the present invention is not limited thereto.

[0070] In addition, the one-time programmable memory structure may further include a dielectric layer 142 and a dielectric layer 144. Dielectric layer 142 is disposed between insulating layer 122 and substrate 100. The material of dielectric layer 142 is, for example, silicon oxide, silicon nitride, or a combination thereof. Dielectric layer 144 is disposed on insulating layer 122. The material of dielectric layer 144 is, for example, silicon oxide, silicon nitride, or a combination thereof.

[0071] In this embodiment, the transistor 102 and the capacitor 104 electrically connected via the interconnect structure 106 may form a memory cell MC. Two adjacent memory cells MC may be mirror images. The electrodes 118 in the capacitors 104 of the two adjacent memory cells MC may be separated from each other. In addition, the capacitors 104 of the two adjacent memory cells MC may share an electrode 120. Initially, all memory cells MC are in an "H state" (i.e., a high resistance state). After a programming operation is performed on a selected memory cell MC, the selected memory cell MC changes to an "L state" (i.e., a low resistance state) due to a breakdown of the insulating layer 122 in the capacitor 104.

[0072] In addition, the one-time programmable memory structure 10 may further include other necessary components, such as an interconnection structure (not shown) electrically connected to the gate 110 , and the description thereof is omitted here.

[0073] Based on the above embodiments, in the one-time programmable memory structure 10 , since the electrodes 118 and 120 of the capacitor 104 are both disposed above the substrate 100 , noise sources generated by the capacitor electrodes disposed in the substrate can be prevented.

[0074] Figure 2A FIG. 1 is a top view of a one-time programmable memory structure according to another embodiment of the present invention. Figure 2B To follow Figure 2A The sectional view of the II-II' section line. Figure 2A in, omit Figure 2B To clearly describe some of the components in Figure 2A The configuration relationship between the components in.

[0075] Please refer to Figure 1A 、 Figure 1B 、 Figure 2A and Figure 2B , Figure 2A and Figure 2B One-time programmable memory structure 20 with Figure 1A and Figure 1B The differences between the one-time programmable memory structure 10 and the one-time programmable memory structure 20 are as follows. In the one-time programmable memory structure 20, the interconnect structure 206 for electrically connecting the transistor 102 and the capacitor 104 may include a contact window 224. The contact window 224 is electrically connected between the doped region 114 and the electrode 118. In some embodiments, the contact window 224 may directly contact the doped region 114 and the electrode 118. The material of the contact window 224 is, for example, a conductive material such as tungsten. Furthermore, components identical to those in the one-time programmable memory structure 20 and the one-time programmable memory structure 10 are represented by the same symbols and are not further described here.

[0076] Based on the above embodiments, in the one-time programmable memory structure 20 , since a single contact window 224 can be used as the interconnection structure 206 for electrically connecting the transistor 102 and the capacitor 104 , the complexity of the interconnection structure 206 can be reduced.

[0077] Figure 3A FIG. 1 is a top view of a one-time programmable memory structure according to another embodiment of the present invention. Figure 3B To follow Figure 3A In addition, in Figure 3A in, omit Figure 3B To clearly describe some of the components in Figure 3A The configuration relationship between the components in.

[0078] Please refer to Figure 1A 、 Figure 1B 、 Figure 3A and Figure 3B , Figure 3A and Figure 3B One-time programmable memory structure 30 with Figure 1A and Figure 1BThe difference between the one-time programmable memory structure 10 and the one-time programmable memory structure 10 is as follows. In the one-time programmable memory structure 10, only one capacitor 104 is electrically connected to the transistor 102. On the other hand, the one-time programmable memory structure 30 may include multiple capacitors 304 electrically connected to the same transistor 102. That is, a single memory cell MC of the one-time programmable memory structure 30 may include multiple capacitors 304. In this embodiment, the number of capacitors 304 electrically connected to the same transistor 102 is two, but the present invention is not limited thereto. The electrodes 120 of the capacitors 304 electrically connected to the same transistor 102 may be separated from each other ( Figure 3A ). Capacitors 304 electrically connected to the same transistor 102 can share electrode 118. Components identical to those in the one-time programmable memory structure 30 and 10 are denoted by the same symbols and are not further described here. The remaining contents of the one-time programmable memory structure 30 are similar to those of the one-time programmable memory structure 10, and reference can be made to the description of the memory structure 10 in the above embodiment.

[0079] Based on the above embodiments, since the one-time programmable memory structure 30 may include multiple capacitors 304 electrically connected to the same transistor 102, the area of ​​the insulating layer 122 in the overlapping region between the electrode 120 and the electrode 118 can be reduced, thereby optimizing the programming operation.

[0080] Figure 4A FIG. 1 is a top view of a one-time programmable memory structure according to another embodiment of the present invention. Figure 4B To follow Figure 4A In addition, in Figure 4A in, omit Figure 4B To clearly describe some of the components in Figure 4A The configuration relationship between the components in.

[0081] Please refer to Figure 1A 、 Figure 1B 、 Figure 4A and Figure 4B , Figure 4A and Figure 4B One-time programmable memory structure 40 with Figure 1A and Figure 1BThe differences between the one-time programmable memory structure 10 and the one-time programmable memory structure 10 are as follows. In the one-time programmable memory structure 40, the interconnect structure 106 is electrically connected between the transistor 102 and the electrode 120 of the capacitor 104. The interconnect structure 106 is electrically connected to the electrode 120 at the top surface of the electrode 120. In some embodiments, the interconnect structure 106 may directly contact the top surface of the electrode 120. For example, a contact window 126 in the interconnect structure 106 is electrically connected to the electrode 120. In some embodiments, the contact window 126 may directly contact the top surface of the electrode 120. The electrodes 120 in the capacitors 104 of two adjacent memory cells MC may be separated from each other. The capacitors 104 in two adjacent memory cells MC may share an electrode 118. The interconnect structure 130 is electrically connected to the electrode 118. In addition, the same symbols are used to represent the same components in the one-time programmable memory structure 40 as in the one-time programmable memory structure 10 and are not described again here.

[0082] Based on the above embodiments, in the one-time programmable memory structure 40 , since the electrodes 118 and 120 of the capacitor 104 are both disposed above the substrate 100 , noise sources generated by the capacitor electrodes disposed in the substrate can be prevented.

[0083] Figure 5A FIG. 1 is a top view of a one-time programmable memory structure according to another embodiment of the present invention. Figure 5B To follow Figure 5A In addition, in the V-V' section line Figure 5A in, omit Figure 5B To clearly describe some of the components in Figure 5A The configuration relationship between the components in.

[0084] Please refer to Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B , Figure 5A and Figure 5B One-time programmable memory structure 50 with Figure 4A and Figure 4B The differences between the one-time programmable memory structure 40 and the one-time programmable memory structure 50 are as follows. In the one-time programmable memory structure 50, the interconnect structure 506 for electrically connecting the transistor 102 and the capacitor 104 may include a contact window 524. The contact window 524 is electrically connected between the doped region 114 and the electrode 120. In some embodiments, the contact window 524 may directly contact the doped region 114 and the electrode 120. The material of the contact window 524 is, for example, a conductive material such as tungsten. Furthermore, components identical to those in the one-time programmable memory structure 50 and the one-time programmable memory structure 40 are represented by the same symbols and are not further described here.

[0085] Based on the above embodiments, it can be seen that in the one-time programmable memory structure 50 , since a single contact window 524 can be used as the interconnection structure 506 for electrically connecting the transistor 102 and the capacitor 104 , the complexity of the interconnection structure 506 can be reduced.

[0086] Figure 6A FIG. 1 is a top view of a one-time programmable memory structure according to another embodiment of the present invention. Figure 6B To follow Figure 6A In addition, in Figure 6A in, omit Figure 6B To clearly describe some of the components in Figure 6A The configuration relationship between the components in.

[0087] Please refer to Figure 4A 、 Figure 4B 、 Figure 6A and Figure 6B , Figure 6A and Figure 6B One-time programmable memory structure 60 with Figure 4A and Figure 4B The difference between the one-time programmable memory structure 40 and the one-time programmable memory structure 40 is as follows. In the one-time programmable memory structure 40, only one capacitor 104 is electrically connected to the transistor 102. On the other hand, the one-time programmable memory structure 60 may include multiple capacitors 604 electrically connected to the same transistor 102. That is, a single memory cell MC of the one-time programmable memory structure 60 may include multiple capacitors 604. In this embodiment, the number of capacitors 604 electrically connected to the same transistor 102 is two, but the present invention is not limited thereto. The electrodes 118 of the capacitors 604 electrically connected to the same transistor 102 may be separated from each other ( Figure 6A ). Capacitors 604 electrically connected to the same transistor 102 can share the electrode 120. Components identical to those in the one-time programmable memory structure 60 and the one-time programmable memory structure 40 are denoted by the same symbols and are not further described here. The remaining contents of the one-time programmable memory structure 60 are similar to those of the one-time programmable memory structure 40, and reference may be made to the description of the memory structure 40 in the above embodiment.

[0088] Based on the above embodiments, since the one-time programmable memory structure 60 may include multiple capacitors 604 electrically connected to the same transistor 102, the area of ​​the insulating layer 122 in the overlapping region between the electrode 120 and the electrode 118 can be reduced, thereby optimizing the programming operation.

[0089] Figure 7 FIG. 4 is a cross-sectional view of a one-time programmable memory structure according to another embodiment of the present invention.

[0090] Please refer to Figure 1B and Figure 7 , Figure 7 The one-time programmable memory structure 70 includes Figure 1B The one-time programmable memory structure 10 further includes a resistor R. In the one-time programmable memory structure 40, the substrate 100 includes a memory region R1 and a resistor region R2. The transistor 102 and the capacitor 104 are located in the memory region R1. The resistor R is located in the resistor region R2 and may include a conductive layer 146. The conductive layer 146 is disposed above the substrate 100. For example, the conductive layer 146 may be disposed above the isolation structure 108. The material of the conductive layer 146 may be a high-resistivity material. For example, the material of the conductive layer 146 may be a metal-containing material. In some embodiments, the material of the conductive layer 146 may be a metal compound, such as titanium nitride or tantalum nitride. In some embodiments, the conductive layer 146 and the electrode 120 may be derived from the same material layer. That is, the conductive layer 146 and the electrode 120 may be formed from the same material layer, thereby integrating the process of the resistor R with the process of the capacitor 104, thereby reducing process complexity. In addition, the conductive layer 146 and the electrode 120 may be made of the same material.

[0091] The one-time programmable memory structure 70 may further include an interconnect structure 148 and an interconnect structure 150. Interconnect structures 148 and 150 are each electrically connected to a resistor R. Interconnect structure 148 can electrically connect resistor R to one voltage source, and interconnect structure 150 can electrically connect resistor R to another voltage source. Interconnect structure 148 may include a contact window 152 and a conductive line 154. Contact window 152 is electrically connected to resistor R. Contact window 152 may be made of a conductive material such as tungsten. Conductive line 154 is electrically connected to contact window 152. Conductive line 154 may be made of a conductive material such as tungsten, aluminum, or copper. Interconnect structure 150 may include a contact window 156 and a conductive line 158. Contact window 156 is electrically connected to resistor R. Contact window 150 may be made of a conductive material such as tungsten. Conductive line 158 is electrically connected to contact window 156. Conductive line 158 may be made of a conductive material such as tungsten, aluminum, or copper.

[0092] In addition, the same components in the one-time programmable memory structure 70 and the one-time programmable memory structure 10 are represented by the same symbols and are not described again.

[0093] Based on the above embodiments, it can be seen that in the one-time programmable memory structure 70 , the process of the resistor R and the process of the capacitor 104 can be integrated, thereby reducing the process complexity.

[0094] Figure 8 FIG. 4 is a cross-sectional view of a one-time programmable memory structure according to another embodiment of the present invention.

[0095] Please refer to Figure 7 and Figure 8 , Figure 8 One-time programmable memory structure 80 with Figure 7 The difference between the one-time programmable memory structure 70 and the one-time programmable memory structure 70 is as follows. The one-time programmable memory structure 80 may further include a dummy electrode 160 and a dummy insulating layer 162. The dummy electrode 160 is disposed on the isolation structure 108. The material of the dummy electrode 160 is, for example, doped polysilicon or metal. In some embodiments, the dummy electrode 160 and the electrode 118 may be derived from the same material layer. That is, the dummy electrode 160 and the electrode 118 may be formed from the same material layer. In addition, the dummy electrode 160 and the electrode 118 may be the same material. The dummy insulating layer 162 is disposed between the resistor R and the dummy electrode 160. The material of the dummy insulating layer 162 is, for example, silicon oxide. In some embodiments, the dummy insulating layer 162 and the insulating layer 122 may be derived from the same material layer. That is, the dummy insulating layer 162 and the insulating layer 122 may be formed from the same material layer, and the dummy insulating layer 162 and the insulating layer 122 may be the same material.

[0096] Based on the above embodiments, it can be seen that in the one-time programmable memory structure 80 , the process of the resistor R and the process of the capacitor 104 can be integrated, thereby reducing the process complexity.

[0097] In other embodiments, the structure in the resistance region R2 of the one-time programmable memory structure 70 or the structure in the resistance region R2 of the one-time programmable memory structure 80 may be applied to the one-time programmable memory structures 20 to 60 .

[0098] In summary, in the one-time programmable memory structure of the above embodiment, since the electrodes of the capacitor are disposed above the substrate, noise sources generated by the capacitor electrodes being disposed in the substrate can be prevented.

[0099] Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.

Claims

1. A one-time programmable memory structure, characterized in that: include: substrate; a transistor located on the substrate, wherein the transistor includes a gate located on the substrate; Capacitors, including: a first electrode disposed above the substrate; a second electrode disposed on the first electrode, wherein the first electrode is located between the second electrode and the substrate; and an insulating layer disposed between the first electrode and the second electrode; and an interconnect structure electrically connected between the transistor and the first electrode of the capacitor, wherein the interconnect structure is electrically connected to the first electrode at a top surface of the first electrode, The top surface of the first electrode and the top surface of the gate are located on the same plane, and the plane is perpendicular to the direction from the first electrode to the second electrode.

2. The one-time programmable memory structure according to claim 1, wherein: The interconnection line structure directly contacts a top surface of the first electrode.

3. The one-time programmable memory structure according to claim 1, wherein: The transistor further includes: a gate dielectric layer disposed between the gate and the substrate; and The first doping region and the second doping region are located in the substrate at both sides of the gate.

4. The one-time programmable memory structure according to claim 3, wherein: The first electrode and the gate are derived from the same material layer.

5. The one-time programmable memory structure according to claim 3, wherein: The interconnect structure comprises: a first contact window electrically connected to the first doped region; a second contact window electrically connected to the first electrode; and A conductive line is electrically connected between the first contact window and the second contact window.

6. The one-time programmable memory structure according to claim 3, wherein: The interconnect structure comprises: A contact window is electrically connected between the first doped region and the first electrode.

7. The one-time programmable memory structure according to claim 6, wherein: The contact window directly contacts the first doped region and the first electrode.

8. The one-time programmable memory structure according to claim 1, wherein: The method includes a plurality of capacitors electrically connected to the same transistor.

9. The one-time programmable memory structure according to claim 1, wherein: Also includes: An isolation structure is located in the substrate, wherein the first electrode is disposed on the isolation structure.

10. A one-time programmable memory structure, characterized in that: include: substrate; a transistor located on the substrate, wherein the transistor includes a gate located on the substrate; Capacitors, including: a first electrode disposed above the substrate; a second electrode disposed on the first electrode, wherein the first electrode is located between the second electrode and the substrate; and an insulating layer disposed between the first electrode and the second electrode; and an interconnect structure electrically connected between the transistor and the second electrode of the capacitor, wherein the interconnect structure is electrically connected to the second electrode at a top surface of the second electrode, The top surface of the first electrode and the top surface of the gate are located on the same plane, and the plane is perpendicular to the direction from the first electrode to the second electrode.

11. The one-time programmable memory structure according to claim 10, wherein: The interconnection line structure directly contacts a top surface of the second electrode.

12. The one-time programmable memory structure according to claim 10, wherein: The transistor further includes: a gate dielectric layer disposed between the gate and the substrate; and The first doping region and the second doping region are located in the substrate at both sides of the gate.

13. The one-time programmable memory structure according to claim 12, wherein: The first electrode and the gate are derived from the same material layer.

14. The one-time programmable memory structure according to claim 12, wherein: The interconnect structure comprises: a first contact window electrically connected to the first doped region; a second contact window electrically connected to the second electrode; and A conductive line is electrically connected between the first contact window and the second contact window.

15. The one-time programmable memory structure according to claim 12, wherein: The interconnect structure comprises: A contact window is electrically connected between the first doped region and the second electrode.

16. The one-time programmable memory structure according to claim 15, wherein: The contact window directly contacts the first doped region and the second electrode.

17. The one-time programmable memory structure according to claim 10, wherein: The method includes a plurality of capacitors electrically connected to the same transistor.

18. The one-time programmable memory structure according to claim 10, wherein: Also includes: An isolation structure is located in the substrate, wherein the first electrode is disposed on the isolation structure.

19. A one-time programmable memory structure, characterized in that: include: a substrate including a memory region and a resistor region; a transistor located on the substrate and in the memory region, the transistor including a gate located on the substrate; a capacitor located in the memory area and comprising: a first electrode disposed above the substrate; a second electrode disposed on the first electrode, wherein the first electrode is located between the second electrode and the substrate; and an insulating layer, disposed between the first electrode and the second electrode; an interconnect structure electrically connected between the transistor and the first electrode of the capacitor, wherein the interconnect structure is electrically connected to the first electrode at a top surface of the first electrode; and a resistor located in the resistance region and comprising: a conductor layer disposed above the substrate, The top surface of the first electrode and the top surface of the gate are located on the same plane, and the plane is perpendicular to the direction from the first electrode to the second electrode.

20. The one-time programmable memory structure according to claim 19, wherein: The conductor layer and the second electrode are derived from the same material layer.

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