A semiconductor device including an interlayer insulating structure containing a metal-organic framework

Abstract

This application relates to a semiconductor device including an interlayer insulating structure containing a metal-organic framework. A semiconductor device according to an embodiment of the present disclosure includes: a substrate; a gate structure disposed above the substrate; a dielectric structure disposed above the substrate to contact a sidewall surface of the gate structure; and a channel layer disposed above the substrate on the sidewall surface of the dielectric structure. The gate structure includes an alternately stacked gate electrode layer and an interlayer insulating structure. The interlayer insulating structure includes a metal-organic framework layer.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices including an interlayer insulating structure. Background Art

[0002] According to the trend of reducing design rules and increasing integration density, semiconductor devices having a three-dimensional (3D) stacked structure have emerged. As an example of a semiconductor device having a 3D stacked structure, there is a NAND type flash memory including a channel layer extending in a direction perpendicular to a substrate and a plurality of memory cells sharing the channel layer with each other.

[0003] Recently, in a memory device having a 3D stacked structure, in order to increase the integration density of memory cells, attempts have been made to reduce the thickness of an interlayer insulating layer that insulates a plurality of memory cells stacked on a substrate from each other. However, when the thickness of the interlayer insulating layer is reduced, the parasitic capacitance between adjacent memory cells may increase and the signal interference between adjacent memory cells may increase. Therefore, in semiconductor devices having a three-dimensional stacked structure, research on semiconductor stacking technologies capable of achieving improved integration density and reliable signal processing operations has been continuously conducted. Summary of the Invention

[0004] A semiconductor device according to an embodiment of the present disclosure may include: a substrate; a gate structure disposed above the substrate; a dielectric structure disposed above the substrate to contact a sidewall surface of the gate structure; and a channel layer disposed above the substrate on the sidewall surface of the dielectric structure. The gate structure may include an alternately stacked gate electrode layer and an interlayer insulating structure. The interlayer insulating structure may include a metal-organic framework layer.

[0005] A semiconductor device according to another embodiment of the present disclosure may include: a substrate; a gate structure disposed above the substrate; a dielectric structure disposed above the substrate to contact a sidewall surface of the gate structure; and a vertical electrode layer disposed above the substrate on the sidewall surface of the dielectric structure and extending in a direction substantially perpendicular to a surface of the substrate. The gate structure may include an alternately stacked horizontal electrode layer and an interlayer insulating structure. The interlayer insulating structure may include a metal-organic framework layer.

[0006] A method of manufacturing a semiconductor device according to another embodiment is disclosed. In the method of manufacturing a semiconductor device, a substrate is prepared. A stacked structure is formed over the substrate. The stacked structure may include an insulating material layer and a sacrificial material layer stacked alternately with each other. The stacked structure may be selectively etched over the substrate to expose sidewall surfaces of the stacked structure. The sacrificial material layer may be removed through the exposed sidewall surfaces to form a recessed space. A metal-organic framework layer may be formed over the insulating material layer. A first conductive layer may be formed by filling the recessed space with a conductive material. The first conductive layer may be disposed between the metal-organic framework layers. A dielectric structure contacting the metal-organic framework layer and the first conductive layer may be formed over the substrate. A second conductive layer contacting the dielectric structure may be formed over the substrate.

[0007] A semiconductor device according to an embodiment of the present disclosure may include: a substrate; a gate structure disposed over the substrate; a dielectric structure disposed over the substrate to contact sidewall surfaces of the gate structure; and a channel layer disposed over the substrate on sidewall surfaces of the dielectric structure. The gate structure may include a stacked gate electrode layer and an interlayer insulating structure. The interlayer insulating structure may include a metal-organic framework. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram schematically illustrating a metal-organic framework according to an embodiment of the present disclosure.

[0009] Figure 2 is a diagram schematically illustrating a metal-organic framework layer according to an embodiment of the present disclosure.

[0010] Figure 3 is a perspective view schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 is along Figure 3 a cross-sectional view of the semiconductor device taken along line I-I'.

[0012] Figure 5 is in combination with Figure 3 and Figure 4 a circuit diagram of the semiconductor device.

[0013] Figure 6 is in combination with Figure 3 and Figure 4 a diagram schematically illustrating a method of operating a semiconductor device.

[0014] Figure 7 is a cross-sectional view schematically illustrating an electronic device according to another embodiment of the present disclosure.

[0015] Figure 8It is a cross-sectional view schematically illustrating an electronic device according to another embodiment of the present disclosure.

[0016] Figure 9 is Figure 8 a circuit diagram of a semiconductor device.

[0017] Figure 10 It is a cross-sectional view schematically illustrating an electronic device according to another embodiment of the present disclosure.

[0018] Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 18 It is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. Detailed Embodiments

[0020] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of components such as the width and thickness of components are enlarged in order to clearly show the components of each device. The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of these terms may be interpreted differently by those of ordinary skill in the art to which the embodiments belong. If the terms are clearly and specifically defined, these terms may be interpreted according to the definitions. Unless otherwise defined, the terms (including technical terms and scientific terms) used herein have the same meaning as that generally understood by those of ordinary skill in the art to which the embodiments belong.

[0021] In addition, unless clearly used otherwise in the context, the expression of the singular form of a word should be understood to include the plural form of the word. It will be understood that the terms "comprising," "including," or "having" are intended to specify the presence of features, numbers, steps, operations, components, elements, parts, or combinations thereof, but are not used to exclude the presence of one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof or the possibility of adding one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof.

[0022] In addition, when performing a method or a manufacturing method, unless a specific order is clearly described in the context, each process constituting the method may occur in a manner different from the prescribed order. In other words, each process may be performed in the same manner as the described order and may be performed substantially simultaneously. In addition, at least a part of the above processes may be performed in the reverse order.

[0023] In this specification, the term "predetermined direction" may represent a direction that encompasses a direction determined in a coordinate system and a direction opposite to the direction. As an example, in an x-y-z coordinate system, the x direction may encompass a direction parallel to the x direction. That is, the x direction may represent all of the direction in which the absolute value of the x-axis increases in the positive direction along the x-axis from the origin 0 and the direction in which the absolute value of the x-axis increases in the negative direction along the x-axis from the origin 0. In the x-y-z coordinate system, the y direction and the z direction may each be interpreted in substantially the same manner.

[0024] Various embodiments of the present disclosure may provide an interlayer insulating structure that electrically insulates different conductive layers adjacent to each other in a direction perpendicular to a substrate in a stacked structure provided above the substrate and including a plurality of conductive layers. The interlayer insulating structure may include a metal-organic framework layer. The metal-organic framework layer may mean that the metal-organic framework exists in the form of a thin film. The metal-organic framework may be a porous material formed by bonding a node including a metal and an organic ligand. The metal-organic framework may have a two-dimensional structure or a three-dimensional structure.

[0025] Figure 1 is a diagram schematically illustrating a metal-organic framework according to an embodiment of the present disclosure. Figure 2 is a diagram schematically illustrating a metal-organic framework layer according to an embodiment of the present disclosure.

[0026] Refer to Figure 1 , the metal-organic framework M may have a two-dimensional structure. The metal-organic framework M may be a material formed by bonding a node Ma including a metal and an organic ligand Mb. The node Ma including a metal may be, for example, a metal ion or a metal cluster.

[0027] In the metal-organic framework M, the metal constituting the node Ma may include, for example, zinc (Zn), chromium (Cr), indium (In), gallium (Ga), copper (Cu), iron (Fe), molybdenum (Mo), cobalt (Co), ruthenium (Ru), manganese (Mn), lanthanum (La), titanium (Ti), hafnium (Hf), cadmium (Cd), zirconium (Zr), etc. In the metal-organic framework M, the organic ligand Mb may include, for example, oxalic acid, fumaric acid, benzenehexathiol, hexamercaptotriphenylene, 1,4-benzenedicarboxylic acid, hexaaminobenzene, tetrakis(4-carboxyphenyl)-porphyrin-cobalt(II), tetrakis(4-carboxyphenyl)-porphyrin, etc. As another example, the organic ligand Mb may include H 2 BDC, H 2 BDC-Br, H 2 BDC-OH, H 2 BDC-NO 2 、H 2 BDC-NH 2 、H 4 DOT, H 2 BDC-(Me) 2 、H 2 BDC-(Cl) 2 etc.

[0028] Referring to Figure 1 , the metal-organic framework M may have a porous structure including a cavity C. In an embodiment, the metal-organic framework M may have a physically and chemically stable two-dimensional network bonding structure. As Figure 1 shown, in the metal-organic framework M, the coordination bonds between the node Ma including the metal and the organic ligand Mb may be regularly formed two-dimensionally. The metal-organic framework M may exist in the form of a sheet having a thickness of nanoscale (e.g., 1 nm to 100 nm).

[0029] In Figure 1 some other embodiments not shown, the metal-organic framework M may have a three-dimensional structure. The node Ma including the metal and the organic ligand Mb are disposed at fixed positions in a three-dimensional unit cell. For example, the metal-organic framework M having a three-dimensional structure may include a zeolitic imidazolate framework represented as ZIF-N (N is from 1 to 12). The metal-organic framework M having a three-dimensional structure may have a porous structure including a cavity C.

[0030] Referring to Figure 2, the metal-organic framework layer N may include a plurality of metal-organic frameworks M1, M2, M3, and M4. In an embodiment, the metal-organic framework layer N may have a form in which a plurality of sheet-like metal-organic frameworks M1, M2, M3, and M4 are stacked in the thickness direction (i.e., the z-direction). The metal-organic frameworks M1, M2, M3, and M4 may be bonded to each other by van der Waals forces acting in a direction perpendicular to the surface of the sheet (i.e., the z-direction) to form the metal-organic framework layer N.

[0031] Referring to Figure 1 and Figure 2 , the metal-organic framework layer N may ensure a low permittivity through the cavities inside the metal-organic framework layer N. As an example, the permittivity of the metal-organic framework layer N may be lower than that of silicon oxide. As an example, the dielectric constant K of the metal-organic framework layer N may be 2 or less. Additionally, because Figure 1 the metal-organic framework M has a stable two-dimensional network bonding structure, the metal-organic framework layer N, which is a laminate of a plurality of metal-organic frameworks M1, M2, M3, and M4, may maintain a structurally stable state.

[0032] In Figure 1 and Figure 2 In some other embodiments not shown, the metal-organic framework layer N may include a metal-organic framework having a three-dimensional structure. Because the metal-organic framework has a porous structure including cavities C, the metal-organic framework layer N may ensure a low permittivity. As an example, the dielectric constant K of the metal-organic framework layer N may be 2 or less.

[0033] Figure 3 is a perspective view schematically illustrating a semiconductor device 1 according to an embodiment of the present disclosure. Figure 4 is a cross-sectional view taken along line I-I' of the semiconductor device Figure 3 . Figure 5 is a circuit diagram of the semiconductor device in combination with Figure 3 and Figure 4 . Figure 6 is a diagram schematically illustrating a method of operating the semiconductor device in combination with Figure 3 and Figure 4 .

[0034] Referring together to Figure 3 and Figure 4, the semiconductor device 1 may include a substrate 101, a gate structure 10 disposed above the substrate 101, a dielectric structure 20 disposed above the substrate 101 to contact the sidewall surface 10W of the gate structure 10, and a channel layer 240 disposed above the substrate 101 on the sidewall surface 20W of the dielectric structure 20. The channel layer 240 may extend in a first direction (i.e., the z direction) perpendicular to the surface 101S of the substrate 101. A channel lower contact layer 105 and a channel upper contact layer 260 may be respectively disposed at opposite ends of the channel layer 240 extending in the z direction.

[0035] The substrate 101 may include a semiconductor material. For example, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc.

[0036] A base insulating layer 102 may be disposed on the substrate 101. The base insulating layer may include an insulating material. The insulating material may include, for example, an oxide, a nitride, a nitrogen oxide, or a combination of two or more of them.

[0037] Although not illustrated in Figure 1 , the substrate 101 may include an integrated circuit. The integrated circuit may constitute active elements such as diodes or transistors. At least one conductive layer and at least one insulating layer may be disposed between the substrate 101 and the base insulating layer 102. The conductive layer and the insulating layer may constitute passive elements such as capacitors or resistors.

[0038] Referring together to Figure 3 and Figure 4 , the channel lower contact layer 105 may be disposed on the base insulating layer 102. The channel lower contact layer 105 may be electrically connected to the channel layer 240. Although not shown, the channel lower contact layer 105 may be electrically connected to a source line. The channel lower contact layer 105 may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of them.

[0039] Referring together to Figure 3 and Figure 4, the gate structure 10 may be disposed on the channel under contact layer 105. The gate structure 10 may include a first gate electrode layer to a third gate electrode layer 120a, 120b, and 120c and a first interlayer insulating structure to a fourth interlayer insulating structure 130a, 130b, 130c, and 130d alternately stacked along a first direction (i.e., the z direction) perpendicular to the surface 101S of the substrate 101. The first interlayer insulating structure 130a may be disposed to contact the channel under contact layer 105. The fourth interlayer insulating structure 130d may be disposed on the uppermost layer of the gate structure 10.

[0040] The first gate electrode layer to the third gate electrode layer 120a, 120b, and 120c may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of them.

[0041] Referring to Figure 4 , the first interlayer insulating structure to the fourth interlayer insulating structure 130a, 130b, 130c, and 130d may include an inner insulating layer 110 and a metal-organic framework layer 115 disposed on the inner insulating layer 110. The metal-organic framework layer 115 may be disposed to surround the corresponding inner insulating layer 110. Specifically, in the first interlayer insulating structure 130a, the metal-organic framework layer 115 may be disposed to surround the upper surface 110S and the sidewall surface 110W of the inner insulating layer 110. In the second interlayer insulating structure to the fourth interlayer insulating structure 130b, 130c, and 130d, the metal-organic framework layer 115 may be disposed to surround the upper surface 110S, the lower surface 110B, and the sidewall surface 110W of the inner insulating layer 110.

[0042] The inner insulating layer 110 may include an insulating material. The insulating material may include, for example, an oxide, a nitride, a nitrogen oxide, or a combination of two or more of them.

[0043] The metal-organic framework layer 115 may include the metal-organic framework M described above with reference to Figure 1 The metal-organic framework layer 115 may be the metal-organic framework layer N described above with reference to Figure 2 That is, the metal-organic framework layer 115 may have a form in which a plurality of sheet-type metal-organic frameworks M1, M2, M3, and M4 are stacked in the thickness direction (i.e., the z direction), as Figure 2 shown.

[0044] Referring together Figure 3 and Figure 4 , the gate structure 10 may include a via pattern H1. The via pattern H1 may penetrate the gate structure 10 to expose the under-channel contact layer 105. Additionally, the via pattern H1 may expose the sidewall surface 10W of the gate structure 10.

[0045] The dielectric structure 20 may be disposed above the under-channel contact layer 105 to contact the sidewall surface 10W of the gate structure 10 that is inside the via pattern H1. The dielectric structure 20 may be a structure that extends in a first direction (i.e., the z-direction) perpendicular to the substrate 101 above the under-channel contact layer 105.

[0046] In an embodiment, the dielectric structure 20 may be a charge storage structure of a flash memory device. The dielectric structure 20 may include a blocking layer 210, a charge storage layer 220, and a tunneling layer 230. The blocking layer 210 may be disposed on the sidewall surface 10W of the gate structure 10. The blocking layer 210 may contact the metal-organic framework layers 115 of the first to third gate electrode layers 120a, 120b, and 120c and the first to fourth interlayer insulation structures 130a, 130b, 130c, and 130d. The charge storage layer 220 may be disposed on the sidewall surface of the blocking layer 210. The tunneling layer 230 may be disposed on the sidewall surface of the charge storage layer 220. The blocking layer 210, the charge storage layer 220, and the tunneling layer 230 may include oxides, nitrides, oxynitrides, or a combination of two or more of them.

[0047] Referring together Figure 3 and Figure 4 , the channel layer 240 may be disposed above the under-channel contact layer 105 on the sidewall surface 20W of the dielectric structure 20 that is inside the via pattern H1. The channel layer 240 may be disposed to contact the tunneling layer 230 of the dielectric structure 20. The channel layer 240 may extend in a first direction (i.e., the z-direction) perpendicular to the substrate 101 above the under-channel contact layer 105.

[0048] The channel layer 240 may include a semiconductor material. As an example, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. As another example, the semiconductor material may include two-dimensional (2D) semiconductor materials. The 2D semiconductor materials may include transition metal dichalcogenides (TMDCs), black phosphorus, etc. The transition metal dichalcogenides may include, for example, molybdenum selenide (MoSe 2 ), hafnium selenide (HfSe 2) Selenium indide (InSe), gallium selenide (GaSe), etc. The semiconductor material may include, for example, a metal oxide such as indium gallium zinc oxide (IGZO). The channel layer 240 may have conductivity. As an example, conductivity may be caused by doping an n-type or p-type dopant into the semiconductor material.

[0049] Referring together Figure 3 and Figure 4 , a filling insulating structure 250 may be disposed inside the hole pattern H1 in which the dielectric structure 20 and the channel layer 240 are disposed. The filling insulating structure 250 may include, for example, an oxide, a nitride, a oxynitride, or a combination of two or more of them.

[0050] In addition, inside the hole pattern H1, a channel upper contact layer 260 may be disposed on the filling insulating structure 250. The channel upper contact layer 260 may be electrically connected to the channel layer 240. Although not shown, the channel upper contact layer 260 may be electrically connected to the bit line.

[0051] The channel upper contact layer 260 may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of them.

[0052] In Figure 3 and Figure 4 , the channel upper contact layer 260 is illustrated as being disposed inside the hole pattern H1, but the present disclosure is not limited thereto. In some embodiments, the channel upper contact layer 260 may be disposed outside the hole pattern H1. As an example, the channel upper contact layer 260 may be disposed above the hole pattern H1 to be electrically connected to the channel layer 240.

[0053] Referring Figure 5 to the circuit diagram U1 of , the semiconductor device 1 may include first to third memory cells MC1, MC2, and MC3 in the form of transistors connected in series between a source line SL and a bit line BL. The semiconductor device 1 may be a NAND-type flash memory device having a string shape.

[0054] The first to third memory cells MC1, MC2, and MC3 may respectively include corresponding first to third gate electrodes GL1, GL2, and GL3 and first to third dielectric structures DL1, DL2, and DL3. Figure 5The first gate electrode to the third gate electrodes GL1, GL2, and GL3 can respectively correspond to Figure 3 and Figure 4 the first gate electrode layer to the third gate electrode layers 120a, 120b, and 120c in the semiconductor device 1 of Figure 5 The first dielectric structure to the third dielectric structures DL1, DL2, and DL3 can respectively correspond to Figure 3 and Figure 4 the regions of the dielectric structure 20 in the semiconductor device 1 of

[0055] will describe the function of the metal-organic framework layer 115 of the semiconductor device 1 with reference to Figure 6 The metal-organic framework layer 115 can form the first interlayer insulation structure to the fourth interlayer insulation structures 130a, 130b, 130c, and 130d together with the inner insulation layer 110. As an example, the metal-organic framework layer 115 can have a low dielectric constant K of 2 or less. Therefore, the first interlayer insulation structure to the fourth interlayer insulation structures 130a, 130b, 130c, and 130d can effectively reduce the parasitic capacitance generated between the first gate electrode layer to the third gate electrode layers 120a, 120b, and 120c. As a result, the RC delay phenomenon caused by the parasitic capacitance can be alleviated.

[0056] In addition, considering the low dielectric constant of the metal-organic framework layer 115 described above, the height of the first interlayer insulation structure to the fourth interlayer insulation structures 130a, 130b, 130c, and 130d provided between the first gate electrode layer to the third gate electrode layers 120a, 120b, and 120c can be reduced. Therefore, by reducing the height of the first interlayer insulation structure to the fourth interlayer insulation structures 130a, 130b, 130c, and 130d, the number of memory cells stacked in the z direction can be increased. As a result, the integration degree of the memory cells of the semiconductor device 1 can be improved.

[0057] In addition, the metal-organic framework layer 115 can effectively control the electrical signal interference between the gate electrode layers 120a, 120b, and 120c. As an implementation, in the case of performing a programming operation or an erasing operation on the second memory cell MC2 having the second gate electrode layer 120b, reference will be made to Figure 6 to describe the signal interference control effect of the metal-organic framework layer 115.

[0058] First, a channel voltage can be applied between the under-channel contact layer 105 and the over-channel contact layer 260 so that electrons can conduct along the z-direction in the channel layer 240. Subsequently, a programming voltage with a positive polarity or an erasing voltage with a negative polarity can be applied to the second gate electrode layer 120b to form an electric field between the second gate electrode layer 120b and the channel layer 240. In addition to the programming electric field E1 acting on the operation region belonging to the second memory cell MC2 (e.g., a part 210B of the blocking layer 210, a part 220B of the charge storage layer 220, a part 230B of the tunneling layer 230, and a part 240B of the channel layer 240), the electric field can include edge electric fields E2 and E3 formed by bypassing the outside of the operation region. In this case, the edge electric field E2 can apply an electric attractive force or a repulsive force to the charges stored in a part 220C of the charge storage layer 220 of the third memory cell MC3 electrically controlled by the third gate electrode layer 120c. As a result, the amount of charge stored in a part 220C of the charge storage layer 220 of the third memory cell MC3 can be changed. In addition, the edge electric field E3 can apply an electric attractive force or a repulsive force to the charges stored in a part 220A of the charge storage layer 220 of the first memory cell MC1 electrically controlled by the first gate electrode layer 120a. As a result, the amount of charge stored in a part 220A of the charge storage layer 220 of the first memory cell MC1 can be changed. The edge electric fields E2 and E3 can change the signal information stored in the first memory cell MC1 and the third memory cell MC3.

[0059] In addition, the edge electric field can be generated by the gate voltage applied to the first gate electrode layer 120a of the first memory cell MC1 or the third gate electrode layer 120c of the third memory cell MC3. The edge electric field can change the amount of charge stored in a part 220B of the charge storage layer 220 of the second memory cell MC2. Therefore, the signal information stored in the second memory cell MC2 can be changed.

[0060] According to an embodiment of the present disclosure, the metal-organic framework layers 115 of the first interlayer insulation structure to the fourth interlayer insulation structures 130a, 130b, 130c, and 130d can include cavities. The cavities can weaken or suppress the edge electric field passing through the metal-organic framework layer 115. Therefore, it is possible to reduce the degradation of the signal information of the memory cell generated by the edge electric field and improve the reliability of the signal information.

[0061] Figure 7 is a cross-sectional view schematically illustrating a semiconductor device 2 according to another embodiment of the present disclosure. Figure 7 The semiconductor device 2 is different from the semiconductor device 1 described above with reference to Figure 3 and Figure 4 in the structure of the gate structure 11.

[0062] Referring to Figure 7 , the gate structure 11 may include first to third gate electrode layers 120a, 120b, and 120c stacked alternately over the channel under contact layer 105, and first to fourth interlayer insulation structures 135a, 135b, 135c, and 135d.

[0063] The first to fourth interlayer insulation structures 135a, 135b, 135c, and 135d may include a metal-organic framework layer 115 and an air gap AG. In an embodiment, the air gap AG may be formed by removing Figure 3 and Figure 4 the inner insulation layer 110 of the first to fourth interlayer insulation structures 130a, 130b, 130c, and 130d in the semiconductor device 1. Thus, in Figure 7 the semiconductor device 2, the metal-organic framework layer 115 of the first to fourth interlayer insulation structures 135a, 135b, 135c, and 135d may be arranged to surround the air gap AG. In an embodiment, the air gap AG may include a gas present in air. In another embodiment, the air gap AG may include other gases in addition to the gas present in air. For example, the air gap AG may include any gas provided for the semiconductor process and any gas formed from the semiconductor process.

[0064] The first to fourth interlayer insulation structures 135a, 135b, 135c, and 135d include the air gap AG, such that Figure 3 and Figure 4 compared with the first to fourth interlayer insulation structures 130a, 130b, 130c, and 130d of the semiconductor device 1, the permittivity of the first to fourth interlayer insulation structures 135a, 135b, 135c, and 135d may be further reduced. As a result, the parasitic capacitance between the plurality of gate electrode layers 120a, 120b, and 120c may be further reduced, enabling further improvement of the RC delay phenomenon.

[0065] Figure 8 is a cross-sectional view schematically illustrating a semiconductor device 3 according to yet another embodiment of the present disclosure. Figure 9 is Figure 8 a schematic circuit diagram of the semiconductor device 3. Figure 8 The semiconductor device 3 differs from the semiconductor device 1 described above with reference to Figure 3 and Figure 4 in the configuration of the dielectric structure 21.

[0066] Referring to Figure 8, the dielectric structure 21 of the semiconductor device 3 may include a ferroelectric memory layer 215 disposed on the sidewall surface 10W of the gate structure 10 above the channel contact layer 105 and an interface insulating layer 225 disposed on the sidewall surface of the ferroelectric memory layer 215.

[0067] The ferroelectric memory layer 215 may include a ferroelectric material. The ferroelectric material may include, for example, binary metal oxides such as hafnium oxide, zirconium oxide, etc. As another example, the ferroelectric material may include perovskite-based materials such as lead zirconate titanate (PZT), bismuth strontium titanate (SBT), etc.

[0068] The interface insulating layer 225 may include, for example, oxides, nitrides, oxynitrides, etc. Specifically, the interface insulating layer 225 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, etc.

[0069] Referring to Figure 9 the circuit diagram U2, the semiconductor device 3 may include first to third memory cells MC1, MC2, and MC3 in the form of transistors connected in series between the source line SL and the bit line BL.

[0070] The first to third memory cells MC1, MC2, and MC3 may respectively include corresponding first to third gate electrodes GL1, GL2, and GL3 and first to third ferroelectric memory elements FL1, FL2, and FL3. The first to third ferroelectric memory elements FL1, FL2, and FL3 may have memory characteristics capable of storing polarization non-volatilely. The first to third gate electrodes GL1, GL2, and GL3 may respectively correspond to Figure 8 the first to third gate electrode layers 120a, 120b, and 120c in the semiconductor device 3 of Figure 8 The first to third ferroelectric memory elements FL1, FL2, and FL3 may respectively correspond to the portions of the ferroelectric memory layer 215 in the semiconductor device 3 of

[0071] Referring again to Figure 8 , the first to fourth interlayer insulating structures 130a, 130b, 130c, and 130d may include a metal-organic framework layer 115 having cavities. When a voltage is applied between the gate electrode layers 120a, 120b, and 120c and the channel layer 240, the cavities may weaken or suppress the edge electric field passing through the metal-organic framework layer 115. Therefore, changes in polarization, which is the signal information stored in the ferroelectric layer portion of the target memory cell, caused by the edge electric field can be prevented or reduced. Therefore, the reliability of the signal information stored in the memory cell can be improved.

[0072] Figure 10 FIG. 3 schematically illustrates a cross-sectional view of a semiconductor device 4 according to yet another embodiment of the present disclosure. The semiconductor device 4 may include a substrate 301, an electrode structure 30 disposed above the substrate 301, and a dielectric structure 40. Additionally, the semiconductor device 4 may include a vertical electrode layer 440 disposed on a sidewall surface 40W of the dielectric structure 40 above the substrate 301.

[0073] Referring to Figure 10 , the substrate 301 may be provided. A base insulating layer 302 may be disposed on the substrate 301. A lower conductive layer 305 may be disposed on the base insulating layer 302. The configurations of the substrate 301 and the base insulating layer 302 of the semiconductor device 4 may be substantially the same as those of the substrate 101 and the base insulating layer 102 of the semiconductor device 1 described above in connection with Figure 3 and Figure 4 . The lower conductive layer 305 may include a conductive material. In an embodiment, the lower conductive layer 305 may be electrically connected to a source line. The lower conductive layer 305 may be made of a material substantially the same as that of the under-channel contact layer 105 of the semiconductor device 1 described above in connection with Figure 3 and Figure 4 . The lower conductive layer 305 may be electrically connected to the vertical electrode layer 440.

[0074] The electrode structure 30 may be disposed on the lower conductive layer 305. The electrode structure 30 may include first to third horizontal electrode layers 320a, 320b, and 320c and first to fourth interlayer insulating structures 330a, 330b, 330c, and 330d that are alternately stacked on each other. The first to third horizontal electrode layers 320a, 320b, and 320c may be disposed on a surface substantially parallel to the surface 301S of the substrate 301. Similarly, the first to fourth interlayer insulating structures 330a, 330b, 330c, and 330d may be disposed on a surface substantially parallel to the surface 301S of the substrate 301.

[0075] The first to third horizontal electrode layers 320a, 320b, and 320c may include a conductive material. In an embodiment, the first to third horizontal electrode layers 320a, 320b, and 320c may be made of a material substantially the same as that of the first to third gate electrode layers 120a, 120b, and 120c described above in connection with Figure 3 and Figure 4 and may have dimensions substantially the same as those of the first to third gate electrode layers 120a, 120b, and 120c described above in connection with Figure 3 and Figure 4The described first to third gate electrode layers 120a, 120b, and 120c have substantially the same structure. The first to fourth interlayer insulation structures 330a, 330b, 330c, and 330d can be substantially the same as the first to fourth interlayer insulation structures 130a, 130b, 130c, and 130d described with reference to Figure 3 and Figure 4 That is, the first to fourth interlayer insulation structures 330a, 330b, 330c, and 330d can include an inner insulation layer 310 and a metal-organic framework layer 315. The inner insulation layer 310 and the metal-organic framework layer 315 can be substantially the same as the inner insulation layer 110 and the metal-organic framework layer 115 described with reference to Figure 3 and Figure 4 respectively.

[0076] Referring to Figure 10 , the electrode structure 30 can include a via pattern H2. The via pattern H2 can penetrate the electrode structure 30 to expose the lower conductive layer 305. Additionally, the via pattern H2 can expose the sidewall surface 30W of the electrode structure 30.

[0077] The dielectric structure 40 can be disposed above the lower conductive layer 305 to contact the sidewall surface 30W of the electrode structure 30 located inside the via pattern H2. The dielectric structure 40 can include a variable resistance layer containing a resistive change material. The resistive change material can, for example, represent a material having an internal resistance that changes upon stimulation such as a voltage or current applied from the outside. Additionally, after removing the external stimulation, the resistive change material can non-volatily store the changed resistance. The dielectric structure 40 can include a single variable resistance layer or two or more variable resistance layers.

[0078] The variable resistance layer can include a metal oxide containing oxygen vacancies or mobile metal ions as the resistive change material. In an embodiment, the resistance of the metal oxide can vary according to the concentration and distribution state of the oxygen vacancies or mobile metal ions. The metal oxide can include, for example, lithium oxide, titanium oxide, nickel oxide, copper oxide, manganese oxide, hafnium oxide, zirconium oxide, tungsten oxide, niobium oxide, vanadium oxide, or a combination of two or more of them.

[0079] Referring to Figure 10 , the vertical electrode layer 440 can be disposed on the sidewall surface 40W of the dielectric structure 40 on the lower conductive layer 305. The vertical electrode layer 440 can extend in a direction substantially perpendicular to the surface 301S of the substrate 301. The vertical electrode layer 440 can include a conductive material. The vertical electrode layer 440 can be made of substantially the same material as the first to third horizontal electrode layers 320a, 320b, and 320c.

[0080] The filling insulating structure 450 can be disposed inside the hole pattern H2 in which the dielectric structure 40 and the vertical electrode layer 440 are disposed. The filling insulating structure 450 can include, for example, an oxide, a nitride, a oxynitride, or a combination of two or more of them.

[0081] In addition, inside the hole pattern H2, the upper conductive layer 460 can be disposed on the filling insulating structure 450. The upper conductive layer 460 can be electrically connected to the vertical electrode layer 440. Although not shown, the upper conductive layer 460 can be electrically connected to the bit line. The upper conductive layer 460 can include a conductive material. The upper conductive layer 460 can be made of a material substantially the same as that of the channel upper contact layer 260 of the semiconductor device 1 described with reference to Figure 3 and Figure 4 .

[0082] In some embodiments other than the Figure 10 illustrated embodiment, an air gap can be provided instead of the inner insulating layer 310. Thus, the first to fourth interlayer insulating structures 330a, 330b, 330c, and 330d can include a metal-organic framework layer 315 and an air gap. The configuration of the first to fourth interlayer insulating structures 330a, 330b, 330c, and 330d including the air gap and the metal-organic framework layer 315 can be substantially the same as the configuration of the first to fourth interlayer insulating structures 135a, 135b, 135c, and 135d of the semiconductor device 2 described above with reference to Figure 7 .

[0083] In the present embodiment, when an operating voltage is applied between the horizontal electrode layer selected from the first to third horizontal electrode layers 320a, 320b, and 320c and the vertical electrode layer 440, the resistance inside the dielectric structure 40 controlled by the operating voltage can be changed. The changed resistance can be stored as signal information of the memory cell. In Figure 10 , the first to third memory cells can be provided respectively between the first to third horizontal electrode layers 320a, 320b, and 320c and the vertical electrode layer 440.

[0084] In the present embodiment, the first to fourth interlayer insulation structures 330a, 330b, 330c, and 330d including the metal-organic framework layer 315 can effectively reduce the parasitic capacitance generated between the first to third horizontal electrode layers 320a, 320b, and 320c. Additionally, the cavities of the metal-organic framework layer 315 can effectively control the edge electric field between the first to third horizontal electrode layers 320a, 320b, and 320c and the vertical electrode layer 440. Therefore, the degradation of the resistance stored in the variable resistance layer of the memory cell due to the edge electric field can be improved. As a result, the reliability of the signal information stored in the memory cell can be enhanced.

[0085] Figures 11 to 17 is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. The method to be referred to Figures 11 to 17 described can be applied to the method of manufacturing Figure 3 and Figure 4 semiconductor device 1, Figure 8 semiconductor device 3, and Figure 10 semiconductor device 4.

[0086] Referring to Figure 11 , a substrate 1101 including a base insulating layer 1102 can be prepared. The substrate 1101 and the base insulating layer 1102 can be substantially the same as the substrate 101 and the base insulating layer 102 of the semiconductor device 1 described with reference to Figure 3 and Figure 4 .

[0087] The lower conductive layer 1105 can be formed on the base insulating layer 1102. The lower conductive layer 1105 can include a conductive material. The conductive material can include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material can include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of them. The lower conductive layer 1105 can be formed by using, for example, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, etc.

[0088] The stacked structure 1000 can be formed on the lower conductive layer 1105. The stacked structure 1000 can include a plurality of insulating material layers 1110 and a plurality of sacrificial material layers 1130 that are alternately stacked with each other. The insulating material layer 1110 can be formed on the lowermost layer and the uppermost layer of the stacked structure 1000.

[0089] The insulating material layer 1110 and the sacrificial material layer 1130 may have an etching selectivity with respect to each other. The insulating material layer 1110 may include, for example, an oxide, a nitride, a oxynitride, or a combination of two or more of them. The sacrificial material layer 1130 may include, for example, a material selected from an oxide, a nitride, a oxynitride, silicon (Si), or a combination of two or more of them to have an etching selectivity with respect to the insulating material layer 1110.

[0090] Referring to Figure 12 , the stacked structure 1000 may be selectively etched to form a via pattern H on the lower conductive layer 1105. The sidewall surface 1000W of the stacked structure 1000 may be exposed through the via pattern H. Additionally, the lower conductive layer 1105 may be exposed through the via pattern H. The etching of the stacked structure 1000 may be performed by a photolithography process and an anisotropic etching process. As an example, as the anisotropic etching process, a dry etching method using plasma may be applied.

[0091] Referring to Figure 13 , the sacrificial material layer ( Figure 12 1130 of ) may be removed from the exposed sidewall surface 1000W of the stacked structure 1000 through Figure 12 to form a recessed space R1. The sacrificial material layer may be removed by an anisotropic etching process. In an embodiment, the sacrificial material layer 1130 may be wet-etched by providing an etchant having an etching selectivity with respect to the insulating material layer 1110 into the via pattern H to remove the sacrificial material layer. In this case, the etchant may not etch the lower conductive layer 1105.

[0092] Referring to Figure 14 , the metal-organic framework layer 1115 may be formed on the insulating material layer 1110. The metal-organic framework layers 1115 may each have a form in which a plurality of sheet-like metal-organic frameworks ( Figure 2 M1, M2, M3, and M4) are stacked in the thickness direction, as described above in connection with Figure 2 . The plurality of metal-organic frameworks M1, M2, M3, and M4 may be bonded to each other by van der Waals forces, thereby forming a thin film.

[0093] The plurality of metal-organic frameworks M1, M2, M3, and M4 may be as Figure 1A material formed by coordination of a node comprising a metal with an organic ligand. The node comprising a metal can be, for example, a metal ion or a metal cluster. The metal constituting the node can include, for example, zinc (Zn), chromium (Cr), indium (In), gallium (Ga), copper (Cu), iron (Fe), molybdenum (Mo), cobalt (Co), ruthenium (Ru), manganese (Mn), lanthanum (La), titanium (Ti), hafnium (Hf), cadmium (Cd), zirconium (Zr), etc. The organic ligand can include, for example, oxalic acid, fumaric acid, benzenehexathiol, hexamercaptotriphenylene, 1,4-benzenedicarboxylic acid, hexaaminobenzene, tetrakis(4-carboxyphenyl)-porphyrin-cobalt(II), tetrakis(4-carboxyphenyl)-porphyrin, etc. As another example, the organic ligand Mb can include H 2 BDC, H 2 BDC-Br, H 2 BDC-OH, H 2 BDC-NO 2 , H 2 BDC-NH 2 , H 4 DOT, H 2 BDC-(Me) 2 , H 2 BDC-(Cl) 2 etc.

[0094] In an embodiment, the metal-organic framework layer 1115 can be formed by using an atomic layer deposition method. The metal-organic framework layer 1115 can be formed by stacking two-dimensional sheet-type metal-organic frameworks including cavities or three-dimensional metal-organic frameworks including cavities. In the atomic layer deposition method, for example, trimethylaluminum (AlMe 3 ) or dimethylaluminum isopropoxide ([Al-Me 2 i OPr] 2 ) can be used as a precursor.

[0095] Referring to Figure 14 , the metal-organic framework layer 1115 can be formed to surround the insulating material layer 1110. That is, the metal-organic framework layer 1115 can be formed on the upper surface 1110S, sidewall surface 1110W, and lower surface 1110B of the insulating material layer 1110. When the lowermost insulating material layer 1110 is in contact with the lower conductive layer 1105, the metal-organic framework layer 1115 can be formed on the upper surface 1110S and sidewall surface 1110W of the lowermost insulating material layer 1110.

[0096] Referring to Figure 15 , it can be filled with a conductive material Figure 14A recessed space R1 is formed to form a first conductive layer 1120. In this case, the first conductive layer 1120 can contact the metal-organic framework layer 1115 in the z direction. In an embodiment, the first conductive layer 1120 can be formed, for example, by depositing a conductive material layer using a chemical vapor deposition method, an atomic layer deposition method, etc. In this case, the process of forming the first conductive layer 1120 can include a process of at least filling the recessed space R1 with the conductive material layer and a process of performing anisotropic etching to remove the conductive material layer formed outside the recessed space R1 in the hole pattern H.

[0097] Referring to Figure 16 , a dielectric structure 2000 can be formed to contact the metal-organic framework layer 1115 and the first conductive layer 1120 in the hole pattern H. The process of forming the dielectric structure 2000 can include forming a first dielectric layer 1210 on the sidewall surfaces of the metal-organic framework layer 1115 and the first conductive layer 1120 in the hole pattern H, forming a second dielectric layer 1220 on the sidewall surface of the first dielectric layer 1210, and forming a third dielectric layer 1230 on the sidewall surface of the second dielectric layer 1220.

[0098] The process of forming the first to third dielectric layers 1210, 1220, and 1230 can include depositing dielectric thin films corresponding to the first to third dielectric layers 1210, 1220, and 1230, and patterning the deposited dielectric thin films to be disposed in a plane parallel to the z direction. The dielectric thin films can be deposited by, for example, a chemical vapor deposition method, an atomic layer deposition method, a sputtering method, etc. The dielectric thin films can be patterned by, for example, an anisotropic etching method using plasma.

[0099] In an embodiment, the first to third dielectric layers 1210, 1220, and 1230 can respectively correspond to the barrier layer 210, the charge storage layer 220, and the tunneling layer 230 of the dielectric structure 20 described in conjunction with Figure 3 and Figure 4 . In another embodiment, the first dielectric layer 1210 and the second dielectric layer 1220 can respectively correspond to the ferroelectric memory layer 215 and the interface insulating layer 225 of the dielectric structure 21 described in conjunction with Figure 8 . In this case, the third dielectric layer 1230 can be omitted. In yet another embodiment, the first to third dielectric layers 1210, 1220, and 1230 can constitute the dielectric structure described in conjunction with Figure 10The described dielectric structure 40. Thus, at least one of the first to third dielectric layers 1210, 1220, and 1230 can be a variable resistance layer including a resistance change material. When the dielectric structure 40 consists of a single variable resistance layer, only one of the first to third dielectric layers 1210, 1220, and 1230 can be formed, and the remaining dielectric layers can be omitted.

[0100] Referring to Figure 16 , a second conductive layer 1240 can be formed to contact the dielectric structure 2000 on the lower conductive layer 1105. The second conductive layer 1240 can include a conductive material. The conductive material can include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of them doped with an n-type or p-type dopant.

[0101] The process of forming the second conductive layer 1240 can include depositing a conductive material layer inside the hole pattern H and patterning the deposited conductive material layer to be disposed in a plane parallel to the z direction. The conductive material layer can be deposited by, for example, a chemical vapor deposition method, an atomic layer deposition method, a sputtering method, etc. The conductive material layer can be patterned by, for example, an anisotropic etching method using plasma.

[0102] Referring to Figure 17 , the hole pattern H in which the dielectric structure 2000 and the second conductive layer 1240 are formed can be filled with an insulating material to form a filled insulating structure 1250. The filled insulating structure 1250 can include, for example, an oxide, a nitride, a nitrogen oxide, or a combination of two or more of them. As an example, the filled insulating structure 1250 can be formed by applying a chemical vapor deposition method, a coating method, a sputtering method, etc.

[0103] Subsequently, the upper portion of the filled insulating structure 1250 can be removed, and the side surface of the second conductive layer 1240 can be exposed. Subsequently, an upper conductive layer 1260 can be formed to contact the exposed side surface of the second conductive layer 1240. The upper conductive layer 1260 can include a conductive material. As an example, the upper conductive layer 1260 can be made of substantially the same material as the lower conductive layer 1150. The upper conductive layer 1260 can be formed by, for example, using a chemical vapor deposition method, an atomic layer deposition method, etc. A semiconductor device according to an embodiment of the present disclosure can be manufactured by the above process.

[0104] Figure 18 is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. Referring to Figure 18The described manufacturing method can be applied to Figure 7 the manufacturing method of the semiconductor device 2.

[0105] After performing the manufacturing method of the semiconductor device described with reference to Figures 11 to 17 it is possible to continuously perform the manufacturing method of the semiconductor device related to Figure 18 . With reference to Figure 18 , in the structure of the semiconductor device of Figure 17 , the insulating material layer 1110 can be selectively etched to form an air gap AG.

[0106] In an embodiment, the process of forming the air gap AG can be performed as follows. Although Figure 18 not shown, a hole or trench passing through the insulating material layer ( Figure 17 1110 of) and the first conductive layer 1120 can be formed on the lower conductive layer 1105. Subsequently, the insulating material layer ( Figure 17 1110 of) can be etched by providing an etchant to the insulating material layer exposed via the hole or trench. Therefore, an air gap AG can be formed in the space surrounded by the metal-organic framework layer 1115. Through the above process, a semiconductor device according to an embodiment of the present disclosure can be manufactured.

[0107] Embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will recognize that various modifications, additions, and substitutions can be made without departing from the scope and spirit of the present disclosure and the appended claims.

[0108] Cross-reference to related applications

[0109] This application claims priority to Korean Application No. 10-2021-0049477, filed on April 15, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprises: a substrate; a gate structure disposed above the substrate, the gate structure including alternately stacked gate electrode layers and interlayer insulation structures; a dielectric structure disposed above the substrate to contact sidewall surfaces of the gate structure; and a channel layer disposed above the substrate on sidewall surfaces of the dielectric structure, wherein the interlayer insulation structure includes a metal-organic framework layer and an inner insulation layer, wherein the metal-organic framework layer contacts a surface of the gate electrode layer in a vertical direction, wherein the inner insulation layer is spaced apart from the gate electrode layer and fills an entire space between the metal-organic framework layers in the vertical direction, and wherein the inner insulation layer includes any one of an oxide, a nitride, and a nitrogen oxide.

2. The semiconductor device according to claim 1, wherein the metal-organic framework layer is arranged to contact the gate electrode layer and the dielectric structure.

3. The semiconductor device according to claim 1, wherein the metal-organic framework layer is arranged to surround the inner insulation layer.

4. The semiconductor device according to claim 1, wherein the metal-organic framework layer has a porous structure.

5. The semiconductor device according to claim 1, wherein the metal-organic framework layer includes a metal-organic framework containing cavities.

6. The semiconductor device according to claim 1, wherein the dielectric structure includes: a barrier layer disposed on sidewall surfaces of the gate structure; a charge storage layer disposed on sidewall surfaces of the barrier layer; and a tunneling layer disposed on sidewall surfaces of the charge storage layer.

7. The semiconductor device according to claim 1, wherein the dielectric structure includes: a ferroelectric memory layer disposed on sidewall surfaces of the gate structure; and an interface insulating layer disposed on sidewall surfaces of the ferroelectric memory layer.

8. The semiconductor device according to claim 1, wherein the channel layer extends in a direction perpendicular to a surface of the substrate.

9. The semiconductor device according to claim 8, the semiconductor device further comprises: a sub-channel contact layer and an upper-channel contact layer, the sub-channel contact layer and the upper-channel contact layer being disposed at opposite ends of the channel layer in a direction perpendicular to a surface of the substrate, wherein the sub-channel contact layer and the upper-channel contact layer are electrically connected to a source line and a bit line, respectively.

10. A semiconductor device, the semiconductor device comprises: a substrate; a gate structure disposed above the substrate, the gate structure including alternately stacked horizontal electrode layers and interlayer insulation structures; a dielectric structure disposed above the substrate to contact sidewall surfaces of the gate structure; and a vertical electrode layer disposed above the substrate on sidewall surfaces of the dielectric structure and extending in a direction perpendicular to a surface of the substrate, Among them, the interlayer insulation structure includes a metal-organic framework layer and an inner insulation layer. Among them, the metal-organic framework layer contacts the surface of the horizontal electrode layer in the vertical direction. Among them, the inner insulation layer is spaced apart from the horizontal electrode layer and fills the entire space between the metal-organic framework layers in the vertical direction, and Among them, the inner insulation layer includes any one of oxides, nitrides, and oxynitrides.

11. The semiconductor device according to claim 10, wherein, the metal-organic framework layer is arranged to surround the inner insulation layer.

12. The semiconductor device according to claim 10, wherein, the metal-organic framework layer has a porous structure.

13. The semiconductor device according to claim 10, wherein, the metal-organic framework layer includes a metal-organic framework containing cavities.

14. A method of manufacturing a semiconductor device, the method comprises the following steps: preparing a substrate; forming a stacked structure above the substrate, the stacked structure including an insulating material layer and a sacrificial material layer stacked alternately with each other; selectively etching the stacked structure above the substrate to expose the sidewall surface of the stacked structure; removing the sacrificial material layer through the exposed sidewall surface to form a recessed space; forming a metal-organic framework layer on the insulating material layer; forming a first conductive layer by filling the recessed space with a conductive material, the first conductive layer being disposed between the metal-organic framework layers; forming a dielectric structure above the substrate that contacts the metal-organic framework layer and the first conductive layer; and forming a second conductive layer above the substrate that contacts the dielectric structure, wherein the method further comprises removing the insulating material layer to form an air gap.

15. The method according to claim 14, wherein, forming the metal-organic framework layer includes the following steps: forming a metal-organic framework containing cavities.

16. The method according to claim 14, wherein, the step of forming the metal-organic framework layer is performed by an atomic layer deposition method.

17. The method according to claim 14, wherein, in the step of forming the metal-organic framework layer, the metal-organic framework layer is formed to surround the insulating material layer.

18. The method according to claim 14, wherein, the step of forming the air gap is performed after the step of forming the second conductive layer.

19. A semiconductor device, the semiconductor device comprises: a gate structure, the gate structure including a stacked gate electrode layer and an interlayer insulation structure; a dielectric structure, the dielectric structure being arranged to contact the sidewall surface of the gate structure; and a channel layer, the channel layer being disposed on the sidewall surface of the dielectric structure, wherein, the interlayer insulation structure includes a metal-organic framework and an inner insulation layer, wherein, the metal-organic framework layer contacts the surface of the gate electrode layer in the vertical direction, wherein, the inner insulation layer is spaced apart from the gate electrode layer and fills the entire space between the metal-organic framework layers in the vertical direction, and Among them, the inner insulating layer includes any one of oxides, nitrides, and oxynitrides.

Images