A fast recovery diode and its manufacturing method and application

Abstract

The application provides a fast recovery diode, a manufacturing method and application thereof. The fast recovery diode comprises a substrate, opposite sides of the surface of the substrate are respectively provided with a P+ cutoff ring region and a P-type active region, the surface of the substrate is further provided with a P+ field limiting ring region and a main junction region at a position between the P+ cutoff ring region and the P-type active region, and the P+ field limiting ring region and the main junction region are sequentially arranged in a direction of the P-type active region along the P+ cutoff ring region; the P-type active region comprises a P-body region with low ion concentration doping and a shallow P+ region with high ion concentration doping, and the P-body region and the shallow P+ region are sequentially arranged in the direction of the P-type active region along the P+ cutoff ring region; wherein the junction depth and the carrier concentration of the P-body region are different from those of the P+ field limiting ring region and the P+ cutoff ring region. In the application, a voltage drop is generated between the P-body region and the P+ field limiting ring region, and at the same time, due to the low ion concentration doping of the P-body region, the width of the depletion region on the side of the main junction region close to the P-body region can be expanded, thereby effectively improving the voltage resistance performance of the fast recovery diode.

Description

[0001] The application relates to the technical field of power electronic devices, in particular to a fast recovery diode and a manufacturing method and application thereof.

[0002] In the related art, a traditional FRD (Fast recovery diode) is mainly subjected to life control through heavy metal (such as nickel-platinum alloy) doping or electron irradiation, that is, the life of minority carriers in the chip is reduced, so that the minority carriers of the FRD can be quickly extracted and recombined during reverse recovery, thereby reducing the reverse recovery time of the FRD. However, if the reverse recovery time of the FRD is to be further reduced to the range of tens of nanoseconds, the concentration of recombination centers introduced into the chip must be increased, which will bring risks such as large leakage current and poor reliability to the FRD, and degrade the performance of the FRD. In addition, the doping of metal will cause the voltage drop of the FRD to have a negative temperature coefficient, which is not conducive to the parallel use of the FRD and an insulated gate bipolar transistor. In addition, the traditional FRD also has many drawbacks, such as: the edge electric field of the FRD terminal is relatively concentrated, which reduces the withstand voltage of the FRD and increases the leakage current, thereby causing the performance of the FRD to deteriorate or be broken down, and further causing the FRD to fail, at which time a protection technology needs to be used at the terminal of the FRD to reduce the surface electric field strength of the edge of the terminal of the FRD and improve the withstand voltage level of the FRD; the reverse recovery time of the FRD is the main factor affecting the turn-off loss thereof, and the forward conduction voltage drop is the main factor affecting the turn-on loss thereof, which makes it contradictory to improve the reverse recovery time of the FRD and reduce the forward conduction voltage drop of the FRD; the recovery softness of the FRD is directly related to the peak current thereof, that is, the harder the recovery characteristic of the FRD is, the greater the peak current is, thereby causing the FRD to bear excessive power consumption, and further causing the performance of the FRD to deteriorate or the service life to decrease; the current of the FRD is prone to instantaneous mutation during reverse recovery, which is easy to cause the FRD to be burned out due to overload.

[0003] Therefore, it is necessary to improve the structure of the fast recovery diode.

[0004] The application provides a fast recovery diode and a manufacturing method and application thereof, and aims to solve the problems of the withstand voltage, current transient, and parallel application of the fast recovery diode in the related art.

[0005] ​​​To solve the above technical problems, the first aspect of the embodiment of the present application provides a fast recovery diode, comprising a substrate, opposite sides of a surface of the substrate are respectively provided with a P+ cutoff ring region and a P-type active region, a position of the surface of the substrate between the P+ cutoff ring region and the P-type active region is further provided with a P+ field limiting ring region and a main junction region, the P+ field limiting ring region and the main junction region are sequentially arranged along a direction in which the P+ cutoff ring region points to the P-type active region;

[0006] The P-type active region comprises a P-body region with low ion concentration doping and a shallow P+ region with high ion concentration doping, the P-body region and the shallow P+ region are sequentially arranged along a direction in which the P+ cutoff ring region points to the P-type active region; wherein the junction depth and the carrier concentration of the P-body region are different from the P+ field limiting ring region and the P+ cutoff ring region.

[0007] The second aspect of the embodiment of the present application provides a manufacturing method of a fast recovery diode, comprising:

[0008] forming a P+ cutoff ring region and a P+ field limiting ring region by implantation on a surface of a substrate; wherein the surface of the substrate has a first side and a second side opposite to the first side, the P+ cutoff ring region and the P+ field limiting ring region are both located on the first side, and the P+ cutoff ring region and the P+ field limiting ring region are sequentially arranged along a direction in which the first side points to the second side;

[0009] forming a main junction region and a P-body region with low ion concentration doping by implantation on the surface of the substrate; wherein the P-body region is located on the second side, the main junction region is arranged adjacent to the P-body region and located between the P-body region and the P+ field limiting ring region, and the junction depth and the carrier concentration of the P-body region are different from the P+ field limiting ring region and the P+ cutoff ring region;

[0010] forming a shallow P+ region with high ion concentration doping by implantation on the surface of the substrate; wherein the shallow P+ region is arranged adjacent to the P-body region and located on a side of the P-body region away from the main junction region.

[0011] The third aspect of the embodiment of the present application provides an application of the fast recovery diode as described in the first aspect of the embodiment of the present application in a power electronic device.

[0012] From the above description, it can be known that, compared with the related art, the beneficial effects of the present application are that:

[0013] The fast recovery diode is composed of a substrate, a P+ cutoff ring region, a P+ field limiting ring region, a main junction region, a P-body region with low ion concentration doping, and a shallow P+ region with high ion concentration doping. The junction depth and the carrier concentration of the P-body region are different from those of the P+ field limiting ring region and the P+ cutoff ring region, that is, the P-body region and the P+ field limiting ring region and the P+ cutoff ring region are formed in different process steps. It can be understood that the active region and the field limiting ring region in the traditional FRD are formed in the same process step, which makes the active region and the field limiting ring region in the traditional FRD have the same junction depth and carrier concentration, that is, there is no longitudinal electric field (or in other words, no potential difference) between the active region and the field limiting ring region in the traditional FRD, thereby causing no voltage drop between the active region and the field limiting ring region in the traditional FRD. In the present application, the junction depth and the carrier concentration of the P-body region are different from those of the P+ field limiting ring region, so there is a longitudinal electric field (or in other words, a potential difference) between the P-body region and the P+ field limiting ring region, that is, a voltage drop occurs between the P-body region and the P+ field limiting ring region. At the same time, since the P-body region is doped with low ion concentration, the width of the depletion region on the side of the main junction region close to the P-body region (that is, the region between the main junction region and the P-body region) can be expanded, thereby effectively improving the voltage withstand performance of the fast recovery diode. At the same time, the manufacturing method of the shallow P+ region and the local metal barrier not only suppresses the transient of the reverse recovery current and enhances the recovery softness of the diode, but also enables the diode to have a positive temperature coefficient characteristic of voltage drop, eliminates the hidden danger caused by the parallel use of the device, and improves the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the related art or the embodiments of the present application, the drawings needed to be used in the description of the related art or the embodiments of the present application will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and not all embodiments. Those skilled in the art can obtain other drawings according to these drawings without creating any inventive labor.

[0015] Figure 1 A structure schematic diagram of a traditional FRD;

[0016] Figure 2 A structure schematic diagram of a fast recovery diode provided by an embodiment of the present application;

[0017] Figure 3 A flowchart of a manufacturing method of a fast recovery diode provided by an embodiment of the present application.

DETAILED DESCRIPTION

[0018] In order to make the purposes, technical solutions and advantages of the present application more obvious and easy to understand, the present application will be described clearly and completely below in combination with the embodiments of the present application and the corresponding drawings, wherein the same or similar reference signs represent the same or similar elements or elements with the same or similar functions throughout. It should be understood that the embodiments of the present application described below are only used to explain the present application and do not limit the present application, that is, based on the various embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0019] In power electronic devices, insulated gate bipolar transistors (IGBT) have a relatively wide application, and the fast recovery diode (FRD) used in parallel with the IGBT also has a great development prospect. The FRD is a semiconductor diode with good switching characteristics and short reverse recovery time, which is mainly used in electronic circuits such as electric vehicles, traction locomotives, switching power supplies, PWM (Pulse Width Modulation) pulse width modulators and frequency converters, and is used as a high-frequency rectifier diode, a freewheeling diode or a damping diode. The internal structure of the FRD is different from that of the ordinary PN junction diode, which has the characteristics of P-I-N (i.e. a base region I is added between the P-type silicon material and the N-type silicon material to form a PIN silicon wafer), and the relationship between the recovery time, the recovery charge and the forward voltage drop is achieved by adjusting the minority carriers. With the continuous improvement and progress of power electronic technology, although the application field of the FRD is expanded, higher requirements are put forward for the frequency response, switching loss and reliability of the FRD.

[0020] In the related art, please refer to Figure 1 , Figure 1The structure diagram of a conventional FRD is shown in FIG. 1. The conventional FRD generally comprises a substrate 1', an epitaxial layer 2', a field limiting ring region 3', a cutoff ring region 4' and an emitting region 5', which is mainly subjected to lifetime control by means of heavy metal (such as nickel platinum alloy) doping or electron irradiation, i.e. by reducing the lifetime of minority carriers in the chip, so that the minority carriers of the FRD can be quickly extracted and recombined during reverse recovery, thereby reducing the reverse recovery time of the FRD. However, if the reverse recovery time of the FRD is to be further reduced to the range of tens of nanoseconds, the concentration of recombination centers introduced into the chip must be increased, which will bring risks such as large leakage current and poor reliability to the FRD, causing the performance of the FRD to degrade. In addition, the conventional FRD also has many drawbacks, such as: the edge electric field of the FRD terminal is relatively concentrated, which reduces the withstand voltage of the FRD and increases the leakage current, thereby causing the functional characteristics of the FRD to deteriorate or be broken down, and thus causing the FRD to fail from time to time. At this time, a protection technology needs to be used in the terminal of the FRD to reduce the surface electric field strength of the edge of the FRD terminal and improve the withstand voltage level of the FRD; the reverse recovery time of the FRD is the main factor affecting its turn-off loss, and the forward conduction voltage drop is the main factor affecting its turn-on loss, which makes it contradictory to improve the reverse recovery time of the FRD and reduce the forward conduction voltage drop of the FRD; the recovery softness of the FRD is directly related to its peak current, that is, the harder the recovery characteristics of the FRD, the greater the peak current, thereby causing the FRD to withstand excessive power consumption, and thus causing the performance of the FRD to degrade or the service life to decrease; the current of the FRD is prone to sudden change during reverse recovery, which is easy to cause the FRD to be burned out due to overload. Therefore, the embodiments of the present application provide a fast recovery diode, which can be applied to various power electronic devices, such as electric vehicles, traction locomotives, switching power supplies, PWM pulse width modulators and frequency converters, etc.

[0021] Please refer to Figure 2 , Figure 2 The structure diagram of the fast recovery diode provided by the embodiments of the present application is shown in FIG. 2. The fast recovery diode provided by the embodiments of the present application comprises a substrate 10, the opposite sides of the surface of the substrate 10 are respectively provided with a P+ cutoff ring region 20 and a P-type active region 30, the surface of the substrate 10 at the position between the P+ cutoff ring region 20 and the P-type active region 30 is further provided with a P+ field limiting ring region 40 and a main junction region 50, and the P+ field limiting ring region 40 and the main junction region 50 are sequentially arranged in the direction of the P+ cutoff ring region 20 pointing to the P-type active region 30. Specifically, the P-type active region 30 comprises a low ion concentration doped P-body region 31 and a high ion concentration doped shallow P+ region 32, and the P-body region 31 and the shallow P+ region 32 are sequentially arranged in the direction of the P+ cutoff ring region 20 pointing to the P-type active region 30; wherein the junction depth and the carrier concentration of the P-body region 31 are different from those of the P+ field limiting ring region 40 and the P+ cutoff ring region 20.

[0022] The embodiment of the present application forms a fast recovery diode with the substrate 10, the P+ cutoff ring region 20, the P+ field limiting ring region 40, the main junction region 50, the P-body region 31 with low ion concentration doping and the shallow P+ region 32 with high ion concentration doping, and the junction depth and the carrier concentration of the P-body region 31 are different from those of the P+ field limiting ring region 40 and the P+ cutoff ring region 20, that is, the P-body region 31 and the P+ field limiting ring region 40 and the P+ cutoff ring region 20 are formed in different process steps. It can be understood that the active region (i.e. the emitting region 5' in Figure 1 the traditional FRD is formed in the same process step with the field limiting ring region 3', which makes the active region and the field limiting ring region 3' in the traditional FRD have the same junction depth and carrier concentration, that is, there is no longitudinal electric field (or in other words, no potential difference) between the active region and the field limiting ring region 3' in the traditional FRD, so that no voltage drop is generated between the active region and the field limiting ring region 3' in the traditional FRD, while the junction depth and the carrier concentration of the P-body region 31 in the embodiment of the present application are different from those of the P+ field limiting ring region 40, so that there is a longitudinal electric field (or in other words, a potential difference) between the P-body region 31 and the P+ field limiting ring region 40 in the embodiment of the present application, that is, a voltage drop is generated between the P-body region 31 and the P+ field limiting ring region 40 in the embodiment of the present application, and at the same time, since the P-body region 31 is doped with low ion concentration, the width of the depletion region (i.e. the region between the main junction region 50 and the P-body region 31) near the side of the main junction region 50 close to the P-body region 31 can be expanded, so that the withstand voltage performance of the fast recovery diode is effectively improved.

[0023] As an implementation form, still referring to Figure 2 , the P+ field limiting ring region 40 can include a plurality of P+ field limiting rings 41 spaced from each other, and the width of the P+ field limiting ring region 40 in the direction from the P-type active region 30 to the P+ cutoff ring region 20 remains unchanged, and the distance between the plurality of P+ field limiting rings 41 shows an increasing trend in the direction from the P-type active region 30 to the P+ cutoff ring region 20. For example, the P+ field limiting ring region 40 includes five P+ field limiting rings 41, which are denoted as A, B, C, D and E respectively, and A-E are arranged in sequence in the direction from the P-type active region 30 to the P+ cutoff ring region 20, and the distance between A and B is denoted as AB, the distance between B and C is denoted as BC, the distance between C and D is denoted as CD, and the distance between D and E is denoted as DE, so DE>CD>BC>AB.

[0024] As a specific implementation of this embodiment, the width of the P+ field limiting ring region 40 in the direction from the P-type active region 30 to the P+ cutoff ring region 20 remains constant at 10 μm, and the distance between the multiple P+ field limiting rings 41 increases from 21 to 30 μm in the direction from the P-type active region 30 to the P+ cutoff ring region 20. Here, still using the example given earlier, AE (the distance between A and E) is 10 μm, while AB can be 22 μm, BC can be 25 μm, CD can be 28 μm, and DE can be 30 μm.

[0025] It should be understood that this embodiment is only a preferred implementation of the embodiments of this application, and it is not the only limitation on the P+ field limiting region 40; those skilled in the art can make flexible settings based on the embodiments of this application and according to the actual application scenario.

[0026] As one implementation method, please refer to Figure 2 The substrate 10 may include an N+ substrate layer 11, an N-type buffer layer 12, and an N-epipolar layer 13; wherein the N-type buffer layer 12 is overlying the surface of the N+ substrate layer 11, and the N-epipolar layer 13 is overlying the surface of the N-type buffer layer 12. It is understood that the substrate of a conventional FRD only includes... Figure 1 The substrate 1′ and epitaxial layer 2′ in this embodiment do not include the N-type buffer layer 12. This means that by adding the N-type buffer layer 12, this embodiment reduces the thickness of the epitaxial layer 2′ in the conventional FRD, thereby reducing the forward conduction voltage drop of the fast recovery diode, that is, reducing the conduction loss of the fast recovery diode.

[0027] As a specific implementation of this embodiment, the thickness of the N-type buffer layer 12 can be 10–30 μm, and the resistivity can be 4–7 Ω·cm. The thickness of the N-epitaxial layer 13 can be 70–120 μm, and the resistivity can be 50–60 Ω·cm. Therefore, it can be seen that both the thickness and resistivity of the N-epitaxial layer 13 are higher than those of the N-type buffer layer 12.

[0028] It should be understood that this embodiment is only a preferred implementation of the embodiments of this application and is not the only limitation on the substrate 10; those skilled in the art can make flexible settings based on the embodiments of this application and according to the actual application scenario.

[0029] As one implementation method, please refer to Figure 2 A metallic barrier region 60 can be formed between the P-body regions 31 in the P-type active region 30, and the metal thickness of the metallic barrier region 60 can be [missing information]. Of course, in this embodiment This application is not intended to limit the specific implementation of this embodiment to any particular one.

[0030] In some embodiments, the fast recovery diode provided by the embodiments of the present application can further include other common structures in FRD in the art, such as a metal field plate 70 and a metal electrode 80 (including an anode, a cathode) on the surface of the substrate 10 (i.e. the surface of the N-epitaxial layer 13), etc., in addition to the substrate 10 (comprising an N+ substrate layer 11, an N-type buffer layer 12 and an N-epitaxial layer 13), a P+ cutoff ring region 20, a P-type active region 30 (comprising a P-body region 31 and a shallow P+ region 32), a P+ field limiting ring region 40 and a main junction region 50. The embodiments of the present application will not be listed one by one here.

[0031] Please refer to Figure 3 , Figure 3 The flowchart of the manufacturing method of the fast recovery diode provided by the embodiments of the present application is shown. The embodiments of the present application further provide a manufacturing method of a fast recovery diode, which is used to manufacture the fast recovery diode provided by the embodiments of the present application, and the manufacturing method of the fast recovery diode comprises the following steps 301 to 303.

[0032] Step 301: implanting a P+ cutoff ring region and a P+ field limiting ring region on the surface of a substrate.

[0033] In the embodiments of the present application, the surface of the substrate 10 has a first side and a second side opposite to the first side. When manufacturing the fast recovery diode, the P+ cutoff ring region 20 and the P+ field limiting ring region 40 need to be formed on the surface of the substrate 10, and the P+ cutoff ring region 20 and the P+ field limiting ring region 40 are both located on the first side of the substrate 10, and the P+ cutoff ring region 20 and the P+ field limiting ring region 40 are sequentially arranged along the direction from the first side to the second side of the substrate 10.

[0034] Step 302: implanting a main junction region and a P-body region with low ion concentration on the surface of the substrate.

[0035] In the embodiments of the present application, after the P+ cutoff ring region 20 and the P+ field limiting ring region 40 are formed on the surface of the substrate 10, the main junction region 50 and the P-body region 31 with low ion concentration need to be formed on the surface of the substrate 10, and the P-body region 31 is located on the second side of the substrate 10, and the main junction region 50 is arranged adjacent to the P-body region 31 and between the P-body region 31 and the P+ field limiting ring region 40.

[0036] It can be understood that the P-body region 31 is formed in step 302, while the P+ stop ring region 20 and the P+ field limiting ring region 40 are both formed in step 301, which makes the junction depth and the carrier concentration of the P-body region 31 different from those of the P+ field limiting ring region 40 and the P+ stop ring region 20, with the purpose of forming a longitudinal electric field (i.e. forming a potential difference) between the P-body region 31 and the P+ field limiting ring region 40, so that a voltage drop is generated between the P-body region 31 and the P+ field limiting ring region 40. At the same time, since the P-body region 31 is a low ion concentration doping, the width of the depletion region near the side of the main junction region 50 close to the P-body region 31 (i.e. the region between the main junction region 50 and the P-body region 31) can be expanded, thereby effectively improving the voltage withstand performance of the fast recovery diode. In an example, the junction depth of the main junction region 50 and the P-body region 31 can be greater than or equal to 4 μm and less than 5 μm, while the junction depth of the P+ stop ring region 20 and the P+ field limiting ring region 40 can be greater than or equal to 5 μm and less than 6 μm.

[0037] Step 303: implanting a shallow P+ region with high ion concentration on the surface of the substrate.

[0038] In the embodiment of the present application, after the main junction region 50 and the P-body region 31 are formed by implanting on the surface of the substrate 10, a shallow P+ region 32 with high ion concentration needs to be formed by implanting on the surface of the substrate 10, and the shallow P+ region 32 is arranged adjacent to the P-body region 31 and on the side of the P-body region 31 away from the main junction region 50, so that the P-body region 31 and the shallow P+ region 32 jointly constitute a P-type active region 30.

[0039] In order to clearly understand the method for manufacturing the fast recovery diode provided by the embodiment of the present application, the method for manufacturing the fast recovery diode will be understood with the aid of a specific example as follows:

[0040] 1. Cleaning and oxidizing the silicon wafer, field oxide growth, temperature 1100 °C, thickness 100 nm;

[0041] 2. After the photoresist coating, photoetching and developing process is completed, the field oxide to be etched of the P+ stop ring region 20 and the P+ field limiting ring region 40 is formed;

[0042] 3. After the field oxide wet etching is completed, the to-be-implanted region of the P+ stop ring region 20 and the P+ field limiting ring region 40 is formed;

[0043] 4. After the photoresist removal and etching is completed, the silicon wafer is cleaned;

[0044] 5. Pre-oxidation layer growth, forming the mask region of the to-be-implanted window of the P+ stop ring region 20 and the P+ field limiting ring region 40;

[0045] 6. After the completion of the glue coating, photoetching and developing process, the P+ cutoff ring region 20 and the P+ field limiting ring region 40 are formed;

[0046] 7. Boron ion implantation is performed with an implantation dose of 2E14 / cm 2 ~ 5E14 / cm 2 to form the P+ cutoff ring region 20 and the P+ field limiting ring region 40 which are not activated;

[0047] 8. After the completion of the glue removal and etching process, the silicon wafer is cleaned;

[0048] 9. The pre-oxidation layer is etched to remove the mask region of the implantation window of the P+ cutoff ring region 20 and the P+ field limiting ring region 40;

[0049] 10. After the completion of the glue coating, photoetching and developing process, the field oxidation etching region of the main junction region 50 and the P-body region 31 is formed;

[0050] 11. After the completion of the field oxidation wet etching, the implantation region of the main junction region 50 and the P-body region 31 is formed;

[0051] 12. After the completion of the glue removal and etching process, the silicon wafer is cleaned;

[0052] 13. The pre-oxidation layer is grown to form the mask region of the implantation window of the main junction region 50 and the P-body region 31;

[0053] 14. Boron ion implantation is performed with an implantation dose of 2E12 / cm 2 ~ 5E11 / cm 2 at a temperature of T = 1050°C for a time period of 400 minutes to form the P+ field limiting ring region 40 and the P+ cutoff ring region 20 with a junction depth of 5 ~ 5.5 μm and the main junction region 50 and the P-body region 31 with a junction depth of 4.2 ~ 4.5 μm;

[0054] 15. LPTEOS growth is performed to a thickness of

[0055] 16. After the completion of the glue coating, photoetching and developing process, the implantation region of the shallow P+ region 32 is formed;

[0056] 17. The thickness of the dielectric layer at the lead hole is etched to form the mask region of the implantation window of the shallow P+ region 32;

[0057] 18. Boron ion implantation is performed with an implantation dose of 3E14 / cm 2 ~ 9E14 / cm 2 to form the shallow P+ region 32 which is not activated;

[0058] 19. Etching and removing the remaining dielectric layer when the shallow P+ region 32 is not activated;

[0059] 20. After the etching and removing the photoresist, cleaning the wafer;

[0060] 21. BPTEOS deposition, thickness is 0.5-1.0 μm;

[0061] 22. BPTEOS reflow, temperature is 950 °C, time is 20-40 min;

[0062] 23. After the photoresist coating, photoetching and developing, the first lead hole is formed;

[0063] 24. BPTEOS etching, removing the oxide layer when the first lead hole is formed;

[0064] 25. After the etching and removing the photoresist, cleaning the wafer;

[0065] 26. Metal nickel platinum deposition, thickness is 0.5-1.0 μm;

[0066] 27. Forming the metal nickel platinum alloy, temperature is 450-500 °C;

[0067] 28. Boiling aqua regia and cleaning the wafer;

[0068] 29. After the photoresist coating, photoetching and developing, the second lead hole is formed;

[0069] 30. BPTEOS etching, removing the oxide layer when the second lead hole is formed;

[0070] 31. After the etching and removing the photoresist, cleaning the wafer;

[0071] 32. Metal wiring, depositing 3.5 μm of aluminum silicon, forming the lead-out end required by the metal electrode 80;

[0072] 33. After the photoresist coating, photoetching and developing, the wiring pattern is formed;

[0073] 34. Metalized aluminum silicon wet etching, forming the anode metal;

[0074] 35. After the etching and removing the photoresist, cleaning the wafer;

[0075] 36. PETEOS deposition, thickness is 0.5-1.0 μm;

[0076] 37. PESIN deposition, thickness is 0.5-1.0 μm;

[0077] 38. Forming metal alloy, temperature 410-450C, time 30-60min;

[0078] 39. Coating polyimide and photoetching polyimide to form complete metal electrode 80;

[0079] 40. High temperature curing of polyimide, temperature 350-400C, time 60min;

[0080] 41. Backside thinning and backside metal evaporation, metal from bottom to top: Ti (titanium) thickness Ni (nickel) thickness and Ag (silver) thickness

[0081] It can be understood that in the above steps 1-41, steps 1-7 are used to form P+ cutoff ring 20 and P+ field limiting ring 40, steps 8-14 are used to form main junction region 50 and P-body region 31, steps 15-19 are used to form shallow P+ region 32, and steps 20-41 are used to ion-activate P+ cutoff ring 20, P+ field limiting ring 40, main junction region 50, P-body region 31 and shallow P+ region 32 which are not activated, and form other common structures in fast recovery diodes, such as metal electrode 80.

[0082] In summary of the above, the embodiment of the present application provides a fast recovery diode which adopts a device structure of N-type buffer layer 12, shallow P+ region 32, P-body region 31, a plurality of P+ field limiting rings 41, P+ cutoff ring region 20, main junction region 50, substrate layer 11, N-epitaxial layer 13, contact metal field plate 70 and metal electrode 80 which are uniformly ion-doped, and combines local metal alloying process of cell region (i.e. P-type active region 30), so that the fast recovery diode has voltage withstand requirement in reverse working, and also has low positive temperature coefficient of forward conduction voltage drop, and the recovery softness of the fast recovery diode is also improved (i.e. no longer "hard"). In addition, in the manufacturing method, growing thin dielectric layer ensures that the fast recovery diode meets the requirement of high reverse breakdown voltage, and ion implantation of shallow P+ region 32 shortens the reverse recovery time of the fast recovery diode, reduces the off loss of the fast recovery diode, has good inhibition ability to instantaneous mutation of reverse recovery current of the fast recovery diode, and has short manufacturing method period, low cost and good ability to meet the demand of large-scale production.

[0083] The present embodiment uses photoresist as a mask layer to realize local ion implantation on the N-epitaxial layer 13 with uniform ion doping and high-temperature drive-in at the same time, which results in the formation of the P+ cutoff ring region 20, the P+ field limiting ring region 40, the main junction region 50, the P-body region 31 and the shallow P+ region 32. Specifically, when the fast recovery diode is under reverse bias, the P-body region 31 with low ion concentration doping is conducive to quickly sweeping out the carriers, thereby reducing the reverse recovery charge and suppressing the reverse peak current. The P+ cutoff ring region 20 can continue to expand the depletion region of the main junction region 50 on the side close to the P-body region 31, thereby improving the withstand voltage capability of the fast recovery diode; on the other hand, it can effectively terminate the electric field within the ring; and on the other hand, it reduces the photolithography process and saves the production cost. In the reverse recovery process of the fast recovery diode, part of the carriers are extracted through the negative electrode (i.e. the cathode in the metal electrode 80), and the other part of the carriers slowly disappear in the form of carrier recombination in the late reverse recovery. Practice shows that if the recombination probability of the carriers increases in the process of reverse recovery of the fast recovery diode, the recovery characteristics of the fast recovery diode will be improved (i.e. from "hard" to "soft").

[0084] In the manufacturing method, the ion implantation step of the shallow P+ region 32 makes the plasma level near the anode in the metal electrode 80 relatively shallow, so that even if a high commutation di / dt produces a reverse peak current, the reverse peak current will not be very large. The shallow plasma layer of the buffer region (i.e. the region between the main junction region 50 and the P-body region 31) in the reverse recovery of the fast recovery diode increases the ratio of base width to minority carriers, which easily causes current transient during reverse recovery, causing damage to the fast recovery diode. The ion implantation process of the shallow P+ region 32 can suppress the occurrence of current transient, and the steeper the ion doping gradient, the fewer the implanted carriers, which means that the reverse recovery time is shorter and the off-state loss is smaller. In addition, the ion implantation process of the shallow P+ region 32 is also conducive to the formation of ohmic contact characteristics, thereby achieving the effect of reducing the forward on-state voltage drop, i.e. reducing the turn-on loss. After the ion implantation of the shallow P+ region 32, the present embodiment uses the BPSG reflow process to achieve the purpose of ion activation (i.e. ion activation of the P+ cutoff ring 20, the P+ field limiting ring 40, the main junction region 50, the P-body region 31 and the shallow P+ region 32 which have not been activated). The present embodiment also uses a polyimide coating process to suppress the fixed charge and movable charge of the terminal oxide layer by using the negative characteristics of polyimide, thereby stabilizing the withstand voltage characteristics of the fast recovery diode and improving the reliability of the fast recovery diode.

[0085] Compared with the traditional FRD, the embodiment of the application has at least the following advantages: by injecting the shallow P+ region 32, the reverse recovery time of the fast recovery diode is improved, and the generation of reverse recovery current transient is inhibited; under the condition of meeting the withstand voltage, by adopting the structure of the N-type buffer layer 12, the purpose of reducing the carrier recovery speed in the late reverse recovery is achieved, and the softness of the reverse recovery is improved to a certain extent; by injecting the P-body region 31 with low ion concentration doping and the shallow P+ region 32 with high ion concentration doping, the effect of reducing the reverse recovery charge and inhibiting the reverse peak current is achieved, and the withstand voltage characteristic of the fast recovery diode is improved; the ion implantation process of the shallow P+ region 32 does not need to be implanted and annealed to realize the adjustment of the implantation efficiency, and the process steps are simple and the manufacturing cost is low; the P-body region 31, the P+ field limiting ring region 40 and the P+ cutoff ring region 20 are formed in different process steps, which is beneficial to the withstand voltage characteristic of the fast recovery diode; the local metal deposition window process is introduced, and the positive temperature coefficient of the voltage drop of the fast recovery diode is realized.

[0086] It should be noted that each of the embodiments in the present application is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For product class embodiments, since they are similar to method class embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method class embodiment.

[0087] It should also be noted that in the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0088] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined in the present application can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in the present application, but will conform to the widest scope consistent with the principles and novel features disclosed in the present application.

Claims

1. A fast recovery diode comprising a substrate, characterized in that, The surface of the substrate is provided with a P+ cutoff ring region and a P-type active region on opposite sides, respectively, and the surface of the substrate is further provided with a P+ field limiting ring region and a main junction region between the P+ cutoff ring region and the P-type active region, the P+ field limiting ring region and the main junction region being sequentially arranged along the direction of the P+ cutoff ring region pointing to the P-type active region; The P-type active region comprises a low ion concentration doped P-body region and a high ion concentration doped shallow P+ region, the P-body region and the shallow P+ region being sequentially arranged along the direction of the P+ cutoff ring region pointing to the P-type active region; wherein the junction depth and the carrier concentration of the P-body region are different from those of the P+ field limiting ring region and the P+ cutoff ring region; and a metal barrier region is formed between the P-body regions.

2. The fast recovery diode of claim 1 wherein, The P+ field limiting ring region comprises a plurality of P+ field limiting rings spaced from each other, the width of the P+ field limiting ring region in the direction from the P-type active region to the P+ cutoff ring region remains unchanged, and the distance between the plurality of P+ field limiting rings increases along the direction of the P-type active region pointing to the P+ cutoff ring region.

3. The fast recovery diode as described in claim 2, characterized in that, The width of the P+ field limiting ring region in the direction from the P-type active region to the P+ cutoff ring region remains unchanged at 10 μm, and the distance between the plurality of P+ field limiting rings increases within 21-30 μm along the direction of the P-type active region pointing to the P+ cutoff ring region.

4. The fast recovery diode as described in claim 1, characterized in that, The substrate comprises an N+ substrate layer, an N-type buffer layer and an N- epitaxial layer; wherein the N-type buffer layer is coated on the surface of the N+ substrate layer, and the N- epitaxial layer is coated on the surface of the N-type buffer layer.

5. The fast recovery diode as described in claim 4, characterized in that, The thickness of the N-type buffer layer is 10-30 μm, and the resistivity is 4-7 Ω·cm.

6. The fast recovery diode as described in claim 4, characterized in that, The thickness of the N- epitaxial layer is 70-120 μm, and the resistivity is 50-60 Ω·cm.

7. The fast recovery diode as described in claim 1, characterized in that, The metal thickness of the metal barrier region is 8. A method of fabricating a fast recovery diode, characterized by, Comprising: forming a P+ cutoff ring region and a P+ field limiting ring region on the surface of a substrate; wherein the surface of the substrate has a first side and a second side opposite to the first side, the P+ cutoff ring region and the P+ field limiting ring region are both located on the first side, and the P+ cutoff ring region and the P+ field limiting ring region are sequentially arranged along the direction of the first side pointing to the second side; forming a main junction region and a low ion concentration doped P-body region on the surface of the substrate; wherein the P-body region is located on the second side, the main junction region is arranged adjacent to the P-body region and between the P-body region and the P+ field limiting ring region, and the junction depth and the carrier concentration of the P-body region are different from those of the P+ field limiting ring region and the P+ cutoff ring region; forming a high ion concentration doped shallow P+ region on the surface of the substrate; wherein the shallow P+ region is arranged adjacent to the P-body region and on the side of the P-body region away from the main junction region; and a metal barrier region is formed between the P-body regions.

9. Use of the fast recovery diode according to any one of claims 1-7 in power electronic devices.

Images