Capacitance multiplier for decoupling capacitor

Abstract

The present disclosure relates to a capacitance multiplier for decoupling capacitors. An integrated circuit can include one or more circuits coupled to a capacitance multiplier circuit. The capacitance multiplier circuit can include a capacitor, fixed and tunable resistors, and a transconductance circuit. The tunable resistor can be adjusted to control the total capacitance of the capacitance multiplier circuit. The transconductance circuit can include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component can be a diode-connected transistor, a direct shorted wire, a resistor, an inductor, or a current source. The second electrical component can be a current source, a direct shorted wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop and without consuming a large amount of power.

Description

[0001] This application claims priority to U.S. Patent Application No. 17 / 574,895, filed January 13, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0002] The implementation schemes described herein relate to integrated circuits in general, and more specifically, to integrated circuits with capacitance multiplier circuits. Background Technology

[0003] Integrated circuits typically include decoupling capacitors to reduce power supply noise for the circuit of interest. Decoupling capacitors shunt noise on the DC power line and help prevent noise from reaching the powered circuit components. Decoupling capacitors with larger capacitance values ​​provide better noise suppression, but at the cost of a larger circuit area. To help provide large capacitance within a small layout area, decoupling capacitors are sometimes implemented as capacitance multiplier circuits.

[0004] Capacitor multiplier circuits can be challenging to design. Conventional capacitor multiplier circuits have inputs and outputs and typically have a voltage drop from input to output, making them unsuitable for low-voltage applications. Conventional capacitor multiplier circuits usually have a fixed capacitance value, requiring the powered circuit of interest to have high impedance, and also consume a significant amount of power. It is under these circumstances that the implementation described in this paper was developed. Summary of the Invention

[0005] Electronic devices may include integrated circuits having one or more circuits coupled to power lines. The integrated circuit may be equipped with decoupling capacitor circuitry to help suppress noise on the power lines. The decoupling capacitor circuitry can be implemented using a capacitance multiplier configuration to minimize the circuit area of ​​the decoupling capacitor circuitry. Decoupling capacitor circuitry that implements capacitance multiplication is sometimes referred to as a decoupling capacitance multiplier circuit or a capacitance multiplier circuit.

[0006] One aspect of this disclosure provides an integrated circuit comprising: a circuit coupled to a power line; and a capacitance multiplier circuit coupled to the power line. The capacitance multiplier circuit may include: a capacitor having a first terminal coupled to the power line and a second terminal; an adjustable resistor having a first terminal coupled to the second terminal of the capacitor and a second terminal; and a transconductance circuit coupled to the capacitor and the adjustable resistor. Optionally, the capacitance multiplier circuit may include: a first resistor having a first terminal coupled to the power line and a second terminal coupled to the second terminal of the adjustable resistor; a second resistor having a first terminal coupled to the second terminal of the adjustable resistor and a second terminal coupled to a ground line; and a transistor having a gate terminal coupled to the second terminal of the capacitor, a first source-drain terminal coupled to the power line, and a second source-drain terminal coupled to ground.

[0007] The transconductance circuit may include: a current source coupled between the second source-drain terminal of the transistor and the ground line; and an additional transistor having a first source-drain terminal coupled to the first source-drain terminal of the transistor, a gate terminal coupled to the first source-drain terminal, and a second source-drain terminal coupled to the power line. In another embodiment, the first source-drain terminal of the transistor may be directly coupled to the power line. The second source-drain terminal of the transistor may also be directly coupled to the ground line. The capacitance multiplier circuit has a capacitance value that can be increased by increasing the resistance value of an adjustable resistor. The capacitance multiplier circuit has a total capacitance value that is greater than one hundred times the capacitance value of the capacitor. This total capacitance value is sometimes referred to as the multiplier capacitance value.

[0008] One aspect of this disclosure provides a capacitance multiplier circuit, comprising: a capacitor having a first terminal coupled to a positive power supply line and a second terminal; an adjustable resistor coupled to the second terminal of the capacitor; and a transistor having a gate terminal coupled to the second terminal of the capacitor, a first source-drain terminal coupled to the positive power supply line, and a second source-drain terminal coupled to a ground power supply line. The capacitance multiplier circuit may further include: a first resistor having a first terminal coupled to the positive power supply line and a second terminal coupled to the adjustable resistor; and a second resistor having a first terminal coupled to the adjustable resistor and a second terminal coupled to the ground power supply line. The capacitance multiplier circuit may include an electrical component coupled between the positive power supply line and the first source-drain terminal of the transistor, the electrical component being selected from the group consisting of a diode-connected transistor, a resistor, and an inductor. The capacitance multiplier circuit may include another electrical component coupled between the second source-drain terminal of the transistor and the ground power supply line. This other electrical component is selected from the group consisting of a current source, a resistor, and an inductor.

[0009] One aspect of this disclosure provides a capacitance multiplier circuit, comprising: a capacitor having a first terminal and a second terminal coupled to a ground power supply line; an adjustable resistor coupled to the first terminal of the capacitor; and a transistor having a gate terminal coupled to the first terminal of the capacitor, a first source-drain terminal coupled to a positive power supply line, and a second source-drain terminal coupled to the ground power supply line. The capacitance multiplier circuit may further include: a first resistor having a first terminal coupled to the positive power supply line and a second terminal coupled to the adjustable resistor; and a second resistor having a first terminal coupled to the adjustable resistor and a second terminal coupled to the ground power supply line. The capacitance multiplier circuit may further include an electrical component coupled to at least one of the first source-drain terminal and the second source-drain terminal of the transistor, the electrical component being a component selected from the group consisting of a diode-connected transistor, a current source, a resistor, and an inductor.

[0010] Other features, properties and various advantages of the invention will become more apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0011] Figure 1 This is a diagram of an exemplary integrated circuit die, including a circuit coupled to a decoupling capacitor, according to some implementation schemes.

[0012] Figure 2 This is a block diagram of an exemplary capacitance multiplier circuit based on some implementation schemes.

[0013] Figure 3 This illustrates some implementation schemes. Figure 2 A circuit diagram of a specific implementation of a capacitor multiplier circuit of the type shown.

[0014] Figure 4 This is a circuit diagram of an exemplary tunable resistor based on some implementation schemes.

[0015] Figure 5 This is a diagram showing the multiplication capacitance as a function of the tunable resistor according to some implementation schemes.

[0016] Figures 6 to 11 This illustrates some implementation schemes. Figure 2 The diagram shows different specific implementations of the type of capacitor multiplier circuit. Detailed Implementation

[0017] This disclosure relates to integrated circuits having a capacitance multiplier circuit coupled to a circuit of interest. Such integrated circuits can be included in any type of electronic device or system, including but not limited to cellular phones, tablet computers, wristwatches, laptop computers, desktop computers, monitors, displays with one or more displays, media players, digital content streaming devices, chargers, earphones, headphones, speakers, styluses, keyboards, accessories, wearable devices, head-mounted devices, automotive, or other electronic systems. The capacitance multiplier circuit can be used as a decoupling capacitor to suppress power supply noise and is therefore sometimes referred to as a decoupling capacitance multiplier circuit.

[0018] A capacitance multiplier circuit may include a capacitor, a tunable resistor, and a transconductance circuit. The tunable resistor can be adjusted to control the capacitance value of the capacitance multiplier circuit. The transconductance circuit may include a transistor having a first source-drain terminal coupled to a first electrical (load) component and a second source-drain terminal coupled to a second electrical (load) component. The first electrical component may be a diode-connected transistor, a resistor, an inductor, or may be omitted entirely. The second electrical component may be a current source, a resistor, an inductor, or may be omitted entirely. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop, does not require the circuit of interest to have high impedance, and does not consume a large amount of power.

[0019] Figure 1This is a diagram of an electronic device (such as electronic device 10) that may be equipped with such decoupling capacitor multiplier circuitry. Electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a wristband, a headset or handset, a device embedded in glasses; or other equipment worn on a user's head; or other wearable or micro-devices, televisions, computer monitors without embedded computers, gaming devices, navigation devices, embedded systems (such as systems in which electronic equipment with a display is installed in a kiosk or car), voice-controlled speakers connected to the wireless internet, home entertainment devices, remote control devices, game controllers, peripheral user input devices, wireless base stations or access points, equipment that enables the functionality of two or more of these devices; or other electronic equipment.

[0020] like Figure 1 As shown in the schematic diagram, device 10 may include integrated circuit 12. Integrated circuit 12 may be a microprocessor, microcontroller, digital signal processor, host processor, baseband processor, application processor, central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array or programmable logic device, sound (audio) chip, wireless communication processor (such as RF transceiver chip), or other types of integrated circuit.

[0021] Integrated circuit 12 may include one or more circuits of interest, such as circuit 20 coupled between positive power supply line 16 and ground power supply line 18. An optional voltage regulator 14, power management circuitry, or other power regulation circuitry may be used to provide a positive power supply voltage Vdd on power supply line 16. Circuit 20 may sometimes be referred to as a circuit under test (CUT) or device under test (DUT). A ground power supply voltage Vss may be provided on ground line 18. Voltage regulator 14 is typically used to maintain a constant voltage level of Vdd. However, voltage regulator 14 is sometimes not included and may not always be effective in suppressing power supply noise. Therefore, integrated circuit 12 may be provided with decoupling capacitor circuitry 22 (sometimes referred to as "decap" circuitry), which is configured to reduce or suppress the amount of power supply noise that may be present on the power supply line. Figure 1 A decoupling capacitor circuit 22 is shown that shunts current from the positive power supply line 16 to the ground line 18.

[0022] To provide improved power supply noise suppression, a higher capacitance value is typically desired for the decoupling capacitor circuit 22. However, higher capacitance usually requires a larger circuit layout area. To help provide high capacitance without requiring a significant circuit coverage area, the decoupling capacitor circuit 22 can be implemented using a capacitance multiplier configuration. Decoupling capacitors based on capacitance multipliers are sometimes referred to as decoupling capacitance multiplier circuits.

[0023] Figure 2 This is a block diagram of capacitor multiplier circuit 22. Figure 2 As shown, the capacitance multiplier circuit 22 may include a capacitor such as capacitor 30, a tunable resistor such as tunable resistor 32, and a transconductance circuit such as transconductance circuit 34. The capacitance multiplier circuit 22 may include only one capacitor (i.e., a single capacitor 30). Capacitor 30 may be directly coupled to a power supply line or directly coupled to a ground power supply line.

[0024] The adjustable tunable resistor 32 controls the multiplication factor of the multiplier circuit 22. For example, increasing the value of resistor 32 increases the effective / total capacitance of circuit 22, while decreasing the value of resistor 32 decreases the effective / total capacitance of circuit 22. The effective (total) capacitance of circuit 22 can be equal to the nominal capacitance of capacitor 30 multiplied by the multiplication factor. The multiplication factor can be adjusted to be equal to two, three, four, 4-10, 10-20, 20-100, 100-200, 200-500, 500-1000, greater than 1000, or other suitable values. The transconductance (Gm) of circuit 34 can also affect the multiplication factor and may include active circuit components and optional passive circuit components.

[0025] Figure 3 This illustrates some implementation schemes. Figure 2 A circuit diagram of a specific implementation of the type of capacitor multiplier circuit 22 shown. (See diagram for example.) Figure 3 As shown, the capacitance multiplier circuit 22 may include a capacitor C, resistors R1, R2 and R3, and a transconductance circuit 34. Figure 3 The capacitor C in the figure can be equivalent to Figure 2 The capacitor 30 and resistor R3 are equivalent to Figure 2 The adjustable resistor 32 is used. Although resistor R3 is adjustable, resistors R1 and R2 can be fixed. Resistors R1 and / or R2 can also be adjustable if desired.

[0026] Capacitor C may have a first terminal and a second terminal coupled to the positive power supply line (terminal) 16. Resistor R1 may have a first terminal and a second terminal coupled to the power supply line 16. Resistor R2 may have a first terminal coupled to the second terminal of resistor R1 and a second terminal coupled to the ground line 18. Tuning resistor R3 may have a first terminal coupled to the second terminal of capacitor C and a second terminal coupled to the second terminal of resistor R1 (i.e., the second terminal of resistor R3 may be coupled to a node between resistors R1 and R2).

[0027] exist Figure 3 In the example, the transconductance circuit 34 may include a first transistor M1 (e.g., an n-channel transistor such as an n-type metal-oxide-semiconductor device), a second transistor M2 (e.g., a p-channel transistor such as a p-type metal-oxide-semiconductor device), and a current source Is. Transistor M1 may have a gate terminal coupled to the second terminal of capacitor C, a drain terminal coupled to power line 16 via transistor M2, and a source terminal coupled to ground line 18 via current source Is. The terms "source" and "drain" terminals used to refer to current-carrying terminals in a transistor are used interchangeably and are sometimes referred to as "source-drain" terminals. Therefore, the drain terminal of transistor M1 may sometimes be referred to as the first source-drain terminal, and the source terminal of transistor M1 may be referred to as the second source-drain terminal (or vice versa).

[0028] Transistor M2 may have a source terminal coupled to power line 16, a gate terminal, and a drain terminal coupled to its gate terminal. A transistor M2 with its gate and drain terminals shorted together is sometimes referred to as being in a "diode-connected" configuration. The current source Is can be implemented using a current mirror circuit (as an example).

[0029] Configured in this way, the capacitor multiplier circuit 22 can have an input impedance Zin (looking towards the first terminal of capacitor C) expressed by the following expression:

[0030]

[0031] Where C is the value of the capacitor and Gm represents the total transconductance of circuit 34. Transconductance circuit 34 can be defined herein as a circuit having an output current controlled by the input voltage (e.g., the drain-to-source current flowing through transistor M1 is a function of the voltage level at the gate of transistor M1). The transconductance Gm of circuit 34 can be expressed by the following equation:

[0032]

[0033] Where gm1 represents the transconductance of transistor M1 and rds represents the resistance of the current source Is looking down from the source terminal of transistor M1 (see [reference]). Figure 3(The arrow in the image). At low operating frequencies and when the value of capacitor C is low, equation 1 can be simplified to the following expression:

[0034]

[0035] As shown in Equation 3, the total capacitance of circuit 22 is equal to C multiplied by (1+Gm*R2*(R1+R3) / (R1+R2)).

[0036] Equation 3 is an approximation of the input impedance Zin for relatively low frequency values ​​(such as operating frequencies less than 1 MHz, less than 10 MHz, less than 100 kHz, less than 1 kHz, less than 100 Hz, less than 10 Hz, 0-10 Hz, 0-1 kHz, 0-10 kHz, 0-100 kHz, 0-1 MHz, 0-10 MHz, etc.). Therefore, circuit 22 can provide very low impedance over a relatively low frequency range, which is useful for applications such as audio systems (as an example). The value of capacitor C can be relatively low to save circuit area, and can be equal to or less than 10pF (picofarad), equal to or less than 1pF, equal to or less than 100pF, equal to or less than 1nF (nanofarad), 10pF-100pF, 1pF-10pF, 1pF-100pF, 0.1pF-100pF, 1pF-1000pF or other low capacitance values.

[0037] Configured in this way, the capacitance multiplier circuit 22 can multiply the capacitance C by a factor of at least 2x, 3x, 2x-10x, 20x, 10x-20x, 20x-100x, 100x-200x, 100x-1000x, 2x-1000x, or greater. As an example where the capacitor C is 10pF, the tunable resistor R3 can be adjusted to a first value to produce an effective total capacitance of 30pF (e.g., to increase the capacitance by 3x), adjusted to a second value to produce an effective total capacitance of 200pF (e.g., to increase the capacitance by 20x), adjusted to a third value to produce an effective total capacitance of 2nF (e.g., to increase the capacitance by 200x), or tuned to other desired values ​​to produce a desired range of total (multiplied) capacitance. Therefore, Figure 3 The exemplary capacitance multiplier circuit 22 can be used to provide a wide range of tunable capacitance without consuming a large amount of circuit area, consuming a large amount of power, and having no voltage drop (which further enables its application in lower power systems). The effective total capacitance value of circuit 22 is sometimes referred to as the multiplier capacitance value.

[0038] Figure 4 This is a circuit diagram showing a specific implementation of a tunable resistor R3 (sometimes referred to as a tunable resistor or tunable resistor circuit). For example... Figure 4As shown, the tunable resistor R3 has a first terminal (port) P1, a second terminal (port) P2, and a plurality of resistors 40 switchably coupled between terminals P1 and P2. For example, a first switch S1 (e.g., by turning S1 on) can be used to selectively activate the first resistor 40, a second switch S2 (e.g., by turning S2 on) can be used to selectively activate the second resistor 40, ..., and a switch SN can be used to selectively activate the Nth resistor 40. The tunable resistor R3 may include any number of resistors 40 (e.g., N may be equal to at least three, four, 4-8, 8-16, 16-32, 32-64, 64-128, or other integer values). The values ​​of the resistors 40 may be the same or different. As an example, the values ​​of the resistors 40 may be binary weighted.

[0039] The effective total capacitance (impedance) of the capacitance multiplier circuit 22 can be controlled by adjusting the value of the tunable resistor R3. Figure 5 This is a graph 50 showing the effective total capacitance Ceff of circuit 22 as a function of the resistance R3. As shown by curve 50, the total capacitance Ceff increases with the value of the tunable resistor. The first subset of resistors 40 within the tunable resistor R3 (see...) Figure 4 A first subset of resistors 40 within the tunable resistor R3, different from the first subset, can be activated to provide a second resistance value (greater than the first resistance value) corresponding to a second capacitance value greater than the first capacitance value. A third subset of resistors 40 within the tunable resistor R3, different from the first and second subsets, can be activated to provide a third resistance value (greater than the second resistance value) corresponding to a third capacitance value even greater than the second capacitance value, and so on. A wide range of capacitance values ​​can be provided in this way.

[0040] The example above, in which the effective capacitance of circuit 22 is adjusted by controlling the value of the tunable resistor R3, is merely illustrative. As shown in Equation 3, the input impedance of circuit 22 is also a function of the Gm (transconductance) of circuit 34. The transconductance circuit 34 includes transistors M1 and M2, and current source Is. Figure 3 The examples are merely illustrative. Figure 6 Another embodiment is shown, in which the transconductance circuit 34 includes only transistors M1 and M2, and no current source is connected at the source terminal of transistor M1. Figure 6 As shown, transistor M1 has a drain terminal coupled to the Vdd power supply line via transistor M2 connected through a diode, and a source terminal directly coupled to the ground line. (The current source is missing.) Figure 6 The transconductance circuit 34 increases the transconductance Gm of the circuit 34, which provides an even higher capacitance multiplier factor while simultaneously trading off higher power consumption.

[0041] The transconducting circuit 34 includes both transistors M1 and M2. Figure 6 The examples are merely illustrative. Figure 7 Another embodiment is shown, in which the transconductance circuit 34 includes only transistor M1, with no current source connected at the source terminal of transistor M1, and no diode-connected transistor M2 connected at the drain terminal of transistor M1. Figure 7 As shown, transistor M1 has a drain terminal directly coupled to the Vdd power supply line and a source terminal directly coupled to the ground line. The transistor lacks a current source and diode connection. Figure 7 The transconductance circuit 34 also increases the transconductance Gm of the circuit 34, which provides an even higher capacitance multiplier factor while simultaneously trading off higher power consumption.

[0042] The transconductance circuit 34 includes a current source Is connected to the source terminal of transistor M1 and a diode connected to transistor M2 connected to the drain terminal of transistor M1. Figure 3 The examples are merely illustrative. Figure 8 Another embodiment is shown, wherein the transconductance circuit 34 has a drain resistor Rd coupled between the drain terminal of M1 and the positive power supply line, and a source resistor Rs coupled between the source terminal of M1 and the ground power supply line. The values ​​of resistors Rd and Rs are adjustable to tune the transconductance Gm of circuit 34, which directly affects the capacitance multiplier factor to increase or decrease the total effective capacitance of circuit 22. If desired, resistors Rd and / or Rs may have fixed or adjustable resistances (e.g., see [reference needed]). Figure 4 (tunable resistor).

[0043] The transconducting circuit 34 includes a drain resistor Rd and a source resistor Rs connected to the drain and source terminals of M1. Figure 8 The examples are merely illustrative. Figure 9 Another embodiment is shown, wherein the transconductance circuit 34 has a drain inductance Ld coupled between the drain terminal of M1 and the positive power supply line, and a source inductance Ls coupled between the source terminal of M1 and the ground power supply line. The values ​​of inductors Ld and Ls can be adjusted to tune the transconductance Gm of circuit 34, which directly affects the capacitance multiplier factor to increase or decrease the total effective capacitance of circuit 22. If desired, inductors Ld and / or Ls can have fixed inductance or adjustable inductance.

[0044] Figure 10 Another embodiment of the capacitance multiplier circuit 22 with transconductance circuit 34 is shown, wherein any desired electrical components are coupled to the drain and source terminals of transistor M1. Figure 10As shown, transistor M1 may have a drain terminal coupled to the positive power supply line via a first electrical component 60 (sometimes referred to as a drain-load component), and a source terminal coupled to the ground line via a second electrical component 62 (sometimes referred to as a source-load component). Electrical component 60 may be a diode-connected PMOS transistor, a shorting wire directly connecting the drain terminal of M1 to the Vdd power supply line, a resistor, an inductor, or a current source. Electrical component 62 may be a current source, a shorting wire directly connecting the source terminal of M1 to the ground line, a resistor, an inductor, or a diode-connected NMOS transistor. Any combination of components 60 and 62 can be implemented (e.g., component 60 may be a resistor and component 62 may be an inductor, component 60 may be an inductor and component 62 may be a diode-connected NMOS, etc.).

[0045] The capacitor C is connected between the Vdd power line and the gate terminal of the transistor M1. Figure 3 and Figures 6 to 10 The examples are merely illustrative. Figure 11 Another embodiment is shown, in which capacitor C is shunt to the ground wire. (See example...) Figure 11 As shown, capacitor C has a first terminal coupled to the gate terminal of transistor M1 and a second terminal directly coupled to ground. The remaining structure and function of the capacitance multiplier circuit 22 are the same as those of the capacitor multiplier circuit 22. Figure 3 The same principles apply, and detailed repetition is unnecessary to avoid obscuring this implementation scheme. Changes may be made if necessary. Figure 11 The transconductance circuit 34 (for example, the diode-connected transistor M2 can be replaced by a shorting wire, resistor, inductor or current source that directly connects the drain terminal of M1 to the Vdd power line, and / or the current source Is can be replaced by a shorting wire, resistor, inductor or diode-connected NMOS transistor that directly connects the source terminal of M1 to the ground line).

[0046] According to one embodiment, an integrated circuit is provided, the integrated circuit comprising: a circuit coupled to a power line; a capacitor having a first terminal coupled to the power line and having a second terminal; an adjustable resistor having a first terminal coupled to the second terminal of the capacitor and having a second terminal; and a transconductance circuit coupled to the capacitor and the adjustable resistor.

[0047] According to another embodiment, the integrated circuit includes: a first resistor having a first terminal coupled to the power supply line and a second terminal coupled to the second terminal of the adjustable resistor; and a second resistor having a first terminal coupled to the second terminal of the adjustable resistor and a second terminal coupled to a ground line.

[0048] According to another embodiment, the transconductance circuit includes a transistor having a gate terminal coupled to the second terminal of the capacitor, a first source-drain terminal coupled to the power supply line, and a second source-drain terminal coupled to the ground line.

[0049] According to another embodiment, the transconductance circuit includes a current source coupled between the second source-drain terminal of the transistor and the ground wire.

[0050] According to another embodiment, the transconductance circuit includes an additional transistor having a first source-drain terminal coupled to the first source-drain terminal of the transistor, a gate terminal coupled to the first source-drain terminal, and a second source-drain terminal coupled to the power line.

[0051] According to another embodiment, the transconductance circuit includes an additional transistor having a first source-drain terminal coupled to the first source-drain terminal of the transistor, a gate terminal coupled to the first source-drain terminal, and a second source-drain terminal coupled to the power line.

[0052] According to another implementation, the first source-drain terminal of the transistor is directly coupled to the power line.

[0053] According to another implementation, the second source-drain terminal of the transistor is directly coupled to the ground line.

[0054] According to another embodiment, the transconductance circuit includes: a first resistor coupled between the power line and the first source-drain terminal of the transistor; and a second resistor coupled between the second source-drain terminal of the transistor and the ground line.

[0055] According to another embodiment, the transconductance circuit includes: a first inductor coupled between the power line and the first source-drain terminal of the transistor; and a second inductor coupled between the second source-drain terminal of the transistor and the ground line.

[0056] According to another embodiment, the adjustable resistor includes: a plurality of resistors; and a plurality of switches configured to activate and deactivate the plurality of resistors.

[0057] According to another embodiment, the capacitor, the adjustable resistor, and the transconductance circuit together form a capacitance multiplier circuit, which has a multiplier capacitance value that is increased by increasing the resistance value of the adjustable resistor.

[0058] According to another embodiment, the capacitor has a capacitance value, and the multiplied capacitance value is greater than one hundred times the capacitance value of the capacitor.

[0059] According to one embodiment, a capacitance multiplier circuit is provided, the capacitance multiplier circuit comprising: a capacitor having a first terminal coupled to a positive power supply line and having a second terminal; an adjustable resistor coupled to the second terminal of the capacitor; and a transistor having a gate terminal coupled to the second terminal of the capacitor, a first source-drain terminal coupled to the positive power supply line, and a second source-drain terminal coupled to a ground power supply line.

[0060] According to another embodiment, the capacitance multiplier circuit includes: a first resistor having a first terminal coupled to the positive power supply line and a second terminal coupled to the adjustable resistor; and a second resistor having a first terminal coupled to the adjustable resistor and a second terminal coupled to the ground power supply line.

[0061] According to another embodiment, the capacitance multiplier circuit includes an electrical component coupled between the positive power supply line and the first source-drain terminal of the transistor. The electrical component is selected from the group consisting of a diode-connected transistor, a resistor, and an inductor.

[0062] According to another embodiment, the capacitance multiplier circuit includes an electrical component coupled between the second source-drain terminal of the transistor and the ground power supply line. The electrical component is selected from the group consisting of a current source, a resistor, and an inductor.

[0063] According to one embodiment, a capacitance multiplier circuit is provided, the capacitance multiplier circuit comprising: a capacitor having a first terminal and a second terminal coupled to a ground power supply line; an adjustable resistor coupled to the first terminal of the capacitor; and a transistor having a gate terminal coupled to the first terminal of the capacitor, a first source-drain terminal coupled to a positive power supply line, and a second source-drain terminal coupled to the ground power supply line.

[0064] According to another embodiment, the capacitance multiplier circuit includes: a first resistor having a first terminal coupled to the positive power supply line and a second terminal coupled to the adjustable resistor; and a second resistor having a first terminal coupled to the adjustable resistor and a second terminal coupled to the ground power supply line.

[0065] According to another embodiment, the capacitance multiplier circuit includes an electrical component coupled to at least one of the first source-drain terminal and the second source-drain terminal of the transistor. The electrical component is selected from the group consisting of a diode-connected transistor, a current source, a resistor, and an inductor.

[0066] The foregoing description is merely illustrative and various modifications can be made to the described implementation scheme. The described implementation scheme can be implemented independently or in any combination.

Claims

1. An integrated circuit, comprising: The circuit is coupled to the positive power supply line; as well as The decoupling capacitor multiplier circuit includes: A capacitor having a first terminal coupled to the positive power supply line and having a second terminal; A first resistor having a first terminal coupled to the positive power supply line and having a second terminal; The second resistor has a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to the ground wire; An adjustable resistor having a first terminal coupled to the second terminal of the capacitor and a second terminal coupled to a node arranged between the first resistor and the second resistor; and A transconducting circuit coupled to the capacitor and the adjustable resistor, wherein the transconducting circuit includes: A transistor having a gate terminal directly coupled to the second terminal of the capacitor, a first source-drain terminal coupled to the positive power supply line, and a second source-drain terminal coupled to a ground line.

2. The integrated circuit according to claim 1, wherein the transconductance circuit further comprises: A current source coupled between the second source-drain terminal of the transistor and the ground wire.

3. The integrated circuit according to claim 2, wherein the transconductance circuit further comprises: An additional transistor having a first source-drain terminal coupled to the first source-drain terminal of the transistor, a gate terminal coupled to the first source-drain terminal, and a second source-drain terminal coupled to the positive power line.

4. The integrated circuit according to claim 1, wherein the transconductance circuit further comprises: An additional transistor having a first source-drain terminal coupled to the first source-drain terminal of the transistor, a gate terminal coupled to the first source-drain terminal, and a second source-drain terminal coupled to the positive power line.

5. The integrated circuit of claim 1, wherein the first source-drain terminals of the transistor are directly coupled to the positive power supply line.

6. The integrated circuit of claim 1, wherein the second source-drain terminal of the transistor is directly coupled to the ground line.

7. The integrated circuit of claim 1, wherein the transconductance circuit further comprises: A third resistor is coupled between the positive power line and the first source-drain terminals of the transistor; and A fourth resistor is coupled between the second source-drain terminal of the transistor and the ground wire.

8. The integrated circuit of claim 1, wherein the transconductance circuit further comprises: A first inductor is coupled between the positive power line and the first source-drain terminal of the transistor. and A second inductor is coupled between the second source-drain terminal of the transistor and the ground wire.

9. The integrated circuit of claim 1, wherein the adjustable resistor comprises: Multiple resistors; and Multiple switches are configured to activate and disable the multiple resistors.

10. The integrated circuit of claim 1, wherein the capacitor, the adjustable resistor, and the transconductance circuit together form a capacitance multiplier circuit, the capacitance multiplier circuit having a multiplier capacitance value increased by increasing the resistance value of the adjustable resistor.

11. The integrated circuit of claim 10, wherein the capacitor has a capacitance value, and wherein the multiplication capacitance value is greater than one hundred times the capacitance value of the capacitor.

12. A capacitance multiplier circuit, comprising: A capacitor having a first terminal coupled to a positive power supply line and having a second terminal; An adjustable resistor is coupled to the second terminal of the capacitor; A transistor having a gate terminal directly coupled to the second terminal of the capacitor, a first source-drain terminal coupled to the positive power supply line, and a second source-drain terminal coupled to a ground power supply line; A first resistor having a first terminal coupled to the positive power supply line and a second terminal coupled to the adjustable resistor; and The second resistor has a first terminal coupled to the adjustable resistor and a second terminal coupled to the ground power line.

13. The capacitance multiplier circuit according to claim 12, further comprising: An electrical component coupled between the positive power line and the first source-drain terminal of the transistor, the electrical component being a component selected from the group consisting of diode-connected transistors, resistors, and inductors.

14. The capacitance multiplier circuit according to claim 12, further comprising: An electrical component coupled between the second source-drain terminal of the transistor and the ground power supply line, the electrical component being a component selected from the group consisting of: a current source, a resistor, and an inductor.

15. A capacitance multiplier circuit, comprising: A capacitor having a first terminal and a second terminal coupled to a grounded power supply line; An adjustable resistor is coupled to the first terminal of the capacitor; A transistor having a gate terminal directly coupled to the first terminal of the capacitor, a first source-drain terminal coupled to a positive power supply line, and a second source-drain terminal coupled to the ground power supply line; A first resistor having a first terminal coupled to the positive power supply line and a second terminal coupled to the adjustable resistor; and The second resistor has a first terminal coupled to the adjustable resistor and a second terminal coupled to the ground power line.

16. The capacitance multiplier circuit according to claim 15, further comprising: An electrical component coupled to at least one of the first source-drain terminal and the second source-drain terminal of the transistor, the electrical component being a component selected from the group consisting of: diode-connected transistors, current sources, resistors, and inductors.

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