Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, the substrate being formed with a polysilicon gate layer, the polysilicon gate layer comprising a bottom gate layer and a plurality of top gate layers standing on the bottom gate layer, adjacent top gate layers and bottom gate layers enclosing a first recess; forming an interlayer dielectric layer on the substrate at sides of the polysilicon gate layer, the interlayer dielectric layer covering sidewalls of the polysilicon gate layer and filling in the first recess; forming a second recess through the interlayer dielectric layer at a top of the bottom gate layer and exposing the bottom gate layer; forming a metal gate layer in the second recess and electrically connecting the bottom gate layer, the polysilicon gate layer and the metal gate layer jointly serving as a first gate structure, and the metal gate layer serving as an external terminal of the first gate structure. The present application avoids damage to the interlayer dielectric layer at sides of the first gate structure caused by a process of forming a metal silicide, thereby reducing the probability of height difference of the interlayer dielectric layer on the substrate in different regions.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the development of high integration of semiconductor devices, the gate length of metal oxide semiconductor devices is being scaled down to smaller sizes, and accordingly, the manufacturing process of semiconductor devices is constantly improving to meet the requirements of device performance.

[0003] At present, devices with higher working voltage are usually integrated with devices with lower working voltage (i.e. logic platform devices) for manufacturing. In order to reduce the contact resistance between the devices with higher working voltage and the contact plug in the integrated circuit, a process of forming metal silicide is needed to be added after the formation of the metal gate structure in the manufacturing process of the original logic platform device, which brings adverse effects to other structures of the semiconductor device. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which improves the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a substrate, the substrate comprising a first device region for forming a first device; a polysilicon gate layer located on the substrate of the first device region, the polysilicon gate layer comprising a bottom gate layer and a plurality of top gate layers standing on the bottom gate layer, the bottom gate layer and the adjacent top gate layer enclosing a first recess; an interlayer dielectric layer located on the side of the polysilicon gate layer of the substrate and covering the sidewall of the polysilicon gate layer, the interlayer dielectric layer also filling in the first recess; a second recess penetrating through the interlayer dielectric layer in the first recess and exposing the bottom gate layer; a metal gate layer located in the second recess and electrically connected to the bottom gate layer, the polysilicon gate layer and the metal gate layer in the first device region serving as a first gate structure together, and the metal gate layer serving as an external terminal of the first gate structure.

[0006] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region for forming a first device, and a polysilicon gate layer formed on the substrate, the polysilicon gate layer in the first device region comprising a bottom gate layer and a plurality of top gate layers standing on the bottom gate layer, and the adjacent top gate layer and the bottom gate layer enclosing a first groove; forming an interlayer dielectric layer on the substrate at the side of the polysilicon gate layer, the interlayer dielectric layer covering the sidewall of the polysilicon gate layer, and the interlayer dielectric layer also filling in the first groove; forming a second groove in the interlayer dielectric layer, the second groove penetrating the interlayer dielectric layer at the top of the bottom gate layer and exposing the bottom gate layer; and forming a metal gate layer in the second groove, the metal gate layer electrically connecting the bottom gate layer, the polysilicon gate layer and the metal gate layer in the first device region jointly serving as a first gate structure, and the metal gate layer serving as an external terminal of the first gate structure.

[0007] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0008] The embodiment of the present application provides a semiconductor structure, comprising a polysilicon gate layer, the polysilicon gate layer comprising a bottom gate layer and a plurality of top gate layers standing on the bottom gate layer, the bottom gate layer and the adjacent top gate layer enclosing a first groove, an interlayer dielectric layer also filling in the first groove, a second groove penetrating the interlayer dielectric layer at the top of the bottom gate layer, and a metal gate layer located in the second groove and electrically connecting the bottom gate layer; in the embodiment, the top surface of the first gate structure exposes the polysilicon gate layer and also exposes the metal gate layer, the metal gate layer serving as an external terminal of the first gate structure, the contact resistance of the metal gate layer is small, and therefore the first gate structure can be directly electrically connected with an external interconnection structure (for example, a gate plug) through the metal gate layer; compared with the scheme of forming a metal silicide on the top surface of the polysilicon gate layer and taking the metal silicide as an external terminal, the embodiment of the present application can omit the process of forming a metal silicide on the polysilicon gate layer exposed at the top of the first gate structure, and accordingly avoid the damage of the process of forming the metal silicide to the interlayer dielectric layer at the side of the first gate structure, thereby reducing the probability of generating a height difference between the interlayer dielectric layer on the substrate in the first device region and the top gate layer and the interlayer dielectric layer on the substrate in other regions; at the same time, the first gate structure comprises the metal gate layer, which is conducive to reducing the resistance of the first gate structure, and the first gate structure also comprises the polysilicon gate layer, so that the first device reaches a target threshold voltage, which is conducive to improving the working performance of the semiconductor structure.

[0009] The forming method provided by the embodiment of the present application, the bottom gate layer and the adjacent top gate layer form a first recess, after forming the interlayer dielectric layer, a second recess is formed in the interlayer dielectric layer, the second recess penetrates the interlayer dielectric layer on the top of the bottom gate layer, the second recess exposes the bottom gate layer, and a metal gate layer electrically connected to the bottom gate layer is formed in the second recess; in the embodiment of the present application, the top surface of the first gate structure exposes the polysilicon gate layer and also exposes the metal gate layer, the metal gate layer is used as an external terminal of the first gate structure, the contact resistance of the metal gate layer is small, and therefore the first gate structure can be directly electrically connected to an external interconnection structure (for example, a gate plug) through the metal gate layer; compared with a scheme in which a metal silicide is formed on the top surface of the polysilicon gate layer and the metal silicide is used as an external terminal, the embodiment of the present application can omit the process of forming the metal silicide on the polysilicon gate layer exposed on the top of the first gate structure, and therefore the damage of the process of forming the metal silicide to the interlayer dielectric layer on the side of the first gate structure is avoided, thereby reducing the probability that the interlayer dielectric layer on the substrate of the first device area and the top gate layer and the interlayer dielectric layer on the substrate of other areas have a height difference; in addition, the first gate structure includes the metal gate layer, which is beneficial to reducing the resistance of the first gate structure, and the first gate structure also includes the polysilicon gate layer, so that the first device reaches a target threshold voltage, and the working performance of the semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figures 1 to 3 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;

[0011] Figure 4 is a structure diagram of an embodiment of the semiconductor structure of the present application;

[0012] Figures 5 to 11 is a structure diagram corresponding to each step in a forming method of a semiconductor structure of the present application. DETAILED DESCRIPTION

[0013] The working performance of the semiconductor structure needs to be improved. The reason why the working performance of the semiconductor structure needs to be improved will be analyzed in combination with a forming method of a semiconductor structure.

[0014] Figures 1 to 3 is a structure diagram corresponding to each step in a forming method of a semiconductor structure.

[0015] REFERENCE Figure 1, a substrate 10 is provided, the substrate 10 includes a first device region 10H for forming a first device and a second device region 10L for forming a second device, the second device has a channel length smaller than that of the first device, a polysilicon gate structure 22 is formed on the substrate 10 in the first device region 10H, a metal gate structure 26 is formed on the substrate 10 in the second device region 10L, and an interlayer dielectric layer 50 is further formed on the substrate 10, the interlayer dielectric layer 50 covers sidewalls of the polysilicon gate structure 22 and sidewalls of the metal gate structure 26.

[0016] The polysilicon gate structure 22 and the substrate 10 form a gate oxide layer (not shown), a high-k gate dielectric layer (not shown) on the gate oxide layer, and a metal barrier layer (not shown) on the high-k gate dielectric layer.

[0017] Referring to Figure 2 An overlying dielectric layer 60 is formed on the interlayer dielectric layer 50, the overlying dielectric layer 60 covers the top of the metal gate structure 22 and exposes the top of the polysilicon gate structure 22.

[0018] Specifically, the step of forming the overlying dielectric layer 60 includes: forming an overlying dielectric material layer (not shown) on the interlayer dielectric layer 50, the overlying dielectric material layer covers the top of the polysilicon gate structure 22 and the metal gate structure 26; removing the overlying dielectric material layer in the first device region 10H to expose the top of the polysilicon gate structure 22, and the remaining overlying dielectric material layer serves as the overlying dielectric layer 60.

[0019] Referring to Figure 3 After forming the overlying dielectric layer 60, a metal silicide layer 70 is formed on the top of the polysilicon gate structure 22.

[0020] Since the contact resistance of the polysilicon in the polysilicon gate structure 22 is large, it is necessary to form a metal silicide layer 70 on the top of the polysilicon gate structure 22 to reduce the contact resistance, and the metal silicide layer 70 serves as an external terminal of the polysilicon gate structure 22.

[0021] It should be noted that the formation of the metal silicide layer 70 needs to be formed after the formation of the metal gate structure 26, if the metal silicide layer 70 is formed before the formation of the metal gate structure 26, the metal silicide layer 70 is easy to cause metal contamination in the subsequent process of forming the metal gate structure 26, therefore, it is necessary to form the overlying dielectric layer 60 covering the metal gate structure 26 after the formation of the metal gate structure 26, and then form the metal silicide layer 70 on the top of the exposed polysilicon gate structure 22.

[0022] However, after the formation of the covering dielectric layer 60, since the covering dielectric layer remains on top of the ILD layer 50 in the second device region 10L, a height difference of dielectric layers between the first device region 10H and the second device region 10L is caused. In order to completely expose the top of the polysilicon gate structure 22, when removing the covering dielectric layer in the first device region 10H, part of the ILD layer 50 in the first device region 10H is also removed, so that a height difference between the top of the ILD layer 50 and the top of the polysilicon gate structure 22 is formed, further increasing the height difference of dielectric layers between the first device region 10H and the second device region 10L, and causing adverse effects on subsequent processes. For example, after the deposition of a dielectric layer, the surface is still uneven, and in the photolithography process for forming a contact hole plug, defocus is easily caused, resulting in the size of the contact hole plug after photolithography and etching exceeding the design and process capability, and further affecting the working performance of the semiconductor structure.

[0023] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region for forming a first device, and a polysilicon gate layer formed on the substrate, the polysilicon gate layer in the first device region comprising a bottom gate layer and a plurality of top gate layers standing on the bottom gate layer, the bottom gate layer and the adjacent top gate layer surrounding a first groove, and an ILD layer formed on the substrate at the side of the polysilicon gate layer, the ILD layer covering the sidewall of the polysilicon gate layer, and the ILD layer also filling in the first groove; forming a second groove in the ILD layer, the second groove penetrating the ILD layer on top of the bottom gate layer and exposing the bottom gate layer; forming a metal gate layer electrically connected to the bottom gate layer in the second groove, the polysilicon gate layer and the metal gate layer in the first device region serving as a first gate structure, and the metal gate layer serving as an external terminal of the first gate structure.

[0024] In the forming method, the bottom gate layer and the adjacent top gate layer enclose a first recess, after forming the interlayer dielectric layer, a second recess is formed in the interlayer dielectric layer, the second recess penetrates the interlayer dielectric layer on the top of the bottom gate layer, the second recess exposes the bottom gate layer, and a metal gate layer electrically connected to the bottom gate layer is formed in the second recess; in the embodiment, the top surface of the first gate structure exposes the polysilicon gate layer and also exposes the metal gate layer, the metal gate layer is used as an external terminal of the first gate structure, the contact resistance of the metal gate layer is small, and therefore the first gate structure can be directly electrically connected to an external interconnection structure (for example, a gate plug) through the metal gate layer; compared with a scheme in which a metal silicide is formed on the top surface of the polysilicon gate layer and the metal silicide is used as an external terminal, the embodiment can omit the process of forming the metal silicide on the polysilicon gate layer exposed on the top of the first gate structure, and therefore the damage of the process of forming the metal silicide to the interlayer dielectric layer on the side of the first gate structure is avoided, thereby reducing the probability that the interlayer dielectric layer on the substrate of the first device region and the top gate layer and the interlayer dielectric layer on the substrate of other regions have a height difference; in addition, the first gate structure includes the metal gate layer, which is beneficial to reducing the resistance of the first gate structure, and the first gate structure also includes the polysilicon gate layer, so that the first device reaches a target threshold voltage, and the working performance of the semiconductor structure is improved.

[0025] In order to make the above objectives, characteristics and advantages of the present application more apparent, clear and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0026] Figure 4 is a structural schematic diagram of an embodiment of the semiconductor structure of the present application.

[0027] The semiconductor structure comprises: a substrate 101, the substrate 101 comprising a first device region 101L for forming a first device; a polysilicon gate layer 201 located on the substrate 101 of the first device region 101H, the polysilicon gate layer 201 comprising a bottom gate layer 221 and a plurality of top gate layers 211 standing on the bottom gate layer 221, the bottom gate layer 221 and the adjacent top gate layer 211 surrounding a first recess (not shown); an interlayer dielectric layer 501 located on the substrate 101 of the side of the polysilicon gate layer 201 and covering the sidewall of the polysilicon gate layer 201, the interlayer dielectric layer 501 also filling in the first recess; a second recess (not shown) penetrating through the interlayer dielectric layer 501 in the first recess and exposing the bottom gate layer 221; a metal gate layer 261 located in the second recess and electrically connected to the bottom gate layer 221, the polysilicon gate layer 201 and the metal gate layer 261 in the first device region 101H jointly serving as a first gate structure 271, and the metal gate layer 261 serving as an external terminal of the first gate structure 271.

[0028] In the embodiment, the top surface of the first gate structure 271 exposes the polysilicon gate layer 201 and also exposes the metal gate layer 261, the metal gate layer 261 serving as an external terminal of the first gate structure 271, and the contact resistance of the metal gate layer 261 is small, so that the first gate structure 271 can be directly electrically connected to an external interconnection structure (for example, a gate plug) through the metal gate layer 261. Compared with the scheme of forming a metal silicide on the top surface of the polysilicon gate layer and taking the metal silicide as an external terminal, the embodiment of the present application can omit the process of forming a metal silicide on the polysilicon gate layer exposed on the top of the first gate structure 271, and accordingly avoid the damage of the process of forming the metal silicide to the interlayer dielectric layer 501 on the side of the first gate structure 271, thereby reducing the probability of generating a height difference between the interlayer dielectric layer 501 on the substrate 101 of the first device region 101H and the top gate layer 211 and the interlayer dielectric layer 501 on the substrate 101 of other regions. At the same time, the first gate structure 271 comprises the metal gate layer 261, which is conducive to reducing the resistance of the first gate structure 271, and the first gate structure 271 also comprises the polysilicon gate layer 201, so that the first device reaches a target threshold voltage, which is conducive to improving the working performance of the semiconductor structure.

[0029] The substrate 101 provides a process operation basis for the forming process of the semiconductor structure.

[0030] The substrate 101 comprises a substrate.

[0031] In this embodiment, the substrate material is silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be a material suitable for process requirements or easy to integrate.

[0032] It should be noted that when the formation method is used to form a fin field-effect transistor, the substrate 101 may also include fins located on the substrate. As an example, the fins and the substrate are made of the same material.

[0033] The substrate includes a first device region 101H for forming a first device and a second device region 101L for forming a second device, wherein the channel length of the second device is less than the channel length of the first device.

[0034] As an example, the operating voltage of the first device is greater than that of the second device, such that the channel length of the first device is greater than that of the second device.

[0035] In this embodiment, the first device includes one or both of medium-voltage and high-voltage devices, and the second device is a low-voltage device. The operating voltages of the low-voltage, medium-voltage, and high-voltage devices increase sequentially. As an example, the operating voltage of the low-voltage device is less than 1V, the operating voltage of the medium-voltage device is 1V to 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0036] The polysilicon gate layer 201 is made of polysilicon and is used as part of the device gate structure (i.e., the first gate structure 271) of the first device region 101H.

[0037] Since the channel length of the first device is relatively long, in the polysilicon gate layer 201 in the first device region 101H, the bottom gate layer 221 and the adjacent top gate layer 211 form a first groove. The linewidth dimension of the top gate layer 211 and the spacing between adjacent top gate layers 211 (i.e., the linewidth dimension of the first groove) are both small. This reduces the probability of dishing defects at the top of the polysilicon gate layer 201 during the planarization process of the semiconductor structure. For example, it improves the probability of top surface dipping problems caused by the formation of the metal gate layer in the polysilicon gate layer 201.

[0038] The depth h of the first recess cannot be too large or too small. If the depth h of the first recess is too large, the bottom gate layer 221 is likely to be etched through in the etching process of forming the first recess; if the depth h of the first recess is too small, the thickness of the top gate layer 211 is correspondingly too small. Since the metal gate layer 261 is also formed in the first recess, and the top of the top gate layer 211 needs to be planarized in the process of forming the metal gate layer 261, the depth h of the first recess being too small is likely to result in the top gate layer 211 being completely removed, thereby causing over-grinding of the bottom gate layer 221 and affecting the performance of the semiconductor structure. Therefore, in this embodiment, the depth h of the first recess is 1 / 2 to 3 / 4 of the total thickness of the polysilicon gate layer 201.

[0039] The interlayer dielectric layer 501 plays a role of isolation between adjacent devices.

[0040] In this embodiment, the material of the interlayer dielectric layer 501 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0041] In this embodiment, the interlayer dielectric layer 501 also fills in the first recess, thereby providing a process basis for forming the second recess.

[0042] In this embodiment, the second recess penetrates the interlayer dielectric layer 501 of the first recess and exposes the bottom gate layer 221, thereby providing space for the metal gate layer 261 of the first device area 101H, and the bottom of the second recess exposes the bottom gate layer 221, which is used to realize the electrical connection between the metal gate layer and the bottom gate layer 221.

[0043] The opening size width d of the second recess cannot be too large or too small. If the opening size width d of the second recess is too large, the top gate layer 211 is likely to be exposed and etched together due to alignment offset in the photolithography process of etching to form the second recess, thereby forming an opening with a small size, so that the metal gate layer 261 in the second recess is difficult to completely fill the opening with a small size, thereby affecting the performance of the semiconductor structure; if the opening size width d of the second recess is too small, the process of forming the second recess is difficult, and the formation of the metal gate layer in the second recess is also difficult, so that it is difficult to form a metal gate layer with a small contact resistance as an external terminal. Therefore, in this embodiment, the opening size width of the second recess is 0.08 μm to 0.15 μm. For example, the opening size width of the second recess is 0.11 μm.

[0044] The metal gate layer 261 comprises a work function layer (not shown) and a gate electrode layer (not shown) on the work function layer.

[0045] The work function layer is used to adjust the threshold voltage of the formed transistor. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or more of TaN, TiAl, Mo, MoN, AlN and TiAlC.

[0046] The gate electrode layer is used to lead out the electrical property of the metal gate layer 261. In the embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti or W.

[0047] The metal gate layer 261 in the second recess of the first device region 101H and the polysilicon gate layer 201 together serve as a first gate structure 271, and the metal gate layer 261 is used as an external terminal of the first gate structure.

[0048] In the embodiment, the metal gate layer 261 is also in the interlayer dielectric layer 501 on the substrate 101 of the second device region 101L, and is used as a second gate structure 281, and the second gate structure 281 is a metal gate structure.

[0049] In the embodiment, the interlayer dielectric layer 501 also covers the sidewall of the metal gate layer 261 of the second device region 101L.

[0050] The process of forming the metal gate layer 261 needs to first form a gate opening in the interlayer dielectric layer 501, and then form the metal gate layer 261 in the gate opening, and thus the interlayer dielectric layer 501 covers the sidewall of the metal gate layer 261 of the second device region 101L, and exposes the top of the metal gate layer 261.

[0051] It should be noted that in the embodiment, the metal gate structure is formed by using a high-k first metal gate last process, and the polysilicon gate layer 201 and a dummy gate layer for occupying the space position of the metal gate layer 261 of the second device region 101L are formed together.

[0052] Therefore, in this embodiment, the semiconductor structure further comprises: a high-k gate dielectric layer 231 and a metal blocking layer 241 located on the high-k gate dielectric layer 231, between the polysilicon gate layer 201 and the substrate 101 in the first device region 101H, and between the metal gate layer 261 and the substrate 101 in the second device region 101L.

[0053] The material of the high-k gate dielectric layer 231 is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 231 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc. As an example, the material of the high-k gate dielectric layer 231 is HfO2.

[0054] The metal blocking layer 241 is used to isolate the high-k gate dielectric layer 231 and the gate electrode layer in the metal gate layer 261, to protect the high-k gate dielectric layer 231, and also to block the diffusion of easily diffusing ions (e.g. Al ions) in the gate electrode layer into the high-k gate dielectric layer 231.

[0055] Specifically, the material of the metal blocking layer 241 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal blocking layer 241 is titanium nitride.

[0056] In this embodiment, in the first device region 101H, the polysilicon gate layer 201, the metal gate layer 261, the high-k gate dielectric layer 231 and the metal blocking layer 241 together form a first gate structure 271; and in the second device region 101L, the metal gate layer 261, the high-k gate dielectric layer 231 and the metal blocking layer 241 together form a second gate structure 281.

[0057] In this embodiment, the semiconductor structure further comprises: a side wall 251 located on the sidewall of the polysilicon gate layer 201, which also covers the sidewall of the first recess.

[0058] The side wall 251 is used to protect the sidewall of the polysilicon gate layer 201. Moreover, the side wall 251 also covers the sidewall of the first recess, to protect the sidewall of the top gate layer 211 and reduce the probability of the top gate layer 211 from being recessed during the planarization process.

[0059] In this embodiment, the side wall 251 also covers the sidewall of the metal gate layer 261 in the second device region 101L, to protect the sidewall of the metal gate layer 261.

[0060] The side wall 251 can be a single-layer structure or a stacked structure, and the material of the side wall 251 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride, and boron carbon nitride. In this embodiment, the side wall 251 is a stacked structure (not shown).

[0061] Specifically, the side wall 251 is an ON (oxide-nitride) structure, that is, the side wall 251 includes a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer.

[0062] The silicon nitride has high hardness, which is beneficial to the protection of the polysilicon gate layer 201.

[0063] In this embodiment, the semiconductor structure further includes a gate hard mask layer 301 located on the sidewall of the first recess and the bottom of the first recess at the side of the metal gate layer 201.

[0064] The gate hard mask layer 301 is used as an etching mask for forming the polysilicon gate layer 201.

[0065] In the process of forming the interlayer dielectric layer 501 and the metal gate layer 261, a planarization process is needed, and the gate hard mask layer 301 located in the first recess is used to protect the top gate layer 211 of the sidewall of the first recess, so as to reduce the probability of recess defects of the polysilicon gate layer 201 in the planarization process.

[0066] In this embodiment, in the first recess, the side wall 251 covers the sidewall of the gate hard mask layer 301, and the gate hard mask layer 301 and the side wall 251 together serve as a protective side wall, thereby enhancing the protection effect and further reducing the probability of recess defects of the polysilicon gate layer 201 in the planarization process.

[0067] In addition, the forming step of the side wall generally includes forming a conformal side wall material layer covering the first recess, removing the side wall material layer located at the bottom of the first recess, and retaining the side wall material layer located at the sidewall of the first recess as a side wall. In the process of removing the side wall material layer located at the bottom of the first recess, the gate hard mask layer 301 at the bottom of the first recess can also function as an etching stop layer, thereby protecting the bottom gate layer 221 and reducing damage to the bottom gate layer 221.

[0068] In this embodiment, the material of the gate hard mask layer 301 includes silicon nitride.

[0069] The silicon nitride has high hardness, which is beneficial to the protection of the polysilicon gate layer 201.

[0070] In this embodiment, the semiconductor structure further includes a metal hard mask layer 431 conformally covering the bottom and sidewall of the second recess.

[0071] Correspondingly, in this embodiment, the metal gate layer 261 in the first device region 101H covers the metal mask layer 431.

[0072] When forming the gate opening in the ILD layer 501 of the second device region 101L, photoresist needs to be formed on the metal hard mask layer 431 of the first device region 101H, the photoresist covers the top of the polysilicon gate layer 201 and fills the second recess, and after forming the gate opening by taking the photoresist and the metal hard mask layer 431 as etching masks, the photoresist needs to be removed. When the photoresist filled in the second recess is removed, the metal hard mask layer 431 protects the sidewall and bottom of the second recess, reducing damage to the ILD layer 501 in the first recess and the bottom gate layer 221 at the bottom of the second recess.

[0073] The metal mask layer 431 is made of metal material and has good conductivity, so that the metal gate layer 261 in the first device region 101H can be electrically connected with the bottom gate layer 221.

[0074] The material of the metal hard mask layer 431 includes titanium nitride.

[0075] The titanium nitride has high hardness and high etching selectivity ratio with polysilicon material, which is beneficial to the etching mask and the protection of the ILD layer 501 in the first recess and the bottom gate layer 221 at the bottom of the second recess.

[0076] In this embodiment, the semiconductor structure further includes an isolation structure 111 in the substrate 101.

[0077] The isolation structure 111 is used to realize insulation between different devices, for example, in the CMOS manufacturing process, an isolation structure 111 is usually formed between NMOS transistors and PMOS transistors.

[0078] In this embodiment, the isolation structure 111 is a shallow trench isolation structure.

[0079] The material of the isolation structure 111 is insulating material. As an example, the material of the isolation structure 111 is silicon oxide.

[0080] Correspondingly, the present embodiment further provides a semiconductor structure forming method.

[0081] Figures 5 to 11is a structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure.

[0082] In combination with reference Figures 5 to 8 , a substrate 100 is provided, the substrate 100 includes a first device region 100H for forming a first device, a polysilicon gate layer 200 is formed on the substrate 100, the polysilicon gate layer 200 in the first device region 100H includes a bottom gate layer 220 and a plurality of top gate layers 210 standing on the bottom gate layer 220, adjacent top gate layers 210 and bottom gate layers 220 enclose a first recess 400; an interlayer dielectric layer 500 is formed on the substrate 100 at the side of the polysilicon gate layer 200, the interlayer dielectric layer 500 covers the sidewall of the polysilicon gate layer 200, and the interlayer dielectric layer 500 also fills in the first recess 400.

[0083] The substrate 100 provides a process operation basis for the forming process of the semiconductor structure.

[0084] In this embodiment, the substrate 100 includes a substrate.

[0085] In this embodiment, the material of the substrate is silicon, and in other embodiments, the material of the substrate can also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates. The material of the substrate can be a material suitable for process needs or easy to integrate.

[0086] It should be noted that when the forming method is used to form a fin field effect transistor, the substrate 100 can also correspondingly include a fin on the substrate. As an example, the material of the fin and the substrate is the same.

[0087] In this embodiment, an isolation structure 110 is also formed in the substrate 100.

[0088] The isolation structure 110 is used to realize insulation between different devices, for example, in a CMOS manufacturing process, an isolation structure 110 is usually formed between an NMOS transistor and a PMOS transistor.

[0089] In this embodiment, the isolation structure 110 is a shallow trench isolation structure.

[0090] The material of the isolation structure 110 is an insulating material. As an example, the material of the isolation structure 110 is silicon oxide.

[0091] In the embodiment, the substrate 100 further comprises a second device region 100L for forming a second device, and the channel length of the second device is smaller than that of the first device.

[0092] As an example, the working voltage of the first device is greater than that of the second device, so that the channel length of the first device is greater than that of the second device.

[0093] In the embodiment, the first device comprises one or both of a medium-voltage device and a high-voltage device, and the second device is a low-voltage device. The working voltages of the low-voltage device, the medium-voltage device and the high-voltage device are sequentially increased. As an example, the working voltage of the low-voltage device is less than 1V, the working voltage of the medium-voltage device is 1V to 10V, and the working voltage of the high-voltage device is greater than 10V.

[0094] The material of the polysilicon gate layer 200 is polysilicon, which is used as part of the device gate structure of the first device region 100H, i.e., for subsequent formation of the first gate structure.

[0095] Since the channel length of the first device is longer, in the polysilicon gate layer 200 in the first device region 100H, the bottom gate layer 220 and the adjacent top gate layer 210 form a first groove 400, and the line width dimension of the top gate layer 210 and the spacing between adjacent top gate layers 210 (i.e., the line width dimension of the first groove 400) are both small, thereby reducing the probability of dishing defects occurring on the top of the polysilicon gate layer 200 in the planarization process of the semiconductor structure, for example, improving the probability of the top surface dishing problem of the polysilicon gate layer 201 when forming a metal gate layer.

[0096] The depth h of the first groove 400 cannot be too large or too small. If the depth h of the first groove 400 is too large, it is easy to cause the bottom gate layer 220 to be etched through during the etching process of forming the first groove 400; if the depth h of the first groove 400 is too small, correspondingly, the thickness of the top gate layer 210 is too small. Since a metal gate layer is also formed in the first groove 400 subsequently, and the top of the top gate layer 210 needs to be planarized during the process of forming the metal gate layer, if the depth h of the first groove is too small, it is easy to cause the top gate layer 210 to be completely removed, thereby causing over-grinding of the bottom gate layer 220 and affecting the performance of the semiconductor structure. Therefore, in the embodiment, the depth h of the first groove 400 is 1 / 2 to 3 / 4 of the total thickness of the polysilicon gate layer 200.

[0097] In this embodiment, after the polysilicon gate layer 200 is formed, an interlayer dielectric layer 500 is formed on the substrate 100 at the side of the polysilicon gate layer 200.

[0098] The interlayer dielectric layer 500 is used to isolate adjacent devices.

[0099] In this embodiment, the material of the interlayer dielectric layer 500 is insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0100] In this embodiment, the interlayer dielectric layer 500 is also filled in the first recess 400, and subsequently, a second recess needs to be formed in the first recess 400, and the interlayer dielectric layer 500 in the first recess 400 provides a process basis for forming the second recess.

[0101] It should be noted that in this embodiment, the metal gate structure is formed by a high-k first metal gate last process, and the polysilicon gate layer 200 of the second device region 100L also serves as a space position for the subsequently formed metal gate layer.

[0102] Therefore, in this embodiment, in the step of providing the substrate 100, a high-k gate dielectric layer 230 and a metal barrier layer 240 located on the high-k gate dielectric layer 230 are further formed between the polysilicon gate layer 200 and the substrate 100.

[0103] The material of the high-k gate dielectric layer 230 is high-k dielectric material, where high-k dielectric material refers to dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 230 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer 230 is HfO2.

[0104] The metal barrier layer 241 is used to isolate the high-k gate dielectric layer 230 and the gate electrode layer in the metal gate layer, to protect the high-k gate dielectric layer 230, and the metal barrier layer 240 is also used to block the diffusion of easily diffusing ions (such as Al ions) in the gate electrode layer into the high-k gate dielectric layer 230.

[0105] Specifically, the material of the metal barrier layer 240 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 240 is titanium nitride.

[0106] Specifically, referring toFigure 7 In the step of providing the substrate 100, a gate hard mask layer 300 is formed in the first recess 400 to cover the bottom and sidewall of the first recess 400.

[0107] The gate hard mask layer 300 is used as an etching mask for forming the polysilicon gate layer 200.

[0108] In the process of forming the interlayer dielectric layer 500 and the polysilicon gate layer 200, a planarization process is needed, and the gate hard mask layer 300 in the first recess 400 is used to protect the top gate layer 210 of the sidewall of the first recess 400, so as to reduce the probability of the polysilicon gate layer 200 from being recessed in the planarization process.

[0109] In the embodiment, the material of the gate hard mask layer 300 includes silicon nitride.

[0110] The silicon nitride has high hardness, which is beneficial to the protection of the polysilicon gate layer 200.

[0111] In the embodiment, the polysilicon gate layer 200 and the gate hard mask layer 300 are formed before the interlayer dielectric layer 500 is formed.

[0112] In combination with reference to Figures 5 to 7 The step of forming the polysilicon gate layer 200 and the gate hard mask layer 300 is described in detail.

[0113] In reference to Figure 5 A polysilicon gate material layer 130 is formed on the substrate 100.

[0114] The polysilicon material layer is used to prepare for forming a plurality of polysilicon gate layers 200 on the substrate 100.

[0115] In reference to Figure 6 A first recess 400 is formed in the polysilicon gate material layer of the first device region 100H, and the first recess 400 is located in a part of the thickness of the polysilicon gate material layer.

[0116] By forming the first recess 400, the polysilicon gate layer 200 subsequently formed in the first device region 100H includes a bottom gate layer 210 and a plurality of top gate layers 220 standing on the bottom gate layer 210, that is, the remaining polysilicon gate material layer 130 at the bottom of the first recess 400 is used to form the bottom gate layer 210, and the remaining polysilicon gate material layer 130 at the side of the first recess 400 is used to form the top gate layer 220.

[0117] In combination with reference to Figure 6A gate hard mask material layer 140 is formed on the polysilicon gate material layer 130, and the gate hard mask material layer 140 conformally covers the bottom and sidewall of the first recess 400 and the top of the polysilicon gate material layer 130.

[0118] The gate hard mask material layer 140 is used to prepare for the subsequent formation of the gate hard mask layer 300.

[0119] In this embodiment, after the first recess 400 is formed, the gate hard mask material layer 140 is formed, so that after the polysilicon gate layer 200 in the first device area 100H is formed, the gate hard mask layer 300 can conformally cover the bottom and sidewall of the first recess 400.

[0120] Referring to Figure 7 , the part of the hard mask material layer 140 outside the first recess 400 is removed, and the gate hard mask layer 300 conformally covering the bottom and sidewall of the first recess 400 and extending to cover part of the top of the polysilicon gate material layer 130 is formed.

[0121] The gate hard mask layer 300 serves as an etching mask for the subsequent formation of the polysilicon gate layer 200.

[0122] Continuing to refer to Figure 7 , the polysilicon gate material layer 130 exposed by the gate hard mask layer 300 is removed, and the polysilicon gate layer 200 is formed.

[0123] The polysilicon gate material layer is etched with the gate hard mask layer 300 formed as an etching mask, and in the same step, the polysilicon gate layer 200 is formed on the substrate 100 of the first device area 100H and the second device area 100L, which simplifies the process steps and saves the process cost.

[0124] Referring to Figure 8 , after the polysilicon gate layer 200 is formed and before the interlayer dielectric layer 500 is formed, it further includes forming a side wall 250 on the sidewall of the polysilicon gate layer 200, and the side wall 250 also covers the sidewall of the first recess 400.

[0125] The side wall 250 is used to protect the sidewall of the polysilicon gate layer 200, and the side wall 250 also covers the sidewall of the first recess 400, which is used to protect the sidewall of the top gate layer 210 and reduce the probability of generating a recess defect in the top gate layer 210 during the planarization process.

[0126] In this embodiment, the side wall 250 is formed after the formation of the gate hard mask layer 300, so that in the first recess, the side wall 250 covers the sidewall of the gate hard mask layer 300, and the gate hard mask layer 300 and the side wall 250 together serve as a protective side wall, enhancing the protection effect.

[0127] In addition, the formation step of the side wall generally includes: forming a side wall material layer conformally covering the first recess 400, removing the side wall material layer at the bottom of the first recess 400, and retaining the side wall material layer at the sidewall of the first recess 400 as a side wall.

[0128] The side wall 250 can be a single-layer structure or a stacked structure, and the material of the side wall 250 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon oxynitride, boron nitride, and boron carbon nitride. In this embodiment, the side wall 250 is a stacked structure (not shown).

[0129] Specifically, the side wall 251 is an ON (oxide-nitride) structure, that is, the side wall 251 includes a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer.

[0130] The silicon nitride has high hardness, which is beneficial to the protection of the polysilicon gate layer 200.

[0131] Continuing to refer to Figure 8 In this embodiment, the interlayer dielectric layer 500 covers the gate hard mask layer 300 in the first recess 400.

[0132] In this embodiment, in the process of forming the interlayer dielectric layer 500, the gate hard mask layer 300 on the top of the polysilicon gate layer 200 is removed.

[0133] The gate hard mask layer 300 on the top of the polysilicon gate layer 210 is removed, exposing the top of the polysilicon gate layer 200, which prepares for the subsequent removal of the polysilicon gate layer 210 of the second device region 100L.

[0134] Referring to Figure 9 A second recess 410 is formed in the interlayer dielectric layer 500, the second recess 410 penetrates the interlayer dielectric layer 500 on the top of the bottom gate layer 220 and exposes the bottom gate layer 220.

[0135] The second recess 410 is used to provide a spatial position for the subsequent formation of a metal gate layer. The second recess 410 penetrates the interlayer dielectric layer 500 on the top of the bottom gate layer 220 and exposes the bottom gate layer 220, so that the subsequently formed metal gate layer is electrically connected with the bottom gate layer 220.

[0136] In this embodiment, the dry etching process is used to etch the interlayer dielectric layer 500 in the first groove 400 (as shown) to form the second groove 410. Figure 5 The dry etching process has the characteristic of anisotropic etching, so by selecting the dry etching process, it is beneficial to reduce the damage to the interlayer dielectric layer 500 on the sidewall of the second groove 410. At the same time, the dry etching is more directional, which can obtain quite accurate pattern conversion, and is beneficial to improve the sidewall morphology quality and size accuracy of the second groove 410.

[0137] The opening size width d of the second groove 410 cannot be too large or too small. If the opening size width d of the second groove 410 is too large, during the photolithography process of etching to form the second groove 410, due to the alignment offset, part of the top gate layer 210 is exposed and etched together, forming an opening with a smaller size. Therefore, it is difficult to completely fill the opening with a smaller size when forming the metal hard mask layer and the metal gate layer on the top gate layer 210, which affects the performance of the semiconductor structure. If the opening size width d of the second groove 410 is too small, it increases the difficulty of forming the second groove 410, and also increases the difficulty of forming the metal gate layer in the second groove 410, which is difficult to form a metal gate layer with low contact resistance as an external terminal. Therefore, in this embodiment, the opening size width of the second groove 410 is 0.08-0.15 μm. For example, the opening size width of the second groove 410 is 0.11 μm.

[0138] In this embodiment, the step of forming the second groove 410 includes forming a shielding layer (not shown) on the interlayer dielectric layer 500, the shielding layer has a patterned opening, and the opening exposes part of the interlayer dielectric layer 500 in the first groove 400.

[0139] The second mask layer is used as an etching mask for forming the second groove 410, and the opening is used as a mask opening.

[0140] In this embodiment, the material of the shielding layer can be photoresist.

[0141] In this embodiment, the interlayer dielectric layer 500 exposed by the opening is removed until the bottom gate layer 220 is exposed to form the second groove 410.

[0142] The second groove 410 exposing the bottom gate layer 220 provides a space position for subsequent formation of a metal gate layer.

[0143] The second groove 410 exposing the bottom gate layer 220 provides a space position for subsequent formation of a metal gate layer.

[0144] Therefore, in the embodiment, after removing part of the interlayer dielectric layer 500 in the first recess 400, the exposed gate hard mask layer 300 in the first recess 400 is removed.

[0145] The exposed gate hard mask layer 300 in the first recess 400 is removed, so that the second recess 410 exposes the bottom gate layer 220, so that the subsequently formed metal gate layer is electrically connected with the bottom gate layer 220.

[0146] In the embodiment, after forming the second recess 410, the shielding layer is removed to prepare for subsequent processes.

[0147] In combination with reference Figure 10 and Figure 11 In the second recess 410, a metal gate layer 260 electrically connected with the bottom gate layer 220 is formed, the polycrystalline silicon gate layer 200 in the first device region 100H and the metal gate layer 260 together serve as a first gate structure 270, and the metal gate layer 260 serves as an external terminal of the first gate structure 270.

[0148] In the embodiment, the top surface of the first gate structure 270 exposes the polycrystalline silicon gate layer 200 and also exposes the metal gate layer 260, the metal gate layer 260 serves as an external terminal of the first gate structure 270, the contact resistance of the metal gate layer 260 is small, and therefore the first gate structure 270 can be directly electrically connected with an external interconnection structure (for example, a gate plug) through the metal gate layer 260. Compared with a scheme in which a metal silicide is formed on the top surface of the polycrystalline silicon gate layer and the metal silicide serves as an external terminal, the embodiment can omit the process of forming a metal silicide on the polycrystalline silicon gate layer 200 exposed on the top of the first gate structure 270, and accordingly avoid damage to the interlayer dielectric layer 500 on the side of the first gate structure 270 caused by the process of forming the metal silicide, thereby reducing the probability of generating a height difference between the interlayer dielectric layer 500 on the substrate 100 of the first device region 100H and the top gate layer 210 and the interlayer dielectric layer 500 on the substrate 100 of other regions. Meanwhile, the first gate structure 270 includes the metal gate layer 260, which is conducive to reducing the resistance of the first gate structure 270, and the first gate structure 270 also includes the polycrystalline silicon gate layer 200, which makes the first device achieve a target threshold voltage and is conducive to improving the working performance of the semiconductor structure.

[0149] The metal gate layer 260 includes a work function layer (not shown) and a gate electrode layer (not shown) on the work function layer.

[0150] The work function layer is used to adjust the threshold voltage of the formed transistor. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TaN, TiAl, Mo, MoN, AlN, and TiAlC.

[0151] The gate electrode layer is used to lead out the electrical property of the metal gate layer 260. In the embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0152] Specifically, referring to Figure 10 , before the metal gate layer 260 (as shown in Figure 11 ) is formed, the method further includes: removing the polysilicon gate layer 200 of the second device area 100L to form a gate opening 600.

[0153] The gate opening 600 is used to provide a spatial position for the subsequent formation of the metal gate layer 260 in the second device area 100L.

[0154] In the embodiment, the gate opening 600 is formed after the second recess 410 is formed.

[0155] If the gate opening 600 is formed before the second recess 410 is formed, process pollution to the gate opening 600 is easily caused, and therefore, the gate opening 600 is formed after the second recess 410 is formed.

[0156] In the embodiment, the step of forming the gate opening 600 includes: forming a metal hard mask material layer (not shown) conformally covering the bottom and sidewall of the second recess 410, the interlayer dielectric layer 500, and the polysilicon gate layer 200.

[0157] The metal hard mask material layer is used to form a metal hard mask layer subsequently.

[0158] In the embodiment, the metal hard mask material layer is formed by a physical vapor deposition process.

[0159] The physical vapor deposition process has a faster deposition efficiency, and the metal hard mask material layer formed thereby has a lower impurity content and a higher material density. In other embodiments, an atomic layer deposition process can also be used to form the metal hard mask material layer.

[0160] In the embodiment, the material of the metal hard mask material layer includes titanium nitride.

[0161] The titanium nitride has high hardness and high etching selectivity ratio with the polysilicon material, which is beneficial to ensure the etching mask effect of the metal hard mask layer and protect the gate layer 220 exposed at the bottom of the second recess 410 and the interlayer dielectric layer 500 exposed at the sidewall of the second recess 410.

[0162] In the embodiment, the metal hard mask material layer is patterned to form a metal hard mask layer 420, and the metal hard mask layer 420 exposes the polysilicon gate layer 200 at the top of the second device area 100L.

[0163] The metal hard mask layer 420 is used as an etching mask for forming a gate opening 600 in the second device area 100L. In addition, the metal hard mask material layer is patterned by forming a photoresist on the metal hard mask material layer and etching the photoresist as a mask. Therefore, the photoresist in the second recess 410 needs to be removed. When the photoresist is removed, the metal hard mask layer 420 protects the gate layer 220 exposed at the bottom of the second recess 410 and the interlayer dielectric layer 500 exposed at the sidewall of the second recess 410.

[0164] In the embodiment, the polysilicon gate layer 200 exposed by the metal hard mask layer 420 is removed to form a gate opening 600.

[0165] The metal hard mask layer 420 is used as an etching mask to etch the polysilicon gate layer 200 to form a gate opening 600.

[0166] Reference Figure 11 In the process of forming a metal gate layer 260 in the second recess 410, which is electrically connected to the bottom gate layer 220, the metal hard mask layer 420 higher than the top of the interlayer dielectric layer 500 is removed.

[0167] Since the metal mask layer 420 is a metal material, it has good electrical conductivity. Therefore, by removing the metal hard mask layer 420 higher than the top of the interlayer dielectric layer 500 and retaining the metal hard mask layer 420 in the second recess 410, the metal gate layer 260 in the first device area 100H can be electrically connected to the bottom gate layer 220.

[0168] In the embodiment, in the process of forming a metal gate layer 260 in the second recess 410, which is electrically connected to the bottom gate layer 220, the metal gate layer 260 is also formed in the gate opening 600 (as shown in Figure 10 The metal gate layer 260 is used as a second gate structure 280.

[0169] The channel length of the second device region 100L is small, and the metal gate layer 260 is used as a device gate structure of the second device region 100L, that is, the second gate structure 280 is a metal gate structure, so as to improve the short channel effect of the second device.

[0170] In summary, in the first device region 100H, the polysilicon gate layer 200, the metal gate layer 260, the high-k gate dielectric layer 230, the metal barrier layer 240 and the metal hard mask layer 420 together form the first gate structure 270; in the second device region 100L, the metal gate layer 260, the high-k gate dielectric layer 230 and the metal barrier layer 240 together form the second gate structure 280.

[0171] It should be noted that, compared with the prior art, the process of forming metal silicide is reduced, the process cost is saved, and the process efficiency is improved in the embodiment.

[0172] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above embodiments. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a first device region for forming a first device; A polysilicon gate layer is located on the substrate of the first device region. The polysilicon gate layer includes a bottom gate layer and a plurality of top gate layers protruding from the bottom gate layer. The bottom gate layer and the adjacent top gate layers form a first groove. An interlayer dielectric layer is located on a substrate on the side of the polysilicon gate layer and covers the sidewall of the polysilicon gate layer. The interlayer dielectric layer also fills the first groove. The second groove penetrates the interlayer dielectric layer in the first groove and exposes the bottom gate layer; A metal gate layer is located in the second groove and electrically connected to the bottom gate layer. The polysilicon gate layer and the metal gate layer in the first device region together serve as the first gate structure, and the metal gate layer is used as an external terminal of the first gate structure. The top surface of the first gate structure exposes the polysilicon gate layer and also exposes the metal gate layer.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a sidewall located on the sidewall of the polysilicon gate layer, the sidewall also covering the sidewall of the first groove.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, The semiconductor structure further includes: a gate hard mask layer located on the sidewall of the first groove and the bottom of the first groove on the side of the metal gate layer; The interlayer dielectric layer covers the gate hard mask layer.

4. The semiconductor structure as described in claim 1, characterized in that, The substrate further includes: a second device region for forming a second device, wherein the channel length of the second device is less than the channel length of the first device; The metal gate layer is also located in an interlayer dielectric layer on the substrate of the second device region, serving as a second gate structure, and the interlayer dielectric layer covers the sidewall of the metal gate layer of the second device region.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a metal hard mask layer, conformally covering the bottom and sidewalls of the second groove; The metal gate layer in the first device region covers the metal mask layer.

6. The semiconductor structure as described in claim 4, characterized in that, The semiconductor structure further includes: a high-k gate dielectric layer and a metal barrier layer located on the high-k gate dielectric layer, between the polysilicon gate layer and the substrate in the first device region, and between the metal gate layer and the substrate in the second device region.

7. The semiconductor structure as described in claim 1, characterized in that, The depth of the first groove is 1 / 2 to 3 / 4 of the total thickness of the polysilicon gate layer.

8. The semiconductor structure as described in claim 1, characterized in that, The opening width of the second groove is 0.08 μm to 0.15 μm.

9. The semiconductor structure as described in claim 5, characterized in that, The material of the metal hard mask layer includes titanium nitride.

10. The semiconductor structure as claimed in claim 1, characterized in that, The material of the interlayer dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

11. The semiconductor structure as claimed in claim 6, characterized in that, The material of the high-k gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

12. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first device region for forming a first device, a polysilicon gate layer is formed on the substrate, the polysilicon gate layer located in the first device region including a bottom gate layer and a plurality of top gate layers protruding on the bottom gate layer, and adjacent top gate layers and bottom gate layers forming a first groove; An interlayer dielectric layer is formed on a substrate on the side of the polysilicon gate layer, the interlayer dielectric layer covers the sidewall of the polysilicon gate layer, and the interlayer dielectric layer also fills the first groove; A second groove is formed in the interlayer dielectric layer, the second groove penetrating the interlayer dielectric layer above the bottom gate layer and exposing the bottom gate layer; A metal gate layer electrically connected to the bottom gate layer is formed in the second groove. The polysilicon gate layer and the metal gate layer in the first device region together serve as the first gate structure, and the metal gate layer is used as an external terminal of the first gate structure. The top surface of the first gate structure exposes the polysilicon gate layer and also exposes the metal gate layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the polysilicon gate layer and before forming the interlayer dielectric layer, the method further includes: forming a sidewall on the sidewall of the polysilicon gate layer, the sidewall also covering the sidewall of the first groove.

14. The method for forming a semiconductor structure as described in claim 12 or 13, characterized in that, In the step of providing the substrate, a gate hard mask layer that conformally covers the bottom and sidewalls of the first groove is also formed in the first groove; In the step of forming the interlayer dielectric layer, the interlayer dielectric layer covers the gate hard mask layer; The step of forming the second groove further includes: removing a portion of the interlayer dielectric layer in the first groove, and then removing the exposed gate hard mask layer in the first groove.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The steps of forming the polysilicon gate layer and the gate hard mask layer include: forming a polysilicon gate material layer on the substrate; A first groove is formed in the polysilicon gate material layer of the first device region, the first groove being located in a portion of the thickness of the polysilicon gate material layer; A gate hard mask material layer is formed on the polysilicon gate material layer, the hard mask material layer conformally covering the bottom and sidewalls of the first groove, as well as the top of the polysilicon gate material layer; Remove a portion of the gate hard mask material layer outside the first groove to form a gate hard mask layer that conformally covers the bottom and sidewalls of the first groove and extends to cover a portion of the top of the polysilicon gate material layer; Remove the polysilicon gate material layer exposed by the gate hard mask layer to form a polysilicon gate layer; During the formation of the interlayer dielectric layer, the gate hard mask layer located on top of the polysilicon gate layer is removed.

16. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of forming the second groove includes: forming a shielding layer on the interlayer dielectric layer, wherein a patterned opening is formed in the shielding layer, the opening exposing a portion of the interlayer dielectric layer in the first groove; Remove the interlayer dielectric layer exposed by the opening until the bottom gate layer is exposed, forming a second groove; Remove the masking layer.

17. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing a substrate, the substrate further includes a second device region for forming a second device, wherein the channel length of the second device is less than the channel length of the first device; Before forming the metal gate layer, the method further includes: removing the polysilicon gate layer of the second device region to form a gate opening; During the process of forming a metal gate layer electrically connected to the bottom gate layer in the second groove, the metal gate layer is also formed in the gate opening to serve as a second gate structure.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, After the second groove is formed, the gate opening is formed.

19. The method for forming a semiconductor structure as described in claim 17, characterized in that, The step of forming the gate opening includes: forming a metal hard mask material layer that conformally covers the bottom and sidewalls of the second groove, the interlayer dielectric layer, and the polysilicon gate layer; The metal hard mask material layer is patterned to form a metal hard mask layer, which exposes the top of the polysilicon gate layer of the second device region; Remove the metal hard mask layer to expose the polysilicon gate layer, forming a gate opening; During the process of forming a metal gate layer electrically connected to the bottom gate layer in the second groove, the metal hard mask layer above the top of the interlayer dielectric layer is removed.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, A metal hard mask material layer is formed using a physical vapor deposition process.

21. The method for forming a semiconductor structure as described in claim 17, characterized in that, In the step of providing the substrate, a high-k gate dielectric layer and a metal barrier layer located on the high-k gate dielectric layer are further formed between the polysilicon gate layer and the substrate.

22. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of forming the second groove includes: etching the interlayer dielectric layer in the first groove using a dry etching process.

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