Power switch circuit and corresponding operation method

Abstract

Embodiments of the present disclosure generally relate to power switch circuits and corresponding operation methods. A circuit includes a high-side switch and a low-side switch. A first inverter includes a first discharge current path and a second discharge current path that can be activated to absorb a first discharge current and a second discharge current from a control terminal of the high-side switch, respectively. A second inverter includes a first charging current path and a second charging current path that can be activated to provide a first charging current and a second charging current to a control terminal of the low-side switch. The high-side sensing current path includes an intermediate high-side control node, and the low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enabled in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charging current path is selectively enabled in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102021000009773, filed on April 19, 2021, which is incorporated herein by reference. Technical Field

[0003] This specification relates to power switching circuits.

[0004] One or more embodiments may be applied to amplifiers operating in a pulse width modulation (PWM) mode, such as for a half-bridge power switching stage used in a class D amplifier. Background Art

[0005] Monitoring and controlling the operating region of a power transistor (eg, a power metal oxide semiconductor MOS transistor) driving an output load is a desirable feature of a switching amplifier (eg, such as a class D switching amplifier) ​​including a half-bridge arrangement.

[0006] Typically, logic circuits and analog circuits can be used to counteract cross conduction between two power transistors in the same half-bridge circuit. An example of a circuit configured to counteract cross conduction in a half-bridge power device is known from document US 6,288,605 B1 assigned to the same applicant of the present application. As disclosed in document US 6,288,605 B1, an output power switch stage is provided with a sensor, the output power switch stage includes a power switch device for a power line and a complementary power switch device for a ground rail driven inversely by a pulse width modulation (PWM) drive signal, the sensor detects the basic off state of each of the two power switch devices and generates a pair of logic signals. The combinational logic circuit combines the drive signal of the half bridge with the pair of logic signals, and generates a pair of drive signals with opposite phases for the corresponding power switch devices. When verifying that the off state is basically reached by a device complementary to the device commanded to be turned on, the switching of any one of the two power devices to the on state is enabled. Specifically, each of a pair of complementary power switching devices constituting the high-side driver stage and the low-side driver stage is provided with a circuit capable of monitoring the on or off state, generating corresponding logic signals sens-H and sens-L, and indicating the state of the switching device. This pair of logic signals is combined with the digital drive input signal INPUT by a combinational logic circuit, which in the example is implemented by an AND gate that switches the low-side driver device to the ground potential and an OR gate that switches the high-side driver device to the power line. This ensures that one or the other power switching device is switched from the off state to the on state only when this is achieved by a positive verification of the substantially achieved off state of the switching device complementary to the switching device that is commanded to be turned on.

[0007] According to the example disclosed in document US 6,288,605 B1, the state (on or off) of the power devices constituting the output stage of the half-bridge can be detected by a corresponding detection circuit. Each power device has a related transistor of the same kind, but has a fractional size, for example, 1 / 100 of the size of the corresponding power device. Each detection transistor has an associated bias load current generator (Iref-H and Iref-L). The output node of the detection stage thus constituted is coupled to the input of the logic inverter. The detection transistor is driven in parallel with the corresponding power transistor (for example, by the same drive signal), and when the current flowing in the detection transistor exceeds the current established by the corresponding bias current generator, the corresponding inverter switches to generate an output logic signal (sens-H and sens-L, respectively). A certain current level is established, which can be defined by determining the size of the corresponding current generator, suitable for considering the actual closing of the corresponding power switch device, and a pair of logic signals (sens-H and sens-L) are obtained, which reliably confirms the basic realization of the cut-off phase of one or the other of the two power switch devices of the switching output stage. The two logic signals sens-H and sens-L combined into the driving digital signal INPUT ensure that the turn-on states of the two power devices of the stage do not overlap.

[0008] In addition, a circuit that regulates or controls the speed at which the (e.g., instantaneous) forward-conducting power transistor is turned on can be used to avoid excessive current changes per unit time (di / dt) that may lead to operational and reliability problems of the half-bridge arrangement. Indeed, an excessive slope of the current flowing through the power transistor of the half-bridge may generate excessive voltage overshoots due to parasitic inductances in the circuit (e.g., inductances caused by the bonding of the integrated circuit within the package). In a half-bridge arrangement comprising a forward-conducting power transistor driving an external load and a reverse-conducting complementary (e.g., opposite) power transistor, the commutation of the turn-on of the power transistor opposite to the reverse-conducting transistor may be critical, as long as the turned-on power transistor discharges the intrinsic recirculation diode of the power transistor when reverse-conducting.

[0009] Therefore, there is a need in the art to provide a power switching circuit that includes improved control of the turn-on phase of a power transistor included therein. Summary of the invention

[0010] It is an object of one or more embodiments to help provide such improved power switching circuits.

[0011] One or more embodiments may be directed to a corresponding method of operating a power switching circuit.

[0012] In one or more embodiments, a circuit may include a high-side switch coupled between a power supply voltage rail and an output node and a low-side switch coupled between the output node and a reference voltage rail. The circuit may include a first inverter arrangement configured to receive a high-side control signal and generate a high-side gate control signal for the high-side switch, and a second inverter arrangement configured to receive a low-side control signal and generate a low-side gate control signal for the low-side switch. The first inverter arrangement may include a first discharge current path between a control terminal of the high-side switch and a corresponding reference voltage rail, the first discharge current path being activatable to absorb a first discharge current from the control terminal of the high-side switch, and the first inverter arrangement may also include a second discharge current path between the control terminal of the high-side switch and the corresponding reference voltage rail, the second discharge current path being activatable to absorb a second discharge current from the control terminal of the high-side switch. The second inverter arrangement may include a first charging current path between the control terminal of the low side switch and the corresponding supply voltage rail, the first charging current path being activatable to provide a first charging current to the control terminal of the low side switch, and the second inverter arrangement may also include a second charging current path between the control terminal of the low side switch and the corresponding supply voltage rail, the second charging current path being activatable to provide a second charging current to the control terminal of the low side switch.

[0013] The circuit may include a high-side sensing current path disposed between a power supply voltage rail and a corresponding reference voltage rail. The high-side sensing current path may include a high-side sensing transistor having a current path coupled between the power supply voltage rail and an intermediate high-side control node and a gate terminal coupled to a control terminal of the high-side switch, and a first high-side current source coupled between the intermediate high-side control node and the corresponding reference voltage rail to sink a first high-side reference current from the intermediate high-side control node.

[0014] The circuit may include a low-side sensing current path disposed between a reference voltage rail and a corresponding power supply voltage rail. The low-side sensing current path may include a low-side sensing transistor having a current path coupled between the reference voltage rail and an intermediate low-side control node and a gate terminal coupled to a control terminal of a low-side switch and a first low-side current source coupled between the intermediate low-side control node and the corresponding power supply voltage rail to provide a first low-side reference current to the intermediate low-side control node.

[0015] The second discharge current path may be selectively enableable in response to the high side detection signal at the intermediate high side control node having a high logic value, and the second charge current path may be selectively enableable in response to the low side detection signal at the intermediate low side control node having a low logic value.

[0016] Thus, one or more embodiments may facilitate controlling a turn-on phase of a power transistor included in a half-bridge arrangement of a power switching circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0018] Figure 1 is an exemplary circuit diagram of a power switching circuit including an output half-bridge arrangement and associated control circuitry;

[0019] Figure 2 is an exemplary circuit diagram of a power switching circuit including an output half-bridge arrangement and associated control circuitry according to one or more embodiments of the present specification; and

[0020] Figure 3 is another exemplary circuit diagram of a power switching circuit including an output half-bridge arrangement and associated control circuitry according to one or more embodiments of the present description. DETAILED DESCRIPTION

[0021] In the following description, one or more specific details are described to provide a deeper understanding of the examples of embodiments of the present specification. The embodiments may be obtained without one or more specific details, or may be obtained using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not described or illustrated in detail so that certain aspects of the embodiments will not be obscured.

[0022] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more places in this specification do not necessarily refer to the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0023] The headings / labels used herein are provided for convenience only and do not define the scope of protection or the scope of the embodiments.

[0024] In all drawings attached herein, unless the context indicates otherwise, like components or elements are denoted by like reference numerals / numbers, and the corresponding description will not be repeated for the sake of brevity.

[0025] One or more embodiments may be directed to a power switch circuit that includes improved control of a turn-on phase of a power transistor. As an introduction to a detailed description of exemplary embodiments, reference may first be made to Figure 1 , Figure 1 is an exemplary circuit diagram of the power switching circuit 10 and associated control circuitry.

[0026] The switch circuit 10 includes an output half-bridge arrangement including a high-side switch HS (e.g., a p-channel MOS power transistor) coupled between a supply voltage rail 102 configured to provide a supply voltage VCC (e.g., in the range of 12 V to 18 V) and an output node 104, and a low-side switch LS (e.g., an n-channel MOS power transistor) coupled between the output node 104 and a reference voltage rail 106 configured to provide a reference voltage GND (e.g., 0 V). Complementary commutation of the high-side switch HS and the low-side switch LS results in the generation of a PWM output signal OUTPUT at the output node 104.

[0027] like Figure 1 As shown, the switch circuit 10 is configured to receive a high-side input control signal IN-H and a low-side input control signal IN-L to control the commutation of the high-side switch and the low-side switch, respectively. The high-side input control signal IN-H and the low-side input control signal IN-L may not be directly applied to the control terminal of the high-side switch HS and the control terminal of the low-side switch LS, but may be used to control a corresponding "soft-on" circuit, which generates a (gate) control signal IN-H applied to the control terminal of the high-side switch HS and the control terminal of the low-side switch LS, respectively. gate 、IN-L gate .

[0028] like Figure 1 As shown, the high-side soft-start circuit may include a first inverter circuit 108H and a second inverter circuit, wherein the first inverter circuit 108H is configured to receive the high-side input control signal IN-H and generate an inverted high-side input control signal The second inverter circuit is configured to receive an inverted high-side input control signal and generates a high-side (gate) control signal IN-H having substantially the same polarity as the high-side input control signal IN-H gate In particular, the second inverter circuit may include a single "upper" branch and a pair of "lower" branches, for example, it may include:

[0029] A transistor Q0H (e.g., a p-channel MOS transistor) having a current path coupled between the supply voltage rail 102 and the control terminal of the high-side switch HS and configured to receive an inverted high-side input control signal from the inverter 108H The (gate) control terminal;

[0030] a transistor Q1H (e.g., an n-channel MOS transistor) having a current path coupled between a control terminal of the high-side switch HS and a corresponding reference voltage rail 110H configured to provide a reference voltage GndH (which may be the same as the reference voltage rail 106), and configured to receive an inverted high-side input control signal GndH from the inverter 108H; The (gate) control terminal;

[0031] - a transistor Q2H (e.g., an n-channel MOS transistor) having a current path coupled between the control terminal of the high-side switch HS and the reference voltage rail 110H and configured to receive an inverted high-side input control signal from the inverter 108H A (gate) control terminal; and

[0032] - a control transistor Q3H (eg, an n-channel MOS transistor) having a current path coupled in series to transistor Q2H and a (gate) control terminal configured to receive a high-side enable control signal OutSens-H.

[0033] like Figure 1 As shown, the high-side start-up control signal OutSens-H can be generated by a high-side high voltage comparator circuit 112H, which is configured to compare the output signal OUTPUT with a threshold voltage VthH (e.g., a threshold between GND and VCC). For example, the high-side comparator circuit 112H can receive the output signal OUTPUT at a corresponding non-inverting input and receive the threshold voltage VthH at a corresponding inverting input.

[0034] Similarly, the low-side soft-start circuit may include a first inverter circuit 108L and a second inverter circuit, wherein the first inverter circuit 108L is configured to receive the low-side input control signal IN-L and generate an inverted low-side input control signal IN-L. The second inverter circuit is configured to receive an inverted low-side input control signal and generates a low-side (gate) control signal IN-L having substantially the same polarity as the low-side input control signal IN-L gate In particular, the second inverter circuit may include a single "lower" branch and a pair of "upper" branches, for example, it may include:

[0035] A transistor Q0L (e.g., an n-channel MOS transistor) having a current path coupled between the reference voltage rail 106 and the control terminal of the low-side switch LS and configured to receive an inverted low-side input control signal Q0L from the inverter 108L (gate

[0036] Pole) control terminal;

[0037] a transistor Q1L (e.g., a p-channel MOS transistor) having a current path coupled between a control terminal of the low-side switch LS and a corresponding supply voltage rail 110L configured to provide a supply voltage VccL (which may be the same as the supply voltage rail 102), and configured to receive an inverted low-side input control signal VccL from the inverter 108L;

[0038] The (gate) control terminal;

[0039] a transistor Q2L (e.g., a p-channel MOS transistor) having a current path coupled between the control terminal of the low-side switch LS and the supply voltage rail 110L and configured to receive an inverted low-side input control signal Q2L from the inverter 108L A (gate) control terminal; and

[0040] - a control transistor Q3L (eg, a p-channel MOS transistor) having a current path coupled in series to transistor Q2L and a (gate) control terminal configured to receive a low-side enable control signal OutSens-L.

[0041] like Figure 1 As shown, the low-side start-up control signal OutSens-L can be generated by a low-side high voltage comparator circuit 112L, which is configured to compare the output signal OUTPUT with a threshold voltage VthL (e.g., a threshold between GND and VCC). For example, the low-side comparator circuit 112L can receive the output signal OUTPUT at a corresponding non-inverting input and receive the threshold voltage VthL at a corresponding inverting input.

[0042] therefore, Figure 1 The illustrated switching circuit 10 facilitates controlling current flowing into the high-side switch HS and the low-side switch LS during respective turn-on phases. Figure 1 The control circuit shown allows switching on the power transistors HS, LS in forward conduction by means of an intermediate control stage which controls the charging current of the gate terminals of the power transistors HS, LS, thereby controlling the slope of the corresponding (drain) current.

[0043] For example, referring to the high-side control circuit, and referring to the driving situation in which the high-side transistor HS is directly turned on and the low-side transistor LS is reversely turned on, the transistors Q1H and Q2H operate as current generators to generate corresponding currents i1H and i2H to turn on the power transistor HS (e.g., by discharging the gate terminal of the transistor HS by sinking currents i1H and i2H from the gate terminal of the power transistor HS). The transistors Q1H and Q2H are activated according to the high-side input control signal IN-H (as long as Basically an inverted copy of IN-H). When the high-side power transistor HS is turned on in forward conduction (IN-H switches from '1' to '0'), the output signal OUTPUT is held at the ground level GND by the low-side power transistor LS, which is reverse-conducted via the corresponding recycling diode. Therefore, the high-side turn-on control signal OutSens-H is at a low logic level, which causes the control transistor Q3H to be turned off. In this case, only the transistor Q1H can sink the current i1H from the (gate) control terminal of the high-side power transistor HS, which causes the high-side power transistor HS to turn on slowly and to discharge the recycling diode of the low-side power transistor LS likewise slowly (if the discharge is too fast, a high current spike may be generated). After the recycling diode of the low-side power transistor LS has been (slowly) discharged, the output signal OUTPUT exceeds the threshold voltage VthH and the high-side turn-on control signal OutSens-H switches to a high logic level, thereby switching the control transistor Q3H to the on state. In turn, both transistors Q1H and Q2H may sink current (i1H and i2H, respectively) from the (gate) control terminal of the high-side power transistor HS, which causes the high-side power transistor HS to turn on faster. Alternatively, current i1H may be lower than current i2H.

[0044] Similarly, referring to the low-side control circuit, and referring to the driving situation in which the low-side transistor LS is directly turned on and the high-side transistor HS is reversely turned on, the transistors Q1L and Q2L operate as current generators to generate corresponding currents i1L and i2L to turn on the power transistor LS (e.g., by providing currents i1L and i2L to the gate terminal of the power transistor LS to charge the gate terminal of the transistor LS). The transistors Q1L and Q2L are activated according to the low-side input control signal IN-L (as long as Basically, it is an inverted copy of IN-L). When the low-side power transistor LS is turned on in forward conduction (IN-L switches from '0' to '1'), the output signal OUTPUT is maintained at the power supply level VCC by the high-side power transistor HS, which is reverse-conducted through the corresponding recycling diode. Therefore, the low-side start control signal OutSens-L is at a high logic level, which causes the control transistor Q3L to be turned off. In this case, only the transistor Q1L can provide the current i1L to the (gate) control terminal of the low-side power transistor LS, which causes the low-side power transistor LS to turn on slowly and to discharge the recycling diode of the high-side power transistor HS likewise slowly (if the discharge is too fast, a high current spike may be generated). After the (slow) discharge of the recycling diode of the high-side power transistor HS, the output signal OUTPUT drops below the threshold voltage VthL and the low-side start control signal OutSens-L switches to a low logic level, thereby switching the control transistor Q3L to the on state. In turn, both transistors Q1L and Q2L may provide currents (i1L and i2L respectively) to the (gate) control terminal of the low-side power transistor LS, which causes the low-side power transistor LS to turn on faster. Alternatively, current i1L may be lower than current i2L.

[0045] therefore, Figure 1 The illustrated switch circuit 10 facilitates controlling the current flowing into the power transistors HS, LS during respective turn-on phases at the expense of implementing a pair of high voltage comparators 112H, 112L. However, such comparators may occupy a large silicon area and / or consume an associated amount of power, so an alternative solution may be required.

[0046] For example, Figure 2 is an exemplary circuit diagram of a switch circuit 10' according to one or more embodiments, wherein control transistors Q3H and Q3L are configured to receive respective turn-on control signals generated without resorting to the use of a voltage comparator. and

[0047] In particular, the switch circuit 10' may include a reference Figure 1 The same components HS, 108H, Q0H, Q1H, Q2H, Q3H, LS, 108L, Q0L, Q1L, Q2L, Q3L described and operate in a similar manner. For the sake of brevity, the corresponding descriptions are not repeated here.

[0048] In addition, the switch circuit 10' may include a high-side sensing circuit including a current line arranged between the power supply voltage rail 102 and the reference voltage rail 110H, the current line including:

[0049] - a sense transistor QsH (e.g., a p-channel MOS transistor) having a current path coupled between the supply voltage rail 102 and the intermediate node 203H, and coupled to the (gate) control terminal of the high-side power transistor HS to receive the same high-side (gate)

[0050] Control signal IN-H gate The (gate) control terminal, and

[0051] A first current generator 202H coupled between the intermediate node 203H and the reference voltage rail 110H to sink a current IcrossH from the intermediate node 203H.

[0052] like Figure 2 As shown, the intermediate node 203H can be coupled to the (gate) control terminal of the control transistor Q3H. It can be generated at a node 203H between the detection transistor QsH and the first current generator 202H.

[0053] The sense transistor QsH may, for example, be of the same kind as the high-side power transistor HS, but may have a fractional size, for example between 1 / 100 and 1 / 1000 of the size of the high-side power transistor HS.

[0054] Optionally, the high-side sensing circuit may further include:

[0055] a second current generator 204H coupled between the node 203H and the reference voltage rail 110H to sink a current IsH from the node 203H,

[0056] - an inverter circuit 206H coupled to the node 203H to generate an inverted high-side enable control signal Sens-H, and

[0057] a current regulating transistor Q4H (e.g., an n-channel MOS transistor) having a current path coupled in series to the second current generator 204H and coupled to the output of the inverter circuit 206H to receive the inverted high-side enable control signal Sens-H;

[0058] Control terminals.

[0059] In addition, the switch circuit 10' may include a low-side sensing circuit including a current line arranged between the reference voltage rail 106 and the power supply voltage rail 110L, the current line including:

[0060] - a sense transistor QsL (e.g., an n-channel MOS transistor) having a current path coupled between the reference voltage rail 106 and the intermediate node 203L, and coupled to the (gate) control terminal of the low-side power transistor LS to receive the same low-side (gate)

[0061] Control signal IN-L gate The (gate) control terminal, and

[0062] A first current generator 202L coupled between the intermediate node 203L and the supply voltage rail 110L to provide a current IcrossL to the intermediate node 203L.

[0063] like Figure 2 As shown, the intermediate node 203L can be coupled to the (gate) control terminal of the control transistor Q3L. It can be generated at a node 203L between the detection transistor QsL and the first current generator 202L.

[0064] The sense transistor QsL may, for example, be of the same kind as the low-side power transistor LS, but may have a fractional size, for example between 1 / 100 and 1 / 1000 of the size of the low-side power transistor LS.

[0065] Optionally, the low-side sensing circuit may further include:

[0066] a second current generator 204L coupled between the node 203L and the supply voltage rail 110L to provide a current IsL to the node 203L,

[0067] - an inverter circuit 206L coupled to the node 203L to generate an inverted low-side start control signal Sens-L, and

[0068] a current regulating transistor Q4L (e.g., a p-channel MOS transistor) having a current path coupled in series to the second current generator 204L and coupled to the output of the inverter circuit 206L to receive the inverted low-side enable control signal Sens-L;

[0069] Control terminals.

[0070] Discussed below Figure 2 The operation of the high-side sensing and control circuit system shown. When the low-side power transistor LS is turned on (IN-L = '1', IN-L gate ='1'), the detection transistor QsL is also turned on, resulting in the low-side turn-on control signal With low logic value And therefore the inverted low-side start control signal Sens-L has a high logic value (Sens-L='1'). In the high-side part, the high-side input control signal IN-H has a high logic value (IN-H='1') causing the high-side power transistor HS and the detection transistor QsH to be turned off, thereby causing the high-side start control signal With low logic value And thus the inverted high-side start control signal Sens-H has a high logic value (Sens-H='1'). Since the high-side start control signal Sens-H has a high logic value, the second current generator 204H is enabled to sink the current IsH from the node 203H and the total current IsoftH=IsH+IcrossH is sunk from the node 203H, which results in the high-side power transistor HS being turned on before it is detected as "on" (i.e., before Before switching to a high logic value and Sens-H switching to a low logic value), the upper gate-source voltage threshold (e.g., referred to as Vgs.softH) of the power transistor HS is exceeded. When the high-side power transistor HS switches to a low logic value), the high-side power transistor HS starts to turn on, thereby increasing its gate-source voltage Vgs by the current i1H absorbed by the transistor Q1H. Due to the (slow) discharge of the gate terminal of the high-side power transistor HS, the sense transistor QsH starts to turn on. When the current flowing through the sense transistor QsH exceeds the current IsoftH=IsH+IcrossH absorbed by the current generators 202H and 204H from the node 203H, =Sens-H = '0' and Sens-H = '0'. Thus, current regulating transistor Q4H is turned off and current generator 204H is disabled. Since only current IcrossH is sunk from node 203H in this case, the gate-source voltage threshold of power transistor HS to be exceeded before high-side power transistor HS is detected as 'on' is reduced to a lower value (e.g., referred to as Vgs.crossH) to provide hysteresis. At the same time, Sens-H = '0' and It also causes the control transistor Q3H to become conductive, thereby facilitating a controlled turn-on phase of the high-side power transistor HS and a faster discharge of the gate terminal of the high-side power transistor after a “soft” turn-on of the high-side power transistor.

[0071] Discussed below Figure 2 The operation of the low-side sensing and control circuit shown in the figure. When the high-side power tube HS is turned on (IN-H = '0', IN-H gate ='0'), the detection transistor QsH is also turned on, resulting in the high-side turn-on control signal With high logic value And therefore the inverted high-side start control signal Sens-H has a low logic value (Sens-H='0'). In the low-side part, the low-side input control signal IN-L has a low logic value (IN-L='0') causing the low-side power transistor LS and the detection transistor QsL to be turned off, thereby causing the low-side start control signal With high logic value And thus the inverted low-side start control signal Sens-L has a low logic value (Sens-L='0'). Since the low-side start control signal Sens-L has a low logic value, the second current generator 204L is enabled to provide the current IsL to the node 203L and the total current IsoftL=IsL+IcrossL is provided to the node 203L, which results in the low-side power transistor LS being detected as "on" before (i.e., before Switches to a low logic value and Sens-L switches to a high logic value), the higher gate-source voltage threshold (e.g., referred to as Vgs.softL) of the power transistor LS is exceeded. When the switching stage commutates (e.g., when IN-L switches to a high logic value), the low-side power transistor LS starts to turn on, thereby increasing its gate-source voltage Vgs by the current i1L provided by the transistor Q1L. Due to the (slow) charging of the gate terminal of the low-side power transistor LS, the sense transistor QsL starts to turn on. When the current flowing through the sense transistor QsL exceeds the current IsoftL=IsL+IcrossL provided to the node 203L by the current generators 202L and 204L, ='1' and Sens-L = '1'. Thus, current regulating transistor Q4L is turned off and current generator 204L is disabled. Since only current IcrossL is provided to node 203L in this case, the gate-source voltage threshold of power transistor LS to be exceeded before low-side power transistor LS is detected as "on" is reduced to a lower value (e.g., referred to as Vgs.crossL) to provide hysteresis. At the same time, Sens-L = '1' and It also causes the control transistor Q3L to become conductive, thereby facilitating a controlled turn-on phase of the low-side power transistor LS and a faster charging of the gate terminal of the low-side power transistor after a “soft” turn-on of the low-side power transistor.

[0072] exist Figure 3 In one or more of the illustrated embodiments, the switch circuit 10 ′ may further include circuitry configured to counteract cross conduction between the high-side power transistor HS and the low-side power transistor LS.

[0073] For example, Figure 3As shown, the switch circuit 10' may include an input node 304, an "OR" logic gate 302H, and an "AND" logic gate 302L. The input node 304 is configured to receive a driving digital signal INPUT (e.g., a PWM signal). The "OR" logic gate 302H is configured to apply an "OR" process to the driving digital signal INPUT and the inverted low-side turn-on control signal Sens-L to generate a high-side input control signal IN-H to be fed to an inverter 108H. The "AND" logic gate 302L is configured to apply an "AND" process to the driving digital signal INPUT and the inverted high-side turn-on control signal Sens-H to generate a low-side input control signal IN-L to be fed to an inverter 108L.

[0074] In Figure 3 In the circuit shown, when the low-side power transistor LS is turned on (e.g., INPUT = '1'), the anti-cross-conduction circuit provides IN-L = '1' and Sens-L = '1'. The same circuit turns off the high-side power transistor, so that IN-H = '1' and thus Sens-H = '1'. When the driving digital signal INPUT switches to a low logic value (e.g., INPUT = '0'), the high-side power transistor HS remains off because Sens-L remains at a high logic value. On the low side, the low logic value of the low-side input control signal IN-L causes the gate of the low-side power transistor LS to discharge gradually and causes the detection transistor QsL to turn off until Sens-L switches to a low logic value because the current flowing through the detection transistor QsL is lower than the reference current IcrossL. The low logic value of Sens-L causes a change in the hysteresis Vgs threshold as long as the total current IsoftL = IsL + IcrossL is supplied to node 203L. Since Sens-L switches to a low logic value, the low-side power transistor LS is considered to be absolutely off (Vgs < Vgs.crossL), so the high-side power transistor HS can be turned on when IN-H = '0'. Since Sens-H = '1' at this time, the detection transistor QsH must provide a large current equal to IsoftH = IsH + IcrossH (i.e., to pass through a higher threshold) to make the high-side current regulation signal Sens-H become a low logic value. This same transition changes the hysteresis threshold on the high side to a lower threshold, corresponding to (only) the current IcrossH. At the same time, since Sens-H takes on a low logic value, the gate terminal of the high-side power transistor HS discharges at a higher rate as long as the transistor Q2H is enabled to absorb the current i2H from it.

[0075] During the relative transition ('0' -> '1') of the driving digital signal INPUT, complementary operation occurs.

[0076] In one or more embodiments, the two values ​​of the Vgs threshold (referred to as Vgs.cross and Vgs.soft) can be selected in accordance with system specifications, such as the type of components used, maximum load current, maximum PWM output voltage, and the same temperature. This is facilitated if the power transistors (HS, LS) and corresponding sensing circuitry (sense transistors QsH, QsL) are matched as closely as possible, located close together, and are subject to the same temperature gradient.

[0077] In one or more embodiments, the lower threshold Vgs.cross can be set to a value close to the threshold voltage of the power transistors HS, LS (e.g., approximately 1V or less) so that the relative power transistor is turned on only when the current power transistor is definitely turned off to solve the cross-conduction problem.

[0078] In one or more embodiments, the upper threshold Vgs.soft can be set to a gate-source voltage value in a plateau region close to the end of "soft turn-on" after the recirculation diode in the opposing power transistor is fully discharged. If the threshold Vgs.soft is set too high, the system efficiency may be reduced because the turn-on phase of the power transistor may take longer.

[0079] Thus, one or more embodiments may be applied to systems including class-D half-bridge amplifiers involving demanding (eg, aggressive) drive and improved overall efficiency.

[0080] One or more embodiments may therefore provide one or more of the following advantages:

[0081] - easy to implement circuit for adjusting the speed of the turn-on current of the power transistor, and

[0082] Optionally used to combat cross conduction;

[0083] - The speed of the turn-on current of the power transistor can be adjusted without following the trend of the output signal OUTPUT, which may be affected by the external load.

[0084] As described herein, a circuit (eg, 10') may include:

[0085] - coupled between a power supply voltage rail (e.g., 102) and an output node (e.g., 104)

[0086] A high-side switch (e.g., HS) between

[0087] A low-side switch (eg, 106) coupled between the output node and a reference voltage rail (eg, 106)

[0088] e.g., LS);

[0089] - a first inverter arrangement configured to receive a high-side control signal (e.g. ) and generates a high-side gate control signal for the high-side switch (e.g., IN-H gate );as well as

[0090] - a second inverter arrangement configured to receive a low-side control signal (e.g. ) and generates a low-side gate control signal for the low-side switch (e.g., IN-L gate ). As described herein, the first inverter arrangement may include:

[0091] a charging current path (e.g., Q0H) between the supply voltage rail and the control terminal of the high-side switch, the charging current path being activatable to provide a charging current to the control terminal of the high-side switch,

[0092] a first discharge current path (e.g., Q1H) between the control terminal of the high-side switch and a corresponding reference voltage rail (e.g., 110H), the first discharge current path being activatable to sink a first discharge current (e.g., i1H) from the control terminal of the high-side switch, and

[0093] - A second discharge current path (eg, Q2H, Q3H) between the control terminal of the high-side switch and the respective reference voltage rail, the second discharge current path being activatable to sink a second discharge current (eg, i2H) from the control terminal of the high-side switch.

[0094] As described herein, the second inverter arrangement may include:

[0095] a discharge current path (e.g., Q0L) between the reference voltage rail and the control terminal of the low-side switch, the discharge current path being activatable to sink a discharge current from the control terminal of the low-side switch,

[0096] a first charging current path (e.g., Q1L) between a control terminal of the low-side switch and a corresponding supply voltage rail (e.g., 110L), the first charging current path being activatable to provide a first charging current (e.g., i1L) to the control terminal of the low-side switch, and

[0097] - a second charging current path (eg, Q2L, Q3L) between the control terminal of the low side switch and the respective supply voltage rail, the second charging current path being activatable to provide a second charging current (eg, i2L) to the control terminal of the low side switch.

[0098] As described herein, the circuit may include a high-side sense current path (e.g., QsH, 202H) disposed between a power supply voltage rail and a corresponding reference voltage rail, the high-side sense current path (QsH, 202H) including:

[0099] a high-side sense transistor (e.g., QsH) having a current path coupled between the supply voltage rail and an intermediate high-side control node (e.g., 203H) and a gate terminal coupled to a control terminal of the high-side switch, and

[0100] - A first high-side current source (eg, 202H) coupled between the intermediate high-side control node and a corresponding reference voltage rail to sink a first high-side reference current (eg, IcrossH) from the intermediate high-side control node.

[0101] As described herein, the circuit may include a low-side sense current path (e.g., QsL, 202L) disposed between a reference voltage rail and a corresponding supply voltage rail, the low-side sense current path (QsL, 202L) including:

[0102] a low-side sense transistor (e.g., QsL) having a current path coupled between a reference voltage rail and an intermediate low-side control node (e.g., 203L) and a gate terminal coupled to a control terminal of the low-side switch, and

[0103] - a first low-side current source (eg, 202L) coupled between the intermediate low-side control node and the corresponding supply voltage rail to provide a first low-side reference current (eg, IcrossL) to the intermediate low-side control node.

[0104] As described herein, the second discharge current path may be responsive to a high-side detection signal (eg, ) has a high logic value and is selectively enabled, and the second charging current path can be responsive to a low-side detection signal at the intermediate low-side control node (e.g., ) has a low logic value and is selectively enabled.

[0105] As described herein, the second discharge current path may include a high-side control transistor (e.g., Q3H) having a control terminal coupled (e.g., directly connected) to an intermediate high-side control node and configured to selectively enable the second discharge current path, and the second charging current path may include a low-side control transistor (e.g., Q3L) having a control terminal coupled (e.g., directly connected) to an intermediate low-side control node and configured to selectively enable the second charging current path.

[0106] As described herein, the high-side sensing current path may include a second high-side current source (e.g., 204H) coupled between the intermediate high-side control node and the corresponding reference voltage rail to sink a second high-side reference current (e.g., IsH) from the intermediate high-side control node, and the second high-side current source may be enabled in response to the high-side detection signal at the intermediate high-side control node having a low logic value.

[0107] As described herein, the low-side sensing current path may include a second low-side current source (e.g., 204L) coupled between the intermediate low-side control node and the corresponding power supply voltage rail to provide a second low-side reference current (e.g., IsL) to the intermediate low-side control node, and the second low-side current source may be enabled in response to the low-side detection signal at the intermediate low-side control node having a high logic value.

[0108] As described herein, the first discharge current can be lower than the second discharge current, and / or the first charge current can be lower than the second charge current.

[0109] As described herein, the high-side switch may include a high-side power transistor, optionally a p-channel MOS transistor, and the low-side switch may include a low-side power transistor, optionally an n-channel MOS transistor.

[0110] As described herein, the high-side sensing transistor can be the same type as the high-side power transistor and can have a smaller size (e.g., from 1 / 100 to 1 / 1000 the size of the high-side power transistor), and the low-side sensing transistor can be the same type as the low-side power transistor and can have a smaller size (e.g., from 1 / 100 to 1 / 1000 the size of the low-side power transistor).

[0111] As described herein, the circuit may include:

[0112] - an input node (e.g., 304) configured to receive a pulse width modulated drive signal (e.g., INPUT),

[0113] - an OR logic gate (e.g., 302H) configured to combine the pulse width modulated drive signal and an inverted copy of the low-side sense signal (e.g., Sens-L),

[0114] - an inverter circuit (e.g., 108H) coupled to the output of the OR logic gate to generate a high-side control signal,

[0115] - an AND logic gate (e.g., 302L) configured to combine the pulse width modulated drive signal and an inverted copy of the high-side sense signal (e.g., Sens-H), and

[0116] - An inverter circuit (eg, 108L) coupled to the output of the AND logic gate to generate a low-side control signal.

[0117] As described herein, a method of operating a circuit according to one or more embodiments may include:

[0118] - receiving a high-side control signal and generating a high-side gate control signal for a high-side switch, wherein the high-side gate control signal (IN-H gate ) may include:

[0119] - in response to the high-side control signal having a low logic value, providing a charging current to a control terminal of the high-side switch, and

[0120] - In response to the high-side control signal having a high logic value, the control terminal of the high-side switch is drawn

[0121] receiving a first discharge current;

[0122] - Receives low-side control signals and generates low-side gate control signals for low-side switches

[0123] Signal, wherein generating a low-side gate control signal may include:

[0124] - in response to the low-side control signal having a high logic value, sinking a discharge current from a control terminal of the low-side switch, and

[0125] - in response to the low-side control signal having a low logic value, providing a control terminal of the low-side switch

[0126] Supplying a first charging current;

[0127] - generating a high-side detection signal at the intermediate high-side control node, wherein generating the high-side detection signal may include providing a current to the intermediate high-side control node in response to the high-side switch being in an on-state, and sinking a first high-side reference current from the intermediate high-side control node;

[0128] - generating a low-side detection signal at the intermediate low-side control node, wherein generating the low-side detection signal may include sinking current from the intermediate low-side control node in response to the low-side switch being in an on-state, and providing a first low-side reference current to the intermediate low-side control node;

[0129] - in response to the high-side control signal having a high logic value and the high-side detection signal having a high logic value, sinking a second discharge current from the control terminal of the high-side switch; and

[0130] In response to the low-side control signal having a low logic value and the low-side detection signal having a low logic value, providing a second charging current to the control terminal of the low-side switch.

[0131] The details and embodiments may vary, even significantly, with respect to what is described purely as an example, without prejudice to the underlying principle and without departing from the scope of protection.

[0132] The scope of protection is determined by the appended claims.

Claims

1. A circuit, include: a high-side switch coupled between the first supply voltage rail and the output node; a low-side switch coupled between the output node and a first reference voltage rail; a first inverter arrangement configured to receive a high-side control signal and generate a high-side gate control signal for the high-side switch, the first inverter arrangement comprising: a first discharge current path between a control terminal of the high-side switch and a second reference voltage rail, the first discharge current path being activatable to sink a first discharge current from the control terminal of the high-side switch; and a second discharge current path between the control terminal of the high-side switch and the second reference voltage rail, the second discharge current path being activatable to sink a second discharge current from the control terminal of the high-side switch; a second inverter arrangement configured to receive a low-side control signal and generate a low-side gate control signal for the low-side switch, the second inverter arrangement comprising: a first charging current path between a control terminal of the low-side switch and a second supply voltage rail, the first charging current path being activatable to provide a first charging current to the control terminal of the low-side switch; and a second charging current path between the control terminal of the low-side switch and the second supply voltage rail, the second charging current path being activatable to provide a second charging current to the control terminal of the low-side switch; A high-side sensing current path is arranged between the first power supply voltage rail and the second reference voltage rail, and the high-side sensing current path includes: a high-side sense transistor having a first current path coupled between the first supply voltage rail and an intermediate high-side control node and a gate terminal coupled to the control terminal of the high-side switch; and a first high-side current source coupled between the intermediate high-side control node and the second reference voltage rail to sink a first high-side reference current from the intermediate high-side control node; and A low-side sensing current path is arranged between the first reference voltage rail and the second power supply voltage rail, and the low-side sensing current path includes: a low-side sense transistor having a second current path coupled between the first reference voltage rail and an intermediate low-side control node and a gate terminal coupled to the control terminal of the low-side switch; and a first low-side current source coupled between the intermediate low-side control node and the second power supply voltage rail to provide a first low-side reference current to the intermediate low-side control node; wherein the second discharge current path is selectively enabled in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enabled in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

2. The circuit according to claim 1, in: the second discharge current path comprising a high-side control transistor having a first control terminal coupled to the intermediate high-side control node and configured to selectively enable the second discharge current path; as well as The second charging current path includes a low-side control transistor having a second control terminal coupled to the intermediate low-side control node and configured to selectively enable the second charging current path.

3. The circuit according to claim 1, in: the high-side sensing current path comprising a second high-side current source coupled between the intermediate high-side control node and the second reference voltage rail to sink a second high-side reference current from the intermediate high-side control node, the second high-side current source being enabled in response to the high-side detection signal at the intermediate high-side control node having the low logic value; as well as The low-side sensing current path includes a second low-side current source coupled between the intermediate low-side control node and the second power supply voltage rail to provide a second low-side reference current to the intermediate low-side control node, the second low-side current source being enabled in response to the low-side detection signal at the intermediate low-side control node having the high logic value. 4 . The circuit of claim 1 , wherein the first discharge current is lower than the second discharge current, and / or the first charge current is lower than the second charge current. 5 . The circuit of claim 1 , wherein the high-side switch comprises a high-side power transistor and the low-side switch comprises a low-side power transistor. 6 . The circuit of claim 5 , wherein the high-side power transistor is a p-channel metal oxide semiconductor (MOS) transistor and the low-side power transistor is an n-channel MOS transistor. 7 . The circuit of claim 5 , wherein the high-side sense transistor is of the same type and smaller size than the high-side power transistor, and the low-side sense transistor is of the same type and smaller size than the low-side power transistor.

8. The circuit according to claim 1, include: an input node configured to receive a pulse width modulated drive signal; an OR logic gate configured to combine the pulse width modulated drive signal and an inverted copy of the low side detection signal; A first inverter circuit coupled to the output of the OR logic gate to generate the high-side control signal; an AND logic gate configured to combine the pulse width modulated drive signal and an inverted copy of the high side detection signal; as well as A second inverter circuit is coupled to the output of the AND logic gate to generate the low-side control signal.

9. A method of operating a circuit, the circuit comprising a high-side switch coupled between a first power supply voltage rail and an output node, a low-side switch coupled between the output node and a first reference voltage rail, a high-side sense transistor having a first current path coupled between the first power supply voltage rail and an intermediate high-side control node, and a low-side sense transistor having a second current path coupled between the first reference voltage rail and an intermediate low-side control node, the method include: Receiving a high-side control signal and generating a high-side gate control signal for a high-side switch, generating the high-side gate control signal comprises: In response to the high-side control signal having a low logic value, providing a charging current to a control terminal of the high-side switch; and sinking a first discharge current from the control terminal of the high-side switch in response to the high-side control signal having a high logic value; Receiving a low-side control signal and generating a low-side gate control signal for the low-side switch, the generating the low-side gate control signal comprising: In response to the low-side control signal having the high logic value, sinking a discharge current from a control terminal of the low-side switch; and in response to the low-side control signal having the low logic value, providing a first charging current to the control terminal of the low-side switch; generating a high-side detection signal at the intermediate high-side control node, the generating the high-side detection signal comprising providing a current to the intermediate high-side control node in response to the high-side switch being in an on-state and sinking a first high-side reference current from the intermediate high-side control node; generating a low-side detection signal at the intermediate low-side control node, the generating the low-side detection signal comprising sinking a current from the intermediate low-side control node in response to the low-side switch being in an on-state, and providing a first low-side reference current to the intermediate low-side control node; In response to the high-side control signal having the high logic value and the high-side detection signal having the high logic value, sinking a second discharge current from the control terminal of the high-side switch; and In response to the low-side control signal having the low logic value and the low-side detection signal having the low logic value, a second charging current is provided to the control terminal of the low-side switch.

10. The method of claim 9, wherein the circuit further comprises a first discharge current path between the control terminal of the high-side switch and a second reference voltage rail, a second discharge current path between the control terminal of the high-side switch and the second reference voltage rail, a first charge current path between the control terminal of the low-side switch and a second power supply voltage rail, and a second charge current path between the control terminal of the low-side switch and the second power supply voltage rail, the method further comprising: include: selectively enabling the second discharge current path via a high-side control transistor having a first control terminal coupled to the intermediate high-side control node; as well as The second charging current path is selectively enabled by a low-side control transistor having a second control terminal coupled to the intermediate low-side control node.

11. The method according to claim 9, further comprising: include: enabling a second high-side current source in response to the high-side detection signal at the intermediate high-side control node having the low logic value; as well as In response to the low-side detection signal at the intermediate low-side control node having the high logic value, a second low-side current source is enabled.

12. The method according to claim 11, further comprising: include: sinking a second high-side reference current from the intermediate high-side control node via the second high-side current source coupled between the intermediate high-side control node and a second reference voltage rail; as well as A second low-side reference current is provided to the intermediate low-side control node via the second low-side current source coupled between the intermediate low-side control node and a second power supply voltage rail. 13 . The method according to claim 9 , wherein the first discharge current is lower than the second discharge current, and / or the first charge current is lower than the second charge current.

14. The method according to claim 9, include: receiving a pulse width modulated drive signal via an input node; combining the pulse width modulated drive signal and an inverted copy of the low side detection signal through an OR logic gate; generating the high-side control signal by a first inverter circuit coupled to the output of the OR logic gate; combining the pulse width modulated drive signal and an inverted copy of the high side detection signal via an AND logic gate; as well as The low-side control signal is generated by a second inverter circuit coupled to the output of the AND logic gate.

15. A circuit, include: a high-side switch coupled between the first supply voltage rail and the output node; a low-side switch coupled between the output node and a first reference voltage rail; a first discharge current path between a control terminal of the high-side switch and a second reference voltage rail, the first discharge current path being activatable to sink a first discharge current from the control terminal of the high-side switch; a second discharge current path between the control terminal of the high-side switch and the second reference voltage rail, the second discharge current path being activatable to sink a second discharge current from the control terminal of the high-side switch; a first charging current path between a control terminal of the low-side switch and a second supply voltage rail, the first charging current path being activatable to provide a first charging current to the control terminal of the low-side switch; a second charging current path between the control terminal of the low-side switch and the second supply voltage rail, the second charging current path being activatable to provide a second charging current to the control terminal of the low-side switch; a high-side sense transistor having a first current path coupled between the first supply voltage rail and an intermediate high-side control node and a gate terminal coupled to the control terminal of the high-side switch; a first high-side current source coupled between the intermediate high-side control node and the second reference voltage rail to sink a first high-side reference current from the intermediate high-side control node; a low-side sense transistor having a second current path coupled between the first reference voltage rail and an intermediate low-side control node and a gate terminal coupled to the control terminal of the low-side switch; as well as a first low-side current source coupled between the intermediate low-side control node and the second power supply voltage rail to provide a first low-side reference current to the intermediate low-side control node; wherein the second discharge current path is selectively enabled in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enabled in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

16. The circuit according to claim 15, in: the second discharge current path comprising a high-side control transistor having a first control terminal coupled to the intermediate high-side control node and configured to selectively enable the second discharge current path; as well as The second charging current path includes a low-side control transistor having a second control terminal coupled to the intermediate low-side control node and configured to selectively enable the second charging current path.

17. The circuit according to claim 15, in: a high-side sensing current path comprising a second high-side current source coupled between the intermediate high-side control node and the second reference voltage rail to sink a second high-side reference current from the intermediate high-side control node, the second high-side current source being enabled in response to the high-side detection signal at the intermediate high-side control node having the low logic value; as well as A low-side sensing current path includes a second low-side current source coupled between the intermediate low-side control node and the second power supply voltage rail to provide a second low-side reference current to the intermediate low-side control node, the second low-side current source being enabled in response to the low-side detection signal at the intermediate low-side control node having the high logic value.

18. The circuit of claim 15, wherein the first discharge current is lower than the second discharge current, and / or the first charge current is lower than the second charge current.

19. The circuit of claim 15, wherein the high-side switch comprises a high-side power transistor and the low-side switch comprises a low-side power transistor.

20. The circuit according to claim 15, include: an input node configured to receive a pulse width modulated drive signal; an OR logic gate configured to combine the pulse width modulated drive signal and an inverted copy of the low side detection signal; A first inverter circuit coupled to the output of the OR logic gate to generate a high-side control signal; an AND logic gate configured to combine the pulse width modulated drive signal and an inverted copy of the high side detection signal; as well as A second inverter circuit is coupled to the output of the AND logic gate to generate a low-side control signal.

Images