Current acquisition device, drive assembly and electric tool

Abstract

The present disclosure relates to a current acquisition device, a drive component and an electric tool, wherein the device comprises: a three-phase motor; a three-phase full-bridge inverter, the three-phase full-bridge inverter is used to drive the three-phase motor; a drive module, which is used to output a drive signal to control the three-phase full-bridge inverter; a current sampling module, which comprises at least one resistor, which is used to perform current sampling; a control module, which is used to: acquire the first target phase current at the first moment of the target control cycle and store it in a result register; extract the first target phase current from the result register and output it at the third moment of the target control cycle; acquire the second target phase current at the second moment of the target control cycle and store it in the result register; extract the second target phase current at the fourth moment of the target control cycle and output it, and the fourth moment is after the second moment. The embodiment of the present disclosure can efficiently and accurately acquire the two-phase current of the three-phase motor in one control cycle using a current sampling module with a single resistor.

Description

Technical Field

[0001] The present disclosure relates to the field of motor control technology, and in particular to a current acquisition device, a drive component and an electric tool. Background Art

[0002] DC motors are widely used in high-performance speed regulation systems because of their good speed regulation performance, wide speed regulation range and simple speed regulation method. However, the commutator of brushed motors inevitably has shortcomings such as commutation sparks, mechanical noise, and poor maintainability. In order to make up for these shortcomings of brushed DC motors, brushless DC motors (BLDC for short) came into being. Brushless DC motors not only make up for the shortcomings of brushed DC motors, but also have comparable performance to brushed DC motors, so they are increasingly used in high-performance servos and home appliances.

[0003] When controlling a brushless DC motor, it is necessary to sample the current of each phase of the electrode for feedback control. However, when performing current sampling in related technologies, the current sampling accuracy and efficiency are low. Summary of the invention

[0004] According to one aspect of the present disclosure, a current collection device is provided, the device comprising:

[0005] Three-phase motor;

[0006] A three-phase full-bridge inverter, wherein the three-phase full-bridge inverter is used to drive the three-phase motor;

[0007] A driving module, connected to the three-phase full-bridge inverter, and configured to output a driving signal to control the three-phase full-bridge inverter;

[0008] A current sampling module, comprising at least one resistor, connected to a busbar of the three-phase motor, and used for current sampling through the busbar;

[0009] A control module is connected to the current sampling module and is used to:

[0010] At the first moment of the target control cycle, a first target phase current is collected and stored in a result register, wherein the first moment is during the period when the drive module outputs the first drive signal, and the first target phase current is the phase current of the first target phase of the three-phase motor when the first drive signal acts;

[0011] At a third moment of the target control cycle, extracting the first target phase current from the result register and outputting it;

[0012] At a second moment of the target control period, a second target phase current is collected and stored in a result register, wherein the second moment is during a period when the drive module outputs a second drive signal, the second target phase current is a phase current of a second target phase of the three-phase motor when the second drive signal acts, and the third moment is between the first moment and the second moment;

[0013] The second target phase current is extracted and outputted at a fourth time of the target control period, the fourth time being after the second time.

[0014] In a possible implementation, the control module includes a first timer, a second timer, and an analog-to-digital converter, the first timer and the second timer each include a plurality of timing channels, the first timer and the second timer are cascaded, the timing threshold of the first timing channel of the first timer is a value corresponding to the zeroth moment, the zeroth moment is before the first moment, the timing threshold of the first timing channel of the second timer is a value corresponding to the first moment, wherein the first target phase current is collected at the first moment of the target control cycle and stored in the result register, including:

[0015] When the first timing channel of the first timer reaches the zeroth time point, triggering the timing of the second timer;

[0016] When the timing of the first timing channel of the second timer reaches the first moment, the first target phase current is collected, and analog-to-digital conversion is performed through the analog-to-digital converter, and the conversion result is stored in the result register.

[0017] In a possible implementation manner, the timing threshold of the second timing channel of the second timer is a value corresponding to the third moment, and at the third moment of the target control period, extracting and outputting the first target phase current from the result register includes:

[0018] When the target control cycle timing reaches the third time, the second timing channel of the second timer outputs the first target phase current in the result register through direct memory access.

[0019] In a possible implementation manner, extracting and outputting the first target phase current from the result register at the third moment of the target control cycle includes:

[0020] When the target control cycle timing reaches the third moment, the second timing channel of the second timer outputs a sampling sequence through direct memory access, wherein the sampling sequence includes at least one of a temperature parameter and a bus voltage and a first target phase current obtained from the result register.

[0021] In a possible implementation manner, the timing period of the first timing channel of the second timer is the duration from the first moment to the second moment, and the second target phase current is collected at the second moment of the target control period and stored in the result register, including:

[0022] When the timing duration of the first timing channel of the second timer reaches the timing period, the second target phase current is collected, and analog-to-digital conversion is performed through the analog-to-digital converter, and the conversion result is stored in the result register.

[0023] In a possible implementation, the time difference between the zeroth moment and the first moment is greater than or equal to the sum of the noise time of the switching of the transistors in the three-phase full-bridge inverter, the dead time, and the sampling time of the analog-to-digital converter; and / or the control module includes an analog-to-digital conversion sampling channel and a result register.

[0024] In a possible implementation, the three-phase full-bridge inverter includes a first bridge arm, a second bridge arm and a third bridge arm, each bridge arm includes an upper bridge arm and a lower bridge arm, and the upper bridge arm and the lower bridge arm of each bridge arm are provided with a transistor, and the first bridge arm, the second bridge arm, and the third bridge arm correspond to the first phase, the second phase, and the third phase of the three-phase motor, respectively, wherein the corresponding relationship between the drive signal and the phase current of the three-phase motor detected through the bus includes at least one of the following:

[0025] When the driving signal turns on the upper bridge arm transistor of the first phase, the lower bridge arm transistor of the second phase, and the lower bridge arm transistor of the third phase, the phase current detected by the bus is the phase current of the first phase;

[0026] When the driving signal is to turn on the upper bridge arm transistor of the first phase, the upper bridge arm transistor of the second phase, and the lower bridge arm transistor of the third phase, the phase current detected by the bus is a negative current of the phase current of the third phase;

[0027] When the driving signal turns on the lower bridge arm transistor of the first phase, the upper bridge arm transistor of the second phase, and the lower bridge arm transistor of the third phase, the phase current detected by the bus is the phase current of the second phase;

[0028] When the driving signal turns on the lower bridge arm transistor of the first phase, the upper bridge arm transistor of the second phase, and the upper bridge arm transistor of the third phase, the phase current detected by the bus is a negative current of the phase current of the first phase;

[0029] When the driving signal is to turn on the lower bridge arm transistor of the first phase, the lower bridge arm transistor of the second phase, and the upper bridge arm transistor of the third phase, the phase current detected by the bus is the phase current of the third phase;

[0030] When the driving signal turns on the upper bridge arm transistor of the first phase, the lower bridge arm transistor of the second phase, and the upper bridge arm transistor of the third phase, the phase current detected through the bus is a negative current of the phase current of the second phase.

[0031] In a possible implementation manner, the motor is a three-phase brushless DC motor.

[0032] According to one aspect of the present disclosure, a driving component is provided, and the driving component includes the current collection device.

[0033] According to one aspect of the present disclosure, an electric tool is provided, comprising the driving assembly.

[0034] The current acquisition device of the embodiment of the present disclosure can efficiently and accurately acquire two-phase currents of a three-phase motor in one control cycle using a current sampling module with a single resistor, by acquiring a first target phase current at a first moment in a target control cycle and storing it in a result register, extracting and outputting the first target phase current from the result register at a third moment in the target control cycle, acquiring a second target phase current at a second moment in the target control cycle and storing it in a result register, and extracting and outputting the second target phase current at a fourth moment in the target control cycle.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0037] Figure 1 A block diagram of a current acquisition device according to an embodiment of the present disclosure is shown.

[0038] Figure 2A schematic diagram of a process of executing current acquisition by a control module in a current sampling device according to an embodiment of the present disclosure is shown.

[0039] Figure 3 A schematic diagram of a motor driving device according to an embodiment of the present disclosure is shown.

[0040] Figure 4 A schematic diagram of a process of executing current acquisition by a control module in a current sampling device according to an embodiment of the present disclosure is shown.

[0041] Figure 5 A schematic diagram of motor control according to an embodiment of the present disclosure is shown.

[0042] Figure 6 A schematic diagram showing the operation mode of a timer in a control module according to an embodiment of the present disclosure is shown.

[0043] Figure 7 A block diagram of an electric tool according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0044] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0045] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0047] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0048] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0049] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0050] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0051] See also Figure 1 , Figure 1 A block diagram of a current acquisition device according to an embodiment of the present disclosure is shown.

[0052] See also Figure 2 , Figure 2 A schematic diagram of a process of executing current acquisition by a control module in a current sampling device according to an embodiment of the present disclosure is shown.

[0053] like Figure 1 As shown, the device comprises:

[0054] Three-phase motor 10;

[0055] A three-phase full-bridge inverter 20, wherein the three-phase full-bridge inverter 20 is used to drive the three-phase motor 10;

[0056] A driving module 40, connected to the three-phase full-bridge inverter 20, for outputting a driving signal to control the three-phase full-bridge inverter 20;

[0057] The current sampling module 30 includes at least one resistor, connected to the bus of the three-phase motor 10, and is used to perform current sampling through the bus;

[0058] The control module 50 is connected to the current sampling module 30. Figure 2 As shown, the control module 50 is used to:

[0059] Step S11, collecting a first target phase current at a first moment of a target control cycle and storing it in a result register, wherein the first moment is during a period when the drive module 40 outputs a first drive signal, and the first target phase current is a phase current of a first target phase of the three-phase motor 10 when the first drive signal acts;

[0060] Step S12, at the third moment of the target control cycle, extracting the first target phase current from the result register and outputting it;

[0061] Step S13, collecting a second target phase current at a second moment of the target control period and storing it in a result register, wherein the second moment is during a period when the drive module 40 outputs a second drive signal, the second target phase current is a phase current of a second target phase of the three-phase motor 10 when the second drive signal acts, and the third moment is between the first moment and the second moment;

[0062] Step S14, extracting and outputting the second target phase current at a fourth moment in the target control cycle, wherein the fourth moment is after the second moment.

[0063] The current acquisition device of the disclosed embodiment can efficiently and accurately acquire two-phase currents of a three-phase motor in one control cycle using a current sampling module of a single resistor by acquiring the first target phase current at the first moment of the target control cycle and storing it in a result register, extracting the first target phase current from the result register and outputting it at the third moment of the target control cycle, acquiring the second target phase current at the second moment of the target control cycle and storing it in a result register, and extracting the second target phase current and outputting it at the fourth moment of the target control cycle. In addition, the disclosed embodiment uses a single resistor to perform bus current (IBUS) sampling, which can save costs and avoid the problem of unbalanced three-phase sampling current in the three-phase sampling resistor.

[0064] The target control period of the embodiment of the present disclosure may be any period of the drive signal output by the drive module. For example, the drive signal may be a pulse width modulation (PWM) signal. Therefore, the target control period may be any PWM control period.

[0065] The information of each moment of collecting the target phase current and outputting the target phase current in the disclosed embodiment may be determined in advance and stored in the storage module. When the motor is running, the control module may retrieve the relevant information in the storage module to collect the two-phase current of the three-phase motor in one control cycle using the current sampling module of a single resistor. In one example, the storage module may include a computer-readable storage medium, which may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, - but not limited to - an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples of computer-readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), programmable read-only memory (PROM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical encoding device, such as punch cards or raised structures in grooves with instructions stored thereon, and any suitable combination of the above. Computer-readable storage media as used herein are not to be interpreted as transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0066] It should be noted that each module and unit of the embodiment of the present disclosure may be implemented by a hardware circuit, or by using a general hardware circuit in combination with relevant existing logic.

[0067] First, possible implementations of the three-phase full-bridge inverter 20 are exemplarily introduced. It should be noted that the present disclosure does not limit possible implementations of the three-phase full-bridge inverter 20. In other implementations, the three-phase full-bridge inverter 20 may also have other implementations.

[0068] The following is an exemplary introduction to possible implementations of each module.

[0069] See also Figure 3 , Figure 3 A schematic diagram of a motor driving device according to an embodiment of the present disclosure is shown.

[0070] like Figure 3As shown, the three-phase full-bridge inverter 20 may include a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor Q6, wherein the first transistor Q1 and the fourth transistor Q4 constitute a first bridge arm, and the fourth transistor Q4 is a lower bridge arm, the second transistor Q2 and the fifth transistor Q5 constitute a second bridge arm, and the fifth transistor Q5 is a lower bridge arm, the third transistor Q3 and the sixth transistor Q6 constitute a third bridge arm, and the sixth transistor Q6 is a lower bridge arm, wherein one end of each winding of the three-phase motor 10 is electrically connected, and the other end of each winding is electrically connected between the first transistor Q1 and the fourth transistor Q4, between the second transistor Q2 and the fifth transistor Q5, and between the third transistor Q3 and the sixth transistor Q6.

[0071] In a possible implementation, the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 may be metal-oxide-semiconductor field-effect transistors (MOSFET) and insulated gate bipolar transistors (IGBT), wherein the transistors may be implemented based on silicon carbide SiC and gallium nitride GaN to improve performance.

[0072] In one possible implementation, Figure 3 As shown, the three-phase full-bridge inverter 20 may further include multiple first input resistors, multiple second input resistors, and multiple input capacitors to filter the input signal. The stator of the three-phase motor 10 includes a first winding A, a second winding B, and a third winding C. The gates of the transistors of the three-phase full-bridge inverter 20 are electrically connected to the second end of the first input resistor, the first end of the second input resistor, and the first end of the input capacitor. The sources of the transistors of the three-phase full-bridge inverter 20 are electrically connected to the second end of the input capacitor and the second end of the second input resistor. The first end of the first input resistor is used to input a drive signal.

[0073] The drain of the first transistor Q1, the drain of the second transistor Q2, and the drain of the third transistor Q3 are electrically connected, and the source of the fourth transistor Q4, the source of the fifth transistor Q5, and the source of the sixth transistor Q6 are electrically connected.

[0074] The source of the first transistor Q1 is electrically connected to the drain of the fourth transistor Q4 and the first end of the first winding, the source of the second transistor Q2 is electrically connected to the drain of the fifth transistor Q5 and the first end of the second winding, and the source of the third transistor Q3 is electrically connected to the drain of the sixth transistor Q6 and the first end of the third winding.

[0075] A second end of the first winding A, a second end of the second winding B, and a second end of the third winding C are grounded.

[0076] In one example, if Figure 3 As shown, the first input resistor may include a first resistor R1, a third resistor R3, a fifth resistor R5, a seventh resistor R7, a ninth resistor R9, and an eleventh resistor R11; the second input resistor may include a second resistor R2, a fourth resistor R4, a sixth resistor R6, an eighth resistor R8, a tenth resistor R10, and a twelfth resistor R12; and the input capacitor may include a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6.

[0077] In one example, the three-phase full-bridge inverter 20 may further include a plurality of freewheeling diodes disposed between the source and the drain of each transistor, for providing a freewheeling path when the transistor is turned off to prevent the transistor from being damaged.

[0078] In a possible implementation, the three-phase motor 10 may be a three-phase brushless DC motor.

[0079] In one example, the embodiment of the present disclosure realizes the Y connection (or star connection) of the three-phase motor 10 by electrically connecting one end of each winding of the stator, and the other end of each winding is electrically connected between the first transistor Q1 and the fourth transistor Q4, between the second transistor Q2 and the fifth transistor Q5, and between the third transistor Q3 and the sixth transistor Q6.

[0080] In one example, if Figure 3 As shown, the three-phase motor 10 may include a first winding A, a second winding B and a third winding C (corresponding to phase A, phase B, phase C, and corresponding to the first bridge arm, the second bridge arm, and the third bridge arm, respectively), one end of the first winding A is electrically connected between the first transistor Q1 and the fourth transistor Q4, one end of the second winding B is electrically connected between the second transistor Q2 and the fifth transistor Q5, and one end of the third winding C is electrically connected between the third transistor Q3 and the sixth transistor Q6.

[0081] The control module 50 of the disclosed embodiment may include a processing component, wherein the processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller having an execution instruction function in an electronic device, and the processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. The disclosed embodiment does not limit the specific implementation of the control module 50.

[0082] In one possible implementation, the control module 50 may be a microprocessor MCU that includes only one analog-to-digital converter and only one result register. For an MCU that has only one analog-to-digital converter, the related technology cannot realize the acquisition of two-phase currents in one control cycle. The embodiment of the present disclosure acquires the first target phase current at the first moment of the target control cycle and stores it in the result register, extracts and outputs the first target phase current from the result register at the third moment of the target control cycle, acquires the second target phase current at the second moment of the target control cycle and stores it in the result register, and extracts and outputs the second target phase current at the fourth moment of the target control cycle. This can efficiently and accurately acquire the two-phase current of a three-phase motor in one control cycle using a current sampling module with a single resistor.

[0083] In a possible implementation, the control module 50 may include a first timer, a second timer, and an analog-to-digital converter, the first timer and the second timer each including a plurality of timing channels, the first timer and the second timer are cascaded, the timing threshold of the first timing channel of the first timer is a value corresponding to the zeroth moment, the zeroth moment is before the first moment, and the timing threshold of the first timing channel of the second timer is a value corresponding to the first moment. When the timer of the embodiment of the present disclosure starts timing and reaches the corresponding timing threshold, it can output a valid signal to trigger a corresponding operation.

[0084] The embodiments of the present disclosure do not limit the specific implementation of the control module to perform each step, and those skilled in the art can implement it according to actual conditions and needs.

[0085] See also Figure 4, Figure 4 A schematic diagram of a process of executing current acquisition by a control module in a current sampling device according to an embodiment of the present disclosure is shown.

[0086] In a possible implementation, Figure 4 As shown, step S11 collects the first target phase current at the first moment of the target control cycle and stores it in the result register, which may include:

[0087] Step S111, when the first timing channel of the first timer reaches the zeroth time of the target control cycle, triggering the timing of the second timer;

[0088] Exemplarily, the first timer can start timing from the start time of the current control cycle. When the first timing channel of the first timer reaches the zeroth time in the target control cycle timing, the first timing channel of the first timer can output a valid signal to trigger the second timer to start timing.

[0089] Step S112: when the first timing channel of the second timer reaches the first moment, the first target phase current is collected, analog-to-digital conversion is performed through the analog-to-digital converter, and the conversion result is stored in the result register.

[0090] Exemplarily, when the first timing channel of the second timer reaches the first moment, the control module can control the current sampling module to collect the bus current of the three-phase motor to obtain the first target phase current, and perform analog-to-digital conversion through the analog-to-digital converter, and store the conversion result in the result register.

[0091] In a possible implementation manner, the timing threshold of the second timing channel of the second timer is a value corresponding to the third moment, such as Figure 4 As shown, step S12 extracts and outputs the first target phase current from the result register at the third moment of the target control cycle, which may include:

[0092] Step S121 , when the target control cycle timing reaches the third moment, the second timing channel of the second timer outputs the first target phase current in the result register by direct memory access.

[0093] In one example, when the second timing channel of the second timer reaches the third moment in the target control cycle timing, the control module can output the first target phase current in the result register through direct memory access (DMA), and the control module can select a suitable DMA channel according to actual conditions and needs.

[0094] In a possible implementation manner, step S12, at the third moment of the target control cycle, extracting and outputting the first target phase current from the result register may include:

[0095] Step S122, when the second timing channel of the second timer reaches the third moment in the target control cycle timing, outputs a sampling sequence through direct memory access, wherein the sampling sequence includes at least one of a temperature parameter and a bus voltage and a first target phase current obtained from the result register.

[0096] In one example, in actual applications, it may be necessary to collect parameters other than bus current, such as bus voltage, temperature, etc. In this case, in order to improve the efficiency of parameter collection and transmission, the embodiment of the present disclosure can output a sampling sequence through direct memory access in the second timing channel of the second timer when the target control cycle timing reaches the third moment, wherein the sampling sequence includes at least one of the temperature parameters, bus voltage and the first target phase current obtained from the result register.

[0097] In a possible implementation manner, the timing period of the first timing channel of the second timer is the duration from the first moment to the second moment.

[0098] In a possible implementation, Figure 4 As shown, step S13 collects the second target phase current at the second moment of the target control cycle and stores it in the result register, which may include:

[0099] Step S131, when the timing duration of the first timing channel of the second timer reaches the timing period, the second target phase current is collected, and analog-to-digital conversion is performed through the analog-to-digital converter, and the conversion result is stored in the result register.

[0100] Exemplarily, when the timing duration of the first timing channel reaches the timing period, the first timing channel can be closed, the timing can be stopped, and the initialization can be performed. At this time, the control module can control the current sampling module to collect the second target phase current on the bus, and perform analog-to-digital conversion through the analog-to-digital converter, and store the conversion result in the result register.

[0101] In a possible implementation manner, the time difference between the zeroth moment and the first moment is greater than or equal to the noise time T of the switching of the transistors in the three-phase full-bridge inverter 20. N , the dead time of transistor switching is T D , the sampling time T of the analog-to-digital converter samp sum.

[0102] In a possible implementation, the control module 50 includes an analog-to-digital conversion sampling channel and a result register.

[0103] In a possible implementation, the three-phase full-bridge inverter 20 includes a first bridge arm, a second bridge arm and a third bridge arm, each bridge arm includes an upper bridge arm and a lower bridge arm, the upper bridge arm and the lower bridge arm of each bridge arm are provided with a transistor, the first bridge arm, the second bridge arm, and the third bridge arm correspond to the first phase, the second phase, and the third phase of the three-phase motor 10, respectively, wherein the correspondence between the drive signal and the phase current of the three-phase motor 10 detected through the bus can be as shown in Table 1.

[0104] Table 1

[0105]

[0106]

[0107] Among them, AH represents the upper bridge of phase A (first phase), AH=1 represents that the upper bridge is open (transistor is on) and the lower bridge is closed (transistor is off), and AH=0 represents that the upper bridge is closed and the lower bridge is open.

[0108] Among them, Ia represents the A-phase current (corresponding to the first winding A), Ib represents the B-phase current (corresponding to the first winding B), and Ic represents the C-phase current (corresponding to the first winding C).

[0109] In one example, as shown in Table 1, the corresponding relationship between the drive signal and the phase current of the three-phase motor 10 detected through the bus may include at least one of the following:

[0110] When the driving signal (100) turns on the upper bridge arm transistor of the first phase, the lower bridge arm transistor of the second phase, and the lower bridge arm transistor of the third phase, the phase current detected through the bus is the phase current of the first phase;

[0111] When the driving signal (110) turns on the upper bridge arm transistor of the first phase, the upper bridge arm transistor of the second phase, and the lower bridge arm transistor of the third phase, the phase current detected through the bus is a negative current of the phase current of the third phase;

[0112] When the driving signal (010) turns on the lower bridge arm transistor of the first phase, the upper bridge arm transistor of the second phase, and the lower bridge arm transistor of the third phase, the phase current detected through the bus is the phase current of the second phase;

[0113] When the driving signal (011) turns on the lower bridge arm transistor of the first phase, the upper bridge arm transistor of the second phase, and the upper bridge arm transistor of the third phase, the phase current detected by the bus is a negative current of the phase current of the first phase;

[0114] When the driving signal (001) turns on the lower bridge arm transistor of the first phase, the lower bridge arm transistor of the second phase, and the upper bridge arm transistor of the third phase, the phase current detected by the bus is the phase current of the third phase;

[0115] When the drive signal (101) turns on the upper bridge arm transistor of the first phase, the lower bridge arm transistor of the second phase, and the upper bridge arm transistor of the third phase, the phase current detected through the bus is the negative current of the phase current of the second phase.

[0116] See also Figure 5 , Figure 5 A schematic diagram of motor control according to an embodiment of the present disclosure is shown.

[0117] The control module of the embodiment of the present disclosure can control the operation of the driving module, thereby realizing the control of the three-phase motor. For example, the embodiment of the present disclosure adopts SVPWM (Space Vector Pulse Width Modulation) to control the rotation of the motor.

[0118] In one example, when the six switching devices, the first transistor Q1 to the sixth transistor Q6, are combined (the signals of the upper and lower half bridges of the same bridge arm are opposite), there are 8 safe switching states, of which U0 (000) and U7 (111) will not generate effective current in the motor drive, so they can be called zero vectors. The other 6 switching states are six effective vectors. They divide the 360-degree voltage space into 60-degree sectors, a total of six sectors. Using these six basic effective vectors and two zero quantities, any vector within 360 degrees can be synthesized.

[0119] In one example, SVPWM uses the volt-second balance principle to first determine the sector where the modulation vector voltage is located, and then use the two adjacent vectors in the sector where the vector voltage is located to synthesize the required vector voltage to make the stator flux linkage a circular rotating modulation method (such as Figure 5 As shown, the vector voltage U out In the first sector, the adjacent vectors are U1 and U2). For example, Figure 5 As shown, the circled numbers represent the sectors where the synthetic vector voltage is located, and the six modulation vectors are (100, 110, 010, 011, 001, 101) respectively.

[0120] In one example, when generating a driving signal, the driving module generally adopts a triangular counting timer operation mode.

[0121] See also Figure 6 , Figure 6 A schematic diagram showing the operation mode of a timer in a control module according to an embodiment of the present disclosure is shown.

[0122] like Figure 6 As shown, the current sampling analysis is performed by taking the case where the required vector voltage falls on the first sector as an example. At this time, the vector voltage needs to be synthesized by vectors U1 (100) and U2 (110). The ABC three-phase modulation signal is as follows: Figure 6 As shown, the modulation time of vector U1 is T1, the modulation time of vector U2 is T2, T0 is the zero vector when all the three-phase upper tubes are disconnected, and T7 is the zero vector when all the three-phase lower tubes are disconnected.

[0123] In one example, if Figure 6 As shown, the embodiment of the present disclosure can perform bus current sampling at the time when B (110) and D (100) are present (the time when the drive signal 110 and the drive signal 100 take effect) to obtain the negative value (-Ic) of the phase current (Ia) of the phase A or the phase current (Ic) of the phase C. Of course, the bus current sampling can also be performed at the time when A (100) and B (110) are present to obtain the negative value (-Ic) of the phase current (Ia) of the phase A or the phase current (Ic) of the phase C; or the phase currents of other phases can be collected at other times, and the embodiment of the present disclosure is not limited to this.

[0124] In one example, taking the bus current sampling at the time of B (110) and D (100) as an example, if the ADC result is not moved away in time after the bus current sampling is performed at point B, the first sampling result will be overwritten after the second ADC sampling. The embodiment of the present disclosure transfers the ADC result through DMA. Of course, the specific DMA channel can be selected according to the actual situation, and the embodiment of the present disclosure is not limited.

[0125] In one example, if Figure 6 As shown, Timer1 (first timer) can be three pairs of PWM output time bases, Timer2 (second timer) and Timer1 are in cascade relationship, Timer2 can be triggered by CC4 channel (first timing channel) of Timer1 to start counting, and the timing threshold of CC4 channel of Timer1 is a certain moment before point B (the zeroth moment), which is used to trigger Timer2 counting (step S111, when the first timing channel of the first timer reaches the zeroth moment when the timing of the target control cycle reaches the zeroth moment, the second timer is triggered to count).

[0126] In one example, if Figure 6As shown, the timing threshold of the CC1 channel (first timing channel) of Timer2 is the value exactly at point B (first moment). Exemplarily, ADC sampling can be triggered by the rising edge and falling edge of CC1 of Timer2. For example, when Timer2 counts to the value of point B, the output level of the CC1 channel of Timer2 changes from low to high, and a rising edge occurs, triggering the first ADC sampling (step S112, when the timing of the first timing channel of the second timer reaches the first moment, the first target phase current is collected, and analog-to-digital conversion is performed through the analog-to-digital converter, and the conversion result is stored in the result register).

[0127] Exemplarily, the disclosed embodiment can be set to sample only the current of the bus resistance at this time. After the sampling is completed, the result can be moved by DMA channel 1 or channel 2 (selected according to actual conditions and needs, if there are other MDA channels, other DMA channels can also be selected); because in application, there are ADC channels such as bus voltage and temperature to be collected, so when the ADC is sampled for the second time within a cycle, the ADC channel must include multiple ADC sampling sequences (including bus current, bus voltage, temperature, etc.), and the CC2 (second timing channel) value of channel Timer2 can be set at point C (third moment) to complete, and DMA channel 2 (or others) can be triggered by the CC2 channel of Timer2. When DMA channel 2 is interrupted, all ADC sequences that need to be collected are assigned to the sampling channel peripheral address of the ADC through DMA channel 2 to complete the change of the ADC sampling sequence. Of course, the change of the ADC sampling sequence can also be completed in the CC2 interrupt of Timer2 (step S12 extracts the first target phase current from the result register at the third moment of the target control cycle and outputs it).

[0128] In one example, if Figure 6 As shown, the period value of Timer2 can be the value of point D (the second moment), and Timer2 runs in the single counting mode, so when Timer2 counts to point D, the output level of the CC1 channel of Timer2 changes from high to low, and a falling edge appears, triggering the second ADC sampling. At this time, the ADC sampling sequence is collected again to obtain the bus current and / or ADC of other channels collected for the second time (step S131, when the timing duration of the first timing channel of the second timer reaches the timing period, the second target phase current is collected, and the analog-to-digital conversion is performed through the analog-to-digital converter, and the conversion result is stored in the result register).

[0129] In one example, in the DMA interrupt of Timer2, the ADC sampling sequence is completed again, and only the current sampling of the bus resistance is completed. By looping in this way, the single-cycle double sampling of the single resistor can be completed in each cycle (Ts).

[0130] The current acquisition device of the disclosed embodiment can efficiently and accurately acquire two-phase currents of a three-phase motor in one control cycle using a current sampling module of a single resistor by acquiring the first target phase current at the first moment of the target control cycle and storing it in a result register, extracting the first target phase current from the result register and outputting it at the third moment of the target control cycle, acquiring the second target phase current at the second moment of the target control cycle and storing it in a result register, and extracting the second target phase current and outputting it at the fourth moment of the target control cycle. In addition, the disclosed embodiment uses a single resistor for bus current ( Figure 3 The IBUS) sampling in the three-phase sampling resistor can save costs and avoid the problem of three-phase sampling current imbalance in the three-phase sampling resistor.

[0131] See also Figure 7 , Figure 7 A block diagram of an electric tool according to an embodiment of the present disclosure is shown.

[0132] For example, the electric tool 1900 may be provided as a server. Figure 7 , the power tool 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions, such as applications, that can be executed by the processing component 1922. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above method.

[0133] The power tool 1900 may also include a power supply assembly 1926 configured to perform power management of the power tool 1900, a wired or wireless network interface 1950 configured to connect the power tool 1900 to a network, and an input / output (I / O) interface 1958. The power tool 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2000). TM ), a graphical user interface operating system launched by Apple (Mac OSX TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSDTM ) or similar.

[0134] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the power tool 1900 to perform the above-described method.

[0135] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0136] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0137] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0138] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0139] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0140] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0141] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0142] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0143] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0144] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A current collection device, characterized in that: The device comprises: Three-phase motor; A three-phase full-bridge inverter, wherein the three-phase full-bridge inverter is used to drive the three-phase motor; A driving module, connected to the three-phase full-bridge inverter, and configured to output a driving signal to control the three-phase full-bridge inverter; A current sampling module, comprising at least one resistor, connected to a busbar of the three-phase motor, and used for current sampling through the busbar; A control module is connected to the current sampling module and is used to: At the first moment of the target control cycle, a first target phase current is collected and stored in a result register, wherein the first moment is during the period when the drive module outputs the first drive signal, and the first target phase current is the phase current of the first target phase of the three-phase motor when the first drive signal acts; At a third moment of the target control cycle, extracting the first target phase current from the result register and outputting it; At a second moment of the target control period, a second target phase current is collected and stored in a result register, wherein the second moment is during a period when the drive module outputs a second drive signal, the second target phase current is a phase current of a second target phase of the three-phase motor when the second drive signal acts, and the third moment is between the first moment and the second moment; The second target phase current is extracted and outputted at a fourth time of the target control period, the fourth time being after the second time.

2. The device according to claim 1, characterized in that The control module includes a first timer, a second timer, and an analog-to-digital converter. The first timer and the second timer each include a plurality of timing channels. The first timer and the second timer are cascaded. The timing threshold of the first timing channel of the first timer is a value corresponding to the zeroth moment, and the zeroth moment is before the first moment. The timing threshold of the first timing channel of the second timer is a value corresponding to the first moment. The first target phase current is collected at the first moment of the target control cycle and stored in the result register, including: When the first timing channel of the first timer reaches the zeroth time point, triggering the timing of the second timer; When the timing of the first timing channel of the second timer reaches the first moment, the first target phase current is collected, and analog-to-digital conversion is performed through the analog-to-digital converter, and the conversion result is stored in the result register.

3. The device according to claim 2, characterized in that The timing threshold of the second timing channel of the second timer is a value corresponding to the third moment, and at the third moment of the target control period, extracting and outputting the first target phase current from the result register includes: When the target control cycle timing reaches the third time, the second timing channel of the second timer outputs the first target phase current in the result register through direct memory access.

4. The device according to claim 3, characterized in that The extracting and outputting the first target phase current from the result register at the third moment of the target control cycle comprises: When the target control cycle timing reaches the third moment, the second timing channel of the second timer outputs a sampling sequence through direct memory access, wherein the sampling sequence includes at least one of a temperature parameter and a bus voltage and a first target phase current obtained from the result register.

5. The device according to claim 2, characterized in that The timing cycle of the first timing channel of the second timer is the duration from the first moment to the second moment, and the second target phase current is collected at the second moment of the target control cycle and stored in the result register, including: When the timing duration of the first timing channel of the second timer reaches the timing period, the second target phase current is collected, and analog-to-digital conversion is performed through the analog-to-digital converter, and the conversion result is stored in the result register.

6. The device according to claim 2, characterized in that The time difference between the zeroth moment and the first moment is greater than or equal to the sum of the noise time, the dead time, and the sampling time of the analog-to-digital converter of the switching of the transistors in the three-phase full-bridge inverter; and / or the control module includes an analog-to-digital conversion sampling channel and a result register.

7. The device according to claim 1, characterized in that The three-phase full-bridge inverter comprises a first bridge arm, a second bridge arm and a third bridge arm, each bridge arm comprises an upper bridge arm and a lower bridge arm, the upper bridge arm and the lower bridge arm of each bridge arm are provided with a transistor, the first bridge arm, the second bridge arm and the third bridge arm correspond to the first phase, the second phase and the third phase of the three-phase motor respectively, wherein the corresponding relationship between the drive signal and the phase current of the three-phase motor detected through the bus includes at least one of the following: When the driving signal turns on the upper bridge arm transistor of the first phase, the lower bridge arm transistor of the second phase, and the lower bridge arm transistor of the third phase, the phase current detected by the bus is the phase current of the first phase; When the driving signal is to turn on the upper bridge arm transistor of the first phase, the upper bridge arm transistor of the second phase, and the lower bridge arm transistor of the third phase, the phase current detected by the bus is a negative current of the phase current of the third phase; When the driving signal turns on the lower bridge arm transistor of the first phase, the upper bridge arm transistor of the second phase, and the lower bridge arm transistor of the third phase, the phase current detected by the bus is the phase current of the second phase; When the driving signal turns on the lower bridge arm transistor of the first phase, the upper bridge arm transistor of the second phase, and the upper bridge arm transistor of the third phase, the phase current detected by the bus is a negative current of the phase current of the first phase; When the driving signal is to turn on the lower bridge arm transistor of the first phase, the lower bridge arm transistor of the second phase, and the upper bridge arm transistor of the third phase, the phase current detected by the bus is the phase current of the third phase; When the driving signal turns on the upper bridge arm transistor of the first phase, the lower bridge arm transistor of the second phase, and the upper bridge arm transistor of the third phase, the phase current detected through the bus is a negative current of the phase current of the second phase.

8. The device according to claim 1, characterized in that The motor is a three-phase brushless DC motor.

9. A drive assembly, characterized in that: The driving component comprises the current collection device according to any one of claims 1-8.

10. An electric tool, characterized in that: The electric tool comprises the drive assembly according to claim 9.

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