D flip-flop

Abstract

This invention relates to a D flip-flop, comprising: a clock input module for receiving an external clock signal and generating a delayed clock signal and a direct clock signal based on the external clock signal, thereby generating a first clock signal and a second clock signal; a data input module connected to the clock input module for receiving an external data signal and, in response to the first clock signal and the second clock signal, outputting a first data signal and a second data signal based on the external data signal; a set / reset module for receiving a set signal and a reset signal, generating a set control signal based on the set signal, and generating a reset control signal based on the reset signal; and a latch module connected to the clock input module, the data input module, and the set / reset module for latching the external data signal based on the set control signal and the reset control signal. The D flip-flop provided in this application can resist single-event radiation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a D trigger resistant to single-event radiation effects. Background Technology

[0002] Transistor circuits used in space applications are susceptible to the effects of high-energy particles emitted from the space radiation environment. Failures caused by these radiation particles are a major reliability issue for integrated circuits used in space. Among these, the D flip-flop, as one of the most frequently used timing units in integrated circuits, has its radiation resistance performance being crucial in determining the overall radiation resistance level of the integrated circuit. The main radiation effects faced by D flip-flops include Single Event Upset (SEU) and Single Event Transient (SET). SEU refers to the phenomenon where a single high-energy particle incident on a D flip-flop can cause the stored state to flip. SET refers to the phenomenon where a single high-energy particle incident on a sensitive node of a combinational circuit generates a transient pulse that propagates downwards. If this erroneous pulse reaches the D flip-flop and is latched, it will cause an error in the stored state of the D flip-flop. As semiconductor process nodes continue to shrink, the feature size, operating voltage, and capacitance of MOS devices are also decreasing, leading to an increasingly severe risk of SET effects for integrated circuits. Simultaneously, as the operating frequency of circuits increases, the impact of the SEU effect becomes increasingly significant. The contribution of SET to the SEU rate in combinational logic increases with the circuit's operating frequency. As process nodes drop below 100nm, the width of the SET pulse generated by a single-event event (SEE) incident on combinational logic circuits becomes roughly equivalent to the signal pulse width. The probability that this pulse will be latched by the memory cell and cause a single-event upset (SEE) increases significantly. Therefore, the design of SEE and SEL-hardened D flip-flops is crucial for developing electronic systems suitable for space applications. Summary of the Invention

[0003] Therefore, it is necessary to provide a hardened D trigger that can resist single-event radiation effects.

[0004] A D flip-flop, comprising:

[0005] A clock input module is used to receive an external clock signal, generate a delayed clock signal and a through clock signal based on the external clock signal, and generate a first clock signal and a second clock signal based on the delayed clock signal and the through clock signal, wherein the delayed clock signal is output with a delay relative to the through clock signal, and the delay is greater than the width of a single-particle transient pulse in the external clock signal;

[0006] A data input module, connected to the clock input module, is used to receive external data signals and, in response to the first clock signal and the second clock signal, output a first data signal and a second data signal respectively according to the external data signals.

[0007] The set / reset module is used to receive a set signal and a reset signal, generate a set control signal based on the set signal, and generate a reset control signal based on the reset signal.

[0008] The latch module is connected to the clock input module, the data input module, and the set / reset module, respectively, and is used to respond to the first clock signal and the second clock signal, and to latch the external data signal based on the set control signal and the reset control signal.

[0009] In one embodiment, the clock input module includes:

[0010] The first delay unit is used to receive the external clock signal and perform delay processing on the external clock signal to obtain the delayed clock signal;

[0011] The first through unit is used to receive the external clock signal and generate the through clock signal;

[0012] The first inverting unit is connected to the first delay unit and the first pass-through unit respectively, and is used to generate the first clock signal according to the delayed clock signal and the pass-through clock signal;

[0013] The second inverting unit is connected to the first inverting unit and is used to invert the first clock signal to generate the second clock signal.

[0014] In one embodiment, the first inverting unit includes:

[0015] The first clock pull-up transistor array includes a first PMOS transistor and a second PMOS transistor. The gate of the first PMOS transistor is connected to the first pass-through unit, the source of the first PMOS transistor is used to receive the power supply voltage, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The gate of the second PMOS transistor is connected to the first delay unit and is used to receive the delayed clock signal.

[0016] The first clock pull-down transistor array includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor is connected to the first pass-through unit, and the drain of the first NMOS transistor is connected to the drain of the second PMOS transistor and the second inverting unit, respectively, for outputting the first clock signal. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the first delay unit, and the source of the second NMOS transistor is grounded.

[0017] In one embodiment, the set / reset module includes:

[0018] A set circuit is used to receive an external set signal, generate a delayed set signal and a direct set signal based on the external set signal, and generate a set control signal based on the delayed set signal and the direct set signal.

[0019] A reset circuit is used to receive an external reset signal, generate a delayed reset signal and a direct reset signal based on the external reset signal, and generate a reset control signal based on the delayed reset signal and the direct reset signal.

[0020] In one embodiment, the set circuit includes:

[0021] The second delay unit is used to receive the external set signal and perform delay processing on the external set signal to obtain the delayed set signal.

[0022] The second pass-through unit is used to receive the external set signal and generate the pass-through set signal;

[0023] The first set pull-up transistor array and the first set pull-down transistor array are respectively connected to the second delay unit and the second pass-through unit, and are used to generate the set control signal according to the delayed set signal and the pass-through set signal.

[0024] In one embodiment, the reset circuit includes:

[0025] The third delay unit is used to receive the external reset signal and perform delay processing on the external reset signal to obtain the delayed reset signal;

[0026] The third through unit is used to receive the external reset signal and generate the through reset signal;

[0027] The first reset pull-up transistor array and the first reset pull-down transistor array are respectively connected to the third delay unit and the third pass-through unit, and are used to generate the reset control signal according to the delayed reset signal and the pass-through reset signal.

[0028] In one embodiment, the data input module includes:

[0029] The fourth delay unit is used to receive the external data signal and perform delay processing on the external data signal to obtain a delayed data signal;

[0030] The fourth through unit is used to receive the external data signal and generate a through data signal;

[0031] The third inverting unit is connected to the fourth delay unit and the fourth pass-through unit respectively, and is used to generate a data control signal based on the delayed data signal and the pass-through data signal;

[0032] The fourth inverting unit, connected to the third inverting unit, is used to output the first data signal and the second data signal according to the data control signal.

[0033] In one embodiment, the third inverting unit includes:

[0034] The first data pull-up transistor array includes a third PMOS transistor and a fourth PMOS transistor. The gate of the third PMOS transistor is connected to the fourth through-cell, the source of the third PMOS transistor is used to receive the power supply voltage, and the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to the fourth delay-cell and is used to receive the delayed data signal.

[0035] The first data pull-down transistor array includes a third NMOS transistor and a fourth NMOS transistor. The gate of the third NMOS transistor is connected to the fourth through-cell, and the drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor and the fourth inverting cell, respectively, for outputting the data control signal. The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the fourth delay cell, and the source of the fourth NMOS transistor is grounded.

[0036] In one embodiment, the fourth inverting unit includes:

[0037] A first data input inverter is used to receive the data control signal and output the first data signal according to the data control signal;

[0038] The second data input inverter is used to receive the data control signal and output the second data signal according to the data control signal.

[0039] In one embodiment, the latch module includes:

[0040] The main latch is connected to the clock input module, the set / reset module, and the data input module, respectively. It is used to respond to the first clock signal and the second clock signal, latch the external data signal based on the set control signal and the reset control signal, and output the first latch signal and the second latch signal.

[0041] The latch is connected to the clock input module, the set / reset module, and the main latch respectively. It is used to respond to the first clock signal and the second clock signal, and to latch the first latch signal and the second latch signal based on the set control signal and the reset control signal, and to output the third latch signal and the fourth latch signal.

[0042] In one embodiment, the master latch includes:

[0043] A first latch circuit is connected to the clock input module, the set / reset module, and the data input module, respectively, and is used to respond to the first clock signal and the second clock signal, and output the first latch signal based on the set control signal and the reset control signal according to the first data signal and the second data signal; a second latch circuit is connected to the first latch circuit, the clock input module, the set / reset module, and the data input module, respectively, and is used to respond to the first clock signal and the second clock signal, and output the second latch signal based on the set control signal and the reset control signal according to the first data signal and the second data signal.

[0044] In one embodiment, the first latch circuit includes:

[0045] The first receiving unit is connected to the clock input module and the set / reset module, respectively.

[0046] The first interlocking unit includes a first pull-up switch group and a first pull-down switch group, which are respectively connected to the first receiving unit and the data input module;

[0047] The first transmission gate is connected to the first interlock unit and the clock input module respectively, and is used to output the first latch signal;

[0048] The second latch circuit includes:

[0049] The second receiving unit is connected to the clock input module and the set / reset module, respectively.

[0050] The second interlocking unit includes a second pull-up switch group and a second pull-down switch group, which are respectively connected to the second receiving unit, the data input module and the first latching circuit.

[0051] The second transmission gate is connected to the second interlock unit and the clock input module respectively, and is used to output the second latch signal.

[0052] In one embodiment, the slave latch includes:

[0053] The third latch circuit is connected to the clock input module, the set / reset module and the main latch respectively, and is used to respond to the first clock signal and the second clock signal, and output the third latch signal based on the set control signal and the reset control signal according to the first latch signal and the second latch signal.

[0054] The fourth latch circuit is connected to the third latch circuit, the clock input module, the set / reset module, and the main latch, respectively, and is used to respond to the first clock signal and the second clock signal, and output the fourth latch signal based on the set control signal and the reset control signal according to the first latch signal and the second latch signal.

[0055] In one embodiment, the third latch circuit includes: a third interlock unit connected to the main latch, used to output the third latch signal;

[0056] The fourth latch circuit includes a fourth interlock unit, which is connected to the data input module and the third latch circuit, and is used to output the fourth latch signal.

[0057] In one embodiment, the D flip-flop further includes an output module, the output module comprising:

[0058] A first output circuit, connected to the slave latch, is used to receive the third latch signal and output a first total output signal according to the third latch signal;

[0059] The second output circuit, connected to the slave latch, is used to receive the fourth latch signal and output a second total output signal according to the fourth latch signal.

[0060] The aforementioned D flip-flop receives an external clock signal through a clock input module and generates a delayed clock signal and a through clock signal based on the external clock signal. It can generate a first clock signal and a second clock signal, filtered to remove single-event effects, based on the delayed clock signal and the through clock signal. The data input module responds to the first and second clock signals and outputs a first data signal and a second data signal based on the external data signal. The set / reset module receives a set signal and a reset signal and generates a set control signal and a reset control signal. The latch module latches the external data signal based on the set control signal and the reset control signal. By filtering out the influence of single-event effects on the externally input clock signal through a delay unit, the effects of SET and SEU effects on the final stored signal of the D flip-flop are eliminated, enabling the D flip-flop to store the correct signal. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 This is a structural diagram of a D flip-flop according to an embodiment;

[0063] Figure 2 This is a structural diagram of a clock input module according to one embodiment;

[0064] Figure 3 The simulation waveform of a conventional D flip-flop under the SET effect;

[0065] Figure 4 To reinforce the simulated waveform of the D flip-flop under the SET effect;

[0066] Figure 5 This is a structural diagram of a set circuit according to one embodiment;

[0067] Figure 6 This is a structural diagram of a reset circuit according to one embodiment;

[0068] Figure 7 This is a structural diagram of a data input module according to one embodiment;

[0069] Figure 8 This is a structural diagram of the main latch in one embodiment;

[0070] Figure 9 The simulation waveform of a conventional D flip-flop under the SEU effect;

[0071] Figure 10 To reinforce the simulated waveform of the D flip-flop under the SEU effect;

[0072] Figure 11 This is a structural diagram of a slave latch according to one embodiment;

[0073] Figure 12 This is a structural diagram of a D flip-flop according to another embodiment;

[0074] Figure 13 This is a structural diagram of the output module of one embodiment. Detailed Implementation

[0075] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0076] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0077] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first delay unit may be referred to as a second delay unit, and similarly, a second delay unit may be referred to as a first delay unit. Both the first delay unit and the second delay unit are used for delay, but they are not delay units in the same circuit branch.

[0078] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0079] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0080] In one embodiment, such as Figure 1 As shown, a D flip-flop is provided, including a clock input module 10, a data input module 20, a set / reset module 30, and a latch module.

[0081] The clock input module 10 is used to receive an external clock signal CLK, and generate a delayed clock signal and a through clock signal based on the external clock signal, and generate a first clock signal CLK_bar and a second clock signal CLK_ based on the delayed clock signal and the through clock signal. The delayed clock signal is output with a delay relative to the through clock signal, and the delay is greater than the width of a single-particle transient pulse in the external clock signal.

[0082] Since the delayed clock signal is output with a delay relative to the direct clock signal, when a single particle is incident, the first clock signal CLK_bar and the second clock signal CLK_ generated based on the delayed clock signal and the direct clock signal will not be affected by the single particle and will maintain normal output, thus avoiding the D flip-flop from latching incorrect information based on an incorrect clock signal.

[0083] The data input module 20 is connected to the clock input module 10 and is used to receive external data signal D and respond to the first clock signal CLK_bar and the second clock signal CLK_. Under the action of the first clock signal CLK_bar and the second clock signal CLK_, it outputs the first data signal D1 and the second data signal D1_ according to the external data signal D.

[0084] The first data signal D1 and the second data signal D1_ are output in two separate paths. Under normal circumstances, they are the same signal.

[0085] The set / reset module 30 is used to receive a set signal S and a reset signal RN, generate a set control signal S_bar based on the set signal S, and generate a reset control signal RN_bar based on the reset signal RN.

[0086] Wherein, the set signal S can be "0" or "1", the set control signal S_bar is the opposite of the set signal S, and the set control signal S_bar is used to set the latch module; the reset signal RN can be "0" or "1", the reset control signal RN_bar is the opposite of the reset signal RN, and the reset control signal RN_bar is used to reset the latch module.

[0087] The latch module is connected to the clock input module 10, the data input module 20, and the set / reset module 30, respectively. It is used to receive the first clock signal CLK_bar, the second clock signal CLK, the first data signal D1, the second data signal D1_, the set control signal S_bar, and the reset control signal RN_bar, and latch the external data signal D based on the set control signal S_bar and the reset control signal RN_bar in response to the first clock signal CLK_bar and the second clock signal CLK_.

[0088] The signal ultimately latched by the latch module is determined by the first data signal D1, the second data signal D1, the set control signal S_bar, and the reset control signal RN_bar.

[0089] In this embodiment, an external clock signal is received through a clock input module, and a delayed clock signal and a through clock signal are generated based on the external clock signal. A first clock signal and a second clock signal, filtered to remove single-event effects, are generated based on the delayed clock signal and the through clock signal. A data input module responds to the first clock signal and the second clock signal, and outputs a first data signal and a second data signal based on the external data signal. A set / reset module receives a set signal and a reset signal, and generates a set control signal and a reset control signal. A latch module latches the external data signal based on the set control signal and the reset control signal. By filtering out the influence of single-event effects on the externally input clock signal through a delay unit, the influence of single-event effects on the final stored signal of the D flip-flop is eliminated, enabling the D flip-flop to store the correct signal.

[0090] In one embodiment, such as Figure 2 As shown, the clock input module 10 includes a first delay unit 101, a first direct-through unit 102, a first inverting unit 103, and a second inverting unit 104.

[0091] The first delay unit 101 is used to receive the external clock signal CLK and perform delay processing on the external clock signal CLK to obtain the delayed clock signal. The output node of the first delay unit 101 is denoted as B.

[0092] The first through unit 102 is used to receive the external clock signal CLK and generate the through clock signal.

[0093] The first pass-through unit 102 can be a wire used to transmit the external clock signal CLK. The external clock signal directly transmitted by the first pass-through unit 102 is called the pass-through clock signal. The output node of the first pass-through unit 102 is denoted as A.

[0094] The delayed clock signal is output with a delay relative to the direct clock signal. When a single particle incident causes a momentary level change in the external clock signal CLK, the signals received by nodes A and B at the same moment become inconsistent. For example, when the external clock signal CLK changes level due to a single particle, the signal received at node A also changes level. However, due to the delay of the first delay unit 101, the level change at node B arrives with a delay, resulting in different levels at nodes A and B.

[0095] The first inverting unit 103 is connected to the first delay unit 101 and the first pass-through unit 102, respectively, and is used to generate the first clock signal CLK_bar according to the delayed clock signal and the pass-through clock signal.

[0096] The first inverting unit 103 includes a first clock pull-up transistor array 1031 and a first clock pull-down transistor array 1032.

[0097] The first clock pull-up transistor array 1031 includes a first PMOS transistor M1 and a second PMOS transistor M2. The gate of the first PMOS transistor M1 is connected to the first pass-through unit 102 to receive the pass-through clock signal. The source of the first PMOS transistor M1 receives the power supply voltage VDD, and the drain of the first PMOS transistor M1 is connected to the source of the second PMOS transistor M2. The gate of the second PMOS transistor M2 is connected to the first delay unit 101 to receive the delay clock signal and is turned on or off under the action of the delay clock signal.

[0098] The first clock pull-down transistor array 1032 includes a first NMOS transistor M3 and a second NMOS transistor M4. The gate of the first NMOS transistor M3 is connected to the first pass-through unit 102 to receive the pass-through clock signal. The drain of the first NMOS transistor M3 is connected to the drain of the second PMOS transistor M2 and the second inverting unit 104, respectively, to output the first clock signal CLK_bar to the second inverting unit 104. The source of the first NMOS transistor M3 is connected to the drain of the second NMOS transistor M4. The gate of the second NMOS transistor M4 is connected to the first delay unit 101, and the source of the second NMOS transistor is grounded.

[0099] The second inverting unit 104 is connected to the first inverting unit 103 and is used to invert the first clock signal CLK_bar to generate the second clock signal CLK_.

[0100] Specifically, the second inverting unit 104 may include two MOS transistors M5 and M6. The gates of M5 and M6 are used to receive the first clock signal CLK_bar, and the drains of M5 and M6 are used to output the second clock signal CLK_ based on the first clock signal CLK_bar.

[0101] When a single particle is incident, since the clock signals at nodes A and B are different (A≠B), CLK_bar and CLK remain in the previous state. That is, the first clock signal CLK_bar and the second clock signal CLK_bar will not change with the change of the external clock signal CLK, but will maintain the previous stored state. In other words, the clock signal output by the clock input module 10 will not change with the single-particle transient change of the external clock signal D.

[0102] Comparison of simulation results for single-event transient SET Figure 3 and Figure 4 , Figure 3 The simulated waveforms of a conventional D flip-flop under the SET effect are shown below. Figure 4 The simulation waveform of the ruggedized D flip-flop provided in this application under the SET effect. From Figure 3 It can be seen that when the external clock signal CLK experiences a transient level change due to a single-particle incident event, the waveform Q_SET ultimately output by the D flip-flop also outputs an erroneous signal at the corresponding moment. Figure 4 In this process, the waveform Q_SET output by the D flip-flop is not affected by the transient level change of the external clock signal.

[0103] In this embodiment, the external clock signal is divided into two signals. One signal is directly output as a through clock signal by the first through unit, and the other signal is delayed by the first delay unit and output as a delayed clock signal. The first inverting unit generates a first clock signal based on the through clock signal and the delayed clock signal, and the second inverting unit outputs a second clock signal based on the first clock signal. If the delay of the delay unit is greater than the width of the single-event transient pulse of the external clock signal, the clock input module can shield the single-event transient signal in the clock signal, so that the first clock signal and the second clock signal are not affected by the single-event effect, thereby ensuring that the clock input module latches the correct clock signal.

[0104] In one embodiment, the set / reset module 30 includes a set circuit 301 and a reset circuit 302.

[0105] In one embodiment, such as Figure 5 As shown, the set circuit 301 is used to receive an external set signal S, wherein the external set signal S can be "0" or "1", generate a delayed set signal and a direct set signal based on the external set signal, and generate a set control signal S_bar based on the delayed set signal and the direct set signal. S_bar is the opposite of S. For example, when S = 1, then S_bar = 0.

[0106] When S = 0, then S_bar = 1.

[0107] Specifically, the set circuit 301 includes a second delay unit 3011, a second pass-through unit 3012, a first set pull-up transistor array 3013, and a first set pull-down transistor array 3014.

[0108] The second delay unit 3011 is used to receive the external set signal S and perform delay processing on the external set signal S to obtain the delayed set signal.

[0109] The second pass-through unit 3012 is used to receive the external set signal S and generate the pass-through set signal. The second pass-through unit 3012 can be a wire, and the external set signal directly transmitted by the second pass-through unit 3012 is called the pass-through set signal. The delayed set signal is output with a delay relative to the pass-through set signal.

[0110] The first set pull-up transistor array 3013 and the first set pull-down transistor array 3014 are respectively connected to the second delay unit 3011 and the second pass-through unit 3012, and are used to generate the set control signal S_bar according to the delayed set signal and the pass-through set signal.

[0111] The first set pull-up transistor array 3013 includes two MOS transistors, M7 and M8. The gate of M7 is connected to the second pass-through unit 3012 to receive the pass-through set signal; the source of M7 receives the power supply voltage VDD, and the drain of M7 is connected to the source of M8. The gate of M8 is connected to the second delay unit 3011 and receives the delayed set signal; the drain of M8 outputs the set control signal S_bar.

[0112] The structure of the set circuit 301 is similar to that of the clock input module 10, and its anti-single-event effect principle is also similar to that of the clock input module 10, which will not be elaborated here.

[0113] In this embodiment, the external set signal is split into two inputs. One input is directly output as a pass-through set signal by the second pass-through unit, and the other input is output as a delayed set signal after being delayed by the second delay unit. The first set pull-up transistor array and the first set pull-down transistor array generate a set control signal based on the pass-through set signal and the delayed set signal. In the event of a single-particle incident event, the set control signal does not change with the level of the externally input set signal, so that the set control signal is not affected by the single-particle effect, thereby ensuring that the set circuit performs set control on the latch module based on the correct set control signal.

[0114] In one embodiment, such as Figure 6 As shown, the reset circuit 302 is used to receive an external reset signal RN, which can be "0" or "1". Based on the external reset signal RN, it generates a delayed reset signal and a direct reset signal, and generates a reset control signal RN_bar based on the delayed reset signal and the direct reset signal. RN_bar is the opposite of RN. For example, when RN = 1, then RN_bar = 0; when RN = 0, then RN_bar = 1.

[0115] Specifically, the reset circuit 302 includes a third delay unit 3021, a third through unit 3022, a first reset pull-up transistor array 3023, and a first reset pull-down transistor array 3024.

[0116] The third delay unit 3021 is used to receive the external reset signal RN and perform delay processing on the external reset signal RN to obtain the delayed reset signal.

[0117] The third pass-through unit 3022 is used to receive the external reset signal RN and generate the pass-through reset signal. The third pass-through unit 3022 can be a wire. The delayed reset signal is output with a delay relative to the pass-through reset signal.

[0118] The first reset pull-up transistor array 3023 and the first reset pull-down transistor array 3024 are respectively connected to the third delay unit 3021 and the third pass-through unit 3022, and are used to generate the reset control signal RN_bar according to the delayed reset signal and the pass-through reset signal.

[0119] The first reset pull-up array 3023 includes two MOS transistors, M11 and M12. The gate of M11 is connected to the third pass-through unit 3022 to receive the pass-through reset signal; the source of M11 receives the power supply voltage VDD, and the drain of M11 is connected to the source of M12. The gate of M12 is connected to the third delay unit 3021 and receives the delayed reset signal; the drain of M12 outputs the reset control signal S_bar.

[0120] The structure of the reset circuit 302 is similar to that of the clock input module 10, and its anti-single-event effect principle is also similar to that of the clock input module 10, which will not be elaborated here.

[0121] In this embodiment, the external reset signal is split into two inputs. One input is a direct-through reset signal output by the third through unit, and the other input is a delayed reset signal output by the third delay unit. The first reset pull-up array and the first reset pull-down array generate a reset control signal based on the direct-through reset signal and the delayed reset signal. In the event of a single-event event, the reset control signal does not change with the level of the externally input reset signal, so that the reset control signal is not affected by the single-event effect, thereby ensuring that the reset circuit performs reset control on the latch module based on the correct reset control signal.

[0122] In one embodiment, such as Figure 7 As shown, the data input module 20 includes a fourth delay unit 201, a fourth pass-through unit 202, a third inverting unit 203, and a fourth inverting unit 204.

[0123] The fourth delay unit 201 is used to receive the external data signal D and perform delay processing on the external data signal D to obtain a delayed data signal.

[0124] The fourth through unit 202 is used to receive the external data signal D and generate the through data signal. The delayed data signal is output with a delay relative to the through data signal.

[0125] The third inverting unit 203 is connected to the fourth delay unit 201 and the fourth pass-through unit 202, respectively, and is used to generate a data control signal D' based on the delayed data signal and the pass-through data signal. The data control signal D' is opposite to the external data signal D.

[0126] Specifically, the third inverting unit 203 includes a first data pull-up transistor array 2031 and a first data pull-down transistor array 2032.

[0127] The first data pull-up transistor array 2031 includes a third PMOS transistor M15 and a fourth PMOS transistor M16. The gate of the third PMOS transistor M15 is connected to the fourth pass-through unit 202, the source of the third PMOS transistor M15 is used to receive the power supply voltage VDD, and the drain of the third PMOS transistor M15 is connected to the source of the fourth PMOS transistor M16. The gate of the fourth PMOS transistor M16 is connected to the fourth delay unit 201 and is used to receive the delayed data signal.

[0128] The first data pull-down transistor array 2032 includes a third NMOS transistor M17 and a fourth NMOS transistor M18. The gate of the third NMOS transistor M17 is connected to the fourth pass-through unit 202, and the drain of the third NMOS transistor M17 is connected to the drain of the fourth PMOS transistor M18 and the fourth inverting unit 204, respectively, for outputting the data control signal D' to the fourth inverting unit 204. The source of the third NMOS transistor M17 is connected to the drain of the fourth NMOS transistor M18, the gate of the fourth NMOS transistor M18 is connected to the fourth delay unit 201, and the source of the fourth NMOS transistor M18 is grounded.

[0129] The fourth inverting unit 204, connected to the third inverting unit 203, is used to output the first data signal D1 and the second data signal D1_ according to the data control signal D'. The fourth inverting unit 204 splits the data control signal D' into two signals, and outputs the corresponding first data signal D1 or the second data signal D1_ according to one of the signals. When the data input module 20 is working normally, D1 and D1_ are the same signal.

[0130] Specifically, the fourth inverter unit 204 includes a first data input inverter 2041 and a second data input inverter 2042.

[0131] The first data input inverter 2041 is used to receive the data control signal D' and output the first data signal D1 according to the data control signal D'.

[0132] The second data input inverter 2042 is used to receive the data control signal D' and output the second data signal D1_ according to the data control signal D'.

[0133] The data input module 20 can be used to correct erroneous signals caused by single-event transient effects in the D flip-flop, and its principle is similar to that of the clock input module 10.

[0134] In this embodiment, the external data signal is split into two inputs. One input is directly output as a pass-through data signal by the fourth pass-through unit, and the other input is delayed as a delayed data signal by the fourth delay unit. The third inverting unit generates a data control signal based on the delayed data signal and the pass-through data signal, and the fourth inverting unit generates a first data signal and a second data signal based on the data feeder signal. This ensures that the output data signal has two output channels and is not affected by single-event effects, thereby guaranteeing that the D flip-flop latches the data based on the correct data signal.

[0135] In one embodiment, please continue to refer to Figure 1 The latch module includes a master latch 40 and a slave latch 50.

[0136] The main latch 40 is connected to the clock input module 10, the set / reset module 30, and the data input module 20, respectively. In response to the first clock signal CLK_bar and the second clock signal CLK_, when the rising edge of the clock signal arrives, it latches the external data signal D based on the set control signal S_bar and the reset control signal RN_bar, and outputs the first latch signal D2 and the second latch signal D2_.

[0137] The latch 50 is connected to the clock input module 10, the set / reset module 30, and the main latch 40, respectively. It is used to respond to the first clock signal CLK_bar and the second clock signal, and to latch the first latch signal D2 and the second latch signal D2_ based on the set control signal S_bar and the reset control signal RN_bar, and output the third latch signal D3, D3bar and the fourth latch signal D3_, D3_bar.

[0138] In one embodiment, such as Figure 8 As shown, the main latch 40 includes a first latch circuit 401 and a second latch circuit 402.

[0139] The first latch circuit 401 is connected to the clock input module 10, the set / reset module 30, and the first data input inverter 2041, respectively. It is used to respond to the first clock signal CLK_bar and the second clock signal CLK_, and output the first latch signal D2 based on the set control signal S_bar and the reset control signal RN_bar according to the first data signal D1 and the second data signal D1_.

[0140] The first latch circuit 401 includes a first receiving unit 4011, a first interlocking unit 4012, and a first transmission gate 4013.

[0141] The first receiving unit 4011 includes MOS transistors M19, M24, M23, and M28, which are respectively connected to the clock input module 10 and the set / reset module 30. It is used to receive the first clock signal, the second clock signal, the set control signal, and the reset control signal, and respond to the first clock signal, the second clock signal, the set control signal, and the reset control signal.

[0142] The first interlocking unit 4012 includes a first pull-up switch group and a first pull-down switch group. The first pull-up switch group includes M20 and M25, which are respectively connected to the first receiving unit 4011 and the data input module 20, and are used to latch the first data signal D1 and the second data signal D1_ according to the clock signals CLK_bar and CLK_ and the set and reset control signals S_bar and RN_bar.

[0143] The first transmission gate 4013 is connected to the first interlock unit 4012 and the clock input module 10 respectively. When the first transmission gate 4013 is open, it is used to output the first latch signal D2.

[0144] The second latch circuit 402 is connected to the first latch circuit 401, the clock input module 10, the set / reset module 30, and the second data input inverter 2042, respectively. It is used to respond to the first clock signal CLK_bar and the second clock signal CLK_, and output the second latch signal D2_ based on the set control signal S_bar and the reset control signal RN_bar according to the first data signal D1 and the second data signal D1_.

[0145] The second latch circuit 402 includes a second receiving unit 4021, a second interlocking unit 4022, and a second transmission gate 4023.

[0146] The second receiving unit 4021 includes MOS transistors M19', M24', M23', and M28', which are respectively connected to the clock input module 10 and the set / reset module 30. It is used to receive the first clock signal, the second clock signal, the set control signal, and the reset control signal, and respond to the first clock signal, the second clock signal, the set control signal, and the reset control signal.

[0147] The second interlock unit 4022 includes a second pull-up switch group and a second pull-down switch group. The second pull-up switch group includes M20' and M25', which are respectively connected to the second receiving unit 4021, the data input module 20 and the first latching circuit 401, and are used to latch the first data signal D1 and the second data signal D1_ according to the clock signals CLK_bar and CLK_ and the set and reset control signals S_bar and RN_bar.

[0148] The second transmission gate 4023 is connected to the second interlock unit 4022 and the clock input module 10 respectively. When the second transmission gate 4023 is open, it is used to output the second latch signal D2_.

[0149] The operating logic of the master latch 40 is as follows:

[0150] When the set signal S = "0" and the reset signal RN = "1", then S_bar = "1" and RN_bar = "0". When the rising edge of the clock signal arrives, the input data signals D1 and D1_ are latched, and at the same time the transmission gate opens. The data of the master latch is output to the slave latch through two paths D2 and D2_. At this time, D2 = D1.

[0151] When the set signal S = "1" and the reset signal RN = "0", regardless of the clock signal and data signal, the outputs of the main latches D2 and D2_ remain unchanged from the previous state, and D2 = D2.

[0152] The single-event upset principle of the main latch 40 will be explained below by combining the structures of the first latch circuit 401 and the second latch circuit 402.

[0153] The first interlocking unit 4012 of the first latching circuit 401 includes two latching nodes D1 and E, and the second interlocking unit 4022 of the second latching circuit 402 includes two latching nodes D1_ and F.

[0154] Taking the initial state as D1 = D1_ = 1, S_bar = "1" and RN_bar = "0" as an example, when the rising edge of the clock signal arrives, that is, when CLK_bar = 0 and CLK_ = 1, M25, M25', M21, M22, M22', and M26' are closed, and M24, M24', M28, M28', M19, M19', M23, M23', M27, M27', M26, M20, M20', and M21' are open. Then, the latch node E = F = 0, and the states of E and F are latched and remain unchanged.

[0155] When a single particle is incident on the sensitive node of the D flip-flop, it causes the off transistor M22' to turn on momentarily, pulling D1_ down to 0, which in turn turns on M21. However, since M22 is still off at this time, D1 remains 1 and unchanged. Similarly, after D1_ becomes 0, it causes M27' to turn off, but since M25' is still in the ratio state, the F state remains unchanged.

[0156] Therefore, by connecting M21 and M26 in the first pull-down switch group to the second latch circuit 402 and controlling them with the data signal D1_ of the second latch circuit, and connecting M21' and M26' in the second pull-down switch group to the first latch circuit 401 and controlling them with the data signal D1 of the first latch circuit 401, it is possible to ensure that when one of the signals, such as D1_, changes its level instantaneously due to the single-event upset effect, the states of the other three latch nodes D1, E, and F will not change. Consequently, the first latch signal D2 and the second latch signal D2_ output by the first output gate 4013 and the second output gate 4023 will not change, thus achieving the effect of resisting the single-event upset effect.

[0157] Comparison of simulation results for single-event upset (SEU) Figure 9 and Figure 10 , Figure 9 The simulated waveforms of a conventional D flip-flop under the SEU effect are shown below. Figure 10 Simulation waveforms of the ruggedized D flip-flop provided in this application under the SEU effect. From Figure 9 It can be seen that when a single-particle incident event causes the logic state of the internal node of the latch to flip (from "1" to "0"), the waveform Q_SEU finally output by the D flip-flop also outputs an erroneous signal at the corresponding moment. Figure 10 In this case, when a single particle is incident, the logic state of the internal node of the latch undergoes an instantaneous flip and then returns to the correct state, and the waveform Q_SEU output by the D flip-flop is not affected.

[0158] In one embodiment, such as Figure 11 As shown, the latch 50 includes a third latch circuit 501 and a fourth latch circuit 502.

[0159] The third latch circuit 501 is connected to the clock input module 10, the set / reset module 30, and the main latch 40, respectively. It is used to respond to the first clock signal CLK_bar and the second clock signal CLK_, and output the third latch signal D3 and D3_ based on the set control signal S_bar and the reset control signal RN_bar according to the first latch signal D2 and the second latch signal D2_.

[0160] The third latch circuit 501 includes a third interlock unit 5011, which is connected to the main latch 40 and is used to output the third latch signals D3 and D3_. Its specific working principle is similar to that of the first interlock unit 4012 and the second interlock unit 4022 in the main latch 40, and will not be described in detail here.

[0161] The fourth latch circuit 502 is connected to the third latch circuit 501, the clock input module 10, the set / reset module 30, and the main latch 40, respectively. It is used to respond to the first clock signal CLK_bar and the second clock signal CLK_, and output the fourth latch signal D3bar and D3_bar based on the set control signal S_bar and the reset control signal RN_bar according to the first latch signal D2 and the second latch signal D2_.

[0162] The fourth latch circuit 502 includes a fourth interlock unit 5021, which is connected to the main latch 40 and is used to output the fourth latch signals D3bar and D3_bar. Its specific working principle is similar to that of the first interlock unit 4012 and the second interlock unit 4022 in the main latch 40, and will not be described in detail here.

[0163] In this embodiment, by setting up two branches to receive the first latch signal and the second latch signal respectively, and by using the third interlock unit and the fourth interlock unit to output the third latch signal and the fourth latch signal respectively based on the first latch signal and the second latch signal, the effect of resisting single-event upset effect is achieved.

[0164] In one embodiment, such as Figure 12 As shown, the D flip-flop also includes an output module 60. The structure of the output module 60 is as follows: Figure 13 As shown, the output module 60 includes a first output circuit 601 and a second output circuit 602.

[0165] The first output circuit 601 is connected to the slave latch 50 and is used to receive the third latch signals D3 and D3_ and output the first total output signal Q according to the third latch signals D3 and D3_.

[0166] The working principle of the first output circuit 601 is as follows: if D3_ = D3, then Q = D3; if D3_ ≠ D3, then Q remains unchanged from the previous state.

[0167] The second output circuit 602 is connected to the slave latch 50 and is used to receive the fourth latch signals D3bar and D3_bar and output the second total output signal QBAR according to the fourth latch signals D3bar and D3_bar.

[0168] The working principle of the second output circuit 602 is as follows: if D3bar = D3_bar, then QBAR = D3bar; if D3bar ≠ D3_bar, then QBAR remains unchanged from the previous state.

[0169] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0170] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0171] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A D flip-flop, characterized in that, include: A clock input module is used to receive an external clock signal, generate a delayed clock signal and a through clock signal based on the external clock signal, and generate a first clock signal and a second clock signal based on the delayed clock signal and the through clock signal, wherein the delayed clock signal is output with a delay relative to the through clock signal, and the delay is greater than the width of a single-particle transient pulse in the external clock signal; A data input module, connected to the clock input module, is used to receive external data signals and, in response to the first clock signal and the second clock signal, output a first data signal and a second data signal respectively according to the external data signals. The set / reset module is used to receive a set signal and a reset signal, generate a set control signal based on the set signal, and generate a reset control signal based on the reset signal. The latch module is connected to the clock input module, the data input module, and the set / reset module, respectively, and is used to respond to the first clock signal and the second clock signal, and to latch the external data signal based on the set control signal and the reset control signal.

2. The D flip-flop according to claim 1, characterized in that, The clock input module includes: The first delay unit is used to receive the external clock signal and perform delay processing on the external clock signal to obtain the delayed clock signal; The first through unit is used to receive the external clock signal and generate the through clock signal; The first inverting unit is connected to the first delay unit and the first pass-through unit respectively, and is used to generate the first clock signal according to the delayed clock signal and the pass-through clock signal; The second inverting unit is connected to the first inverting unit and is used to invert the first clock signal to generate the second clock signal.

3. The D flip-flop according to claim 2, characterized in that, The first inverting unit includes: The first clock pull-up transistor array includes a first PMOS transistor and a second PMOS transistor. The gate of the first PMOS transistor is connected to the first through-cell, the source of the first PMOS transistor is used to receive the power supply voltage, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The gate of the second PMOS transistor is connected to the first delay-cell array and is used to receive the delayed clock signal. The first clock pull-down transistor array includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor is connected to the first pass-through unit, and the drain of the first NMOS transistor is connected to the drain of the second PMOS transistor and the second inverting unit, respectively, for outputting the first clock signal. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the first delay unit, and the source of the second NMOS transistor is grounded.

4. The D flip-flop according to claim 1, characterized in that, The position reset module includes: A set circuit is used to receive an external set signal, generate a delayed set signal and a direct set signal based on the external set signal, and generate a set control signal based on the delayed set signal and the direct set signal. A reset circuit is used to receive an external reset signal, generate a delayed reset signal and a direct reset signal based on the external reset signal, and generate a reset control signal based on the delayed reset signal and the direct reset signal.

5. The D flip-flop according to claim 4, characterized in that, The setting circuit includes: The second delay unit is used to receive the external set signal and perform delay processing on the external set signal to obtain the delayed set signal. The second pass-through unit is used to receive the external set signal and generate the pass-through set signal; The first set pull-up transistor array and the first set pull-down transistor array are respectively connected to the second delay unit and the second pass-through unit, and are used to generate the set control signal according to the delayed set signal and the pass-through set signal.

6. The D flip-flop according to claim 4, characterized in that, The reset circuit includes: The third delay unit is used to receive the external reset signal and perform delay processing on the external reset signal to obtain the delayed reset signal; The third through unit is used to receive the external reset signal and generate the through reset signal; The first reset pull-up transistor array and the first reset pull-down transistor array are respectively connected to the third delay unit and the third pass-through unit, and are used to generate the reset control signal according to the delayed reset signal and the pass-through reset signal.

7. The D flip-flop according to claim 1, characterized in that, The data input module includes: The fourth delay unit is used to receive the external data signal and perform delay processing on the external data signal to obtain a delayed data signal; The fourth through unit is used to receive the external data signal and generate a through data signal; The third inverting unit is connected to the fourth delay unit and the fourth pass-through unit respectively, and is used to generate a data control signal based on the delayed data signal and the pass-through data signal; The fourth inverting unit, connected to the third inverting unit, is used to output the first data signal and the second data signal according to the data control signal.

8. The D flip-flop according to claim 7, characterized in that, The third inverting unit includes: The first data pull-up transistor array includes a third PMOS transistor and a fourth PMOS transistor. The gate of the third PMOS transistor is connected to the fourth through-cell, the source of the third PMOS transistor is used to receive the power supply voltage, and the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to the fourth delay-cell unit and is used to receive the delayed data signal. The first data pull-down transistor array includes a third NMOS transistor and a fourth NMOS transistor. The gate of the third NMOS transistor is connected to the fourth through-cell, and the drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor and the fourth inverting cell, respectively, for outputting the data control signal. The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the fourth delay cell, and the source of the fourth NMOS transistor is grounded.

9. The D flip-flop according to claim 7, characterized in that, The fourth inverting unit includes: A first data input inverter is used to receive the data control signal and output the first data signal according to the data control signal; The second data input inverter is used to receive the data control signal and output the second data signal according to the data control signal.

10. The D flip-flop according to claim 1, characterized in that, The latch module includes: The main latch is connected to the clock input module, the set / reset module, and the data input module, respectively. It is used to respond to the first clock signal and the second clock signal, latch the external data signal based on the set control signal and the reset control signal, and output the first latch signal and the second latch signal. The latch is connected to the clock input module, the set / reset module, and the main latch respectively. It is used to respond to the first clock signal and the second clock signal, and to latch the first latch signal and the second latch signal based on the set control signal and the reset control signal, and to output the third latch signal and the fourth latch signal.

11. The D flip-flop according to claim 10, characterized in that, The master latch includes: The first latch circuit is connected to the clock input module, the set / reset module and the data input module respectively, and is used to respond to the first clock signal and the second clock signal, and output the first latch signal based on the set control signal and the reset control signal according to the first data signal and the second data signal. The second latch circuit is connected to the first latch circuit, the clock input module, the set / reset module, and the data input module, respectively, and is used to respond to the first clock signal and the second clock signal, and output the second latch signal based on the set control signal and the reset control signal according to the first data signal and the second data signal.

12. The D flip-flop according to claim 11, characterized in that, The first latch circuit includes: The first receiving unit is connected to the clock input module and the set / reset module, respectively. The first interlocking unit includes a first pull-up switch group and a first pull-down switch group, which are respectively connected to the first receiving unit and the data input module; The first transmission gate is connected to the first interlock unit and the clock input module respectively, and is used to output the first latch signal; The second latch circuit includes: The second receiving unit is connected to the clock input module and the set / reset module, respectively. The second interlocking unit includes a second pull-up switch group and a second pull-down switch group, which are respectively connected to the second receiving unit, the data input module and the first latching circuit; the second transmission gate is respectively connected to the second interlocking unit and the clock input module, and is used to output the second latching signal.

13. The D flip-flop according to claim 10, characterized in that, The slave latch includes: The third latch circuit is connected to the clock input module, the set / reset module and the main latch respectively, and is used to respond to the first clock signal and the second clock signal, and output the third latch signal based on the set control signal and the reset control signal according to the first latch signal and the second latch signal. The fourth latch circuit is connected to the third latch circuit, the clock input module, the set / reset module, and the main latch, respectively, and is used to respond to the first clock signal and the second clock signal, and output the fourth latch signal based on the set control signal and the reset control signal according to the first latch signal and the second latch signal.

14. The D flip-flop according to claim 13, characterized in that, The third latch circuit includes: The third interlock unit is connected to the main latch and is used to output the third latch signal; The fourth latch circuit includes: The fourth interlock unit is connected to the data input module and the third latch circuit, and is used to output the fourth latch signal.

15. The D flip-flop according to claim 10, characterized in that, The D flip-flop further includes an output module, which includes: A first output circuit is connected to the latch module and is used to receive the third latch signal and output a first total output signal according to the third latch signal. The second output circuit is connected to the latch module and is used to receive the fourth latch signal and output the second total output signal according to the fourth latch signal.

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