Clock data calibration circuit

Abstract

The present invention provides a clock data correction circuit. The clock data correction circuit includes a first comparator, a multi-phase clock generator, multiple samplers, multiple data comparators, and a data selector. The first comparator compares first input data and second input data to generate a data signal. The multi-phase clock generator generates multiple clock signals, which are divided into multiple clock groups. The samplers sample the data signals according to the clock groups to generate multiple first sampled data signal groups. The data comparators sample the first sampled data groups according to multiple selected clocks to generate multiple second sampled data groups. Each data comparator generates multiple status flags based on the changing states of the multiple second sampled data. The data selector generates multiple output data signals based on the status flags.

Description

Technical Field

[0001] The present invention relates to a clock data correction circuit, and more particularly to a clock data correction circuit capable of improving skew tolerance between frequency and data. Background Art

[0002] Low Voltage Differential Signaling (LVDS) is a technology that can provide high-efficiency data transmission. In the known technical field, in order to overcome the problem of data errors that may be caused by the skew between the clock signal and the data signal, a clock data correction circuit with a complex structure is often provided. In addition, in the clock data correction circuit of the known technology, it is often necessary to set a reference data signal, provide a full-rate multi-phase clock, and perform the clock data correction action in a closed-loop manner. These requirements make the clock data correction circuit of the known technology often require relatively high power consumption, a relatively large circuit area and a relatively low response speed. Therefore, how to improve the performance of the clock data correction circuit has become an important issue. Summary of the Invention

[0003] The present invention is directed to a clock data correction circuit capable of improving the skew tolerance between clock data.

[0004] According to an embodiment of the present invention, a clock data correction circuit includes a first comparator, a multi-phase clock generator, multiple samplers, multiple data comparators, and a data selector. The first comparator generates a data signal by comparing first input data and second input data. The multi-phase clock generator generates multiple clock signals having different phases by comparing the first input clock signal and the second input clock signal, and the clock signals are divided into multiple clock groups. The samplers sample the data signal according to the clock groups to generate multiple first sampled data signal groups. The data comparators sample the first sampled data groups according to multiple selected clocks in the clock signal to generate multiple second sampled data groups. Each data comparator generates multiple status flags based on the change status of the multiple second sampled data in each second sampled data group. The data selector selects the second sampled data according to the status flags to generate multiple output data signals.

[0005] According to an embodiment of the present invention, a clock data correction circuit utilizes additional data samples for data comparison and, by identifying consecutive sampled data, finds the sampled data corresponding to the optimal clock signal. This clock data correction circuit does not require a complex circuit architecture, reference data, a closed-loop architecture, or a full-rate, multi-phase clock signal. This effectively reduces power consumption and circuit area, improving system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0007] Figure 1 is a schematic diagram of a clock data correction circuit according to an embodiment of the present invention;

[0008] Figure 2 Schematic diagram of an implementation of a sampler in a clock data correction circuit according to an embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of an implementation of a data comparator in a clock data correction circuit according to an embodiment of the present invention;

[0010] Figure 4A Schematic diagram of an implementation of a data selector in a clock data correction circuit according to an embodiment of the present invention;

[0011] Figure 4B The implementation details of the multiplexer in the data selector of the embodiment of the present invention are as follows;

[0012] Figure 5A as well as Figure 5B 1. This is an operational waveform diagram of the clock data correction circuit according to an embodiment of the present invention when the clock signal phase lags behind;

[0013] Figure 6A as well as Figure 6B 1 is an operational waveform diagram of the clock data correction circuit according to an embodiment of the present invention when the clock signal phase is advanced;

[0014] Figure 7 is a schematic diagram of a clock data correction circuit according to another embodiment of the present invention;

[0015] Figure 8 FIG. 1 is a schematic diagram illustrating an implementation of a multi-phase clock generator in a clock and data correction circuit according to an embodiment of the present invention.

[0016] Explanation of Figure Numbers

[0017] 100: clock data correction circuit;

[0018] 110: Comparator;

[0019] 120: Multi-phase clock generator;

[0020] 131-137: sampler;

[0021] 141~147: data comparator;

[0022] 150: data selector;

[0023] DATA_INP, DATA_INN: input data;

[0024] DATA: data signal;

[0025] CLK_INP, CLK_INN: input clock;

[0026] CK[27:0]: clock signal;

[0027] Q[27:0]: first sampling data signal;

[0028] RQ[3:1]~RQ[27:25]: second sampling data;

[0029] S_0[2:0]~S_6[2:0]: status flag;

[0030] SQ[7:1]: output data signal. DETAILED DESCRIPTION

[0031] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0032] Please refer to Figure 1 , Figure 1 Schematic diagram of a clock data correction circuit according to an embodiment of the present invention. The clock data correction circuit 100 includes a comparator 110, a multi-phase clock generator 120, samplers 131-137, data comparators 141-147, and a data selector 150. The comparator 110 generates a data signal DATA by comparing input data DATA_INP and input data DATA_INN. The input data DATA_INP and the input data DATA_INN may be differential signals. The comparator 110 may be implemented by an operational amplifier, with the positive input terminal of the operational amplifier receiving the input data DATA_INP and the negative input terminal of the operational amplifier receiving the input data DATA_INN. The output terminal of the operational amplifier generates the data signal DATA.

[0033] The multi-phase clock generator 120 receives an input clock CLK_INP and an input clock CLK_INN, wherein the input clock CLK_INP and the input clock CLK_INN correspond to the input data DATA_INP and the input data DATA_INN, respectively. The multi-phase clock generator 120 generates a plurality of clock signals CK[27:0] having different phases by comparing the input clock CLK_INP and the input clock signal CLK_INN.

[0034] In this embodiment, the clock signals CK[27:0] can be divided into multiple clock groups. Among them, the clock signals CK[4:0] can be the first clock group, the clock signals CK[8:4] can be the second clock group, and so on. The clock signals CK[27:24] can be divided into the seventh clock group together with CK[0].

[0035] The samplers 131 to 137 correspond to the seven clock groups mentioned above, respectively. The samplers 131 to 137 receive the seven clock groups mentioned above, respectively, and receive the data signal DATA together. The samplers 131 to 137 respectively generate a plurality of first sampled data signals Q[27:0] by sampling the data signal DATA according to the clock groups mentioned above, wherein the first sampled data Q[27:0] can be divided into a plurality of sampled data signal groups. The sampled data signal group generated by the sampler 131 includes the first sampled data Q[4:0], and the first sampled data Q[4:0] corresponds to the clock signal CK[4:0], respectively. The sampled data signal group generated by the sampler 132 includes the first sampled data Q[8:4], and the first sampled data Q[8:4] corresponds to the clock signal CK[8:4]. The rest are similar, and the sample data signal group generated by the sampler 137 includes the first sample data Q[0] and Q[27:24]. The first sample data Q[0] and Q[27:24] correspond to the clock signals CK[0] and CK[27:24] respectively.

[0036] Data comparators 141-147 correspond to samplers 131-137, respectively. Data comparators 141-147 receive the sampled data signal groups generated by samplers 131-137, respectively. Each of data comparators 141-147 also receives a selected clock signal from clock signals CK[27:0]. Data comparators 141-147 sample the corresponding sampled data signal groups based on the multiple selected clock signals received, and generate multiple second sampled data groups. The second sampled data groups include multiple second sampled data.

[0037] Furthermore, each of the data comparators 141-147 generates a plurality of status flags S_0[2:0]-S_6[2:0] based on the change status of the plurality of second sampled data groups generated by the data comparators 141-147. The data comparators 141-147 output portions of the second sampled data RQ[3:1]-RQ[27:25] and the status flags S_0[2:0]-S_6[2:0], respectively.

[0038] The data selector 150 is coupled to the data comparators 141 - 147 and receives the second sampled data RQ[3:1] - RQ[27:25] and the status flags S_0[2:0] - S_6[2:0]. The data selector 150 selects the second sampled data RQ[3:1] - RQ[27:25] according to the status flags S_0[2:0] - S_6[2:0] to generate a plurality of output data signals SQ[7:1].

[0039] It is worth noting that Figure 1 The numbers of samplers 131-137, data comparators 141-147, first sampled data signals Q[27:0], status flags S_0[2:0]-S_6[2:0], clock signals CK[27:0], and second sampled data RQ[3:1]-RQ[27:25] are just examples for illustration purposes. A person skilled in the art can Figure 1 In the implementation example, the quantity of the above components and signals can be changed according to the needs, and there is no fixed limit.

[0040] Please refer to the following Figure 2 , Figure 2 Schematic diagram of an implementation of a sampler in a clock data correction circuit according to an embodiment of the present invention. The sampler 200 includes a plurality of triggers DFF1 to DFF5. The sampler 200 of this embodiment can be Figure 1 The samplers of the Xth stage in the samplers 131-137 of the embodiment, where X is an integer not less than 0, each flip-flop DFF1-DFF5 has a data terminal D, a clock terminal CKE, and an output terminal O. The data terminals D of the flip-flops DFF1-DFF5 collectively receive a data signal DATA; the clock terminals CKE of the flip-flops DFF1-DFF5 respectively receive clock signals CK[4X]-CK[4X+4], where the clock signals CK[4X]-CK[4X+4] belong to the same clock group; and the output terminals O of the flip-flops DFF1-DFF5 respectively generate first sampled data signals Q[4X]-Q[4X+4], where the first sampled data signals belong to the same sampled data group Q[4X]-Q[4X+4].

[0041] Please refer to Figure 3 , Figure 3Schematic diagram of the implementation of the data comparator in the clock data correction circuit of the embodiment of the present invention. The data comparator 300 includes a plurality of flip-flops DFF1 to DFF5 and a logic circuit 310. The data comparator 300 of this embodiment can be Figure 1 The data comparators of the Xth stage in the data comparators 141-147 of the embodiment, where X is an integer not less than 0, each flip-flop DFF1-DFF5 has a data terminal D, a clock terminal CK, and an output terminal O. The data terminals D of the flip-flops DFF1-DFF5 receive the first sampled data signals Q[4X]-Q[4X+4], respectively; the clock terminals CKE of the flip-flops DFF1-DFF5 receive the clock signal CK[4X+16] in common; and the output terminals O of the flip-flops DFF1-DFF5 generate the second sampled data RQ[4X]-RQ[4X+4], respectively.

[0042] In this embodiment, the clock signal CK[4X+16] commonly received by the clock terminals CKE of flip-flops DFF1-DFF5 is a selected clock signal selected from a plurality of clock signals provided by a multi-phase clock generator. In response to the received first sampled data signals Q[4X]-Q[4X+4], the selected clock signal can be set to generate a sampling point (transition) at approximately 1 / 2 of the period of the first sampled data signals Q[4X]-Q[4X+4].

[0043] When the index value 4X+16 in the clock signal CK[4X+16] is greater than or equal to the maximum index value, the maximum index value is subtracted from 4X+16, and then 1 is subtracted to generate a new index value. For example, when the maximum index value is 27, and X = 3, 4X+16 = 28, which is greater than 27. Therefore, 28 - 27 - 1 is required to generate a new index value of 0.

[0044] On the other hand, the second sampled data RQ[4X] to RQ[4X+4] are transmitted to the logic circuit 310. The logic circuit 310 is used to calculate the change states of the second sampled data RQ[4X] to RQ[4X+4], three consecutive second sampled data, and generate state flags S[0] to S[2] accordingly. In this embodiment, the logic circuit 310 respectively calculates the change states of the second sampled data RQ[4X] to RQ[4X+2], the change states of the second sampled data RQ[4X+1] to RQ[4X+3], and the change states of the second sampled data RQ[4X+2] to RQ[4X+4], and generates state flags S[0] to S[2] respectively. The relationship between the second sampled data RQ[4X] to RQ[4X+4] and the state flags S[0] to S[2] is shown in Table 1 below:

[0045] Table 1:

[0046]

[0047]

[0048]

[0049] In Table 1 above, the state flag S[0] is generated according to the change state of the second sampled data RQ[4X], RQ[4X+1], and RQ[4X+2]. When the second sampled data RQ[4X], RQ[4X+1], and RQ[4X+2] are all equal, the state flag S[0] is equal to logic 1. When the second sampled data RQ[4X], RQ[4X+1], and RQ[4X+2] are not equal, the state flag S[0] is equal to logic 0. The status flag S[1] is generated according to the changing state of the second sampling data RQ[4X+1], RQ[4X+2], and RQ[4X+3]. When the second sampling data RQ[4X+1], RQ[4X+2], and RQ[4X+3] are all equal, the status flag S[1] is equal to logic 1. When the second sampling data RQ[4X+1], RQ[4X+2], and RQ[4X+3] are not all equal, the status flag S[1] is equal to logic 0. The status flag S[2] is generated according to the changing state of the second sampling data RQ[4X+2], RQ[4X+3], and RQ[4X+4]. When the second sampling data RQ[4X+2], RQ[4X+3], and RQ[4X+4] are all equal, the status flag S[2] is equal to logic 1. When the second sampling data RQ[4X+2], RQ[4X+3], and RQ[4X+4] are not equal, the status flag S[2] is equal to logic 0.

[0050] In terms of hardware architecture, logic circuit 310 includes exclusive OR gates (also known as "XOR gates") XOR1-XOR6 and NOR gates NO1-NO3. Exclusive OR gate XOR1 compares the second sample data RQ[4X] and RQ[4X+1], while exclusive OR gate XOR2 compares the second sample data RQ[4X+1] and RQ[4X+2]. NOR gate NO1 generates a state flag S[0] equal to logic 0 when the second sample data RQ[4X] differs from RQ[4X+1] and / or the two sample data RQ[4X+1] differ from RQ[4X+2]. Conversely, when the second sample data RQ[4X]-RQ[4X+2] are identical, NOR gate NO1 generates a state flag S[0] equal to logic 1. In addition, the exclusive OR gate XOR3 compares the second sample data RQ[4X+1] and RQ[4X+2], and the exclusive OR gate XOR4 compares the second sample data RQ[4X+2] and RQ[4X+3]. The NOR gate NO2 generates a state flag S[1] equal to logic 0 when the second sample data RQ[4X+1] is different from RQ[4X+2] and / or the second sample data RQ[4X+2] is different from RQ[4X+3]. Conversely, when the second sample data RQ[4X+1] to RQ[4X+3] are all the same, the NOR gate NO2 generates a state flag S[1] equal to logic 1. The exclusive OR gate XOR5 compares the second sample data RQ[4X+2] and RQ[4X+3], and the exclusive OR gate XOR6 compares the second sample data RQ[4X+3] and RQ[4X+4]. The NOR gate NO3 generates a state flag S[2] equal to logic 0 when the second sample data RQ[4X+2] is different from RQ[4X+3] and / or the second sample data RQ[4X+3] is different from RQ[4X+4]. Conversely, when the second sample data RQ[4X+2] to RQ[4X+4] are all the same, the NOR gate NO3 generates a state flag S[2] equal to logic 1.

[0051] Please refer to Figure 4A as well as Figure 4B ,in Figure 4A FIG. 1 is a schematic diagram of an implementation of a data selector in a clock data correction circuit according to an embodiment of the present invention. Figure 4BThe following are the implementation details of the multiplexer in the data selector of an embodiment of the present invention. Data selector 400 includes multiple logic gates XNOR1-XNOR3, AD1, multiple gate controllers GC1-GC3, and multiple multiplexers 411-417. In this embodiment, logic gates XNOR1-XNOR3 are exclusive NOR gates, and logic gate AD1 is an AND gate. Logic gate XNOR1 receives status flags S_6[2]-S_0[2]; logic gate XNOR2 receives status flags S_6[1]-S_0[1]; and logic gate XNOR3 receives status flags S_6[0]-S_0[0].

[0052] Logic gates XNOR1-XNOR3 are used to compare the states of state flags S_6[2]-S_0[2], S_6[1]-S_0[1], and S_6[0]-S_0[0], respectively. When S_6[2]-S_0[2] are identical, S_6[1]-S_0[1] are identical, and S_6[0]-S_0[0] are identical, logic gate AD1 generates an output equal to logic 1 to gate controllers GC1-GC3.

[0053] Each gate controller GC1-GC3 has a data terminal D, an output terminal O, and a control terminal G. The data terminals D of the gate controllers GC1-GC3 receive the state flags S_0[2], S_0[1], and S_0[0], respectively. When the output of the logic gate AD1 is equal to logic 1, the output terminals Q of the gate controllers GC1-GC3 generate selection signals S[2], S[1], and S[0], which are equal to the state flags S_0[2], S_0[1], and S_0[0], respectively.

[0054] In this embodiment, the status flags S_0[0] to S_6[0] correspond to the following: Figure 1 The data comparators 141 to 147 shown in FIG. 1 and the status flags S_0[1] to S_6[1] correspond to the following: Figure 1 The data comparators 141 to 147 shown in FIG. 1 and the status flags S_0[2] to S_6[2] also correspond to the following: Figure 1 Data comparators 141-147 are shown.

[0055] The selection signals S[2], S[1], and S[0] are transmitted to the multiplexers 411 to 417. The multiplexers 411 to 417 receive the corresponding Figure 1 The data comparators 141 to 147 shown generate the second sampling data RQ[3:1], RQ[7:5], RQ[11:9], RQ[15:13]RQ[19:17], RQ[23:21]RQ[27:25] and together generate a plurality of output data signals SQ[1] to SQ[7] according to the selection signals S[2], S[1], and S[0].

[0056] Please refer to the following Figure 4B .exist Figure 4B In the example, the multiplexer 40 corresponds to the data comparator of the Xth stage and receives the second sampled data RQ[4X+1], RQ[4X+2], and RQ[4X+3]. The multiplexer 40 selects one of the second sampled data RQ[4X+1], RQ[4X+2], and RQ[4X+3] according to the selection signals S[0], S[1], and S[2] to generate the output signal SQ[X+1]. The truth table of the multiplexer 40 can be shown in Table 2:

[0057] Table 2

[0058]

[0059]

[0060] Please refer to the following Figure 5A as well as Figure 5B , Figure 5A as well as Figure 5B This is an operational waveform diagram of the clock data correction circuit according to an embodiment of the present invention when the clock signal phase lags behind. Figure 5A In the example, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] obtained by sampling the clock signals CK[0] to CK[4] can be respectively obtained as follows: Figure 5A As shown. When the phase of the clock signal lags behind the data signal by 0 to 0.25 unit intervals (UI), and when the data D[7] and D[8] in the data signal DATA are the same, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] (i.e., the second sampled data RQ[0], RQ[1], RQ[2], RQ[3] and RQ[4]) obtained by sampling the data signal DATA according to the second sampling point of the clock signal CK

[16] are data D[7], D[7], D[7], D[7] and D[8], respectively, which can all be logic 1 or logic 0. Under such conditions, according to the change state of the second sampled data, the state flags S[2], S[1], S[0] generated by the data comparator of the embodiment of the present invention can be logic 1, 1, 1, respectively. Furthermore, the data selector can select the first sampling data Q[2] (equal to the second sampling data RQ[2]) in the middle as the output data signal according to the state flags S[2], S[1], S[0] of logic 1, 1, 1, referring to Table 2.

[0061] Based on the above, when the data D[7] and D[8] in the data signal DATA are different, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] (i.e., the second sampled data RQ[0], RQ[1], RQ[2], RQ[3] and RQ[4]) obtained by sampling the data signal DATA according to the second sampling point of the clock signal CK

[16] are respectively data D[7], D[7], D[7], D[7] and D[8], which can be logic 0, 0, 0, 0, 1 or logic 1, 1, 1, 1, 0. Under such conditions, according to the change state of the second sampled data, the state flags S[2], S[1] and S[0] generated by the data comparator of the embodiment of the present invention can be logic 0, 1, 1, respectively. Furthermore, the data selector can select the first sampling data Q[2] (equal to the second sampling data RQ[2]) as the output data signal according to the state flags S[2], S[1], S[0] of logic 0, 1, and 1, referring to Table 2.

[0062] exist Figure 5A In the embodiment, when the data D[7] and D[8] are the same, the selected output data signal (first sampled data Q[2]) can satisfy the requirement of having a setup time greater than 0.5UI and a hold time greater than 1.25UI. When the data D[7] and D[8] are different, the selected output data signal (first sampled data Q[2]) can satisfy the requirement of having a setup time greater than 0.5UI and a hold time greater than 0.25UI.

[0063] exist Figure 5B In the example, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] obtained by sampling the clock signals CK[0] to CK[4] can be respectively obtained as follows: Figure 5BAs shown. When the clock signal phase lags behind the data signal by 0.25 to 0.5UI, and when the data D[7] and D[8] in the data signal DATA are the same, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] (i.e., the second sampled data RQ[0], RQ[1], RQ[2], RQ[3] and RQ[4]) obtained by sampling the data signal DATA according to the second sampling point of the clock signal CK

[16] are data D[7], D[7], D[7], D[8] and D[8], respectively, which can all be logic 1 or logic 0. Under such conditions, according to the change state of the second sampled data, the state flags S[2], S[1], S[0] generated by the data comparator of the embodiment of the present invention can be logic 1, 1, 1, respectively. Furthermore, the data selector can select the first sampling data Q[2] (equal to the second sampling data RQ[2]) in the middle as the output data signal according to the state flags S[2], S[1], S[0] of logic 1, 1, 1, referring to Table 2.

[0064] Based on the above, when the data D[7] and D[8] in the data signal DATA are different, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] (i.e., the second sampled data RQ[0], RQ[1], RQ[2], RQ[3] and RQ[4]) obtained by sampling the data signal DATA according to the second sampling point of the clock signal CK

[16] are respectively data D[7], D[7], D[7], D[8] and D[8], which can be logic 0, 0, 0, 1, 1 or logic 1, 1, 1, 0, 0. Under such conditions, according to the change state of the second sampled data, the state flags S[2], S[1] and S[0] generated by the data comparator of the embodiment of the present invention can be logic 0, 0, 1, respectively. Furthermore, the data selector can select the first sampling data Q[1] (equal to the second sampling data RQ[1]) as the output data signal according to the state flags S[2], S[1], S[0] of logic 0, 0, and 1, referring to Table 2.

[0065] exist Figure 5B In the embodiment, when the data D[7] and D[8] are the same, the selected output data signal (first sampled data Q[2]) can satisfy the requirements of having a setup time greater than 0.75UI and a hold time greater than 1.0UI. When the data D[7] and D[8] are different, the selected output data signal (first sampled data Q[2]) can satisfy the requirements of having a setup time greater than 0.5UI and a hold time greater than 0.25UI.

[0066] Please refer to the following Figure 6A as well as Figure 6B , Figure 6A as well as Figure 6B FIG1 is an operation waveform diagram of the clock data correction circuit of an embodiment of the present invention when the clock signal phase is advanced. Figure 6A In the example, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] obtained by sampling the clock signals CK[0] to CK[4] can be respectively obtained as follows: Figure 6A As shown. When the phase of the clock signal leads the data signal by 0 to 0.25UI, and when the data D[6] and D[7] in the data signal DATA are the same, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] (i.e., the second sampled data RQ[0], RQ[1], RQ[2], RQ[3] and RQ[4]) obtained by sampling the data signal DATA according to the second sampling point of the clock signal CK

[16] are data D[6], D[7], D[7], D[7] and D[7], respectively, which can all be logic 1 or logic 0. Under such conditions, according to the change state of the second sampled data, the state flags S[2], S[1], S[0] generated by the data comparator of the embodiment of the present invention can be logic 1, 1, 1, respectively. Furthermore, the data selector can select the first sampling data Q[2] (equal to the second sampling data RQ[2]) in the middle as the output data signal according to the state flags S[2], S[1], S[0] of logic 1, 1, 1, referring to Table 2.

[0067] Based on the above, when the data D[6] and D[7] in the data signal DATA are different, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] (i.e., the second sampled data RQ[0], RQ[1], RQ[2], RQ[3] and RQ[4]) obtained by sampling the data signal DATA according to the second sampling point of the clock signal CK

[16] are respectively data D[6], D[7], D[7], D[7] and D[7], which can be logic 0, 1, 1, 1, 1 or logic 1, 0, 0, 0, 0. Under such conditions, according to the change state of the second sampled data, the state flags S[2], S[1] and S[0] generated by the data comparator of the embodiment of the present invention can be logic 1, 1, 0, respectively. Furthermore, the data selector can select the first sampling data Q[2] (equal to the second sampling data RQ[2]) as the output data signal according to the state flags S[2], S[1], S[0] of logic 1, 1, and 0, referring to Table 2.

[0068] exist Figure 6AIn the embodiment, when the data D[6] and D[7] are the same, the selected output data signal (first sampled data Q[2]) can satisfy the requirement of having a setup time greater than 1.25UI and a hold time greater than 0.5UI. When the data D[6] and D[7] are different, the selected output data signal (first sampled data Q[2]) can satisfy the requirement of having a setup time greater than 0.25UI and a hold time greater than 0.5UI.

[0069] exist Figure 6B In the example, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] obtained by sampling the clock signals CK[0] to CK[4] can be respectively obtained as follows: Figure 6B As shown. When the phase of the clock signal leads the data signal by 0.25 to 0.5UI, and when the data D[6] and D[7] in the data signal DATA are the same, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] (i.e., the second sampled data RQ[0], RQ[1], RQ[2], RQ[3] and RQ[4]) obtained by sampling the data signal DATA according to the second sampling point of the clock signal CK

[16] are data D[6], D[6], D[7], D[7] and D[7], respectively, which can all be logic 1 or logic 0. Under such conditions, according to the change state of the second sampled data, the state flags S[2], S[1], S[0] generated by the data comparator of the embodiment of the present invention can be logic 1, 1, 1, respectively. Furthermore, the data selector can select the first sampling data Q[2] (equal to the second sampling data RQ[2]) in the middle as the output data signal according to the state flags S[2], S[1], S[0] of logic 1, 1, 1, referring to Table 2.

[0070] Based on the above, when the data D[6] and D[7] in the data signal DATA are different, the first sampled data Q[0], Q[1], Q[2], Q[3] and Q[4] (i.e., the second sampled data RQ[0], RQ[1], RQ[2], RQ[3] and RQ[4]) obtained by sampling the data signal DATA according to the second sampling point of the clock signal CK

[16] are respectively data D[6], D[6], D[7], D[7] and D[7], which can be logic 0, 0, 1, 1, 1 or logic 1, 1, 0, 0, 0. Under such conditions, according to the change state of the second sampled data, the state flags S[2], S[1] and S[0] generated by the data comparator of the embodiment of the present invention can be logic 1, 0, 0, respectively. Furthermore, the data selector can select the first sampling data Q[3] (equal to the second sampling data RQ[3]) as the output data signal according to the state flags S[2], S[1], S[0] of logic 1, 0, 0, referring to Table 2.

[0071] exist Figure 6B In the embodiment, when the data D[6] and D[7] are the same, the selected output data signal (first sampled data Q[2]) can satisfy the requirements of having a setup time greater than 1.0UI and a hold time greater than 0.75UI. When the data D[6] and D[7] are different, the selected output data signal (first sampled data Q[3]) can satisfy the requirements of having a setup time greater than 0.25UI and a hold time greater than 0.5UI.

[0072] Please refer to the following Figure 7 , Figure 7 Schematic diagram of a clock data correction circuit according to another embodiment of the present invention. The clock data correction circuit 700 includes a comparator 710, a multi-phase clock generator 720, samplers 731-737, data comparators 741-747, a data selector 750, and a data retiming circuit 760. Figure 1 In different embodiments, the clock data correction circuit 700 further includes a data retiming circuit 760. The data retiming circuit 760 is coupled to the output terminal of the data selector 750. The data retiming circuit 760 receives the output data signal SQ[7:1] generated by the data selector 750 and receives one of the multiple clock signals CK[27:0]. The data retiming circuit 760 retimes the output data signal SQ[7:1] according to the received clock signal to generate multiple retimed output data signals OUT[7:1]. The data retiming circuit 760 can be constructed using multiple flip-flops. In this embodiment, the data retiming circuit 760 can select the received clock signal CK

[16] or CK[0] as the reference for retiming.

[0073] Please refer to the following Figure 8 , Figure 8 Figure 8 is a schematic diagram illustrating an embodiment of a multi-phase clock generator in a clock and data correction circuit according to an embodiment of the present invention. Multi-phase clock generator 800 includes a comparator 810 and a phase-locked circuit 820. Comparator 810 compares the input clock CLK_INP with the input clock signal CLK_INN to generate a reference clock CKR. Phase-locked circuit 820 receives the reference clock CKR and performs phase-locking operation on the reference clock CKR to generate multiple clock signals CK[27:0] of different phases.

[0074] In detail, comparator 810 can be implemented using an operational amplifier, wherein the positive input of the operational amplifier receives the input clock CLK_INP, and the negative input of the operational amplifier receives the input clock signal CLK_INN. The output of the operational amplifier can generate the reference clock CKR. Phase-locked circuit 820 can be a phase-locked loop (PLL) or a delay-locked loop (DLL). Those skilled in the art can use any well-known PLL circuit or DLLL circuit to implement PLL 820 without limitation.

[0075] Based on the above, the present invention utilizes multiple clock signals with different phases to sample data signals, and selects one of the multiple sampled data as the appropriate output data signal based on the change state of the multiple consecutive sampled data. In this way, the selected output data signal can have a sufficiently long hold time and setup time, which can improve the skew tolerance between the clock and data and enhance data reliability.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock data correction circuit, comprising: A first comparator generates a data signal by comparing the first input data and the second input data; a multi-phase clock generator for generating a plurality of clock signals having different phases by comparing a first input clock signal and a second input clock signal, wherein the plurality of clock signals are divided into a plurality of clock groups; a plurality of samplers, sampling the data signal according to the plurality of clock groups to generate a plurality of first sampled data groups; a plurality of data comparators, which respectively sample the plurality of first sampled data groups according to transition points of a plurality of selected clock signals from the plurality of clock signals via a plurality of triggers to generate a plurality of second sampled data groups, each of the data comparators generating a plurality of status flags according to a change state of the plurality of second sampled data in each of the second sampled data groups; as well as The data selector selects the plurality of second sampling data according to the plurality of status flags to generate a plurality of output data signals.

2. The clock data correction circuit according to claim 1 , wherein the Xth data comparator samples the 4Xth first sampling data to the 4X+4th first sampling data according to the 4X+16th clock signal to generate the 4Xth second sampling data to the 4X+4th second sampling data, respectively, where X is an integer not less than 0.

3. The clock data correction circuit according to claim 2, wherein the Xth data comparator further generates a first status flag according to a change state from the 4Xth second sampling data to the 4X+2th second sampling data; generates a second status flag according to a change state from the 4X+1th second sampling data to the 4X+3th second sampling data; and generates a third status flag according to a change state from the 4X+2th second sampling data to the 4X+4th second sampling data.

4. The clock data correction circuit according to claim 3 , wherein the Xth data comparator comprises: the plurality of flip-flops receiving the 4Xth to 4X+4th first sampling data, respectively, and sampling the 4Xth to 4X+4th first sampling data according to the 4X+16th clock signal to generate the 4Xth to 4X+4th second sampling data, respectively; as well as a logic circuit that generates the first state flag by comparing the 4Xth second sampling data with the 4X+2th second sampling data; generates the second state flag by comparing the 4X+1th second sampling data with the 4X+3th second sampling data; and generates the third state flag by comparing the 4X+2th second sampling data with the 4X+4th second sampling data.

5. The clock data correction circuit according to claim 1 , wherein corresponding to the Xth data comparator, when a plurality of first state flags are all the same, a plurality of second state flags are all the same, and a plurality of third state flags are all the same, the data selector generates a plurality of selection signals according to the plurality of third state flags, and selects the plurality of second sampling data according to the plurality of selection signals to generate the plurality of output data signals.

6. The clock data correction circuit according to claim 5, wherein the data selector comprises: a plurality of first logic gates, performing a mutually exclusive OR logic operation on the plurality of first state flags to generate a first operation value; a plurality of second logic gates, performing the exclusive OR logic operation on the plurality of second state flags to generate second operation values; a plurality of third logic gates, performing the exclusive OR logic operation on the plurality of third state flags to generate a third operation value; a fourth logic gate, performing an AND operation on the first operation value, the second operation value, and the third operation value to generate a fourth operation value; as well as A plurality of gate controllers select the plurality of first state flags according to the fourth operation value to respectively generate the plurality of selection signals.

7. The clock data correction circuit according to claim 6, wherein corresponding to the X-th data comparator, the data selector further comprises: The multiplexer selects one of the 4X+1th to 4X+3th second sampling data according to the plurality of selection signals to generate an X+1th output data signal.

8. The clock data correction circuit according to claim 1 , wherein the multi-phase clock generator comprises: a second comparator, comparing the first input clock and the second input clock signal to generate a reference clock; as well as The phase-locked circuit performs a phase-locking operation on the reference clock and generates the multiple clock signals accordingly. 9 . The clock data correction circuit according to claim 8 , wherein the phase-locked loop (PLL) is a delay-locked loop (DLL) or a phase-locked loop (PLL).

10. The clock data correction circuit according to claim 1, further comprising: The data retiming circuit retimes the plurality of output data signals according to one of the plurality of clock signals to generate a plurality of retimed output data signals.

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