Analog-to-digital converter device and calibration circuit control method

Abstract

An analog-to-digital converter apparatus and a calibration circuit control method. The apparatus includes a plurality of analog-to-digital conversion circuits, a calibration circuit, and a control circuit. The plurality of analog-to-digital conversion circuits are configured to generate a plurality of first quantized outputs according to a plurality of clock signals. The calibration circuit is configured to perform at least one error operation according to the plurality of first quantized outputs to generate a plurality of second quantized outputs, and analyze a plurality of time difference information of the plurality of clock signals according to the plurality of second quantized outputs to generate a plurality of adjustment signals. The control circuit is configured to analyze the plurality of first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is used to control the calibration circuit to selectively perform the at least one error operation, and selectively analyze the plurality of time difference information of the plurality of clock signals. The present disclosure generates at least one control signal for controlling the calibration circuit through the control circuit to avoid the problem that the calibration performed by the calibration circuit is affected due to weak input signals.

Description

Technical Field

[0001] This disclosure relates to an analog-to-digital converter device and a correction circuit control method, and more particularly to a time-interleaved analog-to-digital converter device and a correction circuit control method. Background Technology

[0002] Analog-to-digital converters (ADCs) are commonly used in various electronic devices to convert analog signals to digital signals for signal processing. In practical applications, ADCs can suffer from gain errors, offset errors, or timing errors, affecting their resolution or linearity. In particular, when the input signal is weak (e.g., with too small an amplitude or too low power), existing techniques for correcting these three types of errors are easily affected, potentially causing phase errors between different channels to converge incorrectly. Summary of the Invention

[0003] One embodiment of this disclosure is an analog-to-digital converter (ADC) device. This ADC device includes multiple analog-to-digital conversion circuits, a correction circuit, and a control circuit. The analog-to-digital conversion circuits convert an input signal based on multiple interleaved clock signals to generate multiple first quantized outputs. The correction circuit performs at least one error operation based on these first quantized outputs to generate at least one correction information, uses this correction information to correct the first quantized outputs to generate multiple second quantized outputs, and analyzes multiple time difference information of the clock signals based on these second quantized outputs to generate multiple adjustment signals, wherein these adjustment signals are used to reduce a clock skew of the analog-to-digital conversion circuits. The control circuit receives these first quantized outputs and analyzes them to generate at least one control signal to the correction circuit, wherein the at least one control signal controls the correction circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

[0004] In another embodiment, the control circuit analyzes the first quantization outputs of the Nth period to generate the at least one control signal of the Nth period, and the correction circuit selectively performs the at least one error operation on the first quantization outputs of the N+1th period based on the at least one control signal of the Nth period, and selectively analyzes the time difference information of the clock signals of the N+1th period, where N is a positive integer.

[0005] In another embodiment, when the correction circuit performs the at least one error operation on the first quantization outputs of the N+1th cycle, the correction circuit uses the at least one correction information generated based on the first quantization outputs of the N+1th cycle to correct the first quantization outputs of the N+1th cycle to generate the second quantization outputs of the N+1th cycle.

[0006] In another embodiment, when the correction circuit does not perform the at least one error operation on the first quantization outputs of the N+1th cycle, the correction circuit uses the previously generated at least one correction information to correct the first quantization outputs of the N+1th cycle to generate the second quantization outputs of the N+1th cycle.

[0007] In another embodiment, when the correction circuit analyzes the time difference information of these clock signals in the (N+1)th cycle, the correction circuit analyzes these second quantization outputs in the (N+1)th cycle to generate these adjustment signals in the (N+1)th cycle.

[0008] In another embodiment, when the correction circuit does not analyze the time difference information of these clock signals in the (N+1)th cycle, the correction circuit outputs the adjustment signals of the Nth cycle.

[0009] In another embodiment, the control circuit includes: a plurality of absolute value circuits for receiving the first quantization outputs to output a plurality of absolute value signals, wherein each absolute value circuit is configured to perform an absolute value operation based on a corresponding first quantization output among the first quantization outputs to generate a corresponding absolute value signal among the absolute value signals; an averaging circuit for performing an averaging operation to average the absolute value signals to generate an average signal; a filtering circuit for filtering the average signal; and a comparison circuit for comparing the filtered average signal with at least one threshold value to generate the at least one control signal.

[0010] In another embodiment, the correction circuit includes a skew adjustment circuit for analyzing the second quantization outputs to generate the adjustment signals to the analog-to-digital conversion circuits.

[0011] In another embodiment, the at least one correction information includes a gain correction information, the at least one error operation includes a gain error operation, and the correction circuit further includes: a gain correction circuit for performing the gain error operation based on the first quantization outputs to generate the gain correction information, and using the gain correction information to generate the second quantization outputs.

[0012] In another embodiment, the at least one correction information further includes offset correction information, the at least one error operation further includes an offset error operation, and the correction circuit further includes: an offset correction circuit that receives the first quantization outputs, performs the offset error operation based on the first quantization outputs to generate the offset correction information, and uses the offset correction information to correct the first quantization outputs to generate a plurality of third quantization outputs, wherein the gain correction circuit uses the gain correction information to correct the third quantization outputs to generate the second quantization outputs.

[0013] Another aspect of this case is a correction circuit control method. This correction circuit control method includes: receiving, via a control circuit, multiple first quantization outputs generated by multiple analog-to-digital converters based on multiple interleaved clock signals; analyzing these first quantization outputs via the control circuit to generate at least one control signal to a correction circuit; via the correction circuit, selectively performing at least one error operation based on the at least one control signal to generate at least one correction information, and selectively analyzing multiple time difference information of the clock signals to generate multiple adjustment signals, wherein these adjustment signals are used to reduce a clock skew of the analog-to-digital converters; and correcting these first quantization outputs via the correction circuit to generate multiple second quantization outputs.

[0014] In another embodiment, generating the at least one control signal includes: performing an absolute value operation on a corresponding first quantization output of the first quantization outputs to generate a corresponding absolute value signal of a plurality of absolute value signals; performing an averaging operation to average the absolute value signals to generate an average signal; filtering the average signal; and comparing the filtered average signal with at least one threshold value to generate the at least one control signal.

[0015] In another embodiment, generating these adjustment signals includes analyzing the second quantization outputs through a skew adjustment circuit of the correction circuit to generate the adjustment signals to the analog-to-digital conversion circuits.

[0016] In another embodiment, the at least one correction information includes a gain correction information, the at least one error operation includes a gain error operation, and generating the second quantization outputs includes: generating the gain correction information by performing the gain error operation based on the first quantization outputs through a gain correction circuit of the correction circuit, and generating the second quantization outputs using the gain correction information.

[0017] In another embodiment, the at least one correction information further includes offset correction information, the at least one error operation further includes an offset error operation, and generating the second quantization outputs further includes: receiving the first quantization outputs through an offset correction circuit of the correction circuit; and generating the offset correction information by performing the offset error operation based on the first quantization outputs through the offset correction circuit, and using the offset correction information to correct the first quantization outputs to generate a plurality of third quantization outputs, wherein the gain correction circuit uses the gain correction information to correct the third quantization outputs to generate the second quantization outputs.

[0018] In summary, the disclosed ADC device and correction circuit control method analyze multiple first quantization outputs generated by multiple analog-to-digital conversion circuits through a control circuit to generate at least one control signal for controlling the correction circuit. When the input signal is weak (e.g., too small an amplitude or too low power), the ADC device controls the correction circuit to generate multiple second quantization outputs based on previously generated correction information (and / or controls the correction circuit to output multiple previously generated adjustment signals) via the at least one control signal, thus avoiding the problem that the correction performed by the correction circuit is affected by the weak input signal. This also solves the problem of incorrect convergence of phase errors among multiple analog-to-digital conversion circuits. Attached Figure Description

[0019] Figure 1A This is a schematic diagram illustrating an analog-to-digital converter device according to some embodiments of this case;

[0020] Figure 1B The illustration is based on some embodiments of this case. Figure 1A A waveform diagram of multiple clock signals;

[0021] Figure 2 This is a schematic diagram of a control circuit in an analog-to-digital converter device, illustrated according to some embodiments of this case;

[0022] Figure 3 This is a flowchart illustrating a correction circuit control method based on some embodiments of this case.

[0023] [Symbol Explanation]

[0024] 100: Analog-to-digital converter device

[0025] 110: Analog-to-digital conversion circuit

[0026] 120: Correction circuit

[0027] 121: Offset Correction Circuit

[0028] 123: Gain Correction Circuit

[0029] 125: Skew adjustment circuit

[0030] 130: Control Circuit

[0031] 131: Absolute value circuit

[0032] 133: Average Circuit

[0033] 135: Filtering Circuit

[0034] 137: Comparator Circuit

[0035] 300: Correction Circuit Control Method

[0036] 331: First operational circuit

[0037] 333: Second Operational Circuit

[0038] CLK0~CLK M-1 Clock signal

[0039] CSo, CSg, CSs: Control signals

[0040] Q0~Q M-1 CQ10~CQ1 M-1 CQ20~CQ2 M-1 Quantization output

[0041] A0~A M-1 Absolute value signal

[0042] T0~T M-1 Adjust signal

[0043] SIN: Input signal

[0044] AVG: Average Signal

[0045] SUM: Sum of signals

[0046] TH: Critical value

[0047] fs: Sampling frequency

[0048] SP: Sampling Period

[0049] S1, S2, S3: Sampling time

[0050] S310~S340: Steps Detailed Implementation

[0051] The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure that is recombined with elements and produces a device with equivalent function is within the scope of this disclosure.

[0052] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.

[0053] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0054] Please see Figure 1A , Figure 1B , Figure 1A This is a schematic diagram illustrating an analog-to-digital converter (ADC) device 100 according to some embodiments of this case. Figure 1B The illustration is based on some embodiments of this case. Figure 1A Multiple clock signals CLK0~CLK M-1 The waveform diagram is shown below. In some embodiments, the ADC device 100 operates as a multi-channel time-interleaved ADC.

[0055] In some embodiments, the ADC device 100 includes a plurality of analog-to-digital conversion circuits 110, a correction circuit 120, and a control circuit 130. Notably, each analog-to-digital conversion circuit 110 operates as a single channel. In other words, the ADC device 100 includes M channels. In some embodiments, M is an even number. Figure 1A As shown, each analog-to-digital converter circuit 110 is used to convert multiple clock signals CLK0 to CLK0. M-1 One of the input signals SIN is converted from analog to digital to generate multiple quantized outputs Q0 to Q1. M-1 One of them.

[0056] like Figure 1B As shown, multiple clock signals CLK0~CLK M-1There is a time interval between two adjacent clock signals. Therefore, two adjacent channels will perform sampling operations and analog-to-digital conversion at different times. For example, the first channel (i.e., the analog-to-digital converter 110 operating according to clock signal CLK0) samples the input signal SIN at the first sampling time S1 and performs analog-to-digital conversion; the second channel (i.e., the analog-to-digital converter 110 operating according to clock signal CLK1) samples the input signal SIN at the second sampling time S2 and performs analog-to-digital conversion; and the third channel (i.e., the analog-to-digital converter 110 operating according to clock signal CLK2) samples the input signal SIN at the third sampling time S3 and performs analog-to-digital conversion. The difference between sampling times S1 and S2 is the sampling period SP (the corresponding sampling frequency is fs, i.e., SP = 1 / fs). And so on, M channels can operate according to multiple interleaved timing sequences.

[0057] The correction circuit 120 is coupled to each analog-to-digital converter circuit 110 to receive multiple quantization outputs Q0 to Q1. M-1 The correction circuit 120 can output Q0~Q based on quantization. M-1 At least one error operation is performed to generate at least one correction information to correct the offset and gain errors in multiple analog-to-digital conversion circuits 110, and to generate multiple corrected quantized outputs CQ20 to CQ20. M-1 Furthermore, the correction circuit 120 can output CQ20 to CQ2 based on the corrected quantization. M-1 The clock skew (equivalent to time difference information) between multiple analog-to-digital conversion circuits 110 is analyzed to generate multiple adjustment signals T0 to T1. M-1 .

[0058] like Figure 1A As shown, the correction circuit 120 includes an offset correction circuit 121, a gain correction circuit 123, and a skew adjustment circuit 125. The offset correction circuit 121 is electrically coupled to each analog-to-digital converter circuit 110 to receive multiple quantization outputs Q0 to Q10. M-1 In some embodiments, the offset correction circuit 121 is used to adjust the outputs Q0 to Q1 based on a plurality of quantization outputs. M-1 An offset error operation (i.e., at least one error operation as described above) is performed to generate offset correction information (i.e., at least one correction information as described above), and the offset correction information is used to reduce multiple quantization outputs Q0 to Q1. M-1 The offset error is used to generate multiple quantization outputs CQ10 to CQ1 M-1 .

[0059] As described above, the gain correction circuit 123 is electrically coupled to the offset correction circuit 121 to receive multiple quantization outputs CQ10 to CQ10.M-1 In some embodiments, the gain correction circuit 123 is used to adjust the multiple quantization outputs CQ10 to CQ10 according to the given values. M-1 Perform a gain error operation (i.e., the aforementioned at least one error operation) to generate gain correction information (i.e., the aforementioned at least one correction information), and use the gain correction information to reduce multiple quantization outputs CQ10 to CQ1. M-1 The gain error is used to generate multiple quantized outputs CQ20 to CQ20 after correction. M-1 .

[0060] As described above, the skew adjustment circuit 125 is electrically coupled to the gain correction circuit 123 to receive the corrected multiple quantization outputs CQ20 to CQ20. M-1 In some embodiments, the skew adjustment circuit 125 is used to analyze the corrected quantization outputs CQ20 to CQ2. M-1 To generate multiple adjustment signals T0~T M-1 In some embodiments, the skew adjustment circuit 125 converts multiple adjustment signals T0 to T1. M-1 The signals are output to multiple analog-to-digital converters 110, and multiple adjustment signals T0 to T1 are respectively output to these circuits. M-1 Used to indicate the timing adjustments required for multiple analog-to-digital conversion circuits 110 due to clock skew.

[0061] In detail, since quantization output CQ20 corresponds to the first sampling time S1 and quantization output CQ21 corresponds to the second sampling time S2, the time difference between these two corresponding times is one sampling period SP. Therefore, by analyzing quantization outputs CQ20 and CQ21, the time difference information within one sampling period SP of clock signals CLK0 and CLK1 can be obtained. Similarly, through this setting, the skew adjustment circuit 125 can analyze the clock signals CLK0 to CLK1. M-1 The time difference information of each pair of adjacent clock signals within one sampling period SP.

[0062] The above analysis uses clock signals CLK0~CLK M-1 The setting of the time difference information of each pair of adjacent clock signals within one sampling period SP is only for illustration and is not limited thereto. In some embodiments, the skew adjustment circuit 125 can analyze the even-numbered clock signals CLK0, CLK2, ..., CLK respectively. M-2 The time difference information within two sampling periods SP and the odd-numbered clock signals CLK1, CLK3, ..., CLK M-1 The time difference information within two sampling periods (SP).

[0063] In some embodiments, the plurality of analog-to-digital conversion circuits 110 can adjust according to the plurality of adjustment signals T0 to T10. M-1The timing of sampling operations and / or analog-to-digital conversion operations is adjusted to effectively correct clock skew. In other embodiments, multiple clock signals CLK0 to CLK... M-1 The timing can be directly based on multiple adjustment signals T0~T M-1 The time skew is adjusted to effectively correct the clock skew. For example, multiple adjustment signals T0 to T10 are used. M-1 Input to generate multiple clock signals CLK0~CLK M-1 A clock generator, phase interpolator, or a digital delay control line can be used to adjust multiple clock signals CLK0 to CLK0. M-1 The phase. The above is based on the adjustment signals T0~T M-1 The settings for correcting clock skew are for illustrative purposes only and are not intended to limit this disclosure.

[0064] For example Figure 1A As shown, the control circuit 130 is electrically coupled to each analog-to-digital converter circuit 110 and the correction circuit 120 to receive multiple quantization outputs Q0 to Q10. M-1 In some embodiments, the control circuit 130 is used to analyze multiple quantization outputs Q0 to Q1. M-1 To generate at least one control signal (e.g.) Figure 1A The CSo, CSg, and CSs shown are connected to the correction circuit 120. The operation of this circuit will be discussed in later paragraphs. Figure 2 Detailed explanation.

[0065] Please see Figure 2 , Figure 2 The illustration is based on some embodiments of this case. Figure 1A A circuit diagram of the control circuit 130 is shown. In some embodiments, the control circuit 130 includes multiple absolute value circuits 131, averaging circuits 133, filtering circuits 135, and comparison circuits 137.

[0066] Multiple absolute value circuits 131 are electrically coupled to multiple analog-to-digital converter circuits 110 to receive multiple quantization outputs Q0 to Q10 respectively. M-1 In some embodiments, each absolute value circuit 131 outputs multiple quantization outputs Q0 to Q0. M-1 The corresponding quantized output performs an absolute value operation to generate multiple absolute value signals A0 to A1. M-1The absolute value signal corresponds to a given absolute value signal. Taking the first absolute value circuit 131 as an example, the first absolute value circuit 131 receives the quantized output Q0 and performs an absolute value operation to obtain the absolute value of the quantized output Q0, thereby generating the absolute value signal A0. The configuration and operation of the remaining absolute value circuits 131 can be deduced similarly, so they will not be described again. In some embodiments, the absolute value circuit 131 can be implemented by a processing circuit or a rectifier circuit, and all circuits that implement the absolute value circuit 131 are within the scope of this disclosure.

[0067] The averaging circuit 133 is electrically coupled to multiple absolute value circuits 131 to receive multiple absolute value signals A0 to A10. M-1 In some embodiments, the averaging circuit 133 is used to calculate based on a plurality of absolute value signals A0 to A10. M-1 Perform an averaging operation to average multiple absolute value signals A0 to A10. M-1 This generates an average signal AVG. In some embodiments, the averaging circuit 133 may be implemented by digital processing circuitry, but this disclosure is not limited thereto.

[0068] like Figure 2 As shown, in some embodiments, the averaging circuit 133 includes a first operational circuit 331 and a second operational circuit 333. The first operational circuit 331 is electrically coupled to a plurality of absolute value circuits 131 to receive a plurality of absolute value signals A0 to A0. M-1 In some embodiments, the first arithmetic circuit 331 is used to calculate based on a plurality of absolute value signals A0 to A10. M-1 Perform a summation operation to sum multiple absolute value signals A0 to A10. M-1 This generates a summing signal SUM. In some embodiments, the first arithmetic circuit 331 may be implemented by an adder or other processing circuits with the same function. Various circuits implementing the first arithmetic circuit 331 are within the scope of this disclosure.

[0069] As described above, the second operational circuit 333 is electrically coupled to the first operational circuit 331 to receive the summation signal SUM. In some embodiments, the second operational circuit 333 performs a division operation on the summation signal SUM to generate an average signal AVG. Specifically, the second operational circuit 333 can divide the summation signal SUM by M (i.e., the number of channels) to generate the average signal AVG. In some embodiments, the second operational circuit 333 can be implemented by a divider or other processing circuits with the same function. Various circuits implementing the second operational circuit 333 are within the scope of this disclosure.

[0070] The filter circuit 135 is electrically coupled to the averaging circuit 133 to receive the average signal AVG. In some embodiments, the filter circuit 135 is used to filter the average signal AVG.

[0071] Comparison circuit 137 is electrically coupled to filter circuit 135 to receive the filtered average signal AVG. In some embodiments, comparison circuit 137 is used to compare the average signal AVG with at least one threshold value (e.g., Figure 2 (as shown in TH) to generate at least one control signal (e.g. Figure 2 The CSo, CSg, and CSs shown are connected to the correction circuit 120.

[0072] Due to multiple quantization outputs Q0~Q M-1 It is generated by converting the amplitude of the input signal SIN through multiple analog-to-digital conversion circuits 110, as mentioned above, based on multiple quantization outputs Q0 to Q10. M-1 The generated average signal AVG is associated with the amplitude of the input signal SIN. Furthermore, the threshold value TH used for comparison with the average signal AVG is also associated with the amplitude of the input signal SIN. Specifically, the average signal AVG can correspond to the amplitude of the current input signal SIN, while the threshold value TH can correspond to a pre-set amplitude (e.g., 20% of the maximum amplitude of the input signal SIN). In other words, at... Figure 2 In the illustrated embodiment, the control circuit 130 is used to generate at least one control signal based on the amplitude of the input signal SIN, but this disclosure is not limited thereto. In other embodiments, the control circuit 130 may also be used to generate at least one control signal based on the power of the input signal SIN.

[0073] In some embodiments, the correction circuit 120 may selectively perform at least one error calculation based on at least one control signal to generate at least one correction information. Furthermore, the correction circuit 120 may selectively analyze clock skew (equivalent to multiple clock signals CLK0 to CLK) between the plurality of analog-to-digital conversion circuits 110 based on at least one control signal. M-1 Multiple adjustment signals T0 to T1 are generated using time difference information. M-1 .

[0074] In some embodiments, the amplitude of the input signal SIN is relatively large (or the quantization output Q0~Q M-1The numerical changes of multiple consecutive signals are relatively large, causing the average signal AVG to be greater than or equal to the critical value TH. Accordingly, the control circuit 130 can generate three control signals CSo, CSg, and CSs for three first voltage levels (e.g., high voltage level) to the correction circuit 120, simultaneously enabling the offset correction circuit 121, the gain correction circuit 123, and the skew adjustment circuit 125. In other words, the offset correction circuit 121 performs offset error calculation based on the high voltage level control signal CSo to generate offset correction information; the gain correction circuit 123 performs gain error calculation based on the high voltage level control signal CSg to generate gain correction information; and the skew adjustment circuit 125 analyzes multiple clock signals CLK0 to CLK based on the high voltage level control signal CSs. M-1 The time difference information is used to generate multiple adjustment signals T0~T M-1 .

[0075] In some embodiments, the input signal SIN amplitude is relatively small (or the quantization output Q0~Q M-1 The numerical changes of multiple consecutive signals are relatively small, causing the average signal AVG to be less than the critical value TH. Accordingly, the control circuit 130 can generate three control signals CSo, CSg, and CSs for the second voltage level (e.g., the low voltage level) to the correction circuit 120, simultaneously disabling the offset correction circuit 121, the gain correction circuit 123, and the skew adjustment circuit 125. In other words, the offset correction circuit 121 does not generate offset correction information based on the low voltage level control signal CSo, the gain correction circuit 123 does not generate gain correction information based on the low voltage level control signal CSg, and the skew adjustment circuit 125 does not analyze the multiple clock signals CLK0 to CLK based on the low voltage level control signal CSs. M-1 Time difference information.

[0076] With the offset correction circuit 121, gain correction circuit 123, and skew adjustment circuit 125 all disabled, the correction circuit 120 will use the previously generated correction information to correct the multiple quantization outputs Q0 to Q1. M-1 To generate multiple quantized outputs CQ20~CQ2 M-1 In addition, the correction circuit 120 will directly output the previously generated adjustment signals T0 to T1. M-1 To correct clock skew. In some embodiments, the ADC device 110 includes a memory circuit (not shown) for storing previously generated correction information and previously generated adjustment signals T0 to T1. M-1 .

[0077] For ease of explanation, the following will refer to the multiple clock signals CLK0 to CLK corresponding to the Nth cycle. M-1 Multiple quantized outputs Q0~Q M-1Multiple quantization outputs CQ10~CQ1 M-1 And multiple quantization outputs CQ20~CQ2 M-1 These are referred to as the multiple quantized outputs Q0 to Q1 of the Nth period. M-1 Multiple quantized outputs CQ10 to CQ1 in the Nth cycle M-1 And multiple quantized outputs CQ20 to CQ2 in the Nth cycle. M-1 The naming of other signals follows the same pattern. In a practical application example, multiple analog-to-digital converter circuits 110 output multiple quantized outputs Q0 to Q1 in the Nth cycle. M-1 Where N is a positive integer. The correction circuit 120 corrects the multiple quantized outputs Q0 to Q1 in the Nth cycle through the offset correction circuit 121 and the gain correction circuit 123. M-1 To generate multiple quantized outputs CQ20 to CQ2 in the Nth cycle. M-1 Furthermore, the correction circuit 120 analyzes the multiple quantization outputs CQ20 to CQ2 in the Nth cycle through the skew adjustment circuit 125. M-1 To generate multiple adjustment signals T0 to T in the Nth cycle. M-1 .

[0078] As described above, control circuit 130 analyzes the multiple quantization outputs Q0 to Q1 in the Nth cycle. M-1 This generates multiple control signals CSo, CSg, and CSs for the Nth cycle and sends them to the correction circuit 120. Accordingly, the correction circuit 120 can selectively output multiple quantized values ​​Q0 to Qs for the (N+1)th cycle based on the multiple control signals CSo, CSg, and CSs for the Nth cycle. M-1 Perform at least one error calculation and selectively analyze multiple clock signals CLK0 to CLK in the (N+1)th cycle. M-1 Time difference information.

[0079] For example, if the control signal CSo in the Nth cycle is at a high voltage level, then the offset correction circuit 121 in the correction circuit 120 outputs Q0 to Q1 based on the multiple quantization outputs in the (N+1)th cycle. M-1 Offset error calculation is performed to generate offset correction information, and the offset correction information is used to reduce multiple quantization outputs Q0 to Q in the (N+1)th cycle. M-1 The offset error is used to generate multiple quantization outputs CQ10 to CQ1 in the (N+1)th cycle. M-1 Conversely, if the control signal CSo in the Nth cycle is at a low voltage level, the offset correction circuit 121 does not perform offset error calculation and utilizes the previously generated offset correction information (e.g., based on the multiple quantization outputs Q0 to Q1 in the Nth cycle). M-1 The generated offset correction information reduces the multiple quantization outputs Q0 to Q1 in the (N+1)th cycle. M-1The offset error is used to generate multiple quantization outputs CQ10 to CQ1 in the (N+1)th cycle. M-1 .

[0080] If the control signal CSg in the Nth cycle is at a high voltage level, then the gain correction circuit 123 in the correction circuit 120 outputs multiple quantizations CQ10 to CQ1 in the (N+1)th cycle. M-1 Gain error calculation is performed to generate gain correction information, and the gain correction information is used to reduce the multiple quantization outputs CQ10 to CQ1 in the (N+1)th cycle. M-1 The gain error is used to generate multiple quantized outputs CQ20 to CQ2 in the (N+1)th cycle. M-1 Conversely, if the control signal CSg in the Nth cycle is at a low voltage level, the gain correction circuit 123 does not perform gain error calculation and utilizes the previously generated gain correction information (e.g., based on the multiple quantization outputs CQ10 to CQ1 in the Nth cycle). M-1 The generated gain correction information reduces the multiple quantization outputs CQ10 to CQ1 in the (N+1)th cycle. M-1 The gain error is used to generate multiple quantized outputs CQ20 to CQ2 in the (N+1)th cycle. M-1 .

[0081] If the control signal CSs in the Nth cycle is at a high voltage level, then the skew adjustment circuit 125 in the correction circuit 120 analyzes the multiple quantization outputs CQ20 to CQ2 in the (N+1)th cycle. M-1 To generate multiple adjustment signals T0 to T in the (N+1)th cycle. M-1 Multiple analog-to-digital conversion circuits 110. Conversely, if the control signal CSs in the Nth cycle is at a low voltage level, the skew adjustment circuit 125 does not adjust the multiple quantization outputs CQ20 to CQ2 in the (N+1)th cycle. M-1 The analysis is performed, and the previously generated adjustment signals T0 to T1 are output. M-1 (For example, based on multiple quantization outputs CQ20~CQ2 in the Nth period) M-1 Multiple adjustment signals T0 to T1 generated in the Nth period M-1 (To multiple analog-to-digital conversion circuits 110.)

[0082] In the above embodiments, the comparator circuit 137 in the control circuit 130 generates multiple control signals CSo, CSg, and CSs based on the comparison result of the filtered average signal AVG and a threshold value TH, so as to simultaneously disable / enable the offset correction circuit 121, gain correction circuit 123, and skew adjustment circuit 125 in the correction circuit 120. However, this disclosure is not limited thereto. In other embodiments, the comparator circuit 137 in the control circuit 130 may generate multiple control signals CSo, CSg, and CSs at different voltage levels based on the comparison result of the filtered average signal AVG and multiple threshold values, so as to disable / enable the offset correction circuit 121, gain correction circuit 123, and skew adjustment circuit 125 in the correction circuit 120, respectively.

[0083] For example, the comparator circuit 137 compares the average signal AVG with a first threshold value TH1 and a second threshold value TH2, wherein the second threshold value TH2 is greater than the first threshold value TH1. If the average signal AVG is less than the first threshold value TH1, the control circuit 130 outputs a high-voltage level control signal CSo and two low-voltage level control signals CSg and CSs to enable the offset correction circuit 121 and disable the gain correction circuit 123 and the skew adjustment circuit 125. If the average signal AVG is greater than the first threshold value TH1 but less than the second threshold value TH2, the control circuit 130 outputs two high-voltage level control signals CSo and CSg and a low-voltage level control signal CSs to enable the offset correction circuit 121 and the gain correction circuit 123 and disable the skew adjustment circuit 125. If the average signal AVG is greater than the second threshold TH2, the control circuit 130 outputs three high-voltage level control signals CSo, CSg, and CSs to enable the offset correction circuit 121, the gain correction circuit 123, and the skew adjustment circuit 125. In other words, the smaller the amplitude of the input signal SIN, the more circuits can be disabled by the control circuit 130.

[0084] Please see Figure 3 , Figure 3 This is a flowchart illustrating a correction circuit control method 300 according to some embodiments of the present invention. For ease of understanding, the correction circuit control method 300 will be described with reference to the foregoing figures. In some embodiments, the correction circuit control method 300 may be... Figure 1A The ADC device 100 performs this operation. In one embodiment, the correction circuit control method 300 first executes step S310, whereby the correction circuit 120 receives data from multiple analog-to-digital converters 110 based on multiple clock signals CLK0 to CLK0. M-1 The resulting multiple quantized outputs Q0 to Q M-1 .

[0085] The correction circuit control method 300 then executes step S320, which analyzes multiple quantization outputs Q0 to Q0 through the control circuit 130. M-1 To generate at least one control signal (e.g., the aforementioned multiple control signals CSo, CSg, CSs) to the correction circuit 120.

[0086] The correction circuit control method 300 then executes step S330, in which the correction circuit 120 selectively performs at least one error calculation based on at least one control signal to generate at least one correction information, and selectively analyzes multiple clock signals CLK0 to CLK0. M-1 The time difference information is used to generate multiple adjustment signals T0~T M-1 .

[0087] The correction circuit control method 300 then executes step S340, correcting multiple quantization outputs Q0 to Q0 through the correction circuit 120. M-1 To generate multiple quantization outputs CQ20~CQ2 M-1 The descriptions and implementation methods of the aforementioned steps can be found in the descriptions of the foregoing embodiments, and therefore will not be repeated here.

[0088] In summary, the ADC device 100 and the correction circuit control method 300 disclosed herein analyze the multiple quantization outputs Q0 to Q1 generated by the multiple analog-to-digital conversion circuits 110 through the control circuit 130. M-1 This generates at least one control signal for controlling the correction circuit 120. When the input signal SIN is weak (e.g., too small an amplitude or too low power), the ADC device 100 controls the correction circuit 120 to generate multiple quantized outputs CQ20 to CQ2 based on previously generated correction information using the at least one control signal. M-1 (or / and control correction circuit 120 outputs multiple previously generated adjustment signals T0~T0) M-1 This is to prevent the correction performed by the correction circuit 120 from being affected by weak input signals. In this way, the problem of incorrect convergence of phase errors among multiple analog-to-digital conversion circuits 110 can also be solved.

[0089] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope defined in the appended claims.

Claims

1. An analog-to-digital converter device, characterized in that, Include: Multiple analog-to-digital converter circuits are used to convert an input signal according to multiple interleaved clock signals to generate multiple first quantized outputs; A correction circuit is configured to perform at least one error operation based on the plurality of first quantization outputs to generate at least one correction information, use the at least one correction information to correct the plurality of first quantization outputs to generate a plurality of second quantization outputs, and analyze a plurality of time difference information of the plurality of clock signals based on the plurality of second quantization outputs to generate a plurality of adjustment signals to the plurality of analog-to-digital converter circuits, wherein the plurality of adjustment signals are used to reduce a clock skew of the plurality of analog-to-digital converter circuits. as well as A control circuit receives the plurality of first quantization outputs and analyzes the plurality of first quantization outputs to generate at least one control signal to the correction circuit, wherein the at least one control signal is used to control the correction circuit to selectively perform the at least one error operation and selectively analyze the plurality of time difference information of the plurality of clock signals.

2. The analog-to-digital converter device according to claim 1, characterized in that, The control circuit analyzes the plurality of first quantization outputs in the Nth period to generate the at least one control signal in the Nth period. The correction circuit selectively performs the at least one error operation on the plurality of first quantization outputs in the N+1th period based on the at least one control signal in the Nth period, and selectively analyzes the plurality of time difference information of the plurality of clock signals in the N+1th period, where N is a positive integer.

3. The analog-to-digital converter device according to claim 2, characterized in that, When the correction circuit performs the at least one error operation on the plurality of first quantization outputs in the N+1th cycle, the correction circuit uses the at least one correction information generated based on the plurality of first quantization outputs in the N+1th cycle to correct the plurality of first quantization outputs in the N+1th cycle, thereby generating the plurality of second quantization outputs in the N+1th cycle.

4. The analog-to-digital converter device according to claim 3, characterized in that, When the correction circuit does not perform the at least one error operation on the plurality of first quantization outputs in the N+1th cycle, the correction circuit uses the previously generated at least one correction information to correct the plurality of first quantization outputs in the N+1th cycle to generate the plurality of second quantization outputs in the N+1th cycle.

5. The analog-to-digital converter device according to claim 2, characterized in that, When the correction circuit analyzes the multiple time difference information of the multiple clock signals in the N+1th period, the correction circuit analyzes the multiple second quantization outputs in the N+1th period to generate the multiple adjustment signals in the N+1th period.

6. The analog-to-digital converter device according to claim 5, characterized in that, When the correction circuit does not analyze the multiple time difference information of the multiple clock signals in the (N+1)th cycle, the correction circuit outputs the multiple adjustment signals in the Nth cycle.

7. The analog-to-digital converter device according to claim 1, characterized in that, The control circuit includes: Multiple absolute value circuits are configured to receive the multiple first quantization outputs to output multiple absolute value signals, wherein each of the absolute value circuits is configured to perform an absolute value operation based on a corresponding first quantization output among the multiple first quantization outputs to generate a corresponding absolute value signal among the multiple absolute value signals. An averaging circuit is used to perform an averaging operation to average the plurality of absolute value signals to generate an average signal; A filter circuit is used to filter the average signal. as well as A comparator circuit is used to compare the filtered average signal with at least one threshold value to generate the at least one control signal.

8. The analog-to-digital converter device according to claim 1, characterized in that, The correction circuit includes: A skew adjustment circuit is used to analyze the plurality of second quantization outputs to generate the plurality of adjustment signals to the plurality of analog-to-digital conversion circuits.

9. The analog-to-digital converter device according to claim 1, characterized in that, The at least one correction information includes gain correction information, the at least one error calculation includes a gain error calculation, and the correction circuit further includes: A gain correction circuit is configured to perform the gain error calculation based on the plurality of first quantization outputs to generate the gain correction information, and to generate the plurality of second quantization outputs using the gain correction information.

10. The analog-to-digital converter device according to claim 9, characterized in that, The at least one correction information further includes offset correction information, the at least one error calculation further includes an offset error calculation, and the correction circuit further includes: An offset correction circuit receives the plurality of first quantization outputs, performs an offset error calculation based on the plurality of first quantization outputs to generate offset correction information, and uses the offset correction information to correct the plurality of first quantization outputs to generate a plurality of third quantization outputs, wherein the gain correction circuit uses the gain correction information to correct the plurality of third quantization outputs to generate the plurality of second quantization outputs.

11. A method for controlling a correction circuit, characterized in that, Include: A control circuit receives multiple first quantization outputs generated by multiple analog-to-digital conversion circuits based on multiple interleaved clock signals; The control circuit analyzes the plurality of first quantization outputs to generate at least one control signal to a correction circuit. The correction circuit selectively performs at least one error operation based on the at least one control signal to generate at least one correction information, and selectively analyzes multiple time difference information of the multiple clock signals to generate multiple adjustment signals to the multiple analog-to-digital converter circuits, wherein the multiple adjustment signals are used to reduce a clock skew of the multiple analog-to-digital converter circuits. as well as The correction circuit corrects the plurality of first quantization outputs to generate a plurality of second quantization outputs.

12. The correction circuit control method according to claim 11, characterized in that, The control circuit analyzes the plurality of first quantization outputs in the Nth period to generate the at least one control signal in the Nth period. The correction circuit selectively performs the at least one error operation on the plurality of first quantization outputs in the N+1th period based on the at least one control signal in the Nth period, and selectively analyzes the plurality of time difference information of the plurality of clock signals in the N+1th period, where N is a positive integer.

13. The correction circuit control method according to claim 12, characterized in that, When the correction circuit performs the at least one error operation on the plurality of first quantization outputs in the N+1th cycle, the correction circuit uses the at least one correction information generated based on the plurality of first quantization outputs in the N+1th cycle to correct the plurality of first quantization outputs in the N+1th cycle, thereby generating the plurality of second quantization outputs in the N+1th cycle.

14. The correction circuit control method according to claim 13, characterized in that, When the correction circuit does not perform the at least one error operation on the plurality of first quantization outputs in the N+1th cycle, the correction circuit uses the previously generated at least one correction information to correct the plurality of first quantization outputs in the N+1th cycle to generate the plurality of second quantization outputs in the N+1th cycle.

15. The correction circuit control method according to claim 12, characterized in that, When the correction circuit analyzes the multiple time difference information of the multiple clock signals in the N+1th period, the correction circuit analyzes the multiple second quantization outputs in the N+1th period to generate the multiple adjustment signals in the N+1th period.

16. The correction circuit control method according to claim 15, characterized in that, When the correction circuit does not analyze the multiple time difference information of the multiple clock signals in the (N+1)th cycle, the correction circuit outputs the multiple adjustment signals in the Nth cycle.

17. The correction circuit control method according to claim 11, characterized in that, Generating the at least one control signal includes: An absolute value operation is performed on a corresponding first quantization output among the plurality of first quantization outputs to generate a corresponding absolute value signal among the plurality of absolute value signals; An averaging operation is performed to average the plurality of absolute value signals to produce an average signal; Perform a filtering operation on the average signal; and The filtered average signal is compared with at least one threshold value to generate the at least one control signal.

18. The correction circuit control method according to claim 11, characterized in that, Generating the plurality of adjustment signals includes: The plurality of second quantization outputs are analyzed by a skew adjustment circuit of the correction circuit to generate the plurality of adjustment signals to the plurality of analog-to-digital conversion circuits.

19. The correction circuit control method according to claim 11, characterized in that, The at least one correction information includes a gain correction information, the at least one error operation includes a gain error operation, and generating the plurality of second quantization outputs includes: A gain correction circuit of the correction circuit performs the gain error calculation based on the plurality of first quantization outputs to generate the gain correction information, and uses the gain correction information to generate the plurality of second quantization outputs.

20. The correction circuit control method according to claim 19, characterized in that, The at least one correction information further includes offset correction information, the at least one error operation further includes an offset error operation, and generating the plurality of second quantization outputs further includes: The plurality of first quantization outputs are received by an offset correction circuit of the correction circuit; and The offset correction circuit performs the offset error calculation based on the plurality of first quantization outputs to generate the offset correction information, and uses the offset correction information to correct the plurality of first quantization outputs to generate a plurality of third quantization outputs, wherein the gain correction circuit uses the gain correction information to correct the plurality of third quantization outputs to generate the plurality of second quantization outputs.

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