Analog-to-digital conversion device and method with fast conversion mechanism

Abstract

An analog-to-digital conversion device with a fast conversion mechanism. The analog-to-digital conversion circuit receives previous high-bit conversion results and predicts them to generate high-bit conversion results; converts an input analog signal using a continuous progressive mechanism according to a sampling clock to generate a low-bit conversion result, wherein the sampling clock frequency is at least twice the frequency of the input analog signal; and combines the high-bit conversion result and the low-bit conversion result to generate a conversion result, and outputs a residual signal quantity as a residual value. A noise shaping circuit operates on the residual value of the previous converter of each analog-to-digital conversion circuit to generate a noise shaping reference signal. Each analog-to-digital conversion circuit combines the current conversion result with the noise shaping reference signal to generate an output digital signal.

Description

Technical Field

[0001] The present invention relates to analog-to-digital conversion technology, and more particularly to an analog-to-digital conversion device and method with a fast conversion mechanism. Background Art

[0002] Wireless communication technology has significantly improved people's lives. 4G communications offer extremely high data speeds, enabling higher-quality phone calls and even face-to-face video calls. In these applications, analog-to-digital converters (ADCs) are essential. Many modern electronic devices require converting analog signals into digital form for processing.

[0003] There are many types of analog-to-digital converters (ADCs) to meet different needs. However, the requirements for high conversion speed and high signal-to-noise ratio (SNR) pose many challenges to the design of ADCs. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide an analog-to-digital conversion device and method with a fast conversion mechanism to improve the prior art.

[0005] The present invention includes an analog-to-digital conversion device with a fast conversion mechanism, comprising: a plurality of analog-to-digital conversion circuits that perform cyclic sampling in a time sequence, and a noise shaping circuit. The analog-to-digital conversion circuits are each configured to: receive a previous high-order conversion result from a previous conversion result and predict a current high-order conversion result based on the result, wherein the previous conversion result was generated by a previous converter in the analog-to-digital conversion circuit; convert an input analog signal using a successive approximation mechanism according to different phases of a sampling clock to generate a current low-order conversion result, wherein the sampling clock frequency is at least twice the frequency of the input analog signal; and combine the current high-order conversion result with the current low-order conversion result to generate a current conversion result, and output a residual signal quantity as a residual value. The noise shaping circuit is configured to operate on the residual value of the previous converter of each analog-to-digital conversion circuit to generate a noise shaping reference signal. Each analog-to-digital conversion circuit combines the current conversion result with the noise shaping reference signal to generate an output digital signal.

[0006] The present invention further includes an analog-to-digital conversion method with a fast conversion mechanism, which is applied to an analog-to-digital conversion device. The analog-to-digital conversion method includes: causing a plurality of analog-to-digital conversion circuits that perform cyclic sampling in a time sequence to respectively receive a previous high-bit conversion result from a previous conversion result and predict a current high-bit conversion result based on the previous conversion result, wherein the previous conversion result was generated by a previous converter in the analog-to-digital conversion circuit; causing the analog-to-digital conversion circuits to respectively convert an input analog signal using a continuous and progressive mechanism according to different phases of a sampling clock to generate a current low-bit conversion result, wherein the frequency of the sampling clock is at least twice the frequency of the input analog signal; causing the analog-to-digital conversion circuits to respectively combine the current high-bit conversion result with the current low-bit conversion result to generate a current conversion result and output a residual signal quantity as a residual value; causing a noise shaping circuit to operate on the residual value of the previous converter of each analog-to-digital conversion circuit to generate a noise shaping reference signal; and causing each analog-to-digital conversion circuit to combine the current conversion result with the noise shaping reference signal to generate an output digital signal.

[0007] The features, implementation and effects of the present invention are now described in detail below with reference to preferred embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram showing an analog-to-digital conversion device with a fast conversion mechanism according to one embodiment of the present invention;

[0009] Figure 2 A block diagram showing an analog-to-digital conversion circuit according to one embodiment of the present invention;

[0010] Figure 3 A block diagram showing an analog-to-digital conversion circuit according to another embodiment of the present invention; and

[0011] Figure 4 A flow chart showing an analog-to-digital conversion method with a fast conversion mechanism according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0012] An object of the present invention is to provide an analog-to-digital conversion device and method with a fast conversion mechanism. By having the previous converter transmit the high-bit conversion result and residual value, the subsequent converter can quickly predict and generate the high-bit conversion result and perform noise shaping based on the result, thereby achieving a fast analog-to-digital conversion result with a high signal-to-noise ratio.

[0013] Please refer to Figure 1 . Figure 1A block diagram of an analog-to-digital conversion device 100 with a fast conversion mechanism according to an embodiment of the present invention is shown. The analog-to-digital conversion device 100 includes analog-to-digital conversion circuits 110A-110D, a noise shaping circuit 120 and a multiplexer 130.

[0014] Analog-to-digital conversion circuits 110A-110D sample the input analog signal ANI in a time-interleaved manner, according to the different phases of a sampling clock CLK. For example, when the sampling clock CLK is 1 GHz, analog-to-digital conversion circuits 110A-110D operate at 250 MHz, sampling at phases of 0, 90, 180, and 270 degrees, respectively, to produce a final conversion result of 1 GHz.

[0015] In one embodiment, the frequency of the sampling clock CLK is at least twice the frequency of the input analog signal ANI. In this case, the oversampling rate of the sampling clock CLK relative to the input analog signal ANI is at least 1. In other embodiments, the frequency of the sampling clock CLK may be four times the frequency of the input analog signal ANI (corresponding to an oversampling rate of 2) or even higher.

[0016] The analog-to-digital conversion circuits 110A-110D generate conversion results SRA-SRD respectively. The conversion results SRA-SRD include high-order conversion results HBA-HBD and low-order conversion results LBA-LBD. Since the conversion results SRA-SRD are generated inside the analog-to-digital conversion circuits 110A-110D, Figure 1 The analog-to-digital conversion circuits 110A-110D are shown in blocks in FIG.

[0017] Since the frequency of the sampling clock CLK is higher than the frequency of the input analog signal ANI, the analog-to-digital conversion circuits 110A-110D can respectively receive the previous high-bit conversion results of the previous conversion results when performing sampling and make predictions based on the previous high-bit conversion results to generate the current high-bit conversion results, where the previous conversion results were generated by the corresponding previous converters of the analog-to-digital conversion circuits 110A-110D.

[0018] Next, each analog-to-digital conversion circuit 110A-110D converts the input analog signal ANI through a successive approximation mechanism according to different phases of the sampling clock CLK to generate current low-bit conversion results LBA-LBD.

[0019] Furthermore, the analog-to-digital conversion circuits 110A-110D respectively combine the corresponding current high-bit conversion results HBA-HBD and the current low-bit conversion results LBA-LBD to generate corresponding current conversion results SRA-SRD and output residual signal quantities as residual values ​​QDA-QDD.

[0020] The analog-to-digital conversion circuit 110B is taken as an example for further description.

[0021] In one embodiment, there is only one previous sampler, the previous one. Therefore, the analog-to-digital conversion circuit 110A serves as the previous sampler for the analog-to-digital conversion circuit 110B. The conversion result SRA, which is the current conversion result for the analog-to-digital conversion circuit 110A, serves as the previous conversion result for the analog-to-digital conversion circuit 110B. The upper-order conversion result HBA in the conversion result SRA serves as the previous upper-order conversion result.

[0022] The analog-to-digital conversion circuit 110B receives the upper-bit conversion result HBA from the conversion result SRA and generates the current upper-bit conversion result HBB accordingly. In one embodiment, the analog-to-digital conversion circuit 110B may perform a prediction based on a default operation method to generate the upper-bit conversion result HBB. Furthermore, if the analog-to-digital conversion circuit 110A generates the upper-bit conversion result HBA but has not yet generated the lower-bit conversion result LBA, the analog-to-digital conversion circuit 110B may receive the upper-bit conversion result HBB and generate its own upper-bit conversion result HBB.

[0023] It should be noted that in one embodiment, the number of previous samplers may be more than one. For example, when the number of previous samplers is two, the analog-to-digital conversion circuit 110A can generate a high-order conversion result HBA by performing a prediction based on the high-order segments HBC and HBD of the conversion results SRC and SRD, for example, by extrapolation or other computational methods. The other analog-to-digital conversion circuits 110B-110D can be similarly deduced and will not be further described here.

[0024] Next, the analog-to-digital conversion circuit 110B converts the input analog signal ANI through a continuous progressive mechanism according to the phase of the sampling clock CLK to generate a low-bit conversion result LBB.

[0025] Furthermore, the analog-to-digital conversion circuit 110B combines the corresponding high-bit conversion result HBB and the low-bit conversion result LBB to generate the corresponding current conversion result SRB, and outputs a residual signal quantity as a residual value QDB.

[0026] An implementation of the analog-to-digital conversion circuit 110B will be described below.

[0027] Please refer to Figure 2 . Figure 2 FIG2 is a block diagram of an analog-to-digital conversion circuit 110B according to an embodiment of the present invention. The analog-to-digital conversion circuit 110B includes a capacitor switching circuit 200 , a digital-to-analog conversion capacitor array 210 , a comparison circuit 220 , and a control circuit 230 .

[0028] The digital-to-analog conversion capacitor array 210 includes a plurality of high-order capacitors 240 and a plurality of low-order capacitors 250, and is configured to receive a first reference voltage Vref1 from a first input terminal IN1 and an input analog signal ANI from a second input terminal IN2 through a capacitor switching circuit 200, and generate an output voltage Vout at an output terminal OUT.

[0029] In practice, the capacitor switching circuit 200 may include multiple switching units (not shown) to enable different connection configurations between the upper capacitor 240 and the lower capacitor 250 and the first input terminal IN1 and the second input terminal IN2. From the highest to the lowest, the upper capacitor 240 and the lower capacitor 250 each have a maximum to minimum voltage adjustment, thereby generating different output voltages Vout at the output terminal OUT depending on the different connection configurations.

[0030] It should be noted that the capacitor switching circuit 200 and the digital-to-analog conversion capacitor array 210 are Figure 2 The schematic diagram is simplified, and the detailed circuit structure can be selected according to actual needs. The present invention is not limited to a specific structure.

[0031] The comparison circuit 220 is configured to compare the output voltage Vout with a second reference voltage Vref2 to generate a comparison result CR. In one embodiment, the second reference voltage Vref2 is a ground voltage GND.

[0032] The control circuit 230 controls the capacitor switching circuit 200 through a set of high-bit digital codes HDC and a set of low-bit digital codes LDC to control the capacitor switching circuit 200 to generate a high-bit connection combination corresponding to the high-bit capacitor 240 according to the previous high-bit conversion result (such as the high-bit conversion result HBA).

[0033] Furthermore, the control circuit 230 controls the capacitor switching circuit 200 to generate a lower-order connection combination corresponding to the lower-order capacitors 250 through a continuous and gradual mechanism based on the comparison result CR. In one embodiment, the continuous and gradual mechanism means that the control circuit 230 controls the capacitor switching circuit 200 to continuously change the connection method of the lower-order capacitors 250 so that the output voltage Vout generated by the digital-to-analog conversion capacitor array 210 approaches the second reference voltage Vref2.

[0034] When the output voltage Vout approaches the second reference voltage Vref2, the high-order digital code HDC and the low-order digital code LDC corresponding to the high-order and low-order combinations approach the input analog signal ANI. At this time, the high-order digital code HDC corresponding to the high-order combination serves as the high-order conversion result HBB, and the low-order digital code LDC corresponding to the low-order combination serves as the low-order conversion result LBB. The combination of the high-order digital code HDC and the low-order digital code LDC serves as the conversion result SRB.

[0035] In one embodiment, since the output voltage Vout approaches the second reference voltage Vref2 but is not completely equal to it, the analog-to-digital conversion circuit 110B outputs the residual signal of the output voltage Vout as a residual value QDB after generating the conversion result SRB.

[0036] The analog-to-digital conversion circuits 110A, 110C, and 110D may have the same architecture and operating method as the analog-to-digital conversion circuit 110 .

[0037] Therefore, the analog-to-digital conversion circuit 110B can serve as a previous sampler for the analog-to-digital conversion circuit 110C. The analog-to-digital conversion circuit 110C receives the upper-bit conversion result HBB and performs a prediction to generate an upper-bit conversion result HBC. The analog-to-digital conversion circuit 110C converts the input analog signal ANI according to the phase of the sampling clock CLK to generate a lower-bit conversion result LBC. The upper-bit conversion result HBC and the lower-bit conversion result LBC are combined to generate a conversion result SRC. The remaining signal quantity is output as a residual value QDC.

[0038] Similarly, analog-to-digital conversion circuit 110C serves as a previous sampler for analog-to-digital conversion circuit 110D. Analog-to-digital conversion circuit 110D receives upper-bit conversion result HBC and performs prediction to generate upper-bit conversion result HBD. Analog-to-digital conversion circuit 110D then converts input analog signal ANI according to the phase of sampling clock CLK to generate lower-bit conversion result LBD. It combines upper-bit conversion result HBD and lower-bit conversion result LBD to generate conversion result SRD, and outputs a residual signal quantity as residual value QDD.

[0039] Finally, since analog-to-digital conversion circuits 110A-110D perform cyclic sampling, analog-to-digital conversion circuit 110D serves as the previous sampler of analog-to-digital conversion circuit 110A. Analog-to-digital conversion circuit 110A receives the upper-bit conversion result HBD and performs prediction to generate an upper-bit conversion result HBA. It then converts the input analog signal ANI according to the phase of the sampling clock CLK to generate a lower-bit conversion result LBA. It then combines the upper-bit conversion result HBA and the lower-bit conversion result LBA to generate a conversion result SRA, and outputs a residual signal quantity as a residual value QDA.

[0040] In this embodiment, the noise shaping circuit 120 is a single circuit provided independently of the analog-to-digital conversion circuits 110A-110D, and is configured to receive the residual values ​​QDA-QDD from each analog-to-digital conversion circuit 110A-110D and perform calculations to generate noise shaping reference signals COA-COD.

[0041] Furthermore, each analog-to-digital conversion circuit 110A-110D combines the current conversion results SRA-SRD with the noise shaping reference signals COA-COD to generate output digital signals DOA-DOD.

[0042] The analog-to-digital conversion circuit 110B is taken as an example for further description.

[0043] For example, if the number of previous converters is only one and it is the previous one, Figure 1 The noise shaping circuit 120, corresponding to the analog-to-digital conversion circuit 110B, receives the residual value QDA from the analog-to-digital conversion circuit 110A to generate a noise shaping reference signal COB. The analog-to-digital conversion circuit 110B then combines the conversion result SRB with the noise shaping reference signal COB to generate an output digital signal DOB. The noise shaping circuit 120 can generate the noise shaping reference signal COB based on the residual value QDA using any predetermined calculation method. The present invention is not limited to a specific generation method.

[0044] In one embodiment, the noise shaping reference signal COB may be fed back to the comparison circuit 220 , so that the comparison circuit 220 compares the sum of the noise shaping reference signal COB and the output voltage Vout with the second reference voltage Vref2 to generate a comparison result CR.

[0045] Based on the comparison result CR, the control circuit 230 controls the capacitor switching circuit 200 to update the high-order and low-order combinations through a continuous and progressive mechanism, so that the sum approaches the second reference signal Vref2. This generates the output digital signal DOB based on the updated high-order and low-order combinations. Specifically, the high-order digital code HDC corresponding to the updated high-order combination and the low-order digital code LDC corresponding to the updated low-order combination are combined to form the output digital signal DOB.

[0046] It should be noted that the aforementioned method of feeding back the noise-shaping reference signal COB to the comparison circuit 220 is merely an example. In another embodiment, the digital-to-analog conversion capacitor array 210 may further include a plurality of noise-shaping capacitors (not shown) so that the analog voltage of the noise-shaping reference signal COB is fed back to these noise-shaping capacitors to calculate the sum of the noise-shaping reference signal COB and the output voltage Vout. The comparison circuit 220 then performs the comparison, and the control circuit 230 updates the high-bit connection combination and the low-bit connection combination to generate the output digital signal DOB based on the updated high-bit connection combination and the updated low-bit connection combination.

[0047] By generating the noise shaping reference signal COB through the noise shaping circuit 120 , the analog-to-digital conversion circuit 110B can reduce the noise caused by digital quantization in the conversion result SRB, thereby improving the signal-to-noise ratio (SNR).

[0048] Similarly, the noise shaping circuit 120 receives the residual value QDB from the analog-to-digital conversion circuit 110B and generates a noise shaping reference signal COC corresponding to the analog-to-digital conversion circuit 110C. The analog-to-digital conversion circuit 110C combines the conversion result SRC with the noise shaping reference signal COC to generate an output digital signal DOC.

[0049] The noise shaping circuit 120 receives the residual value QDC from the analog-to-digital conversion circuit 110C and generates a noise shaping reference signal COD corresponding to the analog-to-digital conversion circuit 110D. The analog-to-digital conversion circuit 110D combines the conversion result SRD with the noise shaping reference signal COD to generate an output digital signal DOD.

[0050] The noise shaping circuit 120 receives the residual value QDD from the analog-to-digital conversion circuit 110D corresponding to the analog-to-digital conversion circuit 110A to generate a noise shaping reference signal COA, and enables the analog-to-digital conversion circuit 110A to combine the conversion result SRA with the noise shaping reference signal COA to generate an output digital signal DOA.

[0051] It should be noted that in order to avoid clutter in the drawing, Figure 1 The noise shaping circuit 120 is shown as not being directly connected to the analog-to-digital conversion circuits 110A-110D. However, in reality, the noise shaping circuit 120 is directly connected to the analog-to-digital conversion circuits 110A-110D to receive and transmit the aforementioned signals.

[0052] The multiplexer 130 then sequentially outputs the output digital signals DOA-DOD of the analog-to-digital conversion circuits 110A- 110D.

[0053] Please refer to Figure 3 . Figure 3 A block diagram of an analog-to-digital conversion circuit 110B is shown in another embodiment of the present invention.

[0054] Figure 3 The analog-to-digital conversion circuit 110B in Figure 2 The analog-to-digital conversion circuit 110B shown is similar to the analog-to-digital conversion circuit 110B, so the common components and structures will not be described in detail. In this embodiment, the noise shaping circuit 120 described above may actually include multiple noise shaping sub-circuits 300, which are respectively configured to correspond to the analog-to-digital conversion circuits 110A-110D and receive the corresponding residual values ​​QDA-QDD to generate noise shaping reference signals COA-COD.

[0055] Therefore, the analog-to-digital conversion device of the present invention can achieve a fast analog-to-digital conversion result with a high signal-to-noise ratio by having the previous converter transmit the high-bit conversion result and residual value so that the subsequent converter can quickly predict and generate the high-bit conversion result and perform noise shaping.

[0056] It should be noted that the above embodiments are described using an analog-to-digital conversion device including four analog-to-digital conversion circuits as an example. In other embodiments, the number of analog-to-digital conversion circuits included in the analog-to-digital conversion device may vary depending on actual needs. The present invention is not limited to a specific number.

[0057] Please refer to Figure 4 . Figure 4 FIG. 4 is a flow chart of an analog-to-digital conversion method 400 with a fast conversion mechanism according to an embodiment of the present invention.

[0058] In addition to the aforementioned devices, the present invention further discloses an analog-to-digital conversion method 400 with a fast conversion mechanism, which is applied to, for example, but not limited to Figure 1 In the analog-to-digital conversion device 100. One embodiment of the analog-to-digital conversion method 400 is as follows: Figure 4 As shown, the following steps are included.

[0059] In step S410 , a plurality of analog-to-digital conversion circuits 110A-110D that are cyclically sampled in a time sequence respectively receive previous high-order conversion results in previous conversion results and perform predictions based thereon to generate current high-order conversion results HBA-HBD, wherein the previous conversion results are generated by previous converters in the analog-to-digital conversion circuits 110A-110D.

[0060] In step S420 , the analog-to-digital conversion circuits 110A-110D convert the input analog signal ANI through a continuous progressive mechanism according to different phases of the sampling clock CLK to generate current low-bit conversion results LBA-LBD, wherein the frequency of the sampling clock CLK is at least twice the frequency of the input analog signal ANI.

[0061] In step S430 , the analog-to-digital conversion circuits 110A- 110D respectively combine the current high-bit conversion results HBA-HBD and the current low-bit conversion results LBA-LBD to generate current conversion results SRA-SRD and output residual values ​​QDA-QDD.

[0062] In step S440 , the noise shaping circuit 120 operates on the residual values ​​QDA-QDD of the analog-to-digital conversion circuits 110A- 110D to generate noise shaping reference signals COA-COD.

[0063] In step S450 , the analog-to-digital conversion circuits 110A- 110D are respectively combined with the current conversion results SRA-SRD and the noise shaping reference signals COA-COD to generate output digital signals DOA-DOD.

[0064] It should be noted that the above-described embodiment is merely an example. In other embodiments, modifications may be made by those skilled in the art without departing from the spirit of the present invention. It should be understood that, except for those steps specifically described, the order of the steps described in the above-described embodiment may be adjusted based on actual needs, and may even be performed simultaneously or partially simultaneously.

[0065] In summary, the analog-to-digital conversion device and method with a fast conversion mechanism of the present invention can achieve fast analog-to-digital conversion results with a high signal-to-noise ratio by having the previous converter transmit the high-bit conversion result and residual value, so that the subsequent converter can quickly predict and generate the high-bit conversion result and perform noise shaping based on them.

[0066] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may modify the technical features of the present invention based on the explicit or implicit content of the present invention. All such modifications may fall within the scope of the patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

[0067] Description of reference numerals:

[0068] 100: Analog to digital converter

[0069] 110A~110D: Analog to digital conversion circuit

[0070] 120: Noise shaping circuit

[0071] 130: Multiplexer

[0072] 200: Capacitor switching circuit

[0073] 210: Digital to Analog Conversion Capacitor Array

[0074] 220: Comparison Circuit

[0075] 230: Control circuit

[0076] 240: High-position capacitor

[0077] 250: Low-position capacitor

[0078] 300: Noise shaping subcircuit

[0079] 400: Analog to digital converter

[0080] S410~S450: Steps

[0081] ANI: Input analog signal

[0082] CLK: sampling clock

[0083] COA~COD: Noise shaping reference signal

[0084] CR: Comparison results

[0085] DOA~DOD: output digital signal

[0086] GND: Ground voltage

[0087] HBA~HBD: high-order conversion result

[0088] HDC: High digit code

[0089] LBA~LBD: low-order conversion result

[0090] LDC: Low Digital Code

[0091] IN1: first input terminal

[0092] IN2: Second input terminal

[0093] OUT: output terminal

[0094] QDA~QDD:Residual value

[0095] SRA~SRD: conversion result

[0096] Vout: output voltage

[0097] Vref1: first reference voltage

[0098] Vref2: second reference voltage

Claims

1. An analog-to-digital conversion device with a fast conversion mechanism, comprising: The multiple analog-to-digital conversion circuits that perform cyclic sampling in a time sequence are configured as follows: receiving a previous high-order conversion result from a previous conversion result and predicting a high-order segment based on the result to generate a current high-order conversion result, wherein the previous conversion result is generated by a previous converter in the plurality of analog-to-digital conversion circuits; Converting the input analog signal by a continuous progressive mechanism according to different phases of a sampling clock to generate a current low-bit conversion result, wherein the frequency of the sampling clock is at least twice the frequency of the input analog signal; as well as Combining the current high-order conversion result and the current low-order conversion result to generate a current conversion result, and outputting a residual signal as a residual value; as well as a noise shaping circuit configured to operate on the residual value output by a previous converter of each of the plurality of analog-to-digital conversion circuits to generate a noise shaping reference signal; Each of the plurality of analog-to-digital conversion circuits combines the current conversion result with the noise shaping reference signal to generate an output digital signal.

2. The analog-to-digital conversion device according to claim 1 , wherein each of the plurality of analog-to-digital conversion circuits comprises: capacitor switching circuit; a digital-to-analog conversion capacitor array, comprising a plurality of high-order capacitors and a plurality of low-order capacitors, configured to receive a first reference voltage from a first input terminal and an input analog signal from a second input terminal through the capacitor switching circuit, and to generate an output voltage at an output terminal; a comparison circuit configured to compare the output voltage with a second reference voltage to generate a comparison result; as well as a control circuit configured to control the capacitor switching circuit using a set of high-order digital codes and a set of low-order digital codes, so as to control the capacitor switching circuit to generate a high-order connection combination corresponding to the plurality of high-order capacitors based on the previous high-order conversion result, and then control the capacitor switching circuit to generate a low-order connection combination corresponding to the plurality of low-order capacitors based on the comparison result using the continuous progressive mechanism; When the output voltage approaches the second reference voltage, the high-order digital code and the low-order digital code corresponding to the high-order connection combination and the low-order connection combination approach the input analog signal, so that the high-order digital code serves as the current high-order conversion result, and the low-order digital code serves as the current low-order conversion result. The signal amount remaining in the output voltage is the residual value.

3. The analog-to-digital conversion device according to claim 2 , wherein the comparison circuit is further configured to compare the sum of the noise shaping reference signal and the output voltage with the second reference voltage to generate the comparison result; The control circuit controls the capacitor switching circuit to update the high-order connection combination and the low-order connection combination through the continuous progressive mechanism according to the comparison result, so that the sum approaches the second reference voltage to generate the output digital signal according to the updated high-order connection combination and the updated low-order connection combination.

4. The analog-to-digital conversion device according to claim 1 , wherein the number of the previous converters is one or more, and when the number of the previous converters is one or more, the analog-to-digital conversion circuit generates the current high-bit conversion result by predicting multiple previous high-bit conversion results among the multiple previous conversion results.

5. The analog-to-digital conversion device according to claim 1 , wherein the noise shaping circuit is provided as a single circuit independent of the plurality of analog-to-digital conversion circuits, or comprises a plurality of noise shaping sub-circuits provided corresponding to the plurality of analog-to-digital conversion circuits, respectively. 6 . The analog-to-digital conversion device according to claim 1 , further comprising a multiplexer configured to sequentially output the output digital signals generated by the plurality of analog-to-digital conversion circuits.

7. An analog-to-digital conversion method with a fast conversion mechanism, applied to an analog-to-digital conversion device, the analog-to-digital conversion method comprising: causing a plurality of analog-to-digital conversion circuits that perform cyclic sampling in a time sequence to respectively receive a previous high-order conversion result from a previous conversion result and predict a high-order segment based on the previous conversion result to generate a current high-order conversion result, wherein the previous conversion result is generated by a previous converter in the plurality of analog-to-digital conversion circuits; The plurality of analog-to-digital conversion circuits are configured to convert the input analog signal using a continuous progressive mechanism according to different phases of a sampling clock to generate a current low-bit conversion result, wherein the sampling clock has a frequency at least twice that of the input analog signal; The plurality of analog-to-digital conversion circuits respectively combine the current high-bit conversion result and the current low-bit conversion result to generate a current conversion result, and output a residual signal amount as a residual value; causing a noise shaping circuit to operate on the residual value output by a previous converter of each of the plurality of analog-to-digital conversion circuits to generate a noise shaping reference signal; as well as Each analog-to-digital conversion circuit of the plurality of analog-to-digital conversion circuits is enabled to combine the current conversion result with the noise shaping reference signal to generate an output digital signal.

8. The analog-to-digital conversion method according to claim 7, further comprising: Enable a digital-to-analog conversion capacitor array including a plurality of high-order capacitors and a plurality of low-order capacitors to receive a first reference voltage from a first input terminal and an input analog signal from a second input terminal through a capacitor switching circuit, and generate an output voltage at an output terminal; enabling the comparison circuit to compare the output voltage with a second reference voltage to generate a comparison result; as well as The control circuit controls the capacitor switching circuit using a set of high-order digital codes and a set of low-order digital codes, so as to control the capacitor switching circuit to generate a high-order connection combination corresponding to the plurality of high-order capacitors according to the previous high-order conversion result, and then controls the capacitor switching circuit to generate a low-order connection combination corresponding to the plurality of low-order capacitors according to the comparison result through the continuous progressive mechanism; When the output voltage approaches the second reference voltage, the high-order digital code and the low-order digital code corresponding to the high-order connection combination and the low-order connection combination approach the input analog signal, so that the high-order digital code serves as the current high-order conversion result, and the low-order digital code serves as the current low-order conversion result. The signal amount remaining in the output voltage is the residual value.

9. The analog-to-digital conversion method according to claim 8, further comprising: The comparison circuit is further configured to compare the sum of the noise shaping reference signal and the output voltage with the second reference voltage to generate the comparison result; The control circuit controls the capacitor switching circuit to update the high-order connection combination and the low-order connection combination through the continuous progressive mechanism according to the comparison result, so that the sum approaches the second reference voltage to generate the output digital signal according to the updated high-order connection combination and the updated low-order connection combination.

10. The analog-to-digital conversion method according to claim 7, wherein the number of the previous converters is one or more, and when the number of the previous converters is one or more, the analog-to-digital conversion method further comprises: The analog-to-digital conversion circuit is enabled to predict and generate the current high-bit conversion result according to a plurality of previous high-bit conversion results.

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