Phase signal determination method and device for low voltage ride-through of photovoltaic system

Abstract

The present invention belongs to the field of optoelectronic technology, and provides a method, a device and an electronic device for determining a phase signal during low-voltage ride-through of a photovoltaic system. The method includes: when a grid fault is detected, the photovoltaic system performs low-voltage ride-through, and the output voltage U of the inverter is collected t ; performing dq coordinate transformation on the output voltage U of the inverter t to obtain a d-axis component U td and a q-axis component U tq , setting the d-axis orientation mode of the grid voltage, and calculating the value of U tq ; setting a feed-forward compensation voltage in the phase-locked loop of the photovoltaic system, and adjusting the value of U tq to 0 so that the phase-locked loop can collect the phase signal of the fault point. The present invention solves the problem that the phase-locked loop may be unable to accurately collect the grid phase signal, that is, the out-of-synchronization problem, during the low-voltage ride-through process of the photovoltaic system when a grid voltage dip fault occurs. At the same time, by selecting different compensation voltages, it can be flexibly applied to different demand scenarios.

Description

Technical Field

[0001] The present invention belongs to the field of optoelectronic technology, and more specifically, relates to a method, device, electronic device and computer-readable medium for determining a phase signal during low voltage ride-through of a photovoltaic system. Background Art

[0002] With the increasing global environmental pollution and fossil energy crisis, clean and renewable energy such as solar energy has received more and more attention, and the photovoltaic power generation industry has developed rapidly. The new energy power generation system mainly adopts the PLL-based phase-locked synchronous control method and uses the grid-connected converter as the power interface.

[0003] When the grid fails and the voltage drops severely, the voltage drop on the grid impedance, transformer impedance and line impedance increases relative to the grid voltage. Therefore, the voltage on the AC side of the inverter is greatly affected by the grid impedance, transformer impedance and line impedance. At this time, the system is equivalent to a weak grid, and the inverter output voltage signal has a large harmonic content. Since the phase-locked loop collects phase signals based on the voltage on the AC side of the inverter, the voltage on the AC side of the inverter is distorted, and it is difficult for the phase-locked loop to accurately collect the grid frequency value. Therefore, when the grid voltage drop fault is very serious, if the frequency value collected by the phase-locked loop deviates seriously from 50HZ, the system will lose synchronization. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] The present invention aims to solve the technical problem that when a grid voltage drop fault occurs, during the low voltage ride-through process of a photovoltaic system, a phase-locked loop may be unable to accurately collect a grid phase signal, i.e., lose synchronization.

[0006] (II) Technical solution

[0007] In order to solve the above technical problems, one aspect of the present invention provides a method for determining a phase signal during low voltage ride-through of a photovoltaic system, comprising:

[0008] When a grid fault is detected, the photovoltaic system performs low voltage ride-through and the collected inverter output voltage U t ;

[0009] The inverter output voltage U t Perform dq coordinate transformation to obtain the d-axis component U td and the q-axis component U tq , set the grid voltage d-axis orientation mode, calculate U tq The value of

[0010] Set the feedforward compensation voltage in the phase-locked loop of the photovoltaic system to adjust U tq The value of is 0, so that the phase-locked loop can collect the phase signal of the fault point.

[0011] According to a preferred embodiment of the present invention, the calculation U tq The value further includes:

[0012] Get the fault point voltage U g ;

[0013] The q-axis component U is calculated according to the following formula tq value:

[0014] U tq =-U g sinδ+a,

[0015] Where δ is the inverter output voltage U t and the fault point voltage U g The angle difference, a is the offset term, which represents the voltage drop of the impedance to U tq degree of impact.

[0016] According to a preferred embodiment of the present invention, the feedforward compensation voltage is set in the phase-locked loop of the photovoltaic system to adjust U tq The value of is 0, so that the phase-locked loop collects the phase signal of the fault point, further comprising:

[0017] Set the feedforward compensation voltage b to reduce the effect of the offset term a on U tq The degree of influence is as follows:

[0018] U tq =-U g sinδ+ab;

[0019] Let U tq =0, that is, ab=U g sinδ;

[0020] Different feedforward compensation voltage values ​​are set respectively so that the phase-locked loop collects and saves the corresponding phase signal.

[0021] According to a preferred embodiment of the present invention, the different feedforward compensation voltage values ​​are set respectively, and the phase-locked loop collects and stores the corresponding phase signal, further comprising:

[0022] Set U separately g sinδ=0、U g sinδ=a / 2、U g sinδ=3a / 4, let the maximum compensation voltage be b max =(a max+ a min ) / 2;

[0023] According to the setting U g The sinδ value sets the feedforward compensation voltage value to b1 =b max 、b 2 =b max / 2, b 3 =b max / 4;

[0024] The phase-locked loop collects the feedforward compensation voltage value as b 1 、b 2 、b 3 The phase signal of the fault point at time.

[0025] According to a preferred embodiment of the present invention, the phase-locked loop is a dual-quadrant generalized integrator phase-locked loop.

[0026] A second aspect of the present invention provides a phase signal determination device for a photovoltaic system during low voltage ride-through, comprising:

[0027] The voltage acquisition module is used to detect a grid fault, and the photovoltaic system performs low voltage ride-through, and the collected inverter output voltage U t ;

[0028] A voltage conversion module is used to convert the inverter output voltage U t Perform dq coordinate transformation to obtain the d-axis component U td and the q-axis component U tq , set the grid voltage d-axis orientation mode, calculate U tq The value of

[0029] Voltage compensation module, used to set the feedforward compensation voltage in the phase-locked loop of the photovoltaic system and adjust U tq The value of is 0, so that the phase-locked loop can collect the phase signal of the fault point.

[0030] According to a preferred embodiment of the present invention, the voltage conversion module further comprises:

[0031] Fault point voltage acquisition unit, used to obtain the fault point voltage U g ;

[0032] The q-axis voltage calculation unit is used to calculate the q-axis component U according to the following formula tq value:

[0033] U tq =-U g sinδ+a,

[0034] Where δ is the inverter output voltage U t and the fault point voltage U g The angle difference, a is the offset term, which represents the voltage drop of the impedance to U tq degree of impact.

[0035] According to a preferred embodiment of the present invention, the voltage compensation module further comprises:

[0036] The compensation voltage setting unit is used to set the feedforward compensation voltage b to reduce the effect of the offset term a on U tq The degree of influence is as follows:

[0037] U tq =-U g sinδ+ab; and let U tq =0, that is, ab=U g sinδ;

[0038] It is also used to set different feedforward compensation voltage values ​​respectively so that the phase-locked loop collects and saves the corresponding phase signal.

[0039] A third aspect of the present invention provides an electronic device, comprising a processor and a memory, wherein the memory is used to store a computer executable program, and when the computer program is executed by the processor, the processor executes the described method.

[0040] A fourth aspect of the present invention further proposes a computer-readable medium storing a computer-executable program, wherein when the computer-executable program is executed, the method described is implemented.

[0041] (III) Beneficial effects

[0042] The present invention collects the inverter output voltage through a phase-locked loop, and obtains the q-axis component U through dq coordinate transformation. tq , and set the feedforward compensation voltage to use the feedforward compensation method to adjust the q-axis voltage collected by the phase-locked loop, which solves the problem of the phase-locked loop being unable to accurately collect the grid phase signal, i.e., loss of synchronization, when the grid voltage drops and the photovoltaic system is under low voltage riding. At the same time, by selecting different compensation voltages, it can be flexibly applied to occasions with different needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a flow chart of a method for determining a phase signal during low voltage ride-through of a photovoltaic system according to an embodiment of the present invention;

[0044] Figure 2 is a vector relationship diagram of various voltages in a phase-locked loop coordinate system according to an embodiment of the present invention;

[0045] Figure 3a It is a schematic diagram showing the influence of different degrees of grid voltage drop on the system balance point according to an embodiment of the present invention;

[0046] Figure 3b is a schematic diagram showing the influence of offset items of different sizes on the system balance point according to an embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of stability of an equal area law analysis system according to an embodiment of the present invention;

[0048] Figure 5a It is a schematic diagram of a phase-locked loop model in the prior art;

[0049] Figure 5b is a schematic diagram of a phase-locked loop model according to an embodiment of the present invention;

[0050] Figure 6 This is a frequency and q-axis voltage waveform diagram collected by a phase-locked loop when simulating a three-phase balanced drop according to an embodiment of the present invention;

[0051] Figure 7a is a feedforward compensation voltage b during a simulated three-phase balanced drop in one embodiment of the present invention 1 =b max The frequency and q-axis voltage waveforms collected by the phase-locked loop;

[0052] Figure 7b is a feedforward compensation voltage b during a simulated three-phase balanced drop in one embodiment of the present invention 2 =0.62b max The frequency and q-axis voltage waveforms collected by the phase-locked loop;

[0053] Figure 7c The feedforward compensation voltage when simulating three-phase balanced drop in one embodiment of the present invention is The frequency and q-axis voltage waveforms collected by the phase-locked loop;

[0054] Figure 8 This is a frequency and q-axis voltage waveform diagram collected by a phase-locked loop when simulating a three-phase unbalanced drop according to an embodiment of the present invention;

[0055] Figure 9a is a feedforward compensation voltage b during a simulated three-phase unbalanced drop in one embodiment of the present invention 1 =b max The frequency and q-axis voltage waveforms collected by the phase-locked loop;

[0056] Figure 9b is a feedforward compensation voltage b during a simulated three-phase unbalanced drop in one embodiment of the present invention 2 =0.62b max The frequency and q-axis voltage waveforms collected by the phase-locked loop;

[0057] Fig.9c The feedforward compensation voltage when simulating three-phase unbalanced drop in one embodiment of the present invention is The frequency and q-axis voltage waveforms collected by the phase-locked loop;

[0058] Fig.10It is a schematic diagram of a phase signal determination device for low voltage ride-through of a photovoltaic system according to an embodiment of the present invention;

[0059] Fig.11 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;

[0060] Fig.12 is a schematic diagram of a computer-readable recording medium according to an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In the process of introducing specific embodiments, the detailed description of the structure, performance, effect or other characteristics is to enable those skilled in the art to fully understand the embodiments. However, it does not exclude that those skilled in the art can implement the present invention with a technical solution that does not contain the above-mentioned structure, performance, effect or other characteristics under certain circumstances.

[0062] The flowchart in the accompanying drawings is only an exemplary process demonstration, and does not mean that the solution of the present invention must include all the contents, operations and steps in the flowchart, nor does it mean that it must be executed in the order shown in the figure. For example, some operations / steps in the flowchart can be decomposed, some operations / steps can be combined or partially combined, etc. The execution order shown in the flowchart can be changed according to actual conditions without departing from the main purpose of the present invention.

[0063] Frames in the attached figure Figure 1 Generally, it refers to functional entities, which do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processing unit devices and / or microcontroller devices.

[0064] The same reference numerals in the drawings represent the same or similar elements, components or parts, and thus the repeated description of the same or similar elements, components or parts may be omitted below. It should also be understood that although the first, second, third and other attributives representing the numbers may be used herein to describe various devices, elements, components or parts, these devices, elements, components or parts should not be limited by these attributives. In other words, these attributives are only used to distinguish one from another. For example, the first device may also be called the second device, but it does not deviate from the essential technical solution of the present invention. In addition, the terms "and / or" and "and / or" refer to all combinations including any one or more of the listed items.

[0065] Figure 1 FIG. 1 is a flow chart of a method for determining a phase signal during low voltage ride-through of a photovoltaic system according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0066] S101, when a grid fault is detected, the photovoltaic system performs low voltage ride-through, and the collected inverter output voltage U t ;

[0067] S102: The inverter output voltage U t Perform dq coordinate transformation to obtain the d-axis component U td and the q-axis component U tq , set the grid voltage d-axis orientation mode, calculate U tq The value of

[0068] S103, set the feedforward compensation voltage in the phase-locked loop of the photovoltaic system to adjust U tq The value of is 0, so that the phase-locked loop can collect the phase signal of the fault point.

[0069] When an asymmetric short circuit or a large voltage drop occurs in the system, the three-phase voltage will have a large proportion of negative-sequence and zero-sequence components. In addition, when the grid voltage drops more seriously, how to quickly and accurately complete the phase locking of the grid voltage during a voltage drop fault is one of the keys to achieving the low voltage ride-through function.

[0070] Among them, in step S101, when the grid voltage drops to a very low level, the voltage drop on the transformer impedance and the line impedance is not negligible relative to the grid voltage, so it will affect the voltage on the AC side of the inverter. At this time, the inverter output voltage, the fault point voltage and the voltage drop on the transformer and the line form a vector triangle. The vector relationship between the voltages is as follows: Figure 2 shown.

[0071] Figure 2 is a vector relationship diagram of each voltage in a phase-locked loop coordinate system of an embodiment of the present invention. Figure 2 Middle,U t is the inverter output voltage, U g is the fault point voltage, IZ p is the voltage drop on the transformer and the line, δ is the inverter output voltage U t and the fault point voltage U g Angle difference: δ = θ t -θ g .

[0072] U t , U g , IZ P The relationship between them is shown as follows:

[0073] U t =IZ P +U g

[0074] I=i d +i q

[0075] Z P =R P +jX P .

[0076] In step S102, the inverter output voltage U t Perform dq coordinate transformation to obtain the d-axis component U td and the q-axis component U tq , set the grid voltage d-axis orientation mode, then under normal circumstances, the q-axis voltage U tq is zero.

[0077] After a power grid failure occurs, U t Projected to the d, q coordinate system, its q-axis component can be expressed as:

[0078] U tq =-U g sinδ+Ri q -Xi d .

[0079] If you cannot make U tq =0, it indicates that the system does not have a stable working state.

[0080] Will U tq Rewrite it into the following form:

[0081] U tq =-U g sinδ+Ri q -Xi d =-U g sinδ+a

[0082] Among them, U g sinδ represents the offset caused by the phase collected by the phase-locked loop and the grid-side phase being not exactly the same. a is the offset term, which represents the voltage drop of the impedance on U tq Under normal circumstances, a>0; in case of failure, a may be less than 0. From the above analysis, we can know that equation U tq =0, that is, a=U g sinδ k If there is a solution, it means that the system has a stable working state. If the fault is serious or the grid impedance is large, causing |a|>U g , then the phase-locked loop will not be able to achieve synchronization. In order to prevent the system from losing synchronization, it should be ensured that |a|<U g .

[0083] Curve aU g sinδ kThe zero crossing point is Figure 3a and 3b As shown, Figure 3a This is a schematic diagram of the influence of different degrees of grid voltage drop on the system balance point according to an embodiment of the present invention. The fault becomes more serious from top to bottom. Figure 3a It can be seen that when the grid voltage drops to a very low level, U tq There is no intersection with the coordinate axis, that is, there is no equilibrium point; Figure 3b Schematic diagram of the influence of different offset items on the system balance point according to an embodiment of the present invention. The curve shows that the offset items increase from top to bottom. Figure 3b It can be seen that if the grid impedance is too large, the offset term will be too large, U q There is no intersection with the coordinate axis, and there is no equilibrium point. Therefore, when the power grid fault is serious or there is a large power grid impedance, there will be no equilibrium point after the fault.

[0084] Even if there is a balance point, the dynamic adjustment process of the phase-locked loop may still make U tq ≠ 0. For the dynamic process analysis of phase-locked loop resynchronization, the equal area law can be used. Figure 4 FIG. 1 is a schematic diagram of stability analysis of an equal area rule system according to an embodiment of the present invention. Figure 4 As shown, When the damping coefficient D eq >0; When D eq <0. Define two coordinate systems, one of which rotates at the grid frequency and the other at the phase-locked loop frequency. Δω is the difference between the angular velocity of the phase-locked loop and the angular velocity of the grid voltage, and δ is the angular difference between the AC side voltage of the inverter and the grid voltage. When Δω>0, δ increases; when Δω<0, δ decreases.

[0085] The grid voltage at t 1 Time falling, that is, U g The phase remains unchanged at the time of falling, and the working point drops from point A to point B. tq <0, the system enters the deceleration stage, the working point moves toward C, and the angle δ decreases. When the working point reaches C, Δω is still less than zero, and δ will continue to decrease, thus passing through point C. After passing through point C, U tq >0, the system enters the acceleration phase, and Δω begins to increase. When Δω increases to zero, δ reaches the minimum value δ min After that, the system's operating point continues to oscillate around point C and eventually converges to point C. It should be noted that the system's operating point should not exceed point D during the acceleration phase, otherwise the operating point will enter the adjacent deceleration zone, resulting in reverse regulation. In this case, the operating point cannot converge to C and a loss of synchronization will occur. From the analysis, it can be seen that when the bias term a is equal to U gWhen the size is relatively small, the system faces less risk of losing synchronization.

[0086] Figure 5a It is a schematic diagram of the phase-locked loop model in the prior art. The traditional software phase-locked loop (DSOGI-PLL) based on dual second-order generalized integrator can well solve the phase-locking problem when the grid voltage is unbalanced, and make the phase-locked loop insensitive to the grid voltage harmonics. DSOGI-PLL achieves 90° phase angle offset and harmonic filtering by constructing an adaptive filter based on a second-order generalized integrator. When the grid voltage is unbalanced, the positive sequence component of the grid voltage in the two-phase stationary αβ coordinate system is as follows:

[0087]

[0088] in,

[0089] DSOGI-PLL uses a 90° phase angle offset scheme of a dual second-order generalized integrator (SOGI) to generate two-phase orthogonal signals. Schemes such as periodic delay, differentiation and full-pass filtering (especially the differentiation scheme is more sensitive to voltage harmonics) respond slowly to frequency changes. The second-order generalized integrator has good bandpass filtering characteristics, and has good steady-state performance and dynamic performance even under non-ideal conditions such as voltage distortion. Therefore, it can achieve phase angle offset of the input signal and frequency adaptation and filter out high-order harmonics, and can quickly and accurately lock the frequency and phase information of the grid voltage when the grid voltage unbalance drops slightly. However, when the grid voltage loses synchronization, that is, the grid voltage drops severely, it is difficult for DSOGI-PLL to accurately lock the phase information of the grid.

[0090] To avoid the phase-locked loop from losing synchronization, two aspects can be considered. The first way is to improve the phase-locked loop to suppress overshoot, and the second way is to adjust the reference value of the current output to compensate for the impact of the offset term on the system characteristics. From the above analysis, it can be seen that U tq It mainly consists of two parts. One part is the offset term caused by the current flowing through the impedance, and the other part is the offset caused by the phase collected by the phase-locked loop and the phase on the grid side being not exactly the same.

[0091] Figure 5b is a schematic diagram of a phase-locked loop model according to an embodiment of the present invention. In step S103, U tq The offset term a in is estimated, and its estimated value is used to tq Before PI regulation, the influence of the offset term a is weakened by feedforward compensation using the change trend of the q-axis voltage. The introduced feedforward voltage is defined as b.

[0092] Since Sinδ takes values ​​between [-1,1]. tqThe maximum and minimum values ​​that can be obtained are as follows:

[0093] U tqmax =U g +a,

[0094] U tqmin =-U g +a,

[0095] Introducing the feedforward compensation voltage b, the compensated q-axis voltage

[0096] U tq =-U g sinδ+ab.

[0097] Consider an extreme case: within a cycle, the maximum and minimum values ​​of Sinδ can reach 1 and -1. Since the control goal is to reduce the offset term, the compensation term needs to be smaller than the result calculated at this time. If the offset term is too large, the system may lose synchronization. However, if the offset term is too small, U g sinδ. The appropriate feedforward compensation should be selected so that U tq = 0. Need to control U tq =0, that is, ab=U g sinδ.

[0098] In addition, since the introduction of the feedforward link will increase the calculation amount of the control link and reduce the operating speed, the feedforward link is introduced only when necessary. The power grid allows the frequency fluctuation range to be ±0.5HZ. Therefore, when the frequency measured by the phase-locked loop exceeds ±0.2Hz, the feedforward compensation link is enabled. The inverter is set to collect the maximum and minimum values ​​of the q-axis voltage once per cycle to calculate the size of the feedforward compensation amount.

[0099] In the embodiment of the present invention, a photovoltaic inverter model with a rated capacity of 500KW is built using simulink to verify the effectiveness of the proposed strategy. Under normal working conditions, the converter outputs all active currents. The three-phase balanced drop fault and the three-phase unbalanced drop fault are simulated respectively, and the frequency and q-axis voltage collected by the phase-locked loop before and after compensation are compared to verify the effectiveness of the proposed strategy.

[0100] Selection of feedforward compensation term:

[0101] After adding the feedforward compensation voltage b, the effect will be significantly improved.

[0102] From the sine theorem analyzed above, we can know that

[0103]

[0104] It can be deduced

[0105] Can get

[0106] That is, the size of the offset term can be accurately obtained through the grid voltage, fault point voltage, line impedance and converter output current. For the entire regulation process, two indicators, the time for the q-axis voltage to recover to stability and the maximum frequency offset, are proposed to measure the impact of the feedforward compensation term on the phase-locked loop. The specific description is as follows:

[0107] First indicator: The time it takes for the q-axis voltage to return to stability:

[0108] When the oscillation amplitude of the q-axis voltage at the feedforward compensation amount uq is less than 0.05V, it is considered to have reached stability. The horizontal axis is the total time to adjust to stability, and the vertical axis is the total time to adjust to stability. The larger the compensation amount, the longer the adjustment time. When the compensation amount is small, the change of the adjustment time is relatively gentle. Matlab is used to fit the adjustment time change curves corresponding to different feedforward compensation items. After comparing different types of fitting functions, it is found that compared with range, in Within the range of , the adjustment time required for feedforward compensation increases sharply and exceeds four cycles.

[0109] Second indicator: Maximum frequency deviation:

[0110] After compensation adjustment, the frequency collected by the phase-locked loop swings around 50Hz and gradually stabilizes. Inaccurate frequency collected by the phase-locked loop will have a greater impact on current control. Therefore, the difference between the frequency with the most serious deviation from 50Hz collected by the phase-locked loop after adjustment and 50Hz is selected as one of the indicators. As the horizontal axis, the offset of the frequency collected by the phase-locked loop is the vertical axis. Matlab is used to fit the adjustment time variation curve corresponding to different feedforward compensation items. It can be concluded that as the compensation item increases, the maximum frequency offset generated by the adjustment tends to decrease. , the maximum deviation produced during the phase-locked loop adjustment process has exceeded 0.3Hz.

[0111] It can be concluded that compared to range, Within the range of , the adjustment time required for feedforward compensation increases sharply, and the adjustment time has exceeded four cycles. Too long an adjustment time is not good for the stability of the system. Therefore, when selecting the feedforward amount, this part should be discarded; on the other hand, With Δf max It can be seen from the relationship curve that with the increase of compensation term, the maximum frequency offset caused by adjustment tends to decrease, and When the maximum offset generated in the phase-locked loop adjustment process exceeds 0.3Hz, excessive frequency offset will have an adverse effect on subsequent current control, so this part of the feedforward should be discarded. Considering the two influencing factors, the selection of the feedforward should be within Within the range.

[0112] The adjustment speed of the phase-locked loop and the maximum deviation change in opposite trends, and the two cannot be completely taken into account. Therefore, the two effects should be considered comprehensively to select a more appropriate compensation item:

[0113] Construct a function y=aΔf that reflects the adverse effects of feedforward compensation max +bt. When the system frequency is required to be more precise, that is, when the phase-locked loop is required to be more stringent, the weight of the frequency offset should be increased; when the system adjustment speed is required to be higher, the weight of the adjustment time should be increased.

[0114] Under fault conditions, due to the Within the range, the adjustment time changes relatively slowly and is more than 4 cycles. It is believed that the frequency offset has a greater impact on the system, so it is given a greater weight. Let the optimization objective function be y = 2Δf max +t. Using Δf max The fitting function of and t is used to solve the minimum value of the objective function. By calculation, the compensation term that minimizes the objective function can be obtained. That is, when the compensation amount b = 0.62b max The compensation effect is best.

[0115] 1) Three-way balance drop

[0116] Figure 6 This is a frequency and q-axis voltage waveform diagram collected by the phase-locked loop when simulating a three-phase balanced drop in one embodiment of the present invention. When performing a three-phase balanced drop, the grid voltage will drop to 0.01 times the rated value within 1 second. Figure 6 It can be seen that U tq Oscillation occurs, and it can be found that the frequency collected by the phase-locked loop is seriously deviated from 50HZ. tq When using the original phase-locked loop, continuous oscillation occurs, and loss of synchronization occurs.

[0117] Select compensation item b respectively 1 =b max 、b 2 =0.62b max , The compensation effect.

[0118] Figure 7a is a feedforward compensation voltage b during a simulated three-phase balanced drop in one embodiment of the present invention 1 =b maxThe frequency and q-axis voltage waveforms collected by the phase-locked loop are shown below. Figure 7b is a feedforward compensation voltage b during a simulated three-phase balanced drop in one embodiment of the present invention 2 =0.62b max The frequency and q-axis voltage waveforms collected by the phase-locked loop are shown below. Figure 7c The feedforward compensation voltage when simulating three-phase balanced drop in one embodiment of the present invention is Frequency and q-axis voltage waveforms collected by the phase-locked loop.

[0119] from Figure 7a , Figure 7b and Figure 7c It can be seen that after experiencing the maximum and minimum points, the offset term can be estimated. Under the power frequency, the frequency collected by the phase-locked loop should be 50Hz. From the simulation results, it can be seen that the feedforward compensation voltage b is selected respectively. 1 =b max , b 2 =0.62b max , When the voltage drops, the maximum frequency overshoots collected by the phase-locked loop are 0.22Hz, 0.27Hz, and 0.32Hz respectively. The q-axis voltage oscillation phenomenon is compensated, and the system frequency collected by the phase-locked loop is within the allowable range. The desynchronization phenomenon is improved.

[0120] 2) Three unbalanced drops

[0121] Figure 8 This is a frequency and q-axis voltage waveform diagram collected by the phase-locked loop when simulating a three-phase unbalanced drop in one embodiment of the present invention. When performing a three-phase unbalanced drop, the grid voltage phase A will drop to 0.02 times the rated value within 1 second, and both phases B and C will drop to 0.01 times the rated value within 1 second. Figure 8 It can be seen that U tq Oscillation occurs, and it can be found that the frequency collected by the phase-locked loop is seriously deviated from 50HZ. tq When using the original phase-locked loop, continuous oscillation occurs, and loss of synchronization occurs.

[0122] After adding the feedforward compensation voltage b, the effect will be significantly improved. Select the compensation item b respectively 1 =b max 、b 2 =0.62b max , The compensation effect.

[0123] Figure 9a is a feedforward compensation voltage b during a simulated three-phase unbalanced drop in one embodiment of the present invention 1 =b max The frequency and q-axis voltage waveforms collected by the phase-locked loop; Figure 9b is a feedforward compensation voltage b during a simulated three-phase unbalanced drop in one embodiment of the present invention 2 =0.62b max The frequency and q-axis voltage waveforms collected by the phase-locked loop; Fig.9c The feedforward compensation voltage when simulating three-phase unbalanced drop in one embodiment of the present invention is Frequency and q-axis voltage waveforms collected by the phase-locked loop.

[0124] from Figure 9a , Figure 9b and Fig.9c It can be seen that after experiencing the maximum and minimum points, the offset term can be estimated. From the simulation results, it can be seen that the feedforward compensation voltage b is selected respectively. 1 =b max , b 2 =0.62b max , When the voltage drops, the maximum frequency overshoots collected by the phase-locked loop are 0.22Hz, 0.26Hz, and 0.28Hz respectively. The q-axis voltage oscillation phenomenon is compensated, and the system frequency collected by the phase-locked loop is within the allowable range. The desynchronization phenomenon is improved.

[0125] When setting the grid voltage d-axis orientation mode, U tq =0. From the simulation results, it can be seen that the feedforward compensation voltage b is selected 1 =b max , b 2 =0.62b max , When the balance falls, U tq They reached stability at 0.33s, 0.26s, and 0.25s respectively. Under the unbalanced drop condition, U tq The system reaches stability at 0.31s, 0.26s, and 0.23s respectively. It can be found that when the feedforward compensation voltage is selected to be smaller, the system can reach stability faster, and the system oscillation is larger after compensation.

[0126] The present invention collects the inverter output voltage through a phase-locked loop, and obtains the q-axis component U through dq coordinate transformation. tq , and set the feedforward compensation voltage to use the feedforward compensation method to adjust the q-axis voltage collected by the phase-locked loop, which solves the problem of the phase-locked loop being unable to accurately collect the grid phase signal, i.e., loss of synchronization, when the grid voltage drops and the photovoltaic system is under low voltage riding. At the same time, by selecting different compensation voltages, it can be flexibly applied to occasions with different needs.

[0127] Those skilled in the art will appreciate that all or part of the steps to implement the above embodiments are implemented as a program (computer program) executed by a computer data processing device. When the computer program is executed, the above method provided by the present invention can be implemented. Moreover, the computer program can be stored in a computer-readable storage medium, which can be a readable storage medium such as a disk, an optical disk, a ROM, a RAM, or a storage array composed of multiple storage media, such as a disk or a tape storage array. The storage medium is not limited to centralized storage, and it can also be distributed storage, such as cloud storage based on cloud computing.

[0128] The following describes an apparatus embodiment of the present invention, which can be used to execute a method embodiment of the present invention. The details described in the apparatus embodiment of the present invention should be regarded as supplementary to the above method embodiment; details not disclosed in the apparatus embodiment of the present invention can be implemented with reference to the above method embodiment.

[0129] Fig.10 FIG. 1 is a schematic diagram of a phase signal determination device for a photovoltaic system during low voltage ride-through according to an embodiment of the present invention. Fig.10 As shown, the device 200 includes:

[0130] Voltage acquisition module 201 is used to detect a grid fault, and the photovoltaic system performs low voltage ride-through, and the collected inverter output voltage U t ;

[0131] The voltage conversion module 202 is used to convert the inverter output voltage U t Perform dq coordinate transformation to obtain the d-axis component U td and the q-axis component U tq , set the grid voltage d-axis orientation mode, calculate U tq The value of

[0132] The voltage compensation module 203 is used to set the feedforward compensation voltage in the phase-locked loop of the photovoltaic system and adjust U tq The value of is 0, so that the phase-locked loop can collect the phase signal of the fault point.

[0133] According to a preferred embodiment of the present invention, the voltage conversion module 202 further comprises:

[0134] Fault point voltage acquisition unit, used to obtain the fault point voltage U g ;

[0135] The q-axis voltage calculation unit is used to calculate the q-axis component U according to the following formula tq value:

[0136] U tq =-U g sinδ+a,

[0137] Where δ is the inverter output voltage U t and the fault point voltage U g The angle difference, a is the offset term, which represents the voltage drop of the impedance to U tq degree of impact.

[0138] According to a preferred embodiment of the present invention, the voltage compensation module 203 further comprises:

[0139] The compensation voltage setting unit is used to set the feedforward compensation voltage b to reduce the effect of the offset term a on U tq The degree of influence is as follows:

[0140] U tq =-U g sinδ+ab; and let U tq =0, that is, ab=U g sinδ;

[0141] It is also used to set different feedforward compensation voltage values ​​respectively so that the phase-locked loop collects and saves the corresponding phase signal.

[0142] Fig.11 It is a structural schematic diagram of an electronic device of an embodiment of the present invention, the electronic device includes a processor and a memory, the memory is used to store a computer executable program, when the computer program is executed by the processor, the processor executes a phase signal determination method when a photovoltaic system is under voltage crossing.

[0143] like Fig.11 As shown, the electronic device is presented in the form of a general computing device. The processor may be one or more and work in coordination. The present invention does not exclude distributed processing, that is, the processor may be dispersed in different physical devices. The electronic device of the present invention is not limited to a single entity, but may also be the sum of multiple physical devices.

[0144] The memory stores a computer executable program, which is usually a machine-readable code. The computer-readable program can be executed by the processor to enable the electronic device to perform the method of the present invention, or at least part of the steps in the method.

[0145] The memory includes a volatile memory, such as a random access memory unit (RAM) and / or a cache memory unit, and may also be a non-volatile memory, such as a read-only memory unit (ROM).

[0146] Optionally, in this embodiment, the electronic device further includes an I / O interface, which is used for the electronic device to exchange data with an external device. The I / O interface can represent one or more of several types of bus structures, including a storage unit bus or a storage unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of a variety of bus structures.

[0147] It should be understood that Fig.11 The electronic device shown is only an example of the present invention, and the electronic device of the present invention may also include elements or components not shown in the above examples. For example, some electronic devices also include display units such as display screens, and some electronic devices also include human-computer interaction elements such as buttons, keyboards, etc. As long as the electronic device can execute the computer-readable program in the memory to implement the method of the present invention or at least part of the steps of the method, it can be considered as an electronic device covered by the present invention.

[0148] Fig.12 Schematic diagram of a computer readable recording medium according to an embodiment of the present invention. Figure 4 As shown, a computer executable program is stored in a computer-readable recording medium, and when the computer executable program is executed, the phase signal determination method for low voltage ride-through of a photovoltaic system described above in the present invention is implemented. The computer-readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, device, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the above.

[0149] The computer-readable medium carries one or more programs. When the one or more programs are executed by a device, the computer-readable medium implements the following functions: when a grid fault is detected, the photovoltaic system performs low voltage ride-through, and the collected inverter output voltage U t ; The inverter output voltage U t Perform dq coordinate transformation to obtain the d-axis component U td and the q-axis component U tq , set the grid voltage d-axis orientation mode, calculate U tq Set the feedforward compensation voltage in the phase-locked loop of the photovoltaic system and adjust U tq The value of is 0, so that the phase-locked loop can collect the phase signal of the fault point.

[0150] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0151] Through the above description of the implementation mode, it is easy for those skilled in the art to understand that the present invention can be implemented by hardware capable of executing a specific computer program, such as the system of the present invention, and the electronic processing unit, server, client, mobile phone, control unit, processor, etc. contained in the system. The present invention can also be implemented by computer software that executes the method of the present invention. However, it should be noted that the computer software that executes the method of the present invention is not limited to being executed by one or a specific hardware entity, and it can also be implemented in a distributed manner by unspecified specific hardware, such as some method steps executed by the computer program can be executed on a mobile client, and another part can be executed in a smart meter, a smart recognition pen, etc. For computer software, the software product can be stored in a computer-readable storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), or it can be distributed and stored on the network, as long as it enables the electronic device to execute the method according to the present invention.

[0152] In summary, the present invention can be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that general data processing devices such as microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the embodiments of the present invention. The present invention can also be implemented as a device or apparatus program (e.g., a computer program and a computer program product) for executing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0153] The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the present invention is not inherently related to any specific computer, virtual device or electronic device, and various general devices can also implement the present invention. The above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for determining a phase signal during low voltage ride-through of a photovoltaic system, characterized in that: include: When a grid fault is detected, the photovoltaic system performs low voltage ride-through, and the collected inverter output voltage U t ; The inverter output voltage U t Perform dq coordinate transformation to obtain the d-axis component U td and the q-axis component U tq , set the grid voltage d-axis orientation mode, calculate U tq The value of U tq The value further includes: Get the fault point voltage U g ; The q-axis component U is calculated according to the following formula tq value: U tq =-U g sinδ+a, Where δ is the inverter output voltage U t With the fault point voltage U g The angle difference, a is the offset term, which represents the voltage drop of the impedance to U tq the extent of the impact; Set the feedforward compensation voltage in the phase-locked loop of the photovoltaic system to adjust U tq The value of is 0, so that the phase-locked loop collects the phase signal of the fault point; The feedforward compensation voltage is set in the phase-locked loop of the photovoltaic system to adjust U tq The value of is 0, so that the phase-locked loop collects the phase signal of the fault point, further comprising: Set the feedforward compensation voltage b to reduce the effect of the offset term a on U tq The degree of influence is as follows: U tq =-U g sinδ+a-b; Let U tq = 0, that is, a - b = U g sinδ; Different feedforward compensation voltage values ​​are set respectively so that the phase-locked loop collects and saves the corresponding phase signal.

2. The method for determining phase signal during low voltage ride-through of a photovoltaic system according to claim 1, characterized in that: The different feedforward compensation voltage values ​​are set respectively, and the phase-locked loop collects and stores the corresponding phase signal, further comprising: Set U separately g sinδ=0、U g sinδ=a / 2、U g sinδ=3a / 4, let the maximum compensation voltage be b max =(a max+ a min ) / 2; According to the setting U g The sinδ value sets the feedforward compensation voltage value to b1=b max 、b2=b max / 2、b3=b max / 4; The phase-locked loop collects phase signals of the fault point when the feedforward compensation voltage values ​​are b1, b2, and b3 respectively.

3. The method for determining phase signal during low voltage ride-through of a photovoltaic system according to claim 1, characterized in that: The phase-locked loop is a dual-quadrant generalized integrator phase-locked loop.

4. A phase signal determination device for low voltage ride-through of a photovoltaic system, characterized in that: include: The voltage acquisition module is used to detect a grid fault, and the photovoltaic system performs low voltage ride-through, and the collected inverter output voltage U t ; A voltage conversion module is used to convert the inverter output voltage U t Perform dq coordinate transformation to obtain the d-axis component U td and the q-axis component U tq , set the grid voltage d-axis orientation mode, calculate U tq The voltage conversion module further comprises: Fault point voltage acquisition unit, used to obtain the fault point voltage U g ; The q-axis voltage calculation unit is used to calculate the q-axis component U according to the following formula tq value: U tq =-U g sinδ+a, Where δ is the inverter output voltage U t With the fault point voltage U g The angle difference, a is the offset term, which represents the voltage drop of the impedance to U tq the extent of the impact; Voltage compensation module, used to set the feedforward compensation voltage in the phase-locked loop of the photovoltaic system and adjust U tq The value of is 0, so that the phase-locked loop collects the phase signal of the fault point; the voltage compensation module further includes: The compensation voltage setting unit is used to set the feedforward compensation voltage b to reduce the effect of the offset term a on U tq The degree of influence is as follows: U tq = -U g sinδ + a - b; and let U tq = 0, that is, a - b = U g sinδ; It is also used to set different feedforward compensation voltage values ​​respectively so that the phase-locked loop collects and saves the corresponding phase signal.

5. An electronic device, comprising a processor and a memory, wherein the memory is used to store a computer executable program, characterized in that: When the computer executable program is executed by the processor, the processor performs the method according to any one of claims 1 to 3.

6. A computer-readable medium storing a computer-executable program, characterized in that: When the computer executable program is executed, the method according to any one of claims 1 to 3 is implemented.

Images