Cache read context switch in memory subsystems

Abstract

The present disclosure relates to cache read context switching in a memory subsystem. A memory device includes a memory array configured with a plurality of memory planes and control logic operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array and dispersed across the plurality of memory planes, and receives, from a requestor, a cache read context switch command and a snapshot read command requesting second data from one of the plurality of memory planes of the memory array. In response to receiving the cache read context switch command, the control logic suspends processing the plurality of cache read commands and processes the snapshot read command to read the second data from the memory array and return the second data to the requestor.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to cache read context switching within memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to one aspect of this disclosure, a memory device is provided. The memory device includes: a memory array configured with a plurality of memory planes; and control logic operably coupled to the memory array for performing operations including: receiving from a requesting party a plurality of cache read commands requesting first data from the memory array and distributed across the plurality of memory planes; receiving from the requesting party a cache read context switching command and a snapshot read command requesting second data from one of the plurality of memory planes of the memory array; suspending processing of the plurality of cache read commands in response to receiving the cache read context switching command; and processing the snapshot read command to read the second data from the memory array and returning the second data to the requesting party.

[0004] According to another aspect of this disclosure, a method is provided. The method includes: receiving, at a memory device, a plurality of cache read commands from a requesting party requesting first data from a memory array of the memory device and distributed across a plurality of memory planes of the memory array; receiving, at the memory device, a cache read context switching command and a snapshot read command requesting second data from one of the plurality of memory planes of the memory array; suspending processing of the plurality of cache read commands in response to receiving the cache read context switching command; and processing the snapshot read command to read the second data from the memory array and returning the second data to the requesting party.

[0005] According to another aspect of this disclosure, a system is provided. The system includes: a memory device including a memory array configured with a plurality of memory planes; and a processing means operably coupled to the memory device for performing operations including: sending to the memory device a plurality of cache read commands requesting first data from the memory array and distributed across the plurality of memory planes; sending to the memory device a cache read context switching command and a snapshot read command requesting second data from one of the plurality of memory planes of the memory array, the cache read context switching command causing the memory device to suspend processing of the plurality of cache read commands and process the snapshot read command to read the second data from the memory array; and receiving the second data from the memory device. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2A This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 2B This is a block diagram 230 illustrating a memory subsystem implementing cache read context switching in a memory device according to some embodiments of the present disclosure.

[0010] Figure 3 This is a block diagram illustrating a multiplane memory device configured for parallel plane access, according to some embodiments of the present disclosure.

[0011] Figure 4 This is a flowchart of an example method for issuing a cache read context switch command according to some embodiments of the present disclosure.

[0012] Figure 5 This is a flowchart of an example method for processing cache read context switching commands according to some embodiments of the present disclosure.

[0013] Figures 6A-6D This is a block diagram illustrating cache read context switching in a memory device according to some embodiments of the present disclosure.

[0014] Figure 7 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0015] Various aspects of this disclosure relate to the use of cache free commands for cache reads in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of both. Examples of storage devices and memory modules are described below. Figure 1 Description. Generally, a host system may use a memory subsystem comprising one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0016] The memory subsystem may include high-density non-volatile memory devices, where data is expected to be retained when no power is supplied to the memory devices. One example of a non-volatile memory device is a NAND flash memory device. Other examples of non-volatile memory devices are described below. Figure 1 Description. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits stored. Logic states may be represented as binary values, such as “0” and “1”, or combinations of such values.

[0017] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in the form of arrays of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells of a memory device used in conjunction with one or more bit lines to generate the address of each memory cell. The intersection of bit lines and word lines constitutes the address of the memory cell. A block, hereinafter, refers to a cell of a memory device used to store data and can contain groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form planes of a memory device to allow parallel operation on each plane. A memory device can contain circuitry that performs parallel memory page accesses on two or more memory planes. For example, a memory device can contain multiple access line driver circuits and power supply circuitry that can be shared by planes of the memory device to facilitate parallel access to pages on two or more memory planes, containing different page types. For ease of description, these circuits can be collectively referred to as independent plane driver circuitry. Depending on the memory architecture employed, data can be stored across memory planes (i.e., in stripes). Therefore, a request to read a data segment (e.g., corresponding to one or more data addresses) can trigger read operations performed on two or more memory planes of the memory device.

[0018] Some memory devices are coupled to a memory subsystem controller, which can send read commands or cache read commands to the memory device via a command queue. When processing such commands, there is a delay period, referred to herein as the cache read latency (tRCBSY), which occurs before the requested data can be returned to the requester (e.g., the memory subsystem controller). During this delay period, the requested data is relocated within the memory device. For example, data may be copied from the memory array (e.g., comprising multiple planes) of the memory device to the page cache of the memory device. When processing a cache read command, data may first be written to the data register of the page cache, then from the data register to the cache register of the page cache, and then output from the cache register to the requester. When processing a general read command, data may be written directly to and from the cache register to the requester (i.e., bypassing the data register). If, for example, data from a previous read command or cache read command has been read from the array and stored in the data register, then during the delay period (e.g., tRCBSY) of the next cache read command, the data is copied from the data register before being output to the requester. In order to allow internal data transfer and thus reduce the latency of cache read commands relative to read commands, this delay period increases the overall latency of read operations, thereby negatively impacting the overall performance of the memory subsystem.

[0019] When receiving read commands of a different type than cache read commands (e.g., snapshot read commands) from the requester, the memory device can handle them differently. Compared to full-page read commands, snapshot reads can be designed for smaller workloads (i.e., limited to a specific amount of data that can be accessed in a single operation) but can be completed faster (i.e., with shorter read times). Furthermore, because snapshot read commands are associated with a higher expected Quality of Service (QoS), the memory device can take steps to reduce read latency. For example, when placed in the command queue, a snapshot read command can have a higher priority indication than a cache read command, and during processing, the requested data can be copied directly from the memory array to the cache register of the page cache before being output to the requester. When such snapshot read commands are received from the host system in the middle of or after a long sequential read stream (e.g., a series of multiple cache read commands), the command queue of the memory subsystem controller can be filled with lower-priority commands. This prevents higher-priority snapshot read commands from being placed in the command queue unless a separate terminate cache command is issued before the snapshot read command actually disrupts the cache read pipeline (i.e., cache registers and data registers). Therefore, these memory devices can only either abort all cache read commands already queued in the command queue, process the terminate cache and snapshot read commands, and then resume the previous cache read commands, or simply wait until all pending cache read commands have been processed before processing the snapshot read command. However, both approaches increase the complexity of the firmware design for the requesting party (e.g., the memory subsystem controller) and increase the associated latency for processing snapshot read commands.

[0020] The aspects of this disclosure address the above and other drawbacks by implementing cache read context switching commands for cache read context switching in the memory subsystem. In one embodiment, the cache read context switching command is issued by a requester and received by a memory device in the memory subsystem, allowing pending memory access commands (e.g., cache read commands) from the requester's command queue to be paused. Upon receiving the cache read context switching command, control logic in the memory device can receive and process a snapshot read command without overwriting cache read data in the page buffer or experiencing the latency introduced by terminating the cache command. For example, the control logic can move any data corresponding to the cache read command in the page buffer's cache register to the page buffer's data register, such that data associated with the snapshot read command can be directly copied from the memory array to the cache register and then passed to the requester. In one embodiment, the cache read context switching command and the snapshot read command are queued in the command queue of the memory subsystem controller with a higher priority than other cache read commands. This higher priority allows the corresponding command to be processed before lower priority commands, even if the lower priority command might have been received and queued before the higher priority command. When executing a snapshot read command, the cache read context recovery command can be processed to restore to the previous context and resume the execution of pending cache read commands or newly received cache read commands.

[0021] The advantages of this approach include, but are not limited to, improved performance of the memory subsystem. In the manner described herein, snapshot read commands can be processed with reduced latency because only the currently executing cache read command needs to complete before processing the snapshot read command, instead of waiting for all previously received and pending cache read commands to complete. This latency reduction can be achieved without increasing firmware overhead and complexity in the memory subsystem controller, and without having to abort and restart all pending cache read commands. Therefore, the quality of service for certain high-priority read commands is improved, and the overall read throughput of the memory subsystem is increased.

[0022] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0027] Host system 120 can be coupled to memory system 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM Fast (NVMe) interface, an Open NAND Flash Interface (ONFI), or some other interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. For example, NAND flash memory includes two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages that can refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memory (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is shown to include a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] In one embodiment, memory subsystem 110 includes a memory interface component 113, which includes a cache manager 114. The memory interface component 113 is responsible for handling the interaction between the memory subsystem controller 115 and memory devices (e.g., memory device 130) of the memory subsystem 110. For example, the memory interface component 113 may send memory access commands, such as programming commands, read commands, or other commands, to the memory device 130 in response to a request received from the host system 120. Additionally, the memory interface component 113 may receive data from the memory device 130, such as data retrieved in response to confirmation that a read command or programming command has been successfully executed. In some embodiments, the memory subsystem controller 115 includes at least a portion of the cache manager 114. For example, the memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the memory interface component 113 is part of the host system 110, an application, or an operating system. In one embodiment, the memory interface 113 includes the cache manager 114 and other subcomponents. The cache manager 114 can direct memory access commands (e.g., read commands, cache read commands, snapshot read commands, cache read context switch commands, or cache reach context restore commands) to the memory device 130. In one embodiment, the memory device 130 includes a cache agent 134 configured to perform a corresponding memory access operation in response to receiving a memory access command from the cache manager 114. In some embodiments, the local media controller 135 includes at least a portion of the cache agent 134 and is configured to perform the functions described herein. In some embodiments, the cache agent 134 is implemented on the memory device 130 using firmware, hardware components, or a combination of the foregoing.

[0039] In one embodiment, cache agent 134 receives from a requesting party, such as cache manager 114, a series of cache read commands (e.g., sequential read commands) requesting first data from the memory array of memory device 130 and distributed across multiple memory planes. Cache agent 134 further receives from the requesting party a cache read context switch command and a snapshot read command requesting second data from one of the multiple memory planes of the memory array of memory device 130. In response to receiving the cache read context switch command, cache agent 134 may suspend processing of the multiple cache read commands and process the snapshot read command to read the second data from the memory array and return the second data to the requesting party. Further details regarding the operation of cache manager 114 and cache agent 134 are described below.

[0040] Figure 2A It is a memory subsystem according to an embodiment (e.g., Figure 1 This is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem 110 and a memory subsystem controller 115. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) can be a memory controller or other external host device.

[0041] Memory device 130 includes an array 250 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 250 ( Figure 2A (Not shown in the text) can be programmed to be one of at least two target data states.

[0042] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode address signals. Address signals are received and decoded to access memory cell array 250. Memory device 130 also includes input / output (I / O) control circuitry 212 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 214 communicates with I / O control circuitry 212, row decoding circuitry 208, and column decoding circuitry 210 to latch address signals before decoding. Command register 224 communicates with I / O control circuitry 212 and local media controller 135 to latch incoming commands.

[0043] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 250 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 250. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control them in response to addresses. In one embodiment, the local media controller 135 includes a cache agent 134 that can implement cache read context switching of memory device 130, as described herein.

[0044] The local media controller 135 also communicates with cache register 242. Cache register 242 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 250 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 242 to data register 244 for transfer to memory cell array 250; then, new data can be latched from I / O control circuitry 212 into cache register 242. During read operations, data can be transferred from cache register 242 to I / O control circuitry 212 for output to memory subsystem controller 115; then, new data can be transferred from data register 244 back to cache register 242. Cache register 242 and / or data register 244 may form a page buffer (e.g., may form a portion thereof) of memory device 130. The page buffer may further include sensing devices ( Figure 2A(Not shown in the diagram) The data state of the memory cells can be sensed, for example, by sensing the state of the data lines of the memory cells connected to the memory cell array 250. The status register 222 can communicate with the I / O control circuitry system 212 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0045] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 232. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 234, and outputs data to memory subsystem controller 115 via I / O bus 234.

[0046] For example, commands can be received via the input / output (I / O) pins [7:0] of the I / O bus 234 at I / O control circuitry system 212, and then written to the command register 224. Addresses can be received via the input / output (I / O) pins [7:0] of the I / O bus 234 at I / O control circuitry system 212, and then written to the address register 214. Data can be received via the input / output (I / O) pins [7:0] for 8-bit devices or the input / output (I / O) pins [15:0] for 16-bit devices at I / O control circuitry system 212, and then written to the cache register 242. Data can then be written to the data register 244 for programming the memory cell array 250.

[0047] In this embodiment, cache register 242 may be omitted, and data may be written directly to data register 244. Data may also be output on input / output (I / O) pins [7:0] for 8-bit devices or on input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0048] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 2AThe memory device 130. It should be understood that, reference Figure 2A The functionality of the various block components described may not necessarily be separate from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2A The functionality can exceed that of a single component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2A The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that combinations of other I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0049] Figure 2B This is a block diagram 230 illustrating a memory subsystem implementing cache read context switching in a memory device according to some embodiments of the present disclosure. In one embodiment, a memory interface 113 is operatively coupled to the memory device 130. In one embodiment, the memory device 130 includes a page cache 240 and a memory array 250. The memory array 250 may comprise an array of memory cells formed at the intersection of a word line and a bit line (not shown), such as word line 252. In one embodiment, the memory cells are grouped into blocks, which may be further divided into sub-blocks, wherein a given word line, such as word line 252, is shared, for example, across multiple sub-blocks 254a, 254b, 254c, 254d. In one embodiment, each sub-block corresponds to a separate plane in the memory array 250. The group of memory cells associated with a word line within a sub-block is referred to as a physical page. Each physical page in one of the sub-blocks may contain multiple page types. For example, a physical page formed by a single level cell (SLC) has a single page type, referred to as a lower logical page (LP). Multilevel cell (MLC) physical page types may include LP and upper logical page (UP), TLC physical page types are LP, UP, and additional logical page (XP), and QLC physical page types are LP, UP, XP, and top logical page (TP). For example, a physical page formed by memory cells of the QLC memory type may have a total of four logical pages, where the data stored in each logical page may be different from the data stored in the other logical pages associated with that physical page.

[0050] Depending on the programming scheme used, each logical page of the memory cell can be programmed in a separate programming pass, or multiple logical pages can be programmed together. For example, in a QLC physical page, LP can be programmed in one pass, and UP, XP, and TP can be programmed in a second pass. Other programming schemes are possible. Page cache 240 is a buffer for temporarily storing data read from or written to the memory array 250 of memory device 130, and may include cache register 242 and one or more data registers 244-246. For a read operation, data is read from memory array 250 into one of data registers 244-246, and then into cache register 242. Memory interface 113 can then read data from cache register 242. For a programming operation, memory interface 113 writes data to cache register 242, then the data is passed to one of data registers 244-246, and finally programmed into memory array 250. If the programming operation involves multiple pages (e.g., UP, XP, and TP), then each page can have a dedicated data register to hold the corresponding page data.

[0051] In one embodiment, cache manager 114 issues a series of cache read commands from command queue 248 (e.g., a hardware queue), which are received by cache agent 134. In one embodiment, the cache read commands are queued in command queue 248 with a low priority indication and issued by cache manager 114 to read first data from memory array 250. In one embodiment, cache manager 114 issues cache read context switch commands and snapshot read commands from command queue 248, which are received by cache agent 134. In one embodiment, cache read context switch commands and snapshot read commands are queued in command queue 248 with a higher priority indication than cache read commands. In response to receiving a cache read context switch command, cache agent 134 may suspend processing of the received cache read command. In one embodiment, to suspend processing of the cache read command, cache agent 134 may move a portion of the first data associated with the cache read command from cache register 242 to one of data registers 244-246. In one embodiment, to process a snapshot read command, cache agent 134 may copy second data associated with the snapshot read command directly from memory array 250 to cache register 242 (i.e., bypassing the one or more data registers 244-246). The second data may be returned to the requesting party. In one embodiment, upon receiving the second data associated with the snapshot read command, cache manager 114 issues a cache read context recovery command, which is received by cache agent 134. In response to receiving the cache read context recovery command, cache agent 134 may resume processing the cache read command by moving the portion of the first data associated with the cache read command from one of the data registers 244-246 back to cache register 242.

[0052] Figure 3 This is a block diagram illustrating a multi-plane memory device 130 configured for independent parallel plane access according to some embodiments of the present disclosure. Memory planes 372(0)-372(3) can each be divided into data blocks, wherein two or more different relative data blocks from memory planes 372(0)-372(3) can be accessed in parallel during a memory access operation. For example, during a memory access operation, two or more of the following can be accessed in parallel: data block 382 of memory plane 372(0), data block 383 of memory plane 372(1), data block 384 of memory plane 372(2), and data block 385 of memory plane 372(3).

[0053] The memory device 130 includes a memory array 250 divided into memory planes 372(0)-372(3), each memory plane containing a corresponding number of memory cells. The multi-plane memory device 130 may further include a local media controller 135, including power control circuitry and access control circuitry, for performing memory access operations on the different memory planes 372(0)-372(3) in parallel. The memory cells may be non-volatile memory cells, such as NAND flash cells, or may generally be any type of memory cell.

[0054] Memory planes 372(0)-372(3) can each be divided into data blocks, wherein different relative data blocks of each of memory planes 372(0)-372(3) can be accessed in parallel during memory access operations. For example, during memory access operations, data block 382 of memory plane 372(0), data block 383 of memory plane 372(1), data block 384 of memory plane 372(2), and data block 385 of memory plane 372(3) can be accessed in parallel respectively.

[0055] Each of the memory planes 372(0)-372(3) may be coupled to a corresponding page buffer 376(0)-376(3). Each page buffer 376(0)-376(3) may be configured to provide data to or receive data from the corresponding memory plane 372(0)-372(3). Page buffers 376(0)-376(3) may be controlled by a local media controller 135. Data received from the corresponding memory planes 372(0)-372(3) may be latched at page buffers 376(0)-376(3) respectively, retrieved by the local media controller 135, and provided to the memory subsystem controller 115, for example, via an ONFI interface.

[0056] Each of the memory planes 372(0)-372(3) may be further coupled to a corresponding access driver circuit 374(0)-374(3), such as an access line driver circuit. The driver circuits 374(0)-374(3) may be configured to regulate the pages of the corresponding block of the associated memory plane 372(0)-372(3) for memory access operations, such as programming data (i.e., writing data), reading data, or erasing data. Each of the driver circuits 374(0)-374(3) may be coupled to a corresponding global access line associated with the corresponding memory plane 372(0)-372(3). During a memory access operation associated with a page within a block, each global access line may be selectively coupled to a corresponding local access line within the block of the plane. The driver circuits 374(0)-374(3) may be controlled based on signals from the local media controller 135. Each of the driver circuits 374(0)-374(3) may include or be coupled to a corresponding power supply circuit, and may supply a voltage to the corresponding access line based on the voltage provided by the corresponding power supply circuit. The voltage provided by the power supply circuit may be based on a signal received from the local media controller 135.

[0057] The local media controller 135 can control driver circuits 374(0)-374(3) and page buffers 376(0)-376(3) to perform memory access operations in parallel with each of a set of memory command and address pairs (e.g., received from the memory subsystem controller 115). For example, the local media controller 135 can control driver circuits 374(0)-374(3) and page buffers 376(0)-376(3) to perform parallel memory access operations. The local media controller 135 may include: power control circuitry that serially configures two or more of the driver circuits 374(0)-374(3) for parallel memory access operations; and access control circuitry configured to control two or more of the page buffers 376(0)-376(3) to sense and latch data from the respective memory planes 372(0)-372(3), or to program data into the respective memory planes 372(0)-372(3) to perform parallel memory access operations.

[0058] In operation, the local media controller 135 may receive a set of memory command and address pairs via an ONFI bus, each pair arriving in parallel or serial. In some instances, the set of memory command and address pairs may each be associated with a different corresponding memory plane 372(0)-372(3) of the memory array 250. The local media controller 135 may be configured to perform parallel memory access operations (e.g., read operations or programming operations) on the different memory planes 372(0)-372(3) of the memory array 250 in response to the set of memory command and address pairs. For example, the power control circuitry of the local media controller 135 may serially configure driver circuitry 374(0)-374(3) of two or more memory planes 372(0)-372(3) associated with the set of memory command and address pairs for parallel memory access operations based on the corresponding page type (e.g., UP, MP, LP, XP, SLC / MLC / TLC / QLC pages). After the access line driver circuits 374(0)-374(3) are configured, the access control circuitry of the local media controller 135 can control the page buffers 376(0)-376(3) in parallel to access, during parallel memory access operations, the corresponding pages of each of the two or more memory planes 372(0)-372(3) associated with the set of memory command and address pairs, for example, to retrieve or write data. For example, the access control circuitry can control the page buffers 376(0)-376(3) in parallel (e.g., in parallel and / or simultaneously) to charge / discharge bit lines, sense data from the two or more memory planes 372(0)-372(3), and / or latch data.

[0059] Based on signals received from the local media controller 135, driver circuits 374(0)-374(3) coupled to memory planes 372(0)-372(3) associated with the set of memory command and address command pairs can select blocks of memory or memory cells from the associated memory planes 372(0)-372(3) for memory operations, such as read, program, and / or erase operations. Driver circuits 374(0)-374(3) can drive different corresponding global access lines associated with the respective memory planes 372(0)-372(3). As an example, driver circuit 374(0) can drive a first voltage on a first global access line associated with memory plane 372(0), driver circuit 374(1) can drive a second voltage on a third global access line associated with memory plane 372(1), driver circuit 374(2) can drive a third voltage on a seventh global access line associated with memory plane 372(2), and so on, and other voltages on each of the remaining global access lines can be driven. In some instances, pass voltages may be provided on all access lines except for those associated with pages of memory planes 372(0)-372(3) to be accessed. The local media controller 135 and driver circuits 374(0)-374(3) may allow parallel access to page buffers 376(0)-376(3) within different corresponding blocks of different corresponding pages and memory cells. For example, the first page of the first block of the first memory plane may be accessed in parallel with the second page of the second block of the second memory plane, regardless of page type.

[0060] Page buffers 376(0)-376(3) can provide data to or receive data from the local media controller 135 in response to signals from the local media controller 135 and the corresponding memory planes 372(0)-372(3) during memory access operations. The local media controller 135 can provide the received data to the memory subsystem controller 115.

[0061] It should be understood that memory device 130 may include more or fewer memory planes, driver circuitry, and page buffers than four. It should also be understood that the corresponding global access lines may include 8, 16, 32, 64, 128, or similar numbers of global access lines. Local media controller 135 and driver circuitry 374(0)-374(3) may access different pages within different blocks of different memory planes in parallel, if the different pages have different page types. For example, local media controller 135 may include multiple different processing threads, such as processing threads 334(0)-334(3). Each of processing threads 334(0)-334(3) may be associated with a corresponding one in memory planes 372(0)-372(3) and may manage operations performed on the corresponding plane. For example, each of the processing threads 334(0)-334(3) may provide control signals to the correspondings in the driver circuits 374(0)-374(3) and page buffers 376(0)-376(3) to perform those memory access operations in parallel (e.g., at least partially overlapping in time).

[0062] In one embodiment, cache agent 134 receives and processes memory access commands, such as read commands, cache read commands, cache read context switching commands, snapshot read commands, and cache read context recovery commands. In one embodiment, cache agent 134 receives a series of cache read commands (e.g., sequential read commands) that request first data from memory array 250 and are distributed across multiple memory planes 372(0)-372(3). For example, a cache read command may request data from two or more of data blocks 382, ​​383, 384, or 385. Cache agent 134 further receives from the requester a cache read context switching command and a snapshot read command that requests second data from one of the memory planes 372(0)-372(3) of memory array 250 of memory device 130. For example, a snapshot read command may request data from one of data blocks 382, ​​383, 384, or 385. In response to receiving a cache read context switch command, cache agent 134 may suspend processing of cache read commands and process snapshot read commands to read second data from memory array 250 and return the second data to the requester.

[0063] Figure 4This is a flowchart illustrating an example method of issuing a cache read context switch command according to some embodiments of the present disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 and Figure 2B The cache manager 114 executes. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0064] At operation 405, a command is sent. For example, processing logic (e.g., cache manager 114) may send a memory access command / request, such as a cache read command, to a memory device (e.g., memory device 130). In one embodiment, a cache read command is one of a series of cache read commands (e.g., sequential read commands) that request first data from a memory array (e.g., memory array 250) and are distributed across multiple memory planes (e.g., memory planes 372(0)-372(3)). In one embodiment, cache manager 114 may store cache read commands in a hardware queue (e.g., command queue 248). In one embodiment, cache read commands are stored in command queue 248 with a low priority indication. For example, the indication may be a unit or multi-bit value associated with each command, wherein the value contains a known pattern indicating low priority. In one embodiment, low priority is indicated when a cache read command is received (e.g., from host system 120). In another embodiment, cache manager 114 identifies low priority based on the type of command received. In one embodiment, cache manager 114 issues commands from command queue 248 according to an indicated priority. If command queue 248 contains only low-priority commands, cache read commands may be issued in the order they were received and stored in command queue 248. Cache agent 134 on memory device 130 may receive and process cache read commands to read and return first data.

[0065] At operation 410, a command is sent. For example, processing logic may send a cache read context switch command to memory device 130. At operation 415, a command is sent. For example, processing logic may send a snapshot read command to memory device 130. In one embodiment, the snapshot read command requests second data from one of memory planes 372(0)-372(3) of memory array 250. Cache agent 134 on memory device 130 may process the cache read context switch command, which causes the memory device to suspend processing of the cache read command and begin processing the snapshot read command to read the second data from memory array 250. In one embodiment, the cache read context switch command and the single-plane read command are stored in command queue 248. In one embodiment, the cache read context switch command and the single-plane read command are stored in command queue 248 with a high priority indication. For example, the indication may be a single or multi-bit value associated with each command, wherein the value contains a known pattern indicating high priority. In one embodiment, high priority is indicated when a command is received (e.g., from host system 120). In another embodiment, cache manager 114 identifies high priority based on the type of the received command. Cache manager 114 issues commands from command queue 248 according to the indicated priority. If command queue 248 contains both high-priority and low-priority commands, then a high-priority single-plane read command may be issued before at least one of the lower-priority cache read commands that precede the high-priority cache read context switch command and the single-plane read command.

[0066] At operation 420, data is received. For example, the processing logic may receive data from memory device 130, such as second data associated with a snapshot read command.

[0067] At operation 425, a command is sent. For example, the processing logic may send a cache read context recovery command to memory device 130. Cache agent 134 on memory device 130 may process the cache read context recovery command that causes the memory device to resume processing cache read commands.

[0068] Figure 5 This is a flowchart illustrating an example method for processing cache read context switch commands according to some embodiments of the present disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figures 1-3The cache agent 134 executes. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0069] At operation 505, a command is received. For example, processing logic (e.g., cache agent 134) may receive a memory access command / request, such as cache read command 502. In one embodiment, a cache read command is one of a series of cache read commands (e.g., sequential read commands) that request first data from a memory array (e.g., memory array 250) and are distributed across multiple memory planes (e.g., memory planes 372(0)-372(3)) of memory device 130. In one embodiment, the cache read command is received from a requester, such as cache manager 114 of memory subsystem controller 115.

[0070] At operation 515, the command is processed. For example, the processing logic may receive a cache read command and process the cache read command. In one embodiment, such as Figure 6A As shown, to process a cache read command, cache agent 134 may copy first data from memory array 250 to one of data registers 244-246, and then to cache register 242, from which the first data may be output to the requesting party. For example, data associated with a cache read command (e.g., page N) may be in cache register 242, while data associated with a subsequent cache read command (e.g., page N+1) may be in data register 244. In one embodiment, data is read from memory array 250 via a sense amplifier (SA).

[0071] At operation 520, a command is received. For example, the processing logic may receive a cache read context switch command from the requester. In one embodiment, the cache read context switch command is a unique memory command that causes the memory device 130 to switch command processing contexts during processing. For example, if a low-priority sequential cache read command is currently being processed, then upon receiving the cache read context switch command, the memory device 130 may switch to a high-priority command processing context to recognize the incoming high-priority memory access command, which may be processed out of order (e.g., before previously received cache read commands). In one embodiment, the read context switch command has a unique format or unique content that can be identified by the memory device 130 to recognize the read context switch command.

[0072] At operation 525, a command is received. For example, the processing logic may receive a snapshot read command from the requesting party. In one embodiment, the snapshot read command requests second data from one of the memory planes 372(0)-372(3) of the memory array 250.

[0073] At operation 535, command processing is paused. For example, the processing logic may pause processing cache read commands. In one embodiment, the currently processed cache read command may be allowed to complete, while processing of any remaining cache read commands is paused. In one embodiment, such as Figure 6B As shown, to pause command processing, cache agent 134 moves the portion of the first data associated with the cache read command from cache register 242 of page cache 240 to data register 246 of page cache 240. Therefore, the portion of data from cache register 242 remains in data register 246, allowing processing of the cache read command to resume later without needing to reread that portion of data from memory array 250. In one embodiment, processing of the cache read command is paused after receiving a cache read context switch command at operation 520 and executing a high-priority cache read context switch command; this execution may occur before or after receiving a snapshot read command at operation 525.

[0074] At operation 540, commands are processed. For example, the processing logic may receive and process a snapshot read command. In one embodiment, such as... Figure 6C As shown, to process a snapshot read command, cache agent 134 can copy second data (e.g., an iWL page) from memory array 250 to cache register 242 (i.e., bypassing data registers 244-246 that store pages N and N+1), from which first data can be output to the requesting party. In one embodiment, data is read from memory array 250 via a sense amplifier (SA).

[0075] At box 545, data is returned. For example, the processing logic may send data, such as second data associated with a snapshot read command, to the requesting party (e.g., cache manager 114 of memory subsystem controller 115).

[0076] At block 550, a command is received. For example, the processing logic may receive a cache read context recovery command from the requester. In one embodiment, the cache read context recovery command is a unique memory command that, upon processing, restores the memory device 130 to the previous command processing context. For example, if a low-priority sequential cache read command was previously processed and a high-priority command processing context has been switched, then upon receiving the cache read context recovery command, the memory device 130 may restore to the previous command processing context and resume processing sequential cache read commands. In one embodiment, the read context recovery command has a unique format or unique content that can be identified by the memory device 130 to recognize the read context recovery command.

[0077] At operation 555, command processing is resumed. For example, the processing logic may resume processing of a previously suspended cache read command. In one embodiment, cache agent 134 on memory device 130 may process a cache read context resume command that causes the memory device to resume processing of cache read commands. In one embodiment, such as Figure 6D As shown, to resume command processing, cache agent 134 moves the portion of the first data associated with the cache read command from data register 246 of page cache 240 back to cache register 242 of page cache 240. This portion of the data can then be returned to the requesting party without needing to be reread from memory array 250.

[0078] Figure 7 An example machine is shown that contains a computer system 700 executable with a set of instructions for causing the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1 (The operation of the cache manager 114 and / or cache agent 134). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0079] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should be considered to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any of the methods discussed herein.

[0080] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0081] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication on network 720.

[0082] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium, such as a non-transitory computer-readable medium) on which one or more sets of instructions 726 or software embodying any one or more methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0083] In one embodiment, instruction 726 includes instructions for implementing the corresponding Figure 1The cache manager 114 and / or cache agent 134 contain functional instructions. While machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0084] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms here and generally are considered as a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0085] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0086] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0087] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to implement the methods. The architectures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0088] This disclosure can be provided as a computer program product or software, which may include machine-readable media having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0089] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: A memory array configured with multiple memory planes; as well as Control logic, operably coupled to the memory array, is used to perform operations including: Receive from the requesting party a request for first data from the memory array and multiple cache read commands distributed across the multiple memory planes; The requester receives a cache read context switch command and a snapshot read command requesting second data to a single plane among the plurality of memory planes of the memory array, wherein the cache read context switch command and the snapshot read command are stored in a command queue associated with the requester with a higher priority than the plurality of cache read commands. In response to receiving the cache read context switching command, the processing of the plurality of cache read commands is suspended; as well as The snapshot read command is processed to read the second data from a single plane among the plurality of memory planes of the memory array and to return the second data to the requesting party.

2. The memory device of claim 1, wherein the requesting party includes a memory subsystem controller of a memory subsystem, the memory subsystem including the memory device.

3. The memory device of claim 1, wherein the cache read context switching command and the snapshot read command are received and processed before at least one cache read command stored in the command queue prior to the cache read context switching command and the snapshot read command.

4. The memory device according to claim 1, further comprising: The page cache includes a cache register and multiple data registers.

5. The memory device of claim 4, wherein pausing processing of the plurality of cache read commands includes moving a portion of the first data associated with the plurality of cache read commands from the cache register to one of the plurality of data registers.

6. The memory device of claim 5, wherein processing the snapshot read command includes copying the second data associated with the snapshot read command from the memory array to the cache register.

7. The memory device of claim 5, wherein the control logic is configured to perform other operations including: Receive a cache read context recovery command from the requesting party; and In response to receiving the cache read context recovery command, the processing of the plurality of cache read commands is resumed.

8. The memory device of claim 7, wherein resuming processing of the plurality of cache read commands includes moving the portion of the first data associated with the plurality of cache read commands from the one of the plurality of data registers back to the cache register.

9. A method comprising: At the memory device, a requesting party receives multiple cache read commands from the requesting party requesting first data from the memory array of the memory device and distributed across multiple memory planes of the memory array; The memory device receives a cache read context switch command and a snapshot read command requesting second data to a single plane among the plurality of memory planes of the memory array from the requesting party, wherein the cache read context switch command and the snapshot read command are stored in a command queue associated with the requesting party with an indication of higher priority than the plurality of cache read commands; In response to receiving the cache read context switching command, the processing of the plurality of cache read commands is suspended; as well as The snapshot read command is processed to read the second data from a single plane among the plurality of memory planes of the memory array and to return the second data to the requesting party.

10. The method of claim 9, wherein the requesting party includes a memory subsystem controller of a memory subsystem, the memory subsystem including the memory device.

11. The method of claim 9, wherein the cache read context switching command and the snapshot read command are received and processed before at least one cache read command stored in the command queue prior to the cache read context switching command and the snapshot read command.

12. The method of claim 9, wherein pausing processing of the plurality of cache read commands includes moving a portion of the first data associated with the plurality of cache read commands from a cache register of the page cache to one of a plurality of data registers of the page cache.

13. The method of claim 12, wherein processing the snapshot read command includes copying the second data associated with the snapshot read command from the memory array to the cache register.

14. The method of claim 12, further comprising: Receive a cache read context recovery command from the requester; as well as In response to receiving the cache read context recovery command, the processing of the plurality of cache read commands is resumed.

15. The method of claim 14, wherein resuming processing of the plurality of cache read commands includes moving the portion of the first data associated with the plurality of cache read commands from the one of the plurality of data registers back to the cache register.

16. A system comprising: A memory device comprising a memory array configured with multiple memory planes; as well as A processing device, operatively coupled to the memory device, for performing operations including: Send to the memory device a request for first data from the memory array and a multi-cache read command distributed across multiple memory planes; Sending a cache read context switch command to the memory device and a snapshot read command requesting second data from a single plane among the plurality of memory planes of the memory array, the cache read context switch command causing the memory device to suspend processing the plurality of cache read commands and process the snapshot read command to read the second data from the single plane among the plurality of memory planes of the memory array, wherein the cache read context switch command and the snapshot read command are sent to the memory device with an indication of higher priority than the plurality of cache read commands; as well as Receive the second data from the memory device.

17. The system of claim 16, wherein, to pause processing of the plurality of cache read commands, the memory device moves a portion of the first data associated with the plurality of cache read commands from a cache register of a page cache to one of a plurality of data registers of the page cache, and wherein, to process the snapshot read command, the memory device copies the second data associated with the snapshot read command from the memory array to the cache register.

18. The system of claim 17, wherein the processing device performs the following operations: A cache read context recovery command is sent to the memory device, which causes the memory device to resume processing the plurality of cache read commands.

19. The system of claim 18, wherein, in order to resume processing of the plurality of cache read commands, the memory device moves the portion of the first data associated with the plurality of cache read commands from one of the plurality of data registers back to the cache register.

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