Automatic calculation method and system for signal sampling delay time in chip post-simulation verification

Abstract

The present invention discloses a method and system for automatically calculating signal sampling delay time during chip post-simulation verification. This method uses a script to extract waveform data to generate a text file. The text file is then parsed to determine the start and end times of the delay chain, the current sampling time point, and the ideal sampling time point. Finally, the signal value is input into a calculation formula to calculate the ideal data sampling delay time. This method is fully automated, reducing human intervention and errors, and improving the efficiency of chip post-simulation verification.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and in particular to a method and system for automatically calculating signal sampling delay time in chip post-simulation verification. Background Art

[0002] Post-simulation verification of digital circuits is a crucial step in digital circuit design, used to check timing compliance and avoid timing violations. Digital post-simulation requires gate-level netlists and SDF (simulation files with delay information) files for each corner (process condition). Engineers need to back-annotate the SDF files, allowing the simulation tool to change the default delay times of digital circuits. In post-simulation verification of some memory chips, the delay chain of the physical interface transceiver (PHY) circuit is often adjusted to meet sampling timing requirements, ensuring that the controller can better sample data from the memory chip. Adjusting the Phy delay can be done by manually extracting and calculating signal values ​​from simulation waveforms. However, circuit delay times vary across multiple channels, and so do delay times for different SDF corners. Sometimes, finding the optimal sampling point for a single channel requires repeated attempts. In time-sensitive post-simulation verification, manual calculation errors can lead to the need for recalculation and post-simulation, which wastes significant time, reduces post-simulation verification efficiency, and impacts the overall chip project progress. Summary of the Invention

[0003] In response to the shortcomings of the prior art, the present invention provides a method and system for automatically calculating the signal sampling delay time in chip post-simulation verification. The method automatically calculates the delay time of data sampling without manual completion, reduces human intervention and errors, and improves the efficiency of chip post-simulation verification.

[0004] In order to solve the above technical problems, the present invention adopts a technical solution: a method for automatically calculating the signal sampling delay time in chip post-simulation verification, comprising the following steps:

[0005] S01) Select the Sdf of a certain Corner or the delay time calculation under a certain channel, and judge whether the current delay time can correctly sample the data. If not, execute the next step, otherwise end;

[0006] S02), inputting a waveform file for signal value extraction, extracting the signal value of the generated waveform file to generate a text file;

[0007] S03) Extract the data of the text file and extract the time value T of the input delay chain. in , the time value T of the output delay chain out , the time value T of the current sampling reference signal dqs ,, the sampled data time value Tdata , the current delay time value T current_delay ;

[0008] S04), determine whether the current sampling time value is advanced or delayed, if it is advanced, execute step S05), if it is delayed, execute step S06);

[0009] S05) The current sampling time value is ahead of the sampled time, and a delay time needs to be added. The delay time is:

[0010]

[0011] Where T clk is the clock frequency, T precision is the accuracy;

[0012] S06) The current sampling time value lags behind the sampled time, and the delay time needs to be reduced. The delay time is:

[0013]

[0014] T clk is the clock frequency, T precision is the accuracy;

[0015] S07), converting the time value output in step S05) or S06) into a register value to be configured and outputting it;

[0016] S08) Determine whether all corners or channels are calculated. If not, execute the first step, otherwise, end.

[0017] Furthermore, in step S01), the fixed data of the chip is read to determine whether the current delay time is sufficient to correctly sample the data.

[0018] Furthermore, in step S02), the signal value is extracted using the Fsdbreport tool to generate a text file.

[0019] The present invention also discloses an automatic calculation system for signal sampling delay time in chip post-simulation verification, comprising a sampling delay time judgment module, a waveform file data extraction module, a signal time value extraction module, a signal sampling time value judgment module, a delay time calculation module A, a delay time calculation module B and a delay time value output module;

[0020] The sampling delay time judgment module judges whether the current delay time can sample the correct data. If not, the waveform file data extraction module inputs the waveform file to be used for signal value extraction, extracts the signal value of the generated waveform file and generates a text file;

[0021] The signal time value extraction module extracts the signal value required for calculating the delay time from the generated text file, including the delay chain input time value extraction module, the delay chain output time value extraction module, the signal sampling time value extraction module, the sampled data time value extraction module, and the current delay time value extraction module. The delay chain input time value extraction module is used to extract the time value T of the input delay chain. in The delay chain output time value extraction module is used to extract the time value T of the output delay chain. out The signal sampling time value extraction module extracts the time value T of the current sampling reference signal. dqs The sampled data time value extraction module extracts the time value T of the sampled data. data The current delay time value extraction module extracts the current delay time value T current_delay The signal sampling time value judgment module determines whether the current sampling time value is ahead of or behind the sampled data. If it is ahead, it enters the delay time calculation module A; if it is behind, it enters the delay time calculation module B.

[0022] Delay time calculation module A and delay time calculation module B are used to calculate the delay time;

[0023] The formula for calculating the delay time by the delay time calculation module A is:

[0024]

[0025] The formula for calculating the delay time by the delay time calculation module B is:

[0026]

[0027] Among them, T clk is the clock frequency, T precision is the accuracy;

[0028] The delay time value output module converts the delay time calculated by the delay time calculation modules A and B into the value to be configured and outputs it.

[0029] Furthermore, the sampling delay time judgment module makes a judgment by reading fixed data from the storage chip. If the read data is wrong, it means that the current delay time is incorrect.

[0030] Furthermore, the waveform file data extraction module uses the Fsdbreport tool to extract signal values ​​and generate a file in txt format.

[0031] The present invention can automatically calculate the delay time for data sampling, eliminating the need for manual work. A script extracts waveform data to generate a text file. This file is then parsed to determine the delay chain's start and end times, the current sampling time point, and the ideal sampling time point. Finally, the signal value is input into a calculation formula to calculate the ideal delay time for data sampling. This automated method reduces manual intervention and errors, improving the efficiency of post-chip simulation verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a system block diagram of Example 1;

[0033] Figure 2 This is a flow chart of Example 2. DETAILED DESCRIPTION

[0034] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0035] Example 1

[0036] This embodiment discloses an automatic calculation system for signal sampling delay time in chip post-simulation verification, such as Figure 1 As shown, the system includes a sampling delay time determination module, a waveform file data extraction module, a signal time value extraction module, a signal sampling time value determination module, a signal sampling time value calculation module A, a signal sampling time value calculation module B, and a delay time value output module. The signal time value extraction module is further divided into a delay chain input time value extraction module, a delay chain output time value extraction module, a signal sampling time value extraction module, a sampled data time value extraction module, and a current delay time value extraction module.

[0037] The sampling delay time judgment module determines whether the current delay time can sample correct data. This can be done by reading fixed data from the memory chip, such as ID information. If the output ID information is incorrect, it means that the current delay time is incorrect.

[0038] The waveform file data extraction module extracts the signal values ​​of the generated waveform and generates a text file for subsequent operations. For example, the Fsdb format waveform file can be used to extract the signal values ​​using the Fsdbreport tool to generate a txt file.

[0039] The signal time value extraction module extracts the signal value required for calculating the delay time from the generated text file. It can be divided into the delay chain input time value extraction module, the delay chain output time value extraction module, the signal sampling time value extraction module, the sampled data time value extraction module, and the current delay time value extraction module. The delay chain input time value extraction module is used to extract the time value T of the input delay chain. inThe delay chain output time value extraction module is used to extract the time value T of the output delay chain. out The signal sampling time value extraction module extracts the time value T of the current sampling reference signal. dqs The sampled data time value extraction module extracts the intermediate value T of the sampled data. data The current delay time value extraction module extracts the current delay time value T current_delay .

[0040] The signal sampling time value judgment module is used to judge whether the current sampling time value is ahead of or behind the sampled data. If it is ahead, it enters the delay time calculation module A; if it is behind, it enters the delay time calculation module B.

[0041] The delay time calculation module A and the delay time calculation module B are used to calculate the delay time.

[0042] The delay time value output module converts the delay time calculated by the delay time calculation module A / B into the value to be configured and outputs it.

[0043] The current sampling time value is ahead of the sampled data, so a delay time needs to be added. The formula for calculating the delay time by the delay time calculation module A is:

[0044]

[0045] T clk is the clock frequency, T precision For accuracy.

[0046] The current sampling time value lags behind the sampled data, and the delay time needs to be reduced. The formula for calculating the delay time by the delay time calculation module B is:

[0047]

[0048] T clk is the clock frequency, T precision For accuracy.

[0049] Example 2

[0050] This embodiment discloses a method for automatically calculating the signal sampling delay time in chip post-simulation verification, such as Figure 2 As shown, the following steps are included:

[0051] S01) Select the Sdf of a certain Corner or the delay time calculation under a certain channel, and judge whether the current delay time can correctly sample the data. If not, execute the next step, otherwise end;

[0052] S02), inputting a waveform file for signal value extraction, extracting the signal value of the generated waveform file to generate a text file;

[0053] S03) Extract the data of the text file and extract the time value T of the input delay chain. in , the time value T of the output delay chain out , the time value T of the current sampling reference signal dqs ,, the sampled data time value T data , the current delay time value T current_delay ;

[0054] S04), determine whether the current sampling time value is advanced or delayed, if it is advanced, execute step S05), if it is delayed, execute step S06);

[0055] S05) The current sampling time value is ahead of the sampled time, and a delay time needs to be added. The delay time is:

[0056]

[0057] Where T clk is the clock frequency, T precision is the accuracy;

[0058] S06) The current sampling time value lags behind the sampled time, and the delay time needs to be reduced. The delay time is:

[0059]

[0060] T clk is the clock frequency, T precision is the accuracy;

[0061] S07), converting the time value output in step S05) or S06) into a register value to be configured and outputting it;

[0062] S08) Determine whether all corners or channels are calculated. If not, execute the first step, otherwise, end.

[0063] In step S01), the current delay time is determined by reading the fixed data of the chip to correctly sample the data. For example, if the ID information is read and the output ID information is wrong, it means that the current delay time is incorrect.

[0064] In step S02), the signal value of the waveform file in Fsdb format is extracted using the Fsdbreport tool to generate a text format file.

[0065] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention fall within the protection scope of the present invention.

Claims

1. A method for automatically calculating signal sampling delay time in chip post-simulation verification, characterized by: The following steps are involved: S01) Select the Sdf of a certain Corner or the delay time calculation under a certain channel, and judge whether the current delay time can correctly sample the data. If not, execute the next step, otherwise end; S02), inputting a waveform file for signal value extraction, extracting the signal value of the generated waveform file to generate a text file; S03) Extract the data of the text file and extract the time value T of the input delay chain. in , the time value T of the output delay chain out , the time value T of the current sampling reference signal dqs , sampled data time value T data , the current delay time value T current_delay ; S04), determine whether the current sampling time value is advanced or delayed, if it is advanced, execute step S05), if it is delayed, execute step S06); S05) The current sampling time value is ahead of the sampled time, and a delay time needs to be added. The delay time is: Where T clk is the clock frequency, T precision is the accuracy; S06) The current sampling time value lags behind the sampled time, and the delay time needs to be reduced. The delay time is: T clk is the clock frequency, T precision is the accuracy; S07) Convert the time value outputted in step S05) or S06) into the register value to be configured and output it; S08) Determine whether all corners or channels are calculated. If not, execute the first step, otherwise, end.

2. The method for automatically calculating signal sampling delay time in chip post-simulation verification according to claim 1, characterized in that: In step S01), the fixed data of the chip is read to determine whether the current delay time can correctly sample the data.

3. The method for automatically calculating signal sampling delay time in chip post-simulation verification according to claim 1, characterized in that: In step S02), the signal value is extracted using the Fsdbreport tool to generate a text file.

4. An automatic calculation system for signal sampling delay time in chip post-simulation verification, characterized by: Sampling delay time judgment module, waveform file data extraction module, signal time value extraction module, signal sampling time value judgment module, delay time calculation module A, delay time calculation module B and delay time value output module; the sampling delay time judgment module judges whether the current delay time can sample correct data. If not, the waveform file data extraction module inputs the waveform file to be extracted for signal value, extracts the signal value of the generated waveform file and generates a text file; The signal time value extraction module extracts the signal value required for calculating the delay time from the generated text file, including the delay chain input time value extraction module, the delay chain output time value extraction module, the signal sampling time value extraction module, the sampled data time value extraction module, and the current delay time value extraction module. The delay chain input time value extraction module is used to extract the time value T of the input delay chain. in The delay chain output time value extraction module is used to extract the time value T of the output delay chain. out The signal sampling time value extraction module extracts the time value T of the current sampling reference signal. dqs The sampled data time value extraction module extracts the time value T of the sampled data. data The current delay time value extraction module extracts the current delay time value T current_delay ; The signal sampling time value judgment module is used to judge whether the current sampling time value is ahead of or behind the sampled data. If it is ahead, it enters the delay time calculation module A; if it is behind, it enters the delay time calculation module B. Delay time calculation module A and delay time calculation module B are used to calculate the delay time; The formula for calculating the delay time by the delay time calculation module A is: The formula for calculating the delay time by the delay time calculation module B is: Among them, T clk is the clock frequency, T precision is the accuracy; The delay time value output module converts the delay time calculated by the delay time calculation modules A and B into the value to be configured and outputs it.

5. The automatic calculation system for signal sampling delay time in chip post-simulation verification according to claim 4 is characterized in that: The sampling delay time judgment module makes judgments by reading fixed data from the storage chip. If the read data is wrong, it means that the current delay time is incorrect.

6. The automatic calculation system for signal sampling delay time in chip post-simulation verification according to claim 4, characterized in that: The waveform file data extraction module uses the Fsdbreport tool to extract signal values ​​and generate a txt format file.

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