Gate drive circuit, display panel and display module

Abstract

The present application discloses a gate drive circuit, a display panel and a display module. The gate drive circuit includes a plurality of cascaded shift registers, and a regulating module is correspondingly provided at the clock signal input end of each shift register, and each regulating module is used to adjust the clock signal line load of the gate drive circuit when the corresponding shift register outputs a gate voltage signal, so as to adjust the rising edge time and falling edge time of the clock signal. Each shift register in the gate drive circuit is provided with a corresponding regulating module to adjust the line resistance load of the clock signal line, thereby changing the gate voltage output waveform of the gate drive circuit. When the clock signal line load increases, the rising edge time and falling edge time of the gate voltage output waveform increase, the gate voltage jumps slowly, and the coupling pulling effect on the common electrode becomes weaker, so that the gate drive circuit effectively improves the corresponding display defects by adjusting the coupling pulling strength of the gate voltage jump to the common electrode.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit, a display panel and a display module. Background Art

[0002] In the related art, in the existing common panel pixel design structure, the gate (Gate) wiring of the thin film transistor (TFT) device runs through the entire display area, and there are coupling capacitors between the gate wiring and the data signal line (data), the common electrode (Com), etc. The coupling capacitor between the gate wiring and the common electrode is Cgc. During normal display, the gate is opened row by row, and the gate voltage switches between high and low (VGH / VGL) voltages. The existence of Cgc causes the Com voltage (Vcom) to be pulled along with the gate voltage switching. When the gate voltage changes from VGL to VGH, Vcom is pulled up, and vice versa, Vcom is pulled down. Summary of the invention

[0003] Embodiments of the present application provide a gate driving circuit, a display panel, and a display module.

[0004] The gate drive circuit of the embodiment of the present application includes a plurality of cascaded shift registers, and a regulating module is correspondingly provided at the clock signal input end of each shift register. Each of the regulating modules is used to adjust the clock signal line load of the gate drive circuit when the corresponding shift register outputs a gate voltage signal, so as to adjust the rising edge time and the falling edge time of the clock signal.

[0005] In some embodiments, the adjustment module includes a signal latch unit, an adjustment resistor and a switch unit, the signal latch unit connects the switch unit, the shift register and the initial signal line, the switch unit connects one end of the adjustment resistor and the clock signal line, and the signal latch unit controls the switch unit to connect the adjustment resistor in parallel with the clock signal line segment corresponding to the shift register under the action of the gate voltage signal output by the corresponding shift register and the initial signal provided by the initial signal line.

[0006] In some embodiments, the ratio of the resistance of the adjustment resistor to the corresponding line group of the clock signal line segment is 1:1.

[0007] In some embodiments, the switching unit includes a first transistor, a gate of the first transistor is connected to the output end of the signal latch unit, a first electrode of the first transistor is connected to the first end of the adjustment resistor, a second end of the first transistor is connected to the corresponding clock signal end of the shift register and the first end of the corresponding clock signal line segment, a first input end of the signal latch unit is connected to the initial signal line, a second input end of the signal latch unit is connected to the corresponding output end of the shift register, and a second end of the adjustment resistor is connected to the second end of the corresponding clock signal line segment.

[0008] In some embodiments, the signal latch unit includes a second transistor, a third transistor and a fourth transistor, the second transistor and the third transistor are N-channel transistors, the fourth transistor is a P-channel transistor, the first electrode of the second transistor is connected to the first power supply terminal, the gate and the second electrode of the second transistor are connected to the output terminal of the signal latch unit, the gate of the third transistor is connected to the corresponding output terminal of the shift register, the first electrode of the third transistor is connected to the initial signal line, the second electrode of the third transistor is connected to the output terminal of the signal latch unit, the first electrode and the gate of the fourth transistor are connected to the output terminal of the signal latch unit, and the second electrode of the fourth transistor is connected to the second power supply terminal.

[0009] In some embodiments, the gate drive circuit is disposed on a display panel, which includes a base substrate, a gate layer, a source and drain layer, and a transparent conductive layer stacked in sequence, the clock signal line is located in the gate layer, and the adjustment resistor is located in the source and drain layer.

[0010] In some embodiments, the regulating module further includes a regulating capacitor, wherein the regulating capacitor is connected to one end of the regulating resistor and ground.

[0011] In some embodiments, the gate layer includes a first electrode plate, and a projection of the adjustment resistor on the gate layer at least partially overlaps with the first electrode plate to form the adjustment capacitor.

[0012] In some embodiments, the transparent conductive layer includes a second electrode plate, and a projection of the adjusting resistor on the transparent conductive layer at least partially overlaps with the second electrode plate to form the adjusting capacitor.

[0013] In some embodiments, the gate layer includes a first electrode plate, the transparent conductive layer includes a second electrode plate, the projection of the adjustment resistor on the gate layer at least partially overlaps with the first electrode plate, and the projection of the adjustment resistor on the transparent conductive layer at least partially overlaps with the second electrode plate to form the adjustment capacitor.

[0014] The display panel according to the embodiment of the present application includes the gate driving circuit according to the embodiment of the present application.

[0015] The display module of the embodiment of the present application includes a timing controller, a waveform integration circuit and a display panel of the embodiment of the present application, wherein the timing controller is used to provide a clock signal to the display panel; the waveform integration circuit connects the display panel and the timing controller, and the waveform integration circuit is used to adjust the rising edge time and the falling edge time of the clock signal provided by the timing controller.

[0016] In some embodiments, the waveform integration circuit includes an integrated resistor and an integrated capacitor, the integrated resistor is connected in series between the timing controller and the display panel, and the integrated capacitor is connected to one end of the integrated resistor and ground.

[0017] In some embodiments, the RC response time of the waveform integration circuit is inversely proportional to the pixel charging time of the display panel.

[0018] In some embodiments, the RC response time of the waveform integration circuit is no more than 3 us.

[0019] In some embodiments, the waveform integration circuit is located on the display panel.

[0020] In some embodiments, the display module includes a circuit board, the circuit board is connected to the timing controller and the display panel, and the waveform integration circuit is disposed on the circuit board.

[0021] In the gate drive circuit, display panel and display module of the embodiment of the present application, each shift register in the gate drive circuit is provided with a corresponding adjustment module to adjust the line resistance load of the clock signal line, thereby changing the gate voltage output waveform of the gate drive circuit. When the clock signal line load increases, the rising edge time and falling edge time of the gate voltage output waveform increase, the gate voltage jumps slowly, and the coupling pulling effect on the common electrode becomes weaker, so that the gate drive circuit effectively improves the corresponding display defect by adjusting the coupling pulling strength of the gate voltage jump on the common electrode.

[0022] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 Schematic diagram of the circuit structure of the gate drive circuit of the embodiment of the present application.

[0025] Figure 2 It is a schematic diagram of the transformation of the gate voltage signal output waveform and the common electrode pull signal under different load conditions of the clock signal line in an embodiment of the present application.

[0026] Figure 3 Schematic diagram of the circuit structure of the signal latch unit according to the embodiment of the present application.

[0027] Figure 4 1 is a control timing diagram of a signal latch unit according to an embodiment of the present application.

[0028] Figure 5 It is a schematic diagram of the film layer structure of the display panel according to the embodiment of the present application.

[0029] Figure 6 It is a schematic diagram of the circuit structure of the display module of the embodiment of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0031] In the description of this application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0032] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0033] For the display panel with touch and display driver integration (TDDI), the common electrode in the display area is designed in blocks. Each block is an independent common electrode in the display period and an independent touch unit in the touch period. The particularity of this structure leads to the fact that the gate cannot offset the up and down pull of the common electrode at the edge of the common electrode block, resulting in uneven display and sensor pad horizontal stripes. Similarly, for the intra-frame touch mode, the gate cannot offset the up and down pull of the common electrode at the display and touch switching node, which easily causes intra-frame touch horizontal stripes.

[0034] In the prior art, the ability to recover after the common electrode is pulled can be enhanced by enhancing the integrated circuit (IC) drive supply, or by adjusting the special drive timing to offset the up and down pull of the common electrode as much as possible. However, such a solution needs to be implemented through IC adjustment, and the improvement effect is often unsatisfactory due to the limitation of IC adjustment ability. Some solutions can also adjust the gate output waveform to reduce the pull of the common electrode caused by the gate voltage jump, but the existing IC basically cannot support the adjustment of the gate output waveform, and a separate gate drive IC needs to be added, which increases the cost of the display panel.

[0035] See also Figure 1 and Figure 2 A gate drive circuit 10 provided in an embodiment of the present application includes a plurality of cascaded shift registers 12, and a regulating module 14 is correspondingly provided at the clock signal input end of each shift register 12. Each regulating module 14 is used to adjust the load of the clock signal line 16 of the gate drive circuit 10 when the corresponding shift register 12 outputs a gate voltage signal, so as to adjust the rising edge time tr and the falling edge time tf of the clock signal.

[0036] It can be understood that each shift register 12 of the gate drive circuit 10 is connected to the clock signal line 16, and the clock signal line 16 provides a clock signal input. The shift register 12 outputs the corresponding gate voltage signal GOA-output row by row to achieve row-by-row scanning of the display panel 100. The clock signal line 16 itself has a line resistance. The clock signal line 16 can be divided into a plurality of clock signal line segments 162 from the proximal end to the distal end along the direction in which the shift register 12 is arranged, which can be equivalent to RA1, RA2, ..., RAN, RAN+1, etc., with a total of N+1 series resistors.

[0037] In the gate drive circuit 10 of the embodiment of the present application, each shift register 12 is provided with a corresponding adjustment module 14, which adjusts the line resistance load of the clock signal line 16 connected to the circuit when the corresponding shift register 12 outputs the gate voltage signal, thereby changing the gate voltage output waveform of the gate drive circuit 10. When the line resistance load of the clock signal line 16 decreases, the rising edge time tr and the falling edge time tf of the gate voltage output waveform increase, the gate voltage jumps slowly, and the coupling pulling effect on the common electrode becomes weaker, so that the gate drive circuit 10 effectively improves the corresponding display defects by adjusting the coupling pulling strength of the gate voltage jump to the common electrode. Figure 2 In the example shown, the waveform shown in the upper part is the gate voltage signal output waveform under different loads of the clock signal line, and the waveform in the lower part is the common electrode pulling waveform under different loads of the clock signal line, where R1>R2>R3.

[0038] In some embodiments, the adjustment module 14 includes a signal latch unit 142, an adjustment resistor 144 and a switch unit 146. The signal latch unit 142 connects the switch unit 146, the shift register 12 and the initial signal line 18. The switch unit 146 connects one end of the adjustment resistor 144 and the clock signal line 16. Under the action of the gate voltage signal output by the corresponding shift register 12 and the initial signal provided by the initial signal line 18, the signal latch unit 142 controls the switch unit 146 to connect the adjustment resistor 144 in parallel with the clock signal line segment 162 corresponding to the shift register 12.

[0039] In this way, the latch unit latches the signal under the action of the gate voltage signal and the initial signal, and controls the switch unit 146 to connect the adjustment resistor 144 in parallel with the clock signal line 16 end corresponding to the shift register 12, thereby reducing the line resistance load of the clock signal line 16 connected to the circuit.

[0040] Specifically, the adjustment resistors 144 of multiple adjustment modules 14 can be connected in series, that is, the gate drive circuit 10 introduces RB1, RB2, ..., RBN, RBN+1, etc., a total of N+1 series resistors, and the adjustment resistors 144RB1, RB2, ..., RBN, RBN+1, etc. are respectively connected in parallel with the clock signal segments 162RA1, RA2, ..., RAN, RAN+1 through a switch unit 146, and the switch unit 146 is controlled by the signal latch to be turned on or off to control the corresponding adjustment resistor 144 to be connected in parallel with the clock signal segment 162 corresponding to the corresponding shift register 12.

[0041] When the switch units 146 of all the regulating modules 14 are disconnected, RB1, RB2, ..., RBN, RBN+1 are ineffective, and the load resistance of the clock signal line 16 is the sum of the series resistances of N+1 clock signal line segments 162: RA1+RA2+...+RAN+RAN+1.

[0042] When the switch unit 146 of the adjustment module 14 corresponding to the i-th shift register 12 is turned on, the line resistance load of the clock signal line 16 becomes (RA1+RA2+…+RAi)*(RB1+RB2+…+RBi) / (RA1+RA2+…+RAi+RB1+RB2+…+RBi)+RAi+1+…+RAN+1. Due to the addition of the parallel adjustment resistor 144, the line resistance load of the clock signal line 16 is reduced.

[0043] In some embodiments, the switch unit 146 includes a first transistor M1, a gate of the first transistor M1 is connected to the output end of the signal latch unit 142, a first electrode of the first transistor M1 is connected to the first end of the adjustment resistor 144, a second end of the first transistor M1 is connected to the clock signal end of the corresponding shift register 12 and the first end of the corresponding clock signal line segment 162, a first input end of the signal latch unit 142 is connected to the initial signal line 18, a second input end of the signal latch unit 142 is connected to the output end of the corresponding shift register 12, and a second end of the adjustment resistor 144 is connected to the second end of the corresponding clock signal line segment 162.

[0044] It should be noted that the first transistor M1 in the embodiment of the present application is described by taking an N-channel transistor as an example, the first electrode of the first transistor M1 may be a source electrode, and the second electrode of the first transistor M1 may be a drain electrode. Of course, in practical applications, the type of the first transistor M1 is not limited thereto, for example, it may also be a P-type transistor.

[0045] Among them, the signal latch unit 142 can latch the initial signal according to the gate voltage signal output by the corresponding shift register 12, so as to keep the first transistor M1 turned on, and realize that a single initial signal line controls all the first transistors M1 to be turned on or off. The gate drive circuit 10 outputs the gate voltage signal (high level signal) row by row, and the signal latch unit 142 works row by row under its triggering. When the i-th row shift register 12 outputs a high level signal, the i-th row signal latch unit 142 starts to work. At this time, the corresponding initial signal line 18 outputs a high level signal, and the signal latch unit 142 also outputs a high-high level signal, turning on the first transistor M1 of the i-th row and adjusting the line resistance load of the clock signal line 16. On the contrary, the signal latch unit 142 outputs a low level signal to turn off the corresponding first transistor M1.

[0046] In some embodiments, the ratio of the resistance of the adjustment resistor 144 to the line group of the corresponding clock signal line segment 162 is 1:1.

[0047] In this way, the resistance value of the resistor 144 is adjusted according to the line resistance of the clock signal line 16, which is beneficial to adjusting the rising edge time tr and the falling edge time tf of the gate voltage signal output waveform.

[0048] In one example, for a 13-inch α-Si panel with a resolution of 2560*1600 and a refresh rate of 60Hz, the ratio of the resistance value of the adjustment resistor 144 and the line group of the corresponding clock signal line segment 162 is set to approximately 1:1. Without considering the mounting capacitance, the rising edge time tr and the falling edge time tf of the gate voltage signal output waveform with the mounted adjustment resistor 144 can be doubled compared to the rising edge time tr and the falling edge time tf of the gate voltage signal output waveform without the mounted adjustment resistor 144.

[0049] See also Figure 3 In some embodiments, the signal latch unit 142 includes a second transistor M2, a third transistor M3 and a fourth transistor M4, the second transistor M2 and the third transistor M3 are N-channel transistors, the fourth transistor M4 is a P-channel transistor, the first electrode of the second transistor M2 is connected to the first power supply terminal VDD, the gate and the second electrode of the second transistor M2 are connected to the output end of the signal latch unit 142, the gate of the third transistor M3 is connected to the output end of the corresponding shift register 12, the first electrode of the third transistor M3 is connected to the initial signal line 18, the second electrode of the third transistor M3 is connected to the output end of the signal latch unit 142, the first electrode and the gate of the fourth transistor M4 are connected to the output end of the signal latch unit 142, and the second electrode of the fourth transistor M4 is connected to the second power supply terminal V22.

[0050] In this way, the signal latching function is realized by the connection setting of the second transistor M2, the third transistor M3 and the fourth transistor M4. The first power supply terminal VDD receives a high level signal, and the second power supply terminal V22 receives a low level signal.

[0051] For details, please refer to Figure 4 When the corresponding shift register 12 outputs a high-level signal, the third transistor M3 is turned on. At this time, if the initial signal line 18 outputs a high-level signal, the second transistor M2 is turned on, and the output end of the signal latch unit 142 continues to output a high-level signal. If the initial signal line 18 outputs a low-level signal, the fourth transistor M4 is turned on, and the output end of the signal latch unit 142 continues to output a low-level signal, thereby latching the initial signal.

[0052] See also Figure 5 In some embodiments, the gate driving circuit 10 is disposed on the display panel 100, and the display panel 100 includes a base substrate 21, a gate layer 22, a source and drain layer 23 and a transparent conductive layer 24 stacked in sequence, the clock signal line 16 is located in the gate layer 22, and the adjustment resistor 144 is located in the source and drain layer 23.

[0053] In this way, the gate driving circuit 10 and the display panel 100 can use the same process to manufacture transistors and internal wiring, and reasonably set the clock signal line 16 and the adjustment resistor 144.

[0054] In some embodiments, the regulating module 14 further includes a regulating capacitor (not shown), and the regulating capacitor is connected to one end of the regulating resistor 144 and the ground.

[0055] In addition to the adjustment resistor 144, the clock signal line 16 can also be equipped with an adjustment capacitor. By cooperating with the adjustment resistor 144 and the adjustment capacitor, the rising edge time tr and the falling edge time tf of the gate voltage output waveform can be adjusted. Therefore, the gate drive circuit 10 can effectively improve the corresponding display defects by adjusting the coupling pull strength of the gate voltage jump on the common electrode.

[0056] In some embodiments, the gate layer 22 includes a first electrode plate C (Gate), and a projection of the adjustment resistor 144 on the gate layer 22 at least partially overlaps with the first electrode plate C (Gate) to form an adjustment capacitor.

[0057] In this way, through the circuit design between different film layers of the display panel 100 , the adjustment resistor 144 and the first electrode plate C (Gate) on the gate layer 22 at least partially overlap to form an adjustment capacitor.

[0058] Specifically, the clock signal line 16 of the gate drive circuit 10 adopts the metal routing of the gate layer 22, and the line resistance of the clock signal line segment 162 corresponding to the length of each shift register 12 is RAN. The adjustment resistor 144 directly adopts the metal routing of the source and drain layer 23 and is parallel to the clock signal line 16, and the line resistance of the adjustment resistor 144 corresponding to the length of each shift register 12 is RBN. The metal of the source and drain layer 23 where the adjustment resistor 144 is located and the metal of the gate layer 22 where the clock signal line 16 is located are connected at the starting end through a via. A transparent conductive layer 24 and a gate layer 22 are respectively arranged in parallel above and below the source and drain layer 23 of the adjustment resistor 144 routing, and are separated by an insulating layer. The transparent conductive layer 24 and the gate layer 22 are directly connected through a via in the place where there is no metal of the passive drain layer 23.

[0059] In some embodiments, the transparent conductive layer 24 includes a second electrode plate C (ITO), and the projection of the adjustment resistor 144 on the transparent conductive layer 24 at least partially overlaps with the second electrode plate C (ITO) to form an adjustment capacitor.

[0060] In this way, through the circuit design between different film layers of the display panel 100, the adjustment resistor 144 and the second electrode plate C (ITO) on the source and drain electrode layer 23 at least partially overlap to form an adjustment capacitor.

[0061] In some embodiments, the gate layer 22 includes a first electrode plate C (Gate), the transparent conductive layer 24 includes a second electrode plate C (ITO), the projection of the adjustment resistor 144 on the gate layer 22 at least partially overlaps with the first electrode plate C (Gate), and the projection of the adjustment resistor 144 on the transparent conductive layer 24 at least partially overlaps with the second electrode plate C (ITO) to form an adjustment capacitor.

[0062] In this way, through the circuit design between different film layers of the display panel 100, the adjustment resistor 144 and the first electrode plate C (Gate) and the second electrode plate C (ITO) on the gate layer 22 and the source and drain layer 23 are at least partially overlapped to form an adjustment capacitor. At this time, the capacitance value of the adjustment capacitor is the sum of the capacitance values ​​of the adjustment resistor 144 and the first electrode plate C (Gate) to form the capacitor C1 and the adjustment resistor 144 and the second electrode plate C (ITO) to form the capacitor C2. The dual capacitor design can increase the capacitance of the mounted capacitor per unit area and reduce the influence of the mounted capacitor on the frame size of the display panel 100.

[0063] The display panel 100 according to the embodiment of the present application includes the gate driving circuit 10 according to the embodiment of the present application.

[0064] See also Figure 6 In the display panel 100 of the embodiment of the present application, each shift register 12 of the gate driving circuit 10 is provided with a corresponding adjustment module 14, which adjusts the line resistance load of the clock signal line 16 connected to the circuit when the corresponding shift register 12 outputs the gate voltage signal, thereby changing the gate voltage output waveform of the gate driving circuit 10. When the line resistance load of the clock signal line 16 decreases, the rising edge time tr and the falling edge time tf of the gate voltage output waveform increase, the gate voltage jumps slowly, and the coupling pulling effect on the common electrode is weaker, so that the gate driving circuit 10 effectively improves the corresponding display defect by adjusting the coupling pulling strength of the gate voltage jump to the common electrode.

[0065] The display module 1000 of the embodiment of the present application includes a timing controller 200, a waveform integration circuit 300 and a display panel 100 of the embodiment of the present application, wherein the timing controller 200 is used to provide a clock signal to the display panel 100; the waveform integration circuit 300 connects the display panel 100 and the timing controller 200, and the waveform integration circuit 300 is used to adjust the rising edge time tr and the falling edge time tf of the clock signal provided by the timing controller 200.

[0066] In the display module 1000 of the embodiment of the present application, the clock signal output by the timing controller 200 is adjusted by the waveform integration circuit 300, and each shift register 12 is provided with a corresponding adjustment module 14, which adjusts the line resistance load of the clock signal line 16 connected to the circuit when the corresponding shift register 12 outputs the gate voltage signal, thereby changing the gate voltage output waveform of the gate driving circuit 10. The rising edge time tr and the falling edge time tf of the gate voltage output waveform are increased, the gate voltage jumps slowly, and the coupling pulling effect on the common electrode is weaker, so that the gate driving circuit 10 effectively improves the corresponding display defects by adjusting the coupling pulling strength of the gate voltage jump to the common electrode.

[0067] It should be noted that, in addition to the implementation method in which the adjustment module 14 and the waveform integration circuit 200 cooperate, in other implementation methods, the adjustment module 14 and the waveform integration circuit 200 can be implemented separately, that is, only the adjustment module 14 is designed in the gate drive circuit 10 to adjust the line resistance load of the clock signal line 16, or only the waveform integration circuit 200 is used to waveform integrate the clock signal input to the display panel 100, thereby changing the gate voltage output waveform of the gate drive circuit 10.

[0068] In some embodiments, the waveform integration circuit 300 includes an integrated resistor R0 and an integrated capacitor C0 . The integrated resistor R0 is connected in series between the timing controller 200 and the display panel 100 . The integrated capacitor C0 is connected between one end of the integrated resistor R0 and ground.

[0069] Thus, by connecting the integrated resistor R0 in series and the integrated capacitor C0 in parallel, the clock signal waveform can be integrated, the rising edge time tr and the falling edge time tf of the gate voltage signal output waveform can be increased, and the pulling effect of the gate voltage signal jump on the common electrode can be reduced.

[0070] In some embodiments, the RC response time of the waveform conforming circuit 300 is inversely proportional to the pixel charging time of the display panel 100 .

[0071] It can be understood that the larger the resistance of the series integrated resistor R0 and the capacitance of the parallel integrated capacitor C0, the smaller the pull of the gate voltage signal jump on the common electrode can be, and the more obvious the improvement effect of the horizontal stripes is. However, since the increase of the rising edge time tr and the falling edge time tf of the clock signal will occupy the charging time of each row of pixels, therefore, when the refresh time of the display panel 100 is determined, the RC response time of the waveform integration circuit 300 is inversely proportional to the pixel charging time of the display panel 100, thereby ensuring the pixel charging time of the display panel 100.

[0072] In some embodiments, the RC response time of the waveform conforming circuit 300 is no greater than 3 us.

[0073] Specifically, in different types of display panels 100 , the RC response time of the waveform integration circuit 300 may be different.

[0074] In one example, for a 13-inch α-Si display panel 100 with a resolution of 2560*1600 and a refresh rate of 60Hz. The load resistance of a single gate signal line is in the order of kilo-ohms, such as 4KΩ, and the equivalent capacitance is in the order of hundreds of pF, such as 300pF. R*C (i.e., the rising edge time tr or the falling edge time tf) is in the order of us, which is 1.2us. At this time, the corresponding common electrode pull is in the order of tens to hundreds of mV. The pixel charging time should be fully considered when setting the integrated resistor R0 and the integrated capacitor C0, and R0*C0 should be controlled within 2.8us.

[0075] In addition, in other examples, the R0*C0 upper limit can be higher for LTPS products due to their low charging time requirements.

[0076] In some embodiments, the waveform integration circuit 300 is located in the display panel 100 .

[0077] In this way, the waveform integration circuit 300 can be integrated into the display panel 100 , which can reduce the peripheral circuit design.

[0078] In some embodiments, the display module 1000 includes a circuit board (not shown), the circuit board connects the timing controller 200 and the display panel 100 , and the waveform integration circuit 300 is disposed on the circuit board.

[0079] In this way, the waveform integration circuit 300 can be provided through the circuit board without changing the manufacturing process of the display panel 100 .

[0080] In some embodiments, the circuit board includes a printed circuit board, a flexible circuit board, and / or a rigid-flex board, etc.

[0081] In some embodiments, the display module 1000 further includes a signal amplifying circuit 400 , and the signal amplifying circuit 400 is connected to the timing controller 200 and the waveform integration circuit 300 .

[0082] In this way, the clock signal output by the timing controller 200 is amplified by the signal amplifying circuit 400 .

[0083] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0084] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A gate drive circuit, characterized in that: A plurality of cascaded shift registers are included, wherein a regulating module is correspondingly provided at a clock signal input end of each shift register, and each regulating module is used to regulate the clock signal line load of the gate drive circuit when the corresponding shift register outputs a gate voltage signal, so as to regulate the rising edge time and the falling edge time of the clock signal; Among them, the adjustment module includes a signal latch unit, an adjustment resistor and a switch unit, the signal latch unit connects the switch unit, the shift register and the initial signal line, the switch unit connects one end of the adjustment resistor and the clock signal line, and the signal latch unit, under the action of the corresponding gate voltage signal output by the shift register and the initial signal provided by the initial signal line, controls the switch unit to connect the adjustment resistor in parallel with the clock signal line segment corresponding to the shift register.

2. The gate driving circuit according to claim 1, characterized in that: The ratio of the resistance of the adjusting resistor to the line group of the corresponding clock signal line segment is 1:

1.

3. The gate driving circuit according to claim 1, characterized in that: The switching unit includes a first transistor, a gate of the first transistor is connected to the output end of the signal latch unit, a first electrode of the first transistor is connected to the first end of the adjusting resistor, a second end of the first transistor is connected to the corresponding clock signal end of the shift register and the first end of the corresponding clock signal line segment, a first input end of the signal latch unit is connected to the initial signal line, a second input end of the signal latch unit is connected to the corresponding output end of the shift register, and a second end of the adjusting resistor is connected to the second end of the corresponding clock signal line segment.

4. The gate driving circuit according to claim 3, characterized in that: The signal latch unit includes a second transistor, a third transistor and a fourth transistor, the second transistor and the third transistor are N-channel transistors, the fourth transistor is a P-channel transistor, the first electrode of the second transistor is connected to the first power supply terminal, the gate and the second electrode of the second transistor are connected to the output terminal of the signal latch unit, the gate of the third transistor is connected to the corresponding output terminal of the shift register, the first electrode of the third transistor is connected to the initial signal line, the second electrode of the third transistor is connected to the output terminal of the signal latch unit, the first electrode and the gate of the fourth transistor are connected to the output terminal of the signal latch unit, and the second electrode of the fourth transistor is connected to the second power supply terminal.

5. The gate driving circuit according to claim 1, characterized in that: The gate driving circuit is arranged on a display panel, which includes a base substrate, a gate layer, a source-drain electrode layer and a transparent conductive layer stacked in sequence, the clock signal line is located in the gate layer, and the regulating resistor is located in the source-drain electrode layer.

6. The gate driving circuit according to claim 5, characterized in that: The regulating module further includes a regulating capacitor, and the regulating capacitor is connected to one end of the regulating resistor and ground.

7. The gate driving circuit according to claim 6, characterized in that: The gate layer includes a first electrode plate, and a projection of the adjustment resistor on the gate layer at least partially overlaps with the first electrode plate to form the adjustment capacitor.

8. The gate driving circuit according to claim 6, characterized in that: The transparent conductive layer includes a second electrode plate, and a projection of the regulating resistor on the transparent conductive layer at least partially overlaps with the second electrode plate to form the regulating capacitor.

9. The gate driving circuit according to claim 6, characterized in that: The gate layer includes a first electrode plate, the transparent conductive layer includes a second electrode plate, the projection of the regulating resistor on the gate layer at least partially overlaps with the first electrode plate, and the projection of the regulating resistor on the transparent conductive layer at least partially overlaps with the second electrode plate to form the regulating capacitor.

10. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit as described in any one of claims 1 to 9.

11. A display module, characterized in that: include: The display panel according to claim 10; A timing controller, used for providing a clock signal to the display panel; A waveform integration circuit is connected to the display panel and the timing controller, and is used to adjust the rising edge time and the falling edge time of the clock signal provided by the timing controller.

12. The display module according to claim 11, characterized in that: The waveform integration circuit includes an integration resistor and an integration capacitor. The integration resistor is connected in series between the timing controller and the display panel. The integration capacitor is connected to one end of the integration resistor and the ground.

13. The display module according to claim 11, characterized in that: The RC response time of the waveform integration circuit is inversely proportional to the pixel charging time of the display panel.

14. The display module according to claim 13, characterized in that: The RC response time of the waveform integration circuit is no more than 3 us.

15. The display module according to claim 14, characterized in that: The waveform integration circuit is located on the display panel.

16. The display module according to claim 11, characterized in that: The display module includes a circuit board, the circuit board is connected to the timing controller and the display panel, and the waveform integration circuit is arranged on the circuit board.

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