A method for regulating the conductance of a memristor based on a lookup table and application thereof

Abstract

The application discloses a kind of based on look-up table's memristor conductance regulation method and its application. Among them, the conductance regulation method includes the following steps: when the conductance of memristor needs to be regulated to target conductance interval, the pulse sequence information matched with target conductance interval is found from the look-up table made in advance, and the look-up table stores the corresponding relationship between at least two conductance states and corresponding pulses;According to pulse sequence information, corresponding pulses are applied between the upper and lower electrodes of memristor, and the regulation of the conductance of memristor is completed.The application statistically analyzes the conductance state distribution of the device, manufactures the look-up table, programs and regulates the conductance of memristor using the look-up table method, which can effectively reduce the number of read operations, and different conductance states correspond to known pulse design and pulse sequence design, without repeated verification whether to reach target conductance interval, the programming process is simple, and since all conductance states are known, there is no situation that cannot be written into the conductance interval during the programming process.

Description

Technical Field

[0001] This invention belongs to the field of memristor technology, and more specifically, relates to a memristor conductance control method based on a lookup table and its application. Background Technology

[0002] With the advent of the 5G and big data era, faster and more efficient computing systems are needed to meet the demands of information technology development. The failure of Moore's Law and the shortcomings of the von Neumann architecture have constrained the development of existing computer technology; therefore, in-memory computing devices have become a new development direction for the semiconductor industry. Memristors possess in-memory computing characteristics, offering faster speeds and lower energy consumption than traditional computers when handling the same amount of computational tasks. Furthermore, most resistive switching materials (ZnO, HfO2) are compatible with semiconductor chip manufacturing (CMOS) processes, making memristors promising for both memory and arithmetic applications. For use in in-memory computing, memristors require a wide range of conductance and adjustability.

[0003] In the past few years, researchers have proposed a variety of schemes to improve the tunable conductance performance of multi-valued memristors from both the device and operation methods levels. Since pulse signals can precisely control the energy applied to the memristor, they are more widely used in the multi-valued control of memristors.

[0004] Currently, there are three main pulse-based operation schemes: In 2015, J. Joshua Yang et al. designed a programming scheme that increments the pulse width by step, such as... Figure 1 As shown, the set process uses a positive pulse with gradually increasing width, and the reset process uses a negative pulse with gradually increasing width, until the memristor resistance falls within the target resistance range. In 2016, Ming-Hsiu Lee et al. designed a set and reset pulse scheme using a fixed voltage, such as... Figure 2 As shown, by repeatedly applying set and reset pulses of the same amplitude, the resistance of each unit falls within the target resistance range. In 2019, ERHsieh et al. designed a method that proposes a mechanism based on whether the resistance of each unit is above or below the target resistance range, such as... Figure 3 As shown, a scheme using set and reset pulses with progressively increasing voltage amplitude is employed until the memristor resistance falls within the target resistance range.

[0005] However, the current methods for controlling the conductance of memristors have the following problems: (1) The programming process involves complex writing algorithms, requiring continuous verification of whether the target conductance range has been successfully written. (2) A read operation is required for each set or reset pulse applied. (3) Multiple set or reset pulses with different amplitudes or widths are required. (4) There is a problem of being unable to write to the target conductance range, leading to writing failure. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a memristor conductance control method based on a lookup table and its application. The control method is simple, can effectively reduce the number of read operations, and can accurately write to the target conductance range without repeatedly verifying whether the write is successful.

[0007] To achieve the above objectives, in a first aspect, the present invention provides a memristor conductance control method based on a lookup table, comprising the following steps:

[0008] (1) When it is necessary to adjust the conductance of the memristor to the target conductance range, the pulse sequence information that matches the target conductance range is searched from a pre-made lookup table. The lookup table stores the correspondence between at least two conductance states and their corresponding pulses.

[0009] The method for creating the lookup table is as follows:

[0010] (a) Using the low or high resistance state of the memristor as the initial resistance state, apply an excitation pulse between the upper and lower electrodes of the memristor in the initial resistance state, and then apply a read voltage to the memristor to perform a read operation, thereby obtaining the conductance state of the memristor at this time.

[0011] (b) Adjust the amplitude of the excitation pulse, apply the adjusted excitation pulse between the upper and lower electrodes of the memristor in the previous step, and then apply the read voltage to the memristor to perform a read operation to obtain the conductance state of the memristor at this time.

[0012] (c) Repeat step (b) until the conductance state of the memristor under multiple excitation pulses is obtained; when the low resistance state of the memristor is the initial resistance state, the multiple excitation pulses are multiple pulses that differ only in amplitude and increase by the same amount; when the high resistance state of the memristor is the initial resistance state, the multiple pulses that differ only in amplitude and decrease by the same amount.

[0013] (2) According to the pulse sequence information, apply a corresponding pulse between the upper and lower electrodes of the memristor to complete the conductance regulation of the memristor.

[0014] In one embodiment, the specific implementation of using the high-resistance state of the memristor as the initial resistance state is as follows: a pre-forming operation of the conductive channel is performed on the memristor; after the pre-forming of the conductive channel is completed, a reset operation is performed on the memristor to bring it to a stable high-resistance state.

[0015] In one embodiment, the specific implementation of using the low-resistance state of the memristor as the initial resistance state is as follows: a pre-forming operation of the conductive channel is performed on the memristor; after the pre-forming of the conductive channel is completed, a reset operation is performed on the memristor to make it in a stable high-resistance state; and a set operation is performed on the memristor in the high-resistance state to make it in a stable low-resistance state.

[0016] In one embodiment, the preforming operation is accomplished by applying a 2V DC scan voltage between the upper and lower electrodes of the memristor.

[0017] In one embodiment, the reset operation uses a DC scan voltage of -1.3V to bring the memristor to a stable high-resistivity state of 35KΩ.

[0018] In one embodiment, the set operation uses a 1V DC scan voltage and limits the current to 1mA, so that the memristor is in a stable low-resistance state of 390Ω.

[0019] In one embodiment, when the initial resistance state of the memristor is the low resistance state and the multiple excitation pulses are multiple pulses that differ only in amplitude and increase by the same amount, the excitation pulse in step (a) is a pulse with an amplitude of -0.8V, a rise time of 10ns, a pulse width of 50ns, and a fall time of 10ns. The amplitude of the excitation pulse used in each step from step (b) onwards is increased by 0.08V compared to the amplitude of the excitation pulse used in the previous step.

[0020] In one embodiment, the read voltage is a DC scan voltage of -100mV.

[0021] Secondly, the present invention provides an application of the memristor conductance modulation method based on lookup table described above, and the application of the conductance state of memristor under multiple excitation pulses in a neuromorphic computing system, using the conductance state of memristor under multiple excitation pulses to characterize synaptic weight values.

[0022] The memristor conductance control method based on lookup tables provided by this invention can stably control multiple conductance states on a two-terminal memristor by applying reset / set pulses of various amplitudes. Based on the conductance values ​​controlled by the reset / set pulses, a lookup table is created. Using this lookup table method to program and control the memristor conductance avoids performing a read operation for each write pulse, effectively reducing the number of read operations and thus reducing programming time. Furthermore, different conductance states correspond to known pulse and pulse sequence designs, eliminating the need for repeated verification of whether the target conductance range has been reached. The programming process is simple, and since all conductance states are known, there are no situations where the conductance range cannot be written during programming. Attached Figure Description

[0023] Figure 1 This is a flowchart of a memristor conductance control method based on a lookup table according to an embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram illustrating the principle of the conductivity control method provided by the present invention;

[0025] Figure 3 This is a schematic diagram of the structure of the memristor testing system provided in a specific embodiment of the present invention;

[0026] Figure 4 This is a statistical distribution diagram of the conductance state of a memristor provided in a specific embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0028] Figure 1 This is a flowchart of a memristor conductance control method based on a lookup table provided in an embodiment of the present invention, as follows: Figure 1 As shown, the conductivity control method includes steps S10 and S20, which are detailed below:

[0029] S10: When it is necessary to adjust the conductance of the memristor to the target conductance range, the pulse sequence information that matches the target conductance range is searched from a pre-made lookup table. The lookup table stores the correspondence between at least two conductances and their corresponding pulses.

[0030] The method for creating a lookup table includes the following steps:

[0031] Step S101: Using the low or high resistance state of the memristor as the initial resistance state, apply an excitation pulse between the upper and lower electrodes of the memristor in the initial resistance state, and then apply a read voltage to the memristor to perform a read operation to obtain the conductance state of the memristor at this time.

[0032] Step S102: Adjust the amplitude of the excitation pulse, apply the adjusted excitation pulse between the upper and lower electrodes of the memristor in the previous step, and then apply a read voltage to the memristor to perform a read operation to obtain the current conductance state of the memristor.

[0033] Step S103: Repeat step S102 until the conductance state of the memristor under multiple excitation pulses is obtained; when the low resistance state of the memristor is taken as the initial resistance state, the multiple excitation pulses are multiple pulses with different amplitudes and equal increases in amplitude; when the high resistance state of the memristor is taken as the initial resistance state, the multiple pulses with different amplitudes and equal decreases in amplitude are multiple pulses.

[0034] like Figure 2As shown, starting with the memristor's low or high resistance state as the initial resistance state S1, a pulse of amplitude V1 is applied across the memristor, and the memristor's conductance state S2 is read. After reaching conductance state S2, a pulse of amplitude V2 is applied across the memristor, and the memristor's conductance state S3 is read. After reaching conductance state S3, a pulse of amplitude V3 is applied across the memristor, and the memristor's conductance state S4 is read. After reaching conductance state S4, a pulse of amplitude V4 is applied across the memristor, and the memristor's conductance state S5 is read. After reaching conductance state Sn-1, a pulse of amplitude Vn-1 is applied across the memristor, and the memristor's conductance state Sn is read. The pulses V1 to Vn-1 include specific pulse and pulse sequence designs, and the amplitudes of V1 to Vn-1 increase or decrease by the same amount.

[0035] Specifically, when the memristor's low-resistance state is used as the initial resistance state, a negative pulse needs to be applied between the upper and lower electrodes of the memristor to perform a reset operation, and the amplitudes of V1 to Vn-1 increase by the same amount; when the memristor's high-resistance state is used as the initial resistance state, a positive pulse needs to be applied between the upper and lower electrodes of the memristor to perform a set operation, and the amplitudes of V1 to Vn-1 decrease by the same amount.

[0036] The method for creating the lookup table provided in this embodiment involves programming and controlling the memristor by changing the amplitude of the excitation pulse to obtain multiple conductance state distributions, with each conductance state corresponding to a known pulse amplitude. After obtaining the correspondence between the conductance state distribution and the pulse amplitude, a lookup table for conductance control is created. The table correlates the conductance states with the pulse amplitudes in a one-to-one manner. Writing the target conductance only requires applying the known corresponding pulse according to the lookup table, as detailed in step S20.

[0037] S20: Based on the pulse sequence information that matches the target conductance range found in step S10, apply a corresponding pulse between the upper and lower electrodes of the memristor to complete the conductance regulation of the memristor.

[0038] The memristor conductance control method based on lookup tables provided in this embodiment can stably control multiple conductance states on a two-terminal memristor by applying reset / set pulses of various amplitudes. A lookup table is created based on the conductance values ​​controlled by the reset / set pulses. Using this lookup table method to program and control the memristor conductance avoids performing a read operation for each write pulse, effectively reducing the number of read operations and thus reducing programming time. Furthermore, different conductance states correspond to known pulse and pulse sequence designs, eliminating the need for repeated verification of whether the target conductance range has been reached. The programming process is simple, and since all conductance states are known, there are no situations where the conductance range cannot be written during programming.

[0039] Preferably, in step S101 of the lookup table creation method, the initial resistive state of the memristor is implemented as follows:

[0040] When the initial state is the high-resistivity state of the memristor, the specific implementation can be as follows:

[0041] Step 1: Perform a pre-forming operation on the memristor, so that the memristor is in a low-resistance state.

[0042] Step 2: Perform a DC reset operation on the memristor to obtain a stable high-resistance state that can be achieved without breaking down the memristor.

[0043] When the initial state is the low-resistance state of the memristor, the specific implementation is to continue with the following steps after step 2 above:

[0044] Step 3: Perform a DC set operation on the memristor to obtain a stable low-resistance state that can be achieved without breaking down the memristor.

[0045] Based on the same inventive concept, this invention also provides an application of the above-mentioned memristor conductance modulation method based on a lookup table, specifically its application in neuromorphic computing systems where the conductance states of a memristor under multiple excitation pulses are used to characterize synaptic weight values. In this embodiment, when characterizing the synaptic weights of a device using the conductance states of a memristor, different conductance states can be written according to a lookup table.

[0046] To more clearly illustrate the present invention, the following description is provided in conjunction with specific embodiments:

[0047] This embodiment preferably uses a memristor with a Ti / HfOx or AlOy / TiN structure. The memristor includes a 50nm Ti upper electrode, a 100nm TiN lower electrode, and a 5nm HfO2 or Al2O3 functional layer in between. During electrical testing, a bias voltage is applied to the Ti electrode, and the TiN electrode is grounded. The testing system is as follows: Figure 3 As shown.

[0048] The specific pulse control parameters of a memristor are related to its electrical performance. The pulse design method and control scheme are described in detail below.

[0049] (1) Select a memristor and perform a pre-forming operation on its conductive channels. The scanning voltage used for the forward DC I / V scan is 2V.

[0050] (2) After the pre-formation of the conductive channel is completed, the memristor is reset. The reset operation uses a DC scan voltage of -1.3V to obtain a stable high impedance state (35kΩ).

[0051] (3) Perform a set operation on the memristor. The set operation uses a DC scan voltage of 1V and limits the current to 1mA to obtain a stable low-resistance state (390Ω) for the device.

[0052] (4) After setting the memristor to a stable low-resistance state, apply a pulse with an amplitude of -0.8V, a rise time of 10ns, a pulse width of 50ns, and a fall time of 10ns, with the low-resistance state as the initial state.

[0053] (5) Perform a read operation on the memristor. The read operation uses a DC scanning voltage of -100mV to read the conductance value of the memristor and obtain the first high-resistance state S1 of the memristor.

[0054] (6) After the memristor reaches a high resistance state, apply a pulse with an amplitude of -0.88V, a rising edge of 10ns, a pulse width of 50ns, and a falling edge of 10ns, and then read out the conductance value to obtain the second high resistance state S2 of the memristor.

[0055] (7) After the memristor reaches two high-resistance states, apply a pulse with an amplitude of -0.96V, a rising edge of 10ns, a pulse width of 50ns, and a falling edge of 10ns, and then read out the conductance value to obtain the third high-resistance state S3 of the memristor.

[0056] (8) After the memristor reaches three high-resistance states, apply a pulse with an amplitude of -1.04V, a rising edge of 10ns, a pulse width of 50ns, and a falling edge of 10ns, and then read out the conductance value to obtain the fourth high-resistance state S4 of the memristor.

[0057] (9) After the memristor reaches four high-resistance states, apply a pulse with an amplitude of -1.12V, a rising edge of 10ns, a pulse width of 50ns, and a falling edge of 10ns, and then read out the conductance value to obtain the fifth high-resistance state S5 of the memristor.

[0058] (10) After the memristor reaches five high-resistance states, apply a pulse with an amplitude of -1.2V, a rising edge of 10ns, a pulse width of 50ns, and a falling edge of 10ns, and read out the conductance value to obtain the sixth high-resistance state S6 of the memristor.

[0059] (11) After the memristor reaches the sixth high-resistance state, apply a pulse with an amplitude of -1.28V, a rising edge of 10ns, a pulse width of 50ns, and a falling edge of 10ns, and then read out the conductance value to obtain the seventh high-resistance state S7 of the memristor.

[0060] (12) After the memristor reaches seven high-resistance states, apply a pulse with an amplitude of -1.36V, a rise time of 10ns, a pulse width of 50ns, and a fall time of 10ns, and then read the conductance value to obtain the eighth high-resistance state S8 of the memristor. For example... Figure 4As shown, based on the statistical results, the conductance ranges of the eight conductance states of the memristor are set.

[0061] (13) Based on the statistical test results of the memristor, a lookup table corresponding to the pulse amplitude and conductance state is constructed, as shown in Table 1. When implementing a neural network using a memristor array, different conductance states can be written according to the lookup table when the conductance value of the memristor is used to characterize the synaptic weight of the device.

[0062] Pulse amplitude (V) Conductivity Conductivity range (mS) 0 S1 2.5～2.9 V1 S2 1.1～1.9 V2 S3 0.3～0.5 V3 S4 0.21～0.27 V4 S5 0.12～0.17 V5 S6 0.06～0.1 V6 S7 0.04～0.06 V7 S8 0.02～0.035

[0063] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A memristor conductance control method based on a lookup table, characterized in that, Includes the following steps: (1) When it is necessary to adjust the conductance of the memristor to the target conductance range, the pulse sequence information that matches the target conductance range is searched from a pre-made lookup table. The lookup table stores the correspondence between at least two conductance states and their corresponding pulses. The method for creating the lookup table is as follows: (a) Using the low or high resistance state of the memristor as the initial resistance state, apply an excitation pulse between the upper and lower electrodes of the memristor in the initial resistance state, and then apply a read voltage to the memristor to perform a read operation, thereby obtaining the conductance state of the memristor at this time. (b) Adjust the amplitude of the excitation pulse, apply the adjusted excitation pulse between the upper and lower electrodes of the memristor in the previous step, and then apply the read voltage to the memristor to perform a read operation to obtain the conductance state of the memristor at this time. (c) Repeat step (b) until the conductance state of the memristor under multiple excitation pulses is obtained; when the low resistance state of the memristor is the initial resistance state, the multiple excitation pulses are multiple pulses that differ only in amplitude and increase by the same amount; when the high resistance state of the memristor is the initial resistance state, the multiple pulses that differ only in amplitude and decrease by the same amount. (2) According to the pulse sequence information, apply a corresponding pulse between the upper and lower electrodes of the memristor to complete the conductance regulation of the memristor.

2. The memristor conductance control method based on a lookup table according to claim 1, characterized in that, The specific implementation method of using the high-resistance state of the memristor as the initial resistance state is as follows: perform a pre-forming operation on the memristor to form a conductive channel; after the pre-forming of the conductive channel is completed, perform a reset operation on the memristor to make it in a stable high-resistance state.

3. The memristor conductance control method based on lookup table according to claim 1, characterized in that, The specific implementation method of using the low-resistance state of the memristor as the initial resistance state is as follows: perform a pre-forming operation on the memristor to form a conductive channel; after the pre-forming of the conductive channel is completed, perform a reset operation on the memristor to make it in a stable high-resistance state; and perform a set operation on the high-resistance state memristor to make it in a stable low-resistance state.

4. The memristor conductance control method based on a lookup table according to claim 2 or 3, characterized in that, The preforming operation is accomplished by applying a 2V DC scan voltage between the upper and lower electrodes of the memristor.

5. The memristor conductance control method based on a lookup table according to claim 2 or 3, characterized in that, The reset operation uses a DC scan voltage of -1.3V to bring the memristor to a stable high-resistivity state of 35KΩ.

6. The memristor conductance control method based on a lookup table according to claim 3, characterized in that, The set operation uses a 1V DC scan voltage and limits the current to 1mA, so that the memristor is in a stable low-resistance state of 390Ω.

7. The memristor conductance control method based on a lookup table according to claim 3, characterized in that, When the initial resistance state of the memristor is the low resistance state, and the multiple excitation pulses are multiple pulses that differ only in amplitude and increase by the same amount, the excitation pulse in step (a) is a pulse with an amplitude of -0.8V, a rise time of 10ns, a pulse width of 50ns, and a fall time of 10ns. The amplitude of the excitation pulse used in each step from step (b) onwards is increased by 0.08V compared to the amplitude of the excitation pulse used in the previous step.

8. The memristor conductance control method based on a lookup table according to claim 1, characterized in that, The reading voltage is a DC scan voltage of -100mV.

9. An application of the memristor conductance control method based on a lookup table as described in any one of claims 1 to 8, characterized in that, Application of memristor conductance under multiple excitation pulses in neuromorphic computing systems: The conductance of memristors under multiple excitation pulses is used to characterize synaptic weight values.

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