Memory chip testing method, computer equipment and medium

Abstract

The present application relates to a memory chip testing method, computer equipment, and medium. The method includes: in response to a memory chip read command, controlling a clock signal to maintain a first state within a first preset time while controlling a complementary clock signal to maintain a second state within the first preset time; in response to a clock signal maintained in the first state and a complementary clock signal maintained in the second state, maintaining a data strobe signal in the first state within a second preset time while maintaining a complementary data strobe signal in the second state within a second preset time; when the data strobe signal maintains the first state and the complementary data strobe signal maintains the second state, controlling a first driver module connected to the data strobe terminal to operate and measure a first resistance value, and controlling a second driver module connected to the complementary data strobe terminal to operate and measure a second resistance value. The test method of the present application is simple, low-cost, and has good test results.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a memory chip testing method, computer equipment, and medium. Background Art

[0002] There are many types of chip packages. These can generally be categorized based on the packaging material, the connection method between the chip package and the printed circuit board (PCB), and the chip package's appearance. Different chip packages require different testing methods and processes.

[0003] With the rapid development of semiconductor and integrated circuit technology, the market demand for chip products is increasing, and the requirements for chip suppliers' production efficiency and supply quality are becoming increasingly higher. Traditional semiconductor chip testing methods are generally difficult to apply to testing the electrical performance parameters of memory chips.

[0004] Common test terminals for memory chip packages typically include data terminals, power terminals, data strobe terminals, and complementary data strobe terminals. Limited by the structural properties and functional parameters of the memory chip itself, the current or voltage signals collected through the data strobe terminals or complementary data strobe terminals of the memory chip are generally pulse signals and cannot be directly used to test the electrical performance parameters of the memory chip. This results in a test blind spot for the data strobe terminals and complementary data strobe terminals of the memory chip. Summary of the Invention

[0005] Based on this, it is necessary to provide a memory chip testing method, computer equipment and medium to address the technical problems in the above-mentioned background technology, which can measure the resistance value of the memory chip through the data selection terminal and complementary data selection terminal of the memory chip, so as to test whether the memory chip has an abnormality based on the resistance value. The testing method is simple, low-cost and effective.

[0006] To achieve the above and other objectives, one aspect of the present application provides a memory chip testing method, comprising:

[0007] In response to a memory chip read command, controlling the clock signal to maintain a first state within a first preset time, while controlling the complementary clock signal to maintain a second state within the first preset time, the first state and the second state being opposite to each other;

[0008] In response to the clock signal maintained in the first state and the complementary clock signal maintained in the second state, a data strobe signal is maintained in the first state for a second preset time, a complementary data strobe signal is maintained in the second state for the second preset time, the data strobe signal is output through a data strobe terminal of the memory chip, and the complementary data strobe signal is output through a complementary data strobe terminal of the memory chip;

[0009] When the data strobe signal is maintained in the first state and the complementary data strobe signal is maintained in the second state, the first driving module connected to the data strobe terminal is controlled to operate and measure a first resistance value, and the second driving module connected to the complementary data strobe terminal is controlled to operate and measure a second resistance value.

[0010] In the memory chip testing method of the above embodiment, the memory chip is controlled to respond to a memory chip read command so that a clock signal of the memory chip is controlled to maintain in a first state, such as a high level state, for a first preset time, while a complementary clock signal of the memory chip is controlled to maintain in a second state, such as a low level state, for a first preset time, wherein the first state and the second state are opposite to each other. Then, the memory chip is controlled to respond to the memory chip read command so that the memory chip responds to the clock signal maintained in the first state and the complementary clock signal maintained in the second state, while a data strobe signal is maintained in the first state for a second preset time, while a complementary data strobe signal is maintained in the second state for a second preset time, wherein the data strobe signal is output through a data strobe terminal of the memory chip, and the complementary data strobe signal is output through a complementary data strobe terminal of the memory chip. Therefore, during the period when the data strobe signal is maintained in the first state and the complementary data strobe signal is maintained in the second state, a first driver module connected to the data strobe terminal is controlled to operate and measure a first resistance value, and a second driver module connected to the complementary data strobe terminal is controlled to operate and measure a second resistance value. The present application sends a memory chip read command to the memory chip, controls the memory chip clock signal to maintain a first state within a first preset time, and the complementary clock signal to maintain a second state within the first preset time, and makes the data strobe signal maintain the first state within a second preset time, while the complementary data strobe signal maintains the second state within the second preset time, thereby enabling the acquisition of a test current or a test voltage via the data strobe terminal and the complementary data strobe terminal, so as to operate and measure a first resistance value via a first driver module connected to the data strobe terminal, and operate and measure a second resistance value via a second driver module connected to the complementary data strobe terminal, thereby determining whether the memory chip has an abnormality based on the measured first and second resistance values. The test method of this embodiment is simple, low-cost, and has good test results.

[0011] In one embodiment, controlling the first driving module connected to the data strobe terminal to operate and measuring the first resistance value includes:

[0012] If the clock signal is maintained in the first state, controlling the first driving module to operate and provide a first test voltage to the data strobe terminal of the memory chip;

[0013] obtaining, via the data strobe terminal, a first test current of the memory chip driven jointly by a power supply voltage and the first test voltage;

[0014] The first resistance value is calculated according to the power supply voltage, the first test voltage, and the first test current.

[0015] In one embodiment, obtaining, via the data strobe terminal, a first test current of the memory chip driven by both a power supply voltage and the first test voltage includes:

[0016] Acquiring, via the data strobe terminal, a first sampled test current of the memory chip driven jointly by a power supply voltage and the first test voltage;

[0017] Obtaining an average of the amplitudes of the first sampled test current within a first preset sampling time, and determining whether the average is greater than or equal to a first preset current threshold;

[0018] If yes, output the mean value of the amplitude of the first sampled test current;

[0019] Otherwise, the first sampled test current is reacquired.

[0020] In the memory chip testing method of the above embodiment, by obtaining the average value of the amplitude of the first sampled test current within the first preset sampling time, and obtaining the first sampled test current whose average value is greater than or equal to the first preset current threshold, the obtained first sampled test current is prevented from being mixed with excessive noise signals, thereby affecting the accuracy of the first resistance value calculated based on the power supply voltage, the first test voltage and the first test current.

[0021] In one embodiment, calculating the first resistance value according to the power supply voltage, the first test voltage, and the first test current includes:

[0022] The first resistance value is calculated according to an average of the power supply voltage, the first test voltage, and the amplitude of the first sampled test current.

[0023] In one embodiment, calculating the first resistance value according to an average of the power supply voltage, the first test voltage, and the amplitude of the first sampled test current includes:

[0024] The first resistance value R is calculated according to the following formula pu ;

[0025]

[0026] Among them, V DDQ is the power supply voltage, V Test1 is the first test voltage, I out1 is the average value of the amplitude of the first sampled test current.

[0027] In one embodiment, controlling the second driving module connected to the complementary data strobe terminal to operate and measuring the second resistance value includes:

[0028] If the complementary clock signal is maintained in the second state, controlling the second driving module to operate and provide a second test voltage to the complementary data strobe terminal of the memory chip;

[0029] obtaining, via the complementary data strobe terminal, a second test current of the memory chip driven by the second test voltage;

[0030] The second resistance value is calculated according to the second test voltage and the second test current.

[0031] In one embodiment, obtaining the second test current of the memory chip driven by the second test voltage via the complementary data strobe terminal includes:

[0032] obtaining, via the complementary data strobe terminal, a second sampled test current of the memory chip driven by the second test voltage;

[0033] Obtaining an average of the amplitudes of the second sampled test current within a second preset sampling time, and determining whether the average is greater than or equal to a second preset current threshold;

[0034] If yes, output the mean value of the amplitude of the second sampled test current;

[0035] Otherwise, the second sampled test current is re-acquired.

[0036] In the memory chip testing method of the above embodiment, by obtaining the average of the amplitudes of the second sampled test current obtained within the second preset sampling time, and obtaining a second sampled test current whose average is greater than or equal to the second preset current threshold, the obtained second sampled test current is prevented from being mixed with excessive noise signals, thereby preventing the accuracy of the second resistance value calculated based on the second test voltage and the second test current from being affected.

[0037] In one embodiment, calculating the second resistance value according to the second test voltage and the second test current includes:

[0038] The second resistance value is calculated according to an average of the amplitudes of the second test voltage and the second sampled test current.

[0039] In one embodiment, the calculating the second resistance value according to the average of the amplitudes of the second test voltage and the second sampled test current includes:

[0040] The second resistance value R is calculated according to the following formula pd ;

[0041]

[0042] Among them, V Test2 For the second test voltage, I out2 is the average value of the amplitude of the second sampling test current.

[0043] In one embodiment, the time difference between the starting point of the second preset time and the starting point of the first preset time is an integer multiple of the period value of the clock signal.

[0044] In one embodiment, the memory chip testing method further includes:

[0045] When the clock signal is maintained in the second state and the complementary clock signal is maintained in the first state, the third driving module connected to the data strobe terminal is controlled to operate and measure a third resistance value; and the fourth driving module connected to the complementary data strobe terminal is controlled to operate and measure a fourth resistance value.

[0046] Another aspect of the present application provides a computer device including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the computer program, the steps of the memory chip testing method described in any embodiment of the present application are implemented.

[0047] Another aspect of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the memory chip testing method described in any embodiment of the present application are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0049] Figure 1 Shown is a schematic diagram of a timing diagram of the working states of a data strobe signal and a complementary data strobe signal of a memory chip;

[0050] Figure 2 This is a flow chart of a memory chip testing method provided in the first embodiment of the present application;

[0051] Figure 3 Schematic diagram of a test state timing diagram of a data strobe signal and a complementary data strobe signal of a memory chip provided in one embodiment of the present application;

[0052] Figure 4 A schematic flow chart of a memory chip testing method provided in the second embodiment of the present application;

[0053] Figure 5 A schematic flow chart of a memory chip testing method provided in the third embodiment of the present application;

[0054] Figure 6 This is a schematic diagram of an application scenario of a memory chip testing method provided in one embodiment of the present application;

[0055] Figure 7 A schematic flow chart of a memory chip testing method provided in the fourth embodiment of the present application;

[0056] Figure 8 Schematic diagram of a flow chart of a memory chip testing method provided in the fifth embodiment of the present application;

[0057] Figure 9 Schematic diagram of a flow chart of a memory chip testing method provided in the sixth embodiment of the present application;

[0058] Figure 10 This is a structural diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0059] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0061] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0062] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0063] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0064] Please refer to Figure 1 For a semiconductor memory chip package, its data strobe terminal and complementary data strobe terminal can be used to test the electrical performance parameters of the semiconductor memory chip. However, during the test, the data strobe signal DQS obtained through the data strobe terminal and the complementary data strobe signal DQSn obtained through the complementary data strobe terminal are displayed as follows: Figure 1The pulsed square wave signal shown cannot be directly used to test the electrical performance parameters of the memory chip, resulting in a test blind spot in the data strobe terminal and complementary data strobe terminal of the memory chip. Therefore, how to control the data strobe signal DQS output by the data strobe terminal of the memory chip and the complementary data strobe signal DQSn output by the complementary data strobe terminal to maintain a preset state during testing has become a technical problem that needs to be solved in the process of testing the electrical performance parameters of the memory chip via the data strobe terminal and complementary data strobe terminal of the memory chip.

[0065] Please refer to Figure 2 In one embodiment of the present application, a memory chip testing method is provided, comprising the following steps:

[0066] Step 22, in response to a memory chip read command, controlling the clock signal to maintain a first state for a first preset time, while controlling the complementary clock signal to maintain a second state for the first preset time, wherein the first state and the second state are opposite to each other;

[0067] Step 24, in response to the clock signal maintained in the first state and the complementary clock signal maintained in the second state, a data strobe signal maintained in the first state for a second preset time, a complementary data strobe signal maintained in the second state for a second preset time, the data strobe signal outputted through a data strobe terminal of the memory chip, and the complementary data strobe signal outputted through a complementary data strobe terminal of the memory chip;

[0068] Step 26: When the data strobe signal is maintained in the first state and the complementary data strobe signal is maintained in the second state, control the first driving module connected to the data strobe terminal to operate and measure the first resistance value, and control the second driving module connected to the complementary data strobe terminal to operate and measure the second resistance value.

[0069] For details, please refer to Figure 2, controlling a clock signal of the memory chip to maintain a first state, such as a high level state, for a first preset time, while controlling a complementary clock signal of the memory chip to maintain a second state, such as a low level state, for a first preset time, wherein the first state and the second state are opposite states to each other, wherein the clock signal is input into the memory chip through a clock port of the memory chip, and the complementary clock signal is input into the memory chip through a complementary clock port of the memory chip; then controlling the memory chip to respond to a memory chip read command so that the memory chip responds to the clock signal maintained in the first state and the complementary clock signal maintained in the second state, while a data strobe signal is maintained in the first state for a second preset time, and a complementary data strobe signal is maintained in the second state for a second preset time, wherein the data strobe signal is output through a data strobe terminal of the memory chip, and the complementary data strobe signal is output through a complementary data strobe terminal of the memory chip; so that during the period when the data strobe signal is maintained in the first state and the complementary data strobe signal is maintained in the second state, controlling a first driver module connected to the data strobe terminal to operate and measure a first resistance value, and controlling a second driver module connected to the complementary data strobe terminal to operate and measure a second resistance value. The present application sends a memory chip read command to the memory chip, and controls the memory chip clock signal to maintain a first state within a first preset time and the complementary clock signal to maintain a second state within the first preset time, so that the data strobe signal maintains the first state within a second preset time, and the complementary data strobe signal maintains the second state within the second preset time, thereby enabling the acquisition of a test current or a test voltage via the data strobe terminal and the complementary data strobe terminal, so that the first driver module connected to the data strobe terminal operates and measures a first resistance value, and the second driver module connected to the complementary data strobe terminal operates and measures a second resistance value, thereby determining whether the memory chip has an abnormality based on the measured first and second resistance values. The test method of this embodiment is simple, low-cost, and has good test results.

[0070] As an example, see Figure 3 In one embodiment of the present application, by controlling the memory chip to respond to the memory chip read command Read CMD, and controlling the clock signal CK of the memory chip to maintain a high level state within a first preset time, the complementary clock signal CKn of the memory chip is controlled to maintain a low level state within a first preset time. Figure 3 Maintain 1 in the code means maintaining the high level state. Figure 3Maintaining 0 in the data strobe indicates maintaining a low level state; the memory chip responds to the read command and the clock signal CK maintained at a high level state and the complementary clock signal CKn maintained at a low level state, while the data strobe signal DQS is maintained at a high level state for a second preset time, and the complementary data strobe signal DQSn is maintained at a low level state for a second preset time, so that during the period when the data strobe signal DQS is maintained at a high level state and the complementary data strobe signal DQSn is maintained at a low level state, the first driving module connected to the data strobe terminal is controlled to work and measure the first resistance value, and the second driving module connected to the complementary data strobe terminal is controlled to work and measure the second resistance value. This embodiment sends a memory chip read command Read CMD to the memory chip, and controls the memory chip clock signal CK to maintain a high level state and the complementary clock signal CKn to maintain a low level state for a first preset time, so that the data strobe signal maintains a high level state for a second preset time, while the complementary data strobe signal maintains a low level state for a second preset time. This allows a test current or a test voltage to be collected via the data strobe terminal and the complementary data strobe terminal, and then a first driver module connected to the data strobe terminal operates and measures a first resistance value, and a second driver module connected to the complementary data strobe terminal operates and measures a second resistance value, thereby determining whether the memory chip has an abnormality based on the measured first and second resistance values. This embodiment's testing method is simple, low-cost, and has good testing results.

[0071] As an example, please refer to Figure 3 In one embodiment of the present application, the time difference between the starting point t2 of the second preset time and the starting point t1 of the first preset time is an integer multiple of the period value T of the clock signal CK. After the memory chip responds to the read command and controls the clock signal CK of the memory chip to maintain in the first state, the complementary clock signal CKn is maintained in the second state. At this time, the clock circuit inside the memory chip, such as the DLL circuit and / or the PLL circuit, can maintain the data strobe signal DQS in the first state while maintaining the complementary data strobe signal DQSn in the second state. That is, the present application utilizes the inherent properties of the internal circuit of the memory chip to achieve control of the data strobe signal DQS and the complementary data strobe signal DQSn, so that the first drive circuit connected to the data strobe terminal operates and measures the first resistance value, and the second drive circuit connected to the complementary data strobe terminal operates and measures the second resistance value.

[0072] For further information, please refer to Figure 4 In one embodiment of the present application, Figure 2 The difference of the illustrated embodiment is that step 26 comprises:

[0073] Step 261: when the data strobe signal is maintained in the first state and the complementary data strobe signal is maintained in the second state, the first driving module is activated and provides a first test voltage to the data strobe terminal of the memory chip;

[0074] Step 262: Acquire, via the data strobe terminal, a first test current of the memory chip driven by both the power supply voltage and the first test voltage;

[0075] Step 263 : Calculate the first resistance value according to the power supply voltage, the first test voltage, and the first test current.

[0076] For details, please refer to Figure 3 and Figure 4 If the clock signal CK is maintained at a high level, the complementary clock signal CKn is maintained at a low level, and the data select signal DQS is maintained at a high level while the complementary data select signal DQSn is maintained at a low level, the first driving module can be controlled to operate and provide a first test voltage to the data select terminal of the memory chip, and a first test current of the memory chip driven by the power supply voltage and the first test voltage is obtained through the data select terminal.

[0077] As an example, see Figure 5 , provides a memory chip testing method, comprising the following steps:

[0078] Step 22, in response to a memory chip read command, controlling the clock signal to maintain a first state for a first preset time, while controlling the complementary clock signal to maintain a second state for the first preset time, wherein the first state and the second state are opposite to each other;

[0079] Step 24, in response to the clock signal maintained in the first state and the complementary clock signal maintained in the second state, a data strobe signal maintained in the first state for a second preset time, a complementary data strobe signal maintained in the second state for a second preset time, the data strobe signal outputted through a data strobe terminal of the memory chip, and the complementary data strobe signal outputted through a complementary data strobe terminal of the memory chip;

[0080] Step 261: when the data strobe signal is maintained in the first state and the complementary data strobe signal is maintained in the second state, the first driving module is activated and provides a first test voltage to the data strobe terminal of the memory chip;

[0081] Step 2621: Acquire, via the data strobe terminal, a first sampled test current of the memory chip driven by both the power supply voltage and the first test voltage;

[0082] Step 2622: Obtain an average value of the amplitude of the first sampled test current within a first preset sampling time, and determine whether the average value is greater than or equal to a first preset current threshold;

[0083] Step 2623: If yes, output the mean value of the amplitude of the first sampled test current;

[0084] Step 2631: Calculate the first resistance value according to the average of the power supply voltage, the first test voltage, and the amplitude of the first sampled test current.

[0085] For details, please refer to Figure 5 By obtaining the average value of the amplitude of the first sampling test current within the first preset sampling time, and obtaining the first sampling test current whose average value is greater than or equal to the first preset current threshold, it is possible to avoid excessive noise signals being mixed in the obtained first sampling test current, thereby affecting the accuracy of the first resistance value calculated based on the power supply voltage, the first test voltage and the first test current.

[0086] For details, please refer to Figure 5 In one embodiment of the present application, calculating the first resistance value based on an average of the power supply voltage, the first test voltage, and the amplitude of the first sampled test current includes:

[0087] The first resistance value R is calculated according to the following formula pu ;

[0088]

[0089] Among them, V DDQ is the power supply voltage, V Test1 is the first test voltage, I out1 is the average value of the amplitude of the first sampled test current.

[0090] As an example, please refer to Figure 5 and Figure 6 When the memory chip responds to a read command and is in a data read mode (output drive mode), the output drive circuit is working, the pull-up drive circuit is working, and the pull-down drive circuit is off, the pull-up drive circuit causes the data strobe terminal DQS to output a high level. At this time, the pull-up drive circuit is turned on, that is, the first drive module is working, and provides the first test voltage V to the data strobe terminal DQS. Test1 , to measure the equivalent resistance R of the pull-up driving circuit, i.e. the first driving module, according to formula (1) pu .

[0091] As an example, see Figure 7 In one embodiment of the present application, Figure 5 The difference of the embodiment shown is that after step 24, the following steps are further included:

[0092] Step 264: When the data strobe signal is maintained in the first state and the complementary data strobe signal is maintained in the second state, controlling the second driving module to operate and provide a second test voltage to the complementary data strobe terminal of the memory chip;

[0093] Step 265: obtaining a second test current of the memory chip driven by the second test voltage via the complementary data strobe terminal;

[0094] Step 266, calculating the second resistance value based on the second test voltage and the second test current.

[0095] For details, please refer to Figure 7 and Figure 3 When the data selection signal DQS is maintained at a high level state and the complementary data selection signal DQSn is maintained at a low level state, the second driving module is controlled to operate and a second test voltage is provided to the complementary data selection terminal of the memory chip to calculate the second resistance value according to the second test voltage and the second test current.

[0096] For further information, please refer to Figure 8 In one embodiment of the present application, Figure 6 The difference of the embodiment shown is that after step 264, the following steps are further included:

[0097] Step 2651: obtaining a second sampled test current of the memory chip driven by the second test voltage via the complementary data strobe terminal;

[0098] Step 2652: Obtain an average of the amplitudes of the second sampled test current within a second preset sampling time, and determine whether the average is greater than or equal to a second preset current threshold;

[0099] Step 2653: If yes, output the mean value of the amplitude of the second sampled test current;

[0100] Step 2661: Calculate the second resistance value according to the average of the amplitudes of the second test voltage and the second sampled test current.

[0101] For details, please refer to Figure 8 By obtaining the average of the amplitudes of the second sampling test current obtained within the second preset sampling time, and obtaining the second sampling test current whose average is greater than or equal to the second preset current threshold, it is possible to avoid excessive noise signals being mixed in the obtained second sampling test current, thereby affecting the accuracy of the second resistance value calculated according to the second test voltage and the second test current.

[0102] As an example, please refer to Figure 8 In one embodiment of the present application, the step of calculating the second resistance value based on the average of the amplitudes of the second test voltage and the second sampled test current includes:

[0103] The second resistance value R is calculated according to the following formula pd ;

[0104]

[0105] Among them, V Test2 For the second test voltage, I out2 is the average value of the amplitude of the second sampling test current.

[0106] As an example, please refer to Figure 8 and Figure 6 When the memory chip responds to a read command and is in a read data mode (output drive mode), the output drive circuit is on, the pull-down drive circuit is on, and the pull-up drive circuit is off. The pull-down drive circuit causes the complementary data strobe terminal DQSn to output a low level. At this time, the pull-down drive circuit is on, that is, the second drive module is on, providing the second test voltage V to the complementary data strobe terminal DQSn. Test2 , to measure the equivalent resistance R of the pull-down driving circuit, i.e. the second driving circuit, according to formula (2) pd .

[0107] For further information, please refer to Figure 9 In one embodiment of the present application, the memory chip testing method further includes:

[0108] Step 267, when the clock signal is maintained in the second state and the complementary clock signal is maintained in the first state, control the third driving module connected to the data enable terminal to operate and measure the third resistance value; and control the fourth driving module connected to the complementary data enable terminal to operate and measure the fourth resistance value.

[0109] As an example, since data strobe terminals and complementary data strobe terminals in a semiconductor memory chip package generally appear in pairs, while the data strobe signal is maintained in a first state and the complementary data strobe signal is maintained in a second state, a first driver module connected to the data strobe terminal can be controlled to operate and measure a first resistance value, and a second driver module connected to the complementary data strobe terminal can be controlled to operate and measure a second resistance value. While the data strobe signal is maintained in the second state and the complementary data strobe signal is maintained in the first state, a third driver module connected to the data strobe terminal can be controlled to operate and measure a third resistance value; and a fourth driver module connected to the complementary data strobe terminal can be controlled to operate and measure a fourth resistance value. This embodiment enables comprehensive testing of the memory chip via the data strobe terminals and the complementary data strobe terminals. By comparing the first resistance value with the fourth resistance value, and the second resistance value with the third resistance value, obtained during the two tests, it can assist in determining whether the memory chip has an abnormality. The first and fourth resistance values ​​are equivalent resistance values ​​obtained by measuring the pull-up drive circuit, and the second and third resistance values ​​are equivalent resistance values ​​obtained by measuring the pull-down drive circuit.

[0110] It should be understood that although Figure 2 、 Figure 4-Figure 5 、 Figure 7-Figure 9 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, although Figure 2 、 Figure 4-Figure 5 、 Figure 7-Figure 9 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0111] Furthermore, in one embodiment of the present application, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 10As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. When the computer program is executed by the processor, a memory chip testing method is implemented. The display screen of the computer device can be a liquid crystal display or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad provided on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0112] Those skilled in the art will understand that Figure 10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0113] In one embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the memory chip testing method described in any embodiment of the present application are implemented.

[0114] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0115] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0116] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A memory chip testing method, characterized in that: include: In response to a memory chip read command, controlling the clock signal to maintain a first state within a first preset time, while controlling the complementary clock signal to maintain a second state within the first preset time, the first state and the second state being opposite to each other; In response to the clock signal maintained in the first state and the complementary clock signal maintained in the second state, a data strobe signal is maintained in the first state for a second preset time, a complementary data strobe signal is maintained in the second state for the second preset time, the data strobe signal is output through a data strobe terminal of the memory chip, and the complementary data strobe signal is output through a complementary data strobe terminal of the memory chip; When the data strobe signal is maintained in the first state and the complementary data strobe signal is maintained in the second state, controlling a first driving module connected to the data strobe terminal to operate and measure a first resistance value, and controlling a second driving module connected to the complementary data strobe terminal to operate and measure a second resistance value; The first driving module is a pull-up driving circuit, the second driving module is a pull-down driving circuit, the first resistance value is an equivalent resistance value obtained by measuring the pull-up driving circuit, and the second resistance value is an equivalent resistance value obtained by measuring the pull-down driving circuit.

2. The method according to claim 1, characterized in that The controlling the first driving module connected to the data strobe terminal to operate and measure the first resistance value includes: If the clock signal is maintained in the first state, controlling the first driving module to operate and provide a first test voltage to the data strobe terminal of the memory chip; obtaining, via the data strobe terminal, a first test current of the memory chip driven jointly by a power supply voltage and the first test voltage; The first resistance value is calculated according to the power supply voltage, the first test voltage, and the first test current.

3. The method according to claim 2, characterized in that The step of obtaining, via the data strobe terminal, a first test current of the memory chip driven by a power supply voltage and the first test voltage comprises: Acquiring, via the data strobe terminal, a first sampled test current of the memory chip driven jointly by a power supply voltage and the first test voltage; Obtaining an average of the amplitudes of the first sampled test current within a first preset sampling time, and determining whether the average is greater than or equal to a first preset current threshold; If yes, output the mean value of the amplitude of the first sampled test current; Otherwise, the first sampled test current is reacquired.

4. The method according to claim 3, characterized in that The calculating the first resistance value according to the power supply voltage, the first test voltage, and the first test current includes: The first resistance value is calculated according to an average of the power supply voltage, the first test voltage, and the amplitude of the first sampled test current.

5. The method according to claim 4, characterized in that The calculating the first resistance value according to the average of the power supply voltage, the first test voltage, and the amplitude of the first sampled test current includes: The first resistance value is calculated according to the following formula ; ； in, is the power supply voltage, For the first test voltage, is the average value of the amplitude of the first sampled test current.

6. The method according to any one of claims 1 to 5, characterized in that The controlling the second driving module connected to the complementary data strobe terminal to operate and measure the second resistance value includes: If the complementary clock signal is maintained in the second state, controlling the second driving module to operate and provide a second test voltage to the complementary data strobe terminal of the memory chip; obtaining, via the complementary data strobe terminal, a second test current of the memory chip driven by the second test voltage; The second resistance value is calculated according to the second test voltage and the second test current.

7. The method according to claim 6, characterized in that The obtaining, via the complementary data strobe terminal, a second test current of the memory chip driven by the second test voltage, comprises: obtaining, via the complementary data strobe terminal, a second sampled test current of the memory chip driven by the second test voltage; Obtaining an average of the amplitudes of the second sampled test current within a second preset sampling time, and determining whether the average is greater than or equal to a second preset current threshold; If yes, output the mean value of the amplitude of the second sampled test current; Otherwise, the second sampled test current is re-acquired.

8. The method according to claim 7, characterized in that The calculating the second resistance value according to the second test voltage and the second test current includes: The second resistance value is calculated according to an average of the amplitudes of the second test voltage and the second sampled test current.

9. The method according to claim 8, characterized in that The calculating the second resistance value according to the average of the amplitudes of the second test voltage and the second sampled test current includes: The second resistance value is calculated according to the following formula ; ； in, For the second test voltage, is the average value of the amplitude of the second sampling test current.

10. The method according to any one of claims 1 to 5, characterized in that A time difference between a starting point of the second preset time and a starting point of the first preset time is an integer multiple of a period value of the clock signal.

11. The method according to any one of claims 1 to 5, characterized in that Also includes: When the clock signal is maintained in the second state and the complementary clock signal is maintained in the first state, controlling the third driving module connected to the data strobe terminal to operate and measure a third resistance value; and controlling the fourth driving module connected to the complementary data strobe terminal to operate and measure a fourth resistance value; The fourth driving module is a pull-up driving circuit, the third driving module is a pull-down driving circuit, the fourth resistance value is an equivalent resistance value obtained by measuring the pull-up driving circuit, and the third resistance value is an equivalent resistance value obtained by measuring the pull-down driving circuit.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, wherein: When the processor executes the program, the steps of the method according to any one of claims 1 to 11 are implemented.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

Images