Semiconductor device and method of forming the same

Abstract

This disclosure relates to a semiconductor device and a method of forming the same. One structure includes: a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and in contact with the first conductive feature. An air spacer surrounds the second conductive feature, and the sidewalls of the second conductive feature are exposed to the air spacer. A guard ring further surrounds the second conductive feature, and the guard ring completely separates the second conductive feature from the air spacer.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods of forming the same. Background Technology

[0002] Integrated circuit devices, such as transistors, are formed on semiconductor wafers. These devices are interconnected via metal lines and vias to form functional circuits, where the metal lines and vias are formed in back-end-of-line processes. To reduce the parasitic capacitance of the metal lines and vias, they are formed in low-k dielectric layers, typically with k values ​​below 3.8, 3.0, or 2.5.

[0003] When forming metal lines and vias in a low-k dielectric layer, the low-k dielectric layer is etched to form trenches and via openings. Etching of the low-k dielectric layer may include forming a patterned hard mask on the low-k dielectric material and using the patterned hard mask as an etching mask to form the trenches. Via openings are also formed below the trenches. The trenches and via openings are then filled with a metal material, which may include copper. A chemical mechanical polishing (CMP) process is then performed to remove excess metal material on the low-k dielectric layer.

[0004] Air spacers are known to have a low k-value, equal to 1.0. In the conventional process of forming air spacers between metal wires, the dielectric material between the two metal wires is first removed, and then another dielectric material is re-deposited between the two metal wires. The deposition process is controlled to form air spacers in the refilled dielectric material. A CMP process is then performed to remove excess filler dielectric material above the metal wires. Summary of the Invention

[0005] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: etching a dielectric layer to form an opening, wherein a first conductive feature beneath the dielectric layer is exposed in the opening; depositing a sacrificial spacer layer extending into the opening; performing a first etching process to etch the sacrificial spacer layer, wherein a first bottom portion of the sacrificial spacer layer at the bottom of the opening is removed to expose the first conductive feature, and a first vertical portion of the sacrificial spacer layer in the opening and on the sidewalls of the dielectric layer is retained to form a sacrificial ring; depositing a protective layer extending into the opening and on the sacrificial ring; performing a second etching process to etch the protective layer, wherein a second bottom portion of the protective layer is removed to expose the first conductive feature, and a second vertical portion of the protective layer in the opening is retained to form a protective ring; forming a second conductive feature in the opening, wherein the second conductive feature is surrounded by the sacrificial ring and is above and electrically coupled to the first conductive feature; and removing the sacrificial ring to form an air spacer.

[0006] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first conductive feature; a first etch stop layer above the first conductive feature; a dielectric layer above the first etch stop layer; a second conductive feature in the dielectric layer and the first etch stop layer, wherein the second conductive feature is above and in contact with the first conductive feature; an air spacer surrounding the second conductive feature, wherein sidewalls of the second conductive feature are exposed to the air spacer; and a protective ring surrounding the second conductive feature, wherein the protective ring completely separates the second conductive feature from the air spacer.

[0007] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first dielectric layer; a first conductive feature in the first dielectric layer; a second conductive feature above and electrically coupled to the first conductive feature, wherein the second conductive feature includes: a diffusion barrier layer; and a metallic material surrounded by the diffusion barrier layer; a protective layer surrounding and contacting the second conductive feature, wherein the protective layer is in contact with the top surface of at least one of the first dielectric layer and the first conductive feature; an air spacer surrounding the protective layer; and a dielectric layer surrounding the air spacer. Attached Figure Description

[0008] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0009] Figures 1-10 , Figure 11A , Figure 11B , Figures 12-16 and Figure 17A A cross-sectional view is shown of an intermediate stage in the formation of conductive features and air spacers according to some embodiments.

[0010] Figure 17B A cross-sectional view of a double damascene structure without air spacers is shown according to some embodiments.

[0011] Figure 17C A top view of an air gap element according to some embodiments is shown.

[0012] Figure 18 An air spacer formed around a contact plug according to some embodiments is shown.

[0013] Figure 19 A process flow for forming conductive features and air spacers according to some embodiments is shown. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, this document may use spatially relevant terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) to facilitate the description of the relationship between one element or feature as shown in the figure and another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein can be interpreted similarly.

[0016] An air spacer and a method of forming the same are provided. According to some embodiments of this disclosure, a sacrificial spacer is deposited, followed by a first anisotropic etching process to remove a horizontal portion of the sacrificial layer and form a sacrificial ring. A protective layer is then deposited, followed by a second anisotropic etching process to remove a horizontal portion of the protective layer to form a protective ring surrounded by the sacrificial ring. By performing the first etching process prior to depositing the protective layer, the protective ring can physically contact the underlying features. Therefore, after removing the sacrificial ring, the protective ring can prevent the bottom of the subsequently formed barrier layer from being oxidized and damaged by chemicals. The embodiments discussed herein are intended to provide examples enabling the manufacture or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0017] Figures 1-10 , Figure 11A , Figure 11B , Figures 12-16 and Figure 17A A cross-sectional view is shown illustrating intermediate stages in the formation of conductive features and air spacers according to some embodiments of the present disclosure. Corresponding processes are also schematically reflected in, for example... Figure 19 The process flow shown is 200.

[0018] Figure 1 A cross-sectional view of package assembly 20 is shown. According to some embodiments of this disclosure, package assembly 20 is a device wafer including active devices and possibly passive devices, represented by the integrated circuit device 26 shown. Device wafer 20 may include a plurality of dies 22, one of which is shown. According to alternative embodiments of this disclosure, package assembly 20 is an interposer wafer, which may or may not include active devices and / or passive devices. In the following discussion, the device wafer is discussed as an example of package assembly 20. Embodiments of this disclosure can also be applied to other types of package assemblies, such as interposer wafers, package substrates, packages, etc.

[0019] According to some embodiments, wafer 20 includes a semiconductor substrate 24 and features formed at the top surface of semiconductor substrate 24. Semiconductor substrate 24 may be formed of crystalline silicon, crystalline germanium, silicon-germanium, or III-V compound semiconductors, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in semiconductor substrate 24 to isolate active regions in semiconductor substrate 24. Although not shown, through-vias may (or may not) be formed to extend into semiconductor substrate 24, wherein the through-vias are used to electrically couple features on opposite sides of semiconductor substrate 24 to each other. According to alternative embodiments, wafer 20 is used to form an interposer, and substrate 24 may be a semiconductor substrate or a dielectric substrate.

[0020] According to some embodiments of this disclosure, integrated circuit device 26 is formed on the top surface of semiconductor substrate 24. According to some embodiments, integrated circuit device 26 may include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit device 26 are not detailed herein. Figure 1 As shown in the image. Figure 18 A schematic diagram of an example transistor according to some embodiments is shown, which includes a gate stack 92 and a source / drain region 94 formed on the top surface of a semiconductor substrate 24.

[0021] Return to reference Figure 1 An interlayer dielectric (ILD) 28 is formed on the semiconductor substrate 24 and fills the space between the gate stacks of transistors (not shown) in the integrated circuit device 26. According to some embodiments, the ILD 28 is formed from or includes phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, etc. The ILD 28 can be formed using spin coating, flow chemical vapor deposition (FCVD), etc. According to some embodiments of this disclosure, the ILD 28 is formed using deposition processes such as plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0022] Contact plugs 30 are formed in the ILD 28 and are used to electrically connect the integrated circuit device 26 to overlying metal lines and vias. According to some embodiments of this disclosure, the contact plugs 30 are formed of a conductive material selected from: tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of the contact plugs 30 may include: forming contact openings in the ILD 28, filling the contact openings with one or more conductive materials, and performing planarization processes such as chemical mechanical polishing (CMP) or mechanical grinding to make the top surface of the contact plugs 30 flush with the top surface of the ILD 28.

[0023] In the subsequent discussion of the air spacer, as an example, the conductive feature surrounded by the air spacer is located in a dielectric layer that is above and in contact with the contact plug 30. It should be understood that the air spacer and the conductive feature surrounded by the air spacer can be in any layer having conductive features, for example, in a layer having... Figure 18 In the layer of the contact plug shown.

[0024] refer to Figure 2 An etch stop layer 32 is formed over ILD 28 and contact plug 30. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 202. According to some embodiments, the etch stop layer 32 contacts the top surfaces of the ILD 28 and the contact plug 30. According to alternative embodiments, one or more dielectric layers and corresponding conductive features (e.g., contact plugs, metal lines, vias, etc.) are present between the ILD 28 and the etch stop layer 32. For example, one or more additional etch stop layers, additional ILDs, low-k dielectric layers, etc., may exist between the ILD 28 and the etch stop layer 32. Accordingly, contact plugs, vias, metal lines, etc., may be present in the dielectric layers.

[0025] The etch stop layer 32 may include silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), etc. The etch stop layer 32 may also include metal oxides, metal nitrides, etc. The etch stop layer 32 may be a single layer formed of a homogeneous material, or a composite layer comprising multiple dielectric sublayers formed of different materials. According to some embodiments of this disclosure, the etch stop layer 32 includes an aluminum nitride (AlN) layer, a silicon oxycarbide layer above the aluminum nitride layer, and an aluminum oxide layer above the silicon oxycarbide layer.

[0026] Further reference Figure 2 The dielectric layer 34 is deposited on top of the etch stop layer 32. The corresponding process is as follows: Figure 19The process flow 200 shown is illustrated as process 204. The dielectric layer 34 may be an ILD layer in which contact plugs are formed. Alternatively, the dielectric layer 34 may be an intermetallic dielectric (IMD) layer for forming metal wires. According to some embodiments of this disclosure, the dielectric layer 34 is formed of or includes a low-k dielectric material with a dielectric constant (k value) less than 3.8, and the dielectric constant may also be less than about 3.0, for example, between about 2.5 and about 3.0. The dielectric layer 34 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of this disclosure, the formation of the dielectric layer 34 includes depositing a dielectric material containing a pore-forming agent, and then performing a curing process to remove the pore-forming agent, and thus the remaining dielectric layer 34 is porous.

[0027] Pad layer 36 and hard mask 38 are formed on semiconductor substrate IMD. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 206. The pad layer 36 can be a thin film formed of silicon oxide or a thin film comprising silicon oxide. According to some embodiments of this disclosure, tetraethyl orthosilicate (TEOS) is used as a precursor to form the pad layer 36, and the deposition process can include PECVD, CVD, low-pressure chemical vapor deposition (LPCVD), etc. The pad layer 36 acts as an adhesion layer between the dielectric layer 34 and the hard mask 38. The pad layer 36 can also act as an etch stop layer for etching the hard mask 38. According to some embodiments of this disclosure, the hard mask 38 is formed of tungsten-doped carbide (WDC), silicon nitride, titanium nitride, boron nitride, etc. The deposition method can include CVD, LPCVD, PECVD, etc. The hard mask 38 is used as a hard mask during subsequent photolithography processes.

[0028] Further reference Figure 2 Photoresist 40 is formed on hard mask 38 and then patterned to form openings 42 in the photoresist 40. In subsequent processes, photoresist 40 is used to etch hard mask 38. The corresponding process is as follows: Figure 19 The process flow 200 shown is also illustrated as process 206. The pad layer 36 can serve as an etch stop layer for the etching process. Therefore, the pad layer 36 is exposed. The photoresist 40 is removed after the etching process, for example, in an ashing process.

[0029] Next, refer to Figure 3 A hard mask 38 is used as an etching mask to etch the pad layer 36 and the dielectric layer 34, and an opening 42 extends into the dielectric layer 34. The corresponding process is as follows: Figure 19The process flow 200 shown is illustrated as process 208. The liner layer 36 can be etched using a dry etching process employing a mixture of NF3 and NH3 gases, a mixture of HF and NH3 gases, etc. Alternatively, the liner layer 36 can be etched using a wet etching process employing, for example, an HF solution. According to some embodiments of this disclosure, etching of the dielectric layer 34 is performed using a process gas containing fluorine and carbon, wherein fluorine is used for etching, and carbon serves to protect the sidewalls of the dielectric layer 34, which face the via openings and trenches. For example, the process gas used for etching may include one or more fluorine and carbon-containing gases, such as C4F8, CH2F2, CH4, CH3F, and / or CF4, and a carrier gas, such as Ar, N2, etc. The etching is anisotropic.

[0030] The etching of dielectric layer 34 stops at etch stop layer 32. Next, etch stop layer 32 is etched through, and opening 42 further penetrates etch stop layer 32. The corresponding process is as follows: Figure 19 The process flow 200 shown is also illustrated as process 208. The etching chemicals are selected based on the material and layer of the etch stop layer 32. For example, when the etch stop layer 32 comprises alumina, silicon carbide, aluminum nitride, etc., etching gases such as BCl3, Cl2, CF4, CHF3, etc., can be used, and oxygen (O2) can be added. After etching the dielectric layer 34, the underlying conductive features (e.g., the contact plug 30 when the etch stop layer 32 is directly above the contact plug 30) are exposed.

[0031] In such Figure 3 In the example embodiment shown, the top surfaces of both the conductive feature 30 and the dielectric layer 28 are exposed to the opening 42. According to an alternative embodiment, the opening 42 is narrower than the corresponding conductive feature 30, and therefore, the top surface of the conductive feature 30 is exposed, while the top surface of the dielectric layer 28 is not exposed. Corresponding embodiments are also shown as examples. Figure 18 As shown, the gate stack 92 and the source / drain contact plug 98 correspond to the conductive feature 30.

[0032] Figure 4 The deposition of sacrificial layer 44 is shown. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 210. According to some embodiments, the sacrificial layer 44 is formed of or includes materials that can be selectively removed in subsequent processes and do not react with surrounding materials. According to some embodiments, the sacrificial layer 44 may be made of a semiconductor such as Si or a material such as titanium oxide (TiO₂). x ), aluminum oxide (AlO) xDielectric materials such as silicon nitride are formed. Deposition can be performed using conformal deposition processes such as CVD, ALD, physical vapor deposition (PVD), and PECVD. Therefore, the horizontal and vertical portions of the sacrificial layer 44 are equal to or substantially equal to each other, for example, the thickness variation is less than about 20% or 10%.

[0033] The desired thickness T1 of the sacrificial layer 44 is related to the location of the dielectric layer 34. For example, when the dielectric layer 34 is a lower IMD layer (e.g., a layer including metallization layers M0, M1, etc.), the thickness T1 can be smaller, and when the dielectric layer 34 is a higher IMD layer (e.g., a layer for metallization layers M8, M9, or higher), the thickness T1 can be larger. Similarly, the width and spacing of adjacent openings 42 have smaller values ​​when formed in the lower layer and larger values ​​when formed in the upper layer. According to some embodiments, the thickness T1 is approximately To date The deposition time can range from approximately 10 seconds to approximately 200 seconds. The deposition temperature can range from approximately 25°C to approximately 50°C.

[0034] Figure 4 A first anisotropic etching process 46 for patterning the sacrificial layer 44 is also shown. The etching process 46 is performed after the deposition of the sacrificial layer 44. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 212. The resulting structure is... Figure 5 As shown in the figure. According to some embodiments, etching is performed using a dry etching process utilizing directional plasma generated from an etching gas. Depending on the material of the sacrificial layer 44, the etching gas may include Cl2, CF4, CHF3, CH4, HBr, CO2, O2, or combinations thereof. Other gases, such as H2 and He, may also be added. According to some embodiments, the etching time may be in the range of about 10 seconds to about 50 seconds. The wafer temperature during etching may be in the range of about 25°C to about 60°C. As a result of the anisotropic etching process, the horizontal portion of the sacrificial layer 44 is removed. Furthermore, at the bottom of the opening 42, the conductive feature 30 is exposed. The vertical portion of the sacrificial layer 44 remains in the opening 42 to form a sacrificial ring 44' surrounding the remaining portion of the opening 42. The sacrificial ring 44' contacts the sidewalls of the etch stop layer 32, the dielectric layer 34, the pad layer 36, and the hard mask 38.

[0035] Figure 6 The deposition of protective layer 48 is shown. The corresponding process is as follows: Figure 19The process flow 200 shown is illustrated as process 214. According to some embodiments, the protective layer 48 is formed of or includes a material different from the material of the sacrificial ring 44'. According to some embodiments, the protective layer 48 may be formed of a conductive or dielectric material. Conductive materials may include TaN, TiN, etc. Dielectric materials may include oxides such as (low-temperature) silicon oxide, silicon nitride, silicon carbide, silicon carbide, etc. The thickness T2 of the protective layer 48 may be approximately... To date Within the range between [specific values]. Deposition can be performed using conformal deposition processes such as CVD, ALD, PVD, PECVD, etc. Therefore, the horizontal and vertical portions of the protective layer 48 are equal to or substantially equal to each other, for example, the thickness variation is less than about 20% or 10%. According to some embodiments, the deposition time of the protective layer 48 can be in the range between about 10 seconds and about 200 seconds. The deposition temperature can be higher than about 100°C, and can be in the range between about 120°C and about 200°C.

[0036] Figure 6 A second anisotropic etching process 50 for patterning the protective layer 48, performed after deposition, is also shown. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 216. The resulting structure is... Figure 7 As shown in the figure. According to some embodiments, etching is performed using a dry etching process utilizing directional plasma generated from an etching gas. Depending on the material of the protective layer 48, the etching gas may include Cl2, CF4, CHF3, CH4, HBr, CO2, H2, O2, etc., or combinations thereof. Other gases, such as H2 and He, may also be added. As a result of the anisotropic etching process, the horizontal portion of the protective layer 48 is removed. Furthermore, at the bottom of the opening 42, the conductive feature 30 is exposed. The vertical portion of the protective layer 48 remains in the opening 42 to form a protective ring 48'. Since the sacrificial layer 44 has been etched to expose the top surface of the underlying feature (e.g., contact plug 30 and dielectric layer 28), the protective ring 48' is able to extend to and contact the top surface of the underlying feature (e.g., conductive feature 30 or dielectric layer 28). According to some embodiments, the etching time may be in the range of about 10 seconds to about 50 seconds. The wafer temperature during the etching process may be in the range of about 25°C to about 60°C.

[0037] Figures 8 to 10 Conductive feature 56 is shown. Figure 10 The formation of ). Reference Figure 8 Deposition barrier layer 52. The corresponding process is as follows: Figure 19The process flow 200 shown is illustrated as process 218. According to some embodiments, the barrier layer 52 is formed of or includes titanium, titanium nitride, tantalum, tantalum nitride, etc. The barrier layer 52 can be formed as a conformal layer, which can be deposited using CVD, ALD, PVD, etc. After forming the barrier layer 52, a metal seed layer (not shown) is formed. The metal seed layer can be formed of or include copper, and can be formed, for example, using PVD.

[0038] Figure 9 The deposition of conductive material 54 is shown. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 220. According to some embodiments, the conductive material 54 includes copper or copper alloys, cobalt, tungsten, aluminum, etc., or combinations thereof. The deposition process may include electrochemical plating (ECP), electroless plating, CVD, etc. The conductive material 54 completely fills the opening 42.

[0039] According to an alternative embodiment, instead of both the deposited barrier layer 52 and the conductive material 54, a single homogeneous material is deposited to fill the opening 42, so that the resulting conductive feature 56 is unobstructed.

[0040] Next, planarization processes such as chemical mechanical polishing (CMP) or mechanical grinding are performed to remove excess portions of the conductive material 54 and the barrier layer 52. Corresponding processes include... Figure 19 The process flow 200 shown is illustrated as process 222. The planarization process can be stopped on the top surface of the dielectric layer 34 or the top surface of the pad layer 36. Alternatively, the planarization process can be performed until the top of the dielectric layer 34 is removed. The resulting structure is... Figure 10 As shown in the diagram. Throughout the description, the remaining portion of the conductive material 54 and the barrier layer 52 is collectively referred to as the conductive feature 56, which may be a metal wire, a metal via, a contact plug, etc. A guard ring 48' surrounds the corresponding conductive feature 56, and a sacrificial ring 44' surrounds the corresponding guard ring 48'.

[0041] Figure 11A The selective formation of the metal cap 58 is shown. The corresponding process is as follows: Figure 19The process flow 200 shown is illustrated as process 224. According to some embodiments, the metal cap 58 is formed by a selective deposition process, such that the metal cap 58 is selectively deposited on the exposed surface of the conductive feature 56, rather than on the exposed surfaces of the sacrificial ring 44' and the dielectric layer 34. When the protective ring 48' is formed of a conductive material, the metal cap 58 may extend over the protective ring 48', the extended portion of which is indicated by the dashed line 58". Otherwise, when the protective ring 48' is formed of a dielectric material, the metal cap 58 may or may not extend over the protective ring 48'. According to these embodiments, the metal cap 58 is generally above the top surface of the dielectric layer 34. The deposition process is controlled, for example, by controlling the thickness of the metal cap 58, such that the lateral extension of the metal cap 58 does not extend over the top of the sacrificial ring 44', or extends only partially over the top of the sacrificial ring 44'. After the metal cap 58 is formed, a sufficient portion of the top surface of the sacrificial layer 44 remains exposed. According to some embodiments, the selective deposition process can be performed by ALD or CVD. According to some embodiments, the metal cap 58 is formed of or includes the following: cobalt (Co), tungsten (W), CoWP, CoB, tantalum (Ta), nickel (Ni), molybdenum (Mo), titanium (Ti), iron (Fe), or combinations thereof. When depositing the metal cap 58, the precursor may include a metal halide (e.g., WCl5) or an organometallic material and a reducing agent (e.g., H2).

[0042] Figure 12 The removal of the sacrificial ring 44' to form the air spacer 60 is shown. The corresponding process is as follows: Figure 19 The process flow 200 is shown as process 226. Due to the uniformity of the sacrificial layer 44, the air spacer 60 has a substantially uniform thickness (lateral dimension), for example, where the thickness variation of most portions of the air spacer is less than about 20%. According to some embodiments, the sacrificial layer 44 is etched using an isotropic etching process, which may include a dry etching process and / or a wet etching process. For example, when performing a dry etching process, the etching gas may include HF, NF3, O2, CO2, H2, NH3, Cl2, C, depending on the material of the sacrificial ring 44'. x F y (e.g., CF4), CHF3, CH4, HBr, He, etc., or combinations thereof. According to some embodiments, the etching time of the dry etching process can be in the range of about 10 seconds to about 60 seconds. The wafer temperature during the etching process can be below about 60°C, and can be in the range of about 25°C to about 60°C.

[0043] When performing a wet etching process, etching chemicals may include HF solution, ammonia (NH4OH), phosphoric acid, etc. According to some embodiments, the etching time of the wet etching process can range from about 10 seconds to about 60 seconds. The wafer temperature during the etching process can be below about 50°C, and can be in the range of about 20°C to about 50°C.

[0044] Figure 11A and Figure 12 The present invention discloses an embodiment in which a metal cap 58 is first formed, followed by the formation of an air spacer 60. According to an alternative embodiment, the sacrificial ring 44' is first removed to form the air spacer 60, followed by the formation of the metal cap 58. This embodiment... Figure 11B and Figure 12 The combination is shown in the middle. (Reference) Figure 11B The sacrificial ring 44' is removed to form an air spacer 60. Then, a metal cap 58 is selectively deposited. The resulting structure is also... Figure 12 As shown in the image.

[0045] According to some embodiments, when using Figure 11A In the embodiment shown, the metal cap 58 is confined to the area directly above the conductive feature 56. When using Figure 11B In the embodiment shown, the metal cap 58 may or may not include a portion that extends slightly laterally to form an overhang. The overhang may contact the top of the sidewall of the conductive feature 56, which faces the air spacer 60. For example, Figure 12 The dashed line 58' is schematically shown, representing an extension of the metal cap 58. The extension 58' of the metal cap 58 can extend into the top of the air spacer 60. Furthermore, the extension 58' can be spaced apart from the dielectric layer 34, or can extend far enough to contact the nearest portion of the dielectric layer 34. Therefore, the metal cap 58 can keep the air spacer 60 open, or can partially or completely seal the air spacer 60.

[0046] The air spacer 60 has a k-value equal to 1.0, which is smaller than that of other dielectric materials, even low-k dielectric materials. With the formation of the air spacer, the parasitic capacitance between adjacent conductive features 56 decreases.

[0047] like Figure 12 As shown, the air spacer 60 can extend to the top surface of the underlying features (e.g., the dielectric layer (e.g., ILD 28) and the conductive features (e.g., contact plug 30)). This is because the horizontal portion of the sacrificial layer 44 deposits a protective layer 48 (in... Figure 6 Removed before (in) Figure 5Therefore, the protective layer 48 does not extend over the horizontal portion of the sacrificial layer 44. Thus, the protective ring 48' can extend all the way to the top surface of the underlying feature (e.g., the contact plug 30 (when the contact plug 30 is sufficiently wide) or the dielectric layer 28). Therefore, in Figure 12 In the structure shown, the protective ring 48' completely protects the sidewalls of the barrier layer 52, and no part of the barrier layer 52 is exposed to the air spacer 60. Therefore, oxygen cannot enter the bottom of the barrier layer 52 and cause it to oxidize.

[0048] In comparison, if the horizontal portions of both the sacrificial layer 44 and the protective layer 48 are removed after depositing the protective layer 48, the bottom of the protective layer 48 in the dashed region 62 will be replaced by some horizontal portions of the sacrificial layer 44. Therefore, after removing the sacrificial layer 44, the portion of the sacrificial layer 44 in the dashed region 62 will also be removed. The bottom sidewalls of the barrier layer 52 will be exposed to oxygen and the chemicals used to remove the sacrificial ring 44', resulting in oxidation and damage, thus increasing the resistance of the conductive features and reducing the performance of the resulting circuit.

[0049] According to some embodiments, after removing the sacrificial ring 44', a cleaning process is performed using a process gas. According to some embodiments, the process gas may include argon, N2, etc. The cleaning process can be performed for a period ranging from about 1 minute to about 10 minutes. Furthermore, a thermal annealing process can be performed, which may be performed simultaneously with the cleaning process, or before or after the cleaning process. In thermal annealing, the wafer temperature can be in the range of about 300°C to about 400°C. The cleaning process can remove moisture and prevent oxidation of the metal (e.g., the bottom of the barrier layer 52) (note that this is Embodiment 2).

[0050] Figure 13 The formation of the etch stop layer 64 is shown. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 228. The etch stop layer 64 contacts the metal cap 58 and seals the air spacer 60 (if it is not already sealed). According to some embodiments, the etch stop layer 64 may be formed of a material selected from SiN, SiC, SiON, SiOC, SiCN, or combinations thereof. The etch stop layer 64 may also include metal oxides, metal nitrides, etc. The etch stop layer 64 may be a single layer formed of a homogeneous material or a composite layer comprising multiple dielectric sublayers. According to some embodiments of this disclosure, the etch stop layer 64 is a composite layer that may include an AlN layer, a SiOC layer above the AlN layer, and an AlO layer above the SiOC layer. x Layers. The bottom layer, such as the AlN layer, prevents copper extrusion, and the top layer is used to stop etching.

[0051] Figures 14 to 16The formation of a dual damascene structure according to some embodiments is illustrated. (Reference) Figure 14 A dielectric layer 66 is deposited. The corresponding process is as follows: Figure 19 The process flow 200 shown is also illustrated as process 228. The dielectric layer 66 can be formed of a low-k dielectric material, which can be selected from candidates of the same (or different) group of materials used to form the dielectric layer 34. Trench 70 and via openings 68 are formed in the dielectric layer 66. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 230. According to some embodiments of this disclosure, a metal hard mask (not shown) is formed and patterned to define a pattern for trench 70. A photolithography process is performed to etch a dielectric layer 66 to form a via opening. The via opening extends from the top surface of the dielectric layer 66 to an intermediate level between the top and bottom surfaces of the dielectric layer 66. An anisotropic etching process is then performed using the metal hard mask as an etching mask to etch the dielectric layer 66 and form trench 70. Simultaneously with the formation of trench 70, the via opening extends downward to a metal cap 58, thereby forming a via opening 68. The etching for forming trench 70 can be performed using a time-mapping pattern. According to an alternative embodiment, via opening 68 and trench 70 are formed in separate photolithography processes. For example, in a first photolithography process, via opening 68 extending downward to metal cap 58 is formed. In a second photolithography process, trench 70 is formed.

[0052] refer to Figure 15 A patterned sacrificial layer 72 is formed, comprising sacrificial rings 72A and 72B. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 232. The process for forming the sacrificial layer 72 includes depositing a conformal sacrificial layer and then performing an anisotropic etching process to remove the horizontal portions of the conformal sacrificial layer. Candidate materials and process details are referenced. Figure 4 and Figure 5 The basic principles discussed are the same and will not be repeated here. The sacrificial layer 72 includes a first vertical portion in the trench 70 to form a first ring 72A, and a second vertical portion in the via opening 68 to form a second ring 72B. The first ring 72A is larger than the second ring 72B and is disconnected from the second ring 72B.

[0053] After forming the patterned sacrificial layer 72, a patterned protective layer 74 is formed. The corresponding process is as follows: Figure 19 The process flow 200 shown is illustrated as process 234. The process for forming the protective layer 74 further includes depositing a conformal protective layer, and then performing an anisotropic etching process to remove the horizontal portions of the conformal protective layer. Candidate materials and process details are in reference. Figure 6 and Figure 7The basic principles discussed are the same, and will not be repeated here. The protective layer 74 includes a first vertical portion in the trench 70 to form a first ring 74A, and a second vertical portion in the through-hole opening 68 to form a second ring 74B. The first ring 74A is larger than the second ring 74B and is disconnected from the second ring 74B.

[0054] Next, refer to Figure 16 76 is a deposition diffusion barrier layer and 78 is a metallic material. Materials and formation processes are referenced. Figure 9 and Figure 10 Similar processes will not be repeated here. After depositing the diffusion barrier layer 76 and the metal material 78, a planarization process is performed to form the vias 80 and the metal lines 82, which include the diffusion barrier layer 76 and the metal material 78. The corresponding processes are as follows... Figure 19 The process flow 200 shown is illustrated as process 236. Each of the vias 80 and metal wires 82 is surrounded by a guard ring and a sacrificial ring.

[0055] Figure 17A The removal of the sacrificial ring 72A is shown, thereby forming an air spacer 84, which appears as a ring when viewed from the top of wafer 20. The corresponding process is as follows: Figure 19 The process flow 200 shown is referred to as process 238. Removal can also be performed by an isotropic etching process. The resulting air spacer 84 can extend to the top surface of the portion below the dielectric layer 66 and can be exposed. The protective ring 74A extends to the top surface of the lower portion of the dielectric layer 66 and thus prevents oxidation of the bottom of the diffusion barrier layer 76 in the metal line 82.

[0056] Since the sacrificial ring 72B cannot be removed, it remains in the final structure. It should be understood that the sacrificial ring 72B will lead to an increase in parasitic capacitance compared to air spacers and low-k dielectric materials. However, via 80 is relatively short laterally and is most likely to have a longer distance from adjacent vias. Therefore, the adverse increase in parasitic capacitance is smaller than the reduction in parasitic capacitance due to the formation of air spacers 84. In other words, the reduction in parasitic capacitance far outweighs the increase.

[0057] Figure 17A The formation of the metal cap 86 is further illustrated, which can be formed from materials and methods selected from the same group of candidate materials and candidate methods for forming the metal cap 58, respectively. The metal cap 86 can be formed before or after the formation of the air spacer 84, similar to... Figure 11A and Figure 11BThe embodiment shown. Furthermore, when the metal cap 86 is formed after the air spacer 84 is formed, the extension portion 86' (of the metal cap 86) can be formed and extend below the top surface of the dielectric layer 66. Alternatively, when the metal cap 86 is formed before the air spacer 84 is formed, the entire sacrificial layer 72, including the extension portion 86' directly above the air spacer 84, will not extend below the top surface of the dielectric layer 66. An etch stop layer 88 can then be deposited.

[0058] Figure 17B The formation of a gapless via 80' and a metal line 82' according to an alternative embodiment is shown. These embodiments are similar to those described above. Figure 17A The illustrated embodiment differs in that no sacrificial layer and protective layer are formed for the via 80' and the metal line 82', and therefore no air spacers are formed. Thus, the via 80' and the metal line 82' are in solid contact with the sidewalls of the surrounding dielectric layer 66. It should be understood that, although Figure 17B The diagram shows a gapless via 80' and metal line 82' located directly above conductive feature 56, but according to alternative embodiments, such as... Figure 17A The air spacer 84 shown can be formed in a dielectric layer directly above the dielectric layer 34, while the air gapless via 80' and metal line 82' are formed in a dielectric layer above the layer in which the air spacer 84 is formed. This is because the parasitic capacitance problem of the upper metal layer is not as severe as that of the lower metal layer, and therefore an air spacer is formed in the lower metal layer, while no air spacer is formed in the upper metal layer.

[0059] Figure 17C A top view is shown of an air spacer 60 or 84, a protective ring 48' or 74A, and a corresponding conductive feature 56 or 82 according to some embodiments. Figure 17C As shown, air spacers 60 or 84 can form a complete loop around the respective conductive features 56 / 82. Air spacers 60 or 84 can have a substantially uniform width W1' (e.g., varying by less than about 10%). The width W1' can be measured at the midpoint height of the respective air spacers 60 and 84. The width W1' of air spacer 60 can be the same as or different from the width W1' of air spacer 84. Furthermore, when viewed in a cross-sectional view, air spacer 60 can have a substantially uniform width from top to bottom (e.g., varying by less than about 20% or less than about 10%), and air spacer 84 can have a substantially uniform width from top to bottom (e.g., varying by less than about 20% or less than about 10%).

[0060] Figure 18An air spacer is shown forming around and contacting the source / drain contact plug 98 and the gate stack 92. According to some embodiments, a transistor 90 is formed on the top surface of a semiconductor substrate 24. The transistor 90 includes a gate stack 92 and a source / drain region 94. A source / drain silicide region 96 is formed over and contacts the source / drain region 94. A source / drain contact plug 98 is formed over and connected to the source / drain silicide region 96. According to some embodiments, a conductive feature 56 is formed over and connected to the gate stack 92 and the source / drain contact plug 98, with an air spacer 60 surrounding the conductive feature 56.

[0061] The embodiments of this disclosure have several advantageous features. By forming air spacers, parasitic capacitance between adjacent conductive features can be reduced. By performing anisotropic etching on the sacrificial layer prior to the deposition and anisotropic etching of the protective layer, the protective layer can extend to the top surface of the underlying feature without leaving any gaps therebetween. This prevents oxidation and damage to the bottom of conductive features, such as barrier layers for conductive features.

[0062] According to some embodiments of this disclosure, a method includes: etching a dielectric layer to form an opening, wherein a first conductive feature beneath the dielectric layer is exposed in the opening; depositing a sacrificial spacer layer extending into the opening; performing a first etching process to etch the sacrificial spacer layer, wherein a first bottom portion of the sacrificial spacer layer at the bottom of the opening is removed to expose the first conductive feature, and a first vertical portion of the sacrificial spacer layer in the opening and on the sidewalls of the dielectric layer is retained to form a sacrificial ring; depositing a protective layer extending into the opening and over the sacrificial ring; performing a second etching process to etch the protective layer, wherein a second bottom portion of the protective layer is removed to expose the first conductive feature, and a second vertical portion of the protective layer in the opening is retained to form a protective ring; forming a second conductive feature in the opening, wherein the second conductive feature is surrounded by the sacrificial ring and is over and electrically coupled to the first conductive feature; and removing the sacrificial ring to form an air spacer. In one embodiment, depositing the sacrificial spacer layer includes a conformal deposition process. In one embodiment, the method further includes: forming a metal cap layer over the second conductive feature, wherein the metal cap layer includes an extension extending into the air spacer. In one embodiment, the first etching process and the second etching process include anisotropic etching processes. In one embodiment, depositing a sacrificial spacer layer includes depositing a silicon layer. In one embodiment, after forming the opening, the top surface of the underlying feature is exposed, and wherein the guard ring includes a bottom surface in solid contact with the top surface. In one embodiment, the guard ring includes a dielectric material. In one embodiment, the guard ring includes a conductive material. In one embodiment, forming the second conductive feature includes: depositing a conductive barrier layer extending into the opening and in contact with the guard ring; and depositing a conductive region on the conductive barrier layer. In one embodiment, the second conductive feature is completely separated from the air spacer by the guard ring. In one embodiment, the opening includes a trench and a via opening located below the trench, the sacrificial ring is located in the trench, and the first etching process further forms an additional sacrificial ring in the via opening. In one embodiment, the guard ring includes a sidewall facing the air spacer.

[0063] According to some embodiments of this disclosure, a structure includes: a first conductive feature; a first etch stop layer over the first conductive feature; a dielectric layer over the first etch stop layer; a second conductive feature in the dielectric layer and the first etch stop layer, wherein the second conductive feature is over and in contact with the first conductive feature; an air spacer surrounding the second conductive feature, wherein sidewalls of the second conductive feature are exposed to the air spacer; and a guard ring surrounding the second conductive feature, wherein the guard ring completely separates the second conductive feature from the air spacer. In one embodiment, the structure further includes: an additional dielectric layer, wherein the first conductive feature is in the additional dielectric layer, and wherein the guard ring has a bottom surface in contact with at least one of the first conductive feature and the additional dielectric layer. In one embodiment, the structure further includes: a second etch stop layer over and in contact with the dielectric layer and the second conductive feature. In one embodiment, the guard ring completely separates the second conductive feature from the air spacer, wherein no portion of the second conductive feature is exposed to any portion of the air spacer. In one embodiment, the guard ring comprises a conductive material.

[0064] According to some embodiments of this disclosure, a structure includes: a first dielectric layer; a first conductive feature in the first dielectric layer; a second conductive feature above and electrically coupled to the first conductive feature, wherein the second conductive feature includes a diffusion barrier layer; and a metallic material surrounded by the diffusion barrier layer; a protective layer surrounding and contacting the second conductive feature, wherein the protective layer is in contact with the top surface of at least one of the first dielectric layer and the first conductive feature; an air spacer surrounding the protective layer; and a dielectric layer surrounding the air spacer. In one embodiment, the protective layer includes a dielectric material. In one embodiment, the second conductive feature is completely separated from the air spacer by the protective layer.

[0065] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0066] Example 1 is a method of forming a semiconductor device, comprising: etching a dielectric layer to form an opening, wherein a first conductive feature beneath the dielectric layer is exposed in the opening; depositing a sacrificial spacer layer extending into the opening; performing a first etching process to etch the sacrificial spacer layer, wherein a first bottom portion of the sacrificial spacer layer at the bottom of the opening is removed to expose the first conductive feature, and a first vertical portion of the sacrificial spacer layer in the opening and on the sidewalls of the dielectric layer is retained to form a sacrificial ring; depositing a protective layer extending into the opening and on the sacrificial ring; performing a second etching process to etch the protective layer, wherein a second bottom portion of the protective layer is removed to expose the first conductive feature, and a second vertical portion of the protective layer in the opening is retained to form a protective ring; forming a second conductive feature in the opening, wherein the second conductive feature is surrounded by the sacrificial ring and is above and electrically coupled to the first conductive feature; and removing the sacrificial ring to form an air spacer.

[0067] Example 2 is the method described in Example 1, wherein depositing the sacrificial spacer layer comprises a conformal deposition process.

[0068] Example 3 is the method of Example 1, further comprising: forming a metal cap layer over the second conductive feature, wherein the metal cap layer includes an extension extending into the air spacer.

[0069] Example 4 is the method described in Example 1, wherein the first etching process and the second etching process include anisotropic etching processes.

[0070] Example 5 is the method described in Example 1, wherein depositing the sacrificial spacer layer includes depositing a silicon layer.

[0071] Example 6 is the method of Example 1, wherein, after the opening is formed, the top surface of the underlying feature is exposed, and wherein the protective ring includes a bottom surface that is in solid contact with the top surface.

[0072] Example 7 is the method described in Example 1, wherein the guard ring comprises a dielectric material.

[0073] Example 8 is the method described in Example 1, wherein the protective ring comprises a conductive material.

[0074] Example 9 is the method described in Example 1, wherein forming the second conductive feature includes:

[0075] A conductive barrier layer is deposited, extending into the opening and contacting the protective ring; and

[0076] A conductive region is deposited on the conductive barrier layer.

[0077] Example 10 is the method of Example 1, wherein the second conductive feature is completely separated from the air spacer by the protective ring.

[0078] Example 11 is the method of Example 1, wherein the opening includes a trench and a via opening located below the trench, the sacrificial ring is located in the trench, and the first etching process further forms an additional sacrificial ring in the via opening.

[0079] Example 12 is the method of Example 11, wherein the protective ring includes a sidewall facing the air gap.

[0080] Example 13 is a semiconductor device comprising: a first conductive feature; a first etch stop layer over the first conductive feature; and a dielectric layer over the first etch stop layer.

[0081] A second conductive feature is located in the dielectric layer and the first etch stop layer, wherein the second conductive feature is above and in contact with the first conductive feature; an air spacer surrounds the second conductive feature, wherein the sidewalls of the second conductive feature are exposed to the air spacer; and a protective ring surrounds the second conductive feature, wherein the protective ring completely separates the second conductive feature from the air spacer.

[0082] Example 14 is the semiconductor device of 13, further comprising: an additional dielectric layer, wherein the first conductive feature is in the additional dielectric layer, and wherein the guard ring has a bottom surface in contact with at least one of the first conductive feature and the additional dielectric layer.

[0083] Example 15 is the semiconductor device of 13, further comprising: a second etch stop layer, over and in contact with the dielectric layer and the second conductive feature.

[0084] Example 16 is the semiconductor device of 13, wherein the guard ring completely separates the second conductive feature from the air spacer, wherein no part of the second conductive feature is exposed to any part of the air spacer.

[0085] Example 17 is the semiconductor device described in 13, wherein the guard ring comprises a conductive material.

[0086] Example 18 is a semiconductor device comprising: a first dielectric layer; a first conductive feature in the first dielectric layer; a second conductive feature above and electrically coupled to the first conductive feature, wherein the second conductive feature includes: a diffusion barrier layer; and a metallic material surrounded by the diffusion barrier layer; a protective layer surrounding and contacting the second conductive feature, wherein the protective layer is in contact with the top surface of at least one of the first dielectric layer and the first conductive feature; an air spacer surrounding the protective layer; and a dielectric layer surrounding the air spacer.

[0087] Example 19 is the semiconductor device described in 18, wherein the protective layer comprises a dielectric material.

[0088] Example 20 is the semiconductor device described in 18, wherein the second conductive feature is completely separated from the air spacer by the protective layer.

Claims

1. A method for forming a semiconductor device, comprising: The dielectric layer is etched to form an opening, wherein a first conductive feature beneath the dielectric layer is exposed in the opening; The deposition extends into the sacrificial spacer layer within the opening; A first etching process is performed to etch the sacrificial spacer layer, wherein a first bottom portion of the sacrificial spacer layer at the bottom of the opening is removed to expose the first conductive feature, and a first vertical portion of the sacrificial spacer layer in the opening and on the sidewall of the dielectric layer is retained to form a sacrificial ring. The deposition extends into the opening and into the protective layer on the sacrificial ring; A second etching process is performed to etch the protective layer, wherein a second bottom portion of the protective layer is removed to expose the first conductive feature, and a second vertical portion of the protective layer in the opening is retained to form a protective ring; A second conductive feature is formed in the opening, wherein the second conductive feature is surrounded by the sacrificial ring and is above and electrically coupled to the first conductive feature; and The sacrificial ring is removed to form an air spacer.

2. The method of claim 1, wherein, The deposition of the sacrificial spacer layer includes a conformal deposition process.

3. The method of claim 1, further comprising: A metal cap layer is formed over the second conductive feature, wherein the metal cap layer includes an extension that extends into the air spacer.

4. The method of claim 1, wherein, The first etching process and the second etching process include anisotropic etching processes.

5. The method of claim 1, wherein, The deposition of the sacrificial spacer layer includes a deposited silicon layer.

6. The method of claim 1, wherein, After the opening is formed, the top surface of the underlying feature is exposed, and the protective ring includes a bottom surface that is in solid contact with the top surface.

7. The method according to claim 1, wherein, The protective ring comprises a dielectric material.

8. The method according to claim 1, wherein, The protective ring comprises a conductive material.

9. The method according to claim 1, wherein, Forming the second conductive feature includes: A conductive barrier layer is deposited, extending into the opening and contacting the protective ring; and A conductive region is deposited on the conductive barrier layer.

10. The method according to claim 1, wherein, The second conductive feature is completely separated from the air spacer by the protective ring.

11. The method according to claim 1, wherein, The opening includes a trench and a via opening located below the trench, the sacrificial ring is located in the trench, and the first etching process further forms an additional sacrificial ring in the via opening.

12. The method according to claim 11, wherein, The protective ring includes a sidewall facing the air gap.

13. A semiconductor device, comprising: First electrical conductivity characteristic; A first etch stop layer is formed on top of the first conductive feature; A dielectric layer is placed above the first etch stop layer; A second conductive feature is present in the dielectric layer and the first etch stop layer, wherein the second conductive feature is above and in contact with the first conductive feature; An air spacer surrounds the second conductive feature, wherein the sidewalls of the second conductive feature are exposed to the air spacer; and A protective ring surrounds the second conductive feature, wherein the protective ring completely separates the second conductive feature from the air spacer.

14. The semiconductor device according to claim 13, further comprising: An additional dielectric layer, wherein the first conductive feature is in the additional dielectric layer, and wherein the guard ring has a bottom surface that contacts at least one of the first conductive feature and the additional dielectric layer.

15. The semiconductor device according to claim 13, further comprising: A second etch stop layer is placed on top of and in contact with the dielectric layer and the second conductive feature.

16. The semiconductor device according to claim 13, wherein, The protective ring completely separates the second conductive feature from the air spacer, wherein no part of the second conductive feature is exposed to any part of the air spacer.

17. The semiconductor device according to claim 13, wherein, The protective ring comprises a conductive material.

18. A semiconductor device, comprising: First dielectric layer; A first conductive feature is present in the first dielectric layer; A second conductive feature is located on top of and electrically coupled to the first conductive feature, wherein the second conductive feature includes: diffusion barrier layer; and Metallic material, surrounded by the diffusion barrier layer; A protective layer surrounds and contacts the second conductive feature, wherein the protective layer contacts the top surface of at least one of the first dielectric layer and the first conductive feature; Air spacers surrounding the protective layer; and A dielectric layer surrounds the air spacer.

19. The semiconductor device according to claim 18, wherein, The protective layer comprises a dielectric material.

20. The semiconductor device according to claim 18, wherein, The second conductive feature is completely separated from the air spacer by the protective layer.

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