Semiconductor power module comprising graphene

Abstract

The invention relates to a semiconductor power module comprising an electrically and thermally conductive substrate (14) and a semiconductor chip (12), and wherein a first graphene layer (32) is placed between the semiconductor chip (12) and the substrate (14) in electrical and thermal contact with a first side of the substrate (14). The cooling of the semiconductor power module is thus improved.

Description

[0001] This application is a divisional application of the invention patent application with application number 201780084256.7, application date December 13, 2017, and invention title "Semiconductor power module including graphene". Technical Field

[0002] This invention relates to a semiconductor power module. Background Technology

[0003] In high-power applications, such as in power transmission and distribution systems, semiconductor components, typically in the form of semiconductor chips or dies, are used for various purposes, such as converting direct current to alternating current and forming circuit breakers.

[0004] Due to the high voltage and high current ratings used, a large number of chips are required. Therefore, several such chips are typically placed in a semiconductor power module, where the chips in the module can be connected in parallel and / or in series.

[0005] Examples of semiconductor power modules can be found in EP 2544229, WO 2012 / 107482, US 6,426,561 and US 9,099,567.

[0006] Therefore, the current levels in such applications can be high. In some cases, semiconductor components may also be switched frequently. Overall, these factors can lead to high power losses in the components.

[0007] Therefore, cooling is an important aspect of semiconductor power modules. Summary of the Invention

[0008] Therefore, one object of the present invention is to improve the cooling of semiconductor chips in semiconductor power modules.

[0009] This objective is achieved by a semiconductor power module comprising a conductive and thermally conductive substrate and a semiconductor chip, wherein a first graphene layer is present between the semiconductor chip and the substrate, and is in electrical and thermal contact with a first side of the substrate.

[0010] Graphene has improved the cooling of semiconductor chips due to its excellent thermal conductivity.

[0011] According to the first variant, the semiconductor power module also includes a second graphene layer on a second opposite side of the substrate, which helps to improve cooling.

[0012] The thickness of at least the first layer of graphene can be in the range of 1nm-10nm, preferably in the range of 2nm-4nm.

[0013] According to another variation, a first metal layer with a low melting point may be present between the chip and the first graphene layer, which has the advantage of improving reliability in entering short-circuit fault modes.

[0014] Furthermore, the first metal layer may include a metal or metal alloy layer, which may be aluminum and / or silver. More specifically, the alloy may be an aluminum-silver alloy or an aluminum-silicon carbide alloy.

[0015] According to another variation, the first metal layer may be disposed on a first side of the chip, and a second metal layer having a low melting point may be disposed on a second opposite side of the chip to further enhance the reliability of entering the short-circuit fault mode.

[0016] The melting points of the first and second metal layers can be in the range of 500℃-700℃.

[0017] According to another variation, the semiconductor power module may include a top electrode and an upper substrate above the second metal layer. In this case, the substrate may form the bottom electrode.

[0018] Semiconductor chips can advantageously be silicon carbide chips. The substrate can also be molybdenum.

[0019] According to another variation, the semiconductor power module may include multiple additional semiconductor chips, each of which is connected to the substrate via a first graphene layer. Attached Figure Description

[0020] The invention will now be described with reference to the accompanying drawings, wherein...

[0021] Figure 1 A semiconductor power module comprising multiple sub-modules is schematically illustrated.

[0022] Figure 2 The diagram schematically illustrates a sub-module comprising a substrate and multiple semiconductor chips, and

[0023] Figure 3 A portion of a submodule provided in association with a chip is shown schematically. Detailed Implementation

[0024] The present invention relates to semiconductor power modules for use, for example, in high-voltage applications (such as in power transmission or distribution systems) with semiconductor chips or dies.

[0025] In such a module, multiple semiconductor chips are provided in a structure that connects chips in parallel or in series.

[0026] In the field of semiconductor power modules, wide-bandgap semiconductors such as silicon carbide (SiC) semiconductors are now considered the most popular candidate for a wide range of power electronics applications in power transmission and distribution systems. Therefore, it offers a potential replacement for the main silicon (Si) material counterparts for various semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), and integrated gate commutated thyristors (IGCTs), primarily due to their higher electric field strength (i.e., ten times that of Si), wider bandgap (three times that of Si), higher thermal conductivity (three times that of Si), and higher carrier velocity (twice that of Si). Earlier power electronic components used in various power converter topologies in power transmission and distribution systems were primarily limited to Si-based power switches, such as IGBTs and IGCTs. From a power system design perspective, semiconductor chips that achieve reduced power losses, provide higher power density, facilitate compact converter designs, lower environmental impact, and simultaneously lower overall system costs will be considered key technological aids for very high-power applications. Considering these key performance indicators, finding good solutions based on the selected semiconductor technology better meets the requirements given by the specific topology, and the standardization of converter building block design represents a step forward in product development.

[0027] The recent trend towards high-power electronic devices has led to increased demand for both improved power converter efficiency and reduced power electronic component coverage. Therefore, better thermal management is a prerequisite for achieving this, especially when multiple power chips with high blocking voltages are placed in parallel to achieve high current capabilities. This also results in higher power loss density in IGBT dies and power modules due to the denser packaging of the dies themselves. Furthermore, the increased switching frequency and rated voltage of IGBTs also lead to higher power losses at the die layer. Therefore, adequate cooling under continuous operation is crucial. Inadequate cooling can limit device performance.

[0028] Therefore, during operation, such semiconductor chips can carry high currents and may sometimes be switched frequently, thus generating a significant amount of heat. This makes cooling important.

[0029] Furthermore, for power modules used in modular multilevel converters (MMCs), such as in high-voltage direct current (HVDC) applications, the switching devices (i.e., Si-IGBTs) must carry load current under short-circuit fault mode (SCFM) conditions for a period of time until the next maintenance. Therefore, a very stable short-circuit condition must be established and maintained through the faulty module until the system is repaired. This SCFM mode has significant implications for power module design because a single faulty chip and its contact system should account for up to at least 1500 A (phase-rms) of the entire module current, where rms represents the root mean square (RMS).

[0030] In power modules, reliable short circuits are typically achieved using a metal layer with a low melting point, such as an aluminum-silver (Al-Ag) alloy placed above the chip. When a short circuit occurs, this metal layer melts and alloys with the silicon of the chip due to the high initiation energy over a short period. Therefore, this layer forms a low-resistance, stable alloy with the Si die. Note that metals like silver and aluminum are generally preferred because they form a low-melting-point eutectic alloy with the underlying silicon die.

[0031] However, if SiC semiconductor chips are used in semiconductor power modules, the operation of switching devices in MMC under SCFM conditions may become unpredictable because the melting point of SiC material is higher than that of Si-corresponding materials, and therefore the formation of a stable short-circuit collector-emitter alloy may be problematic.

[0032] Therefore, reliable short circuits are also important.

[0033] The present invention addresses the two areas mentioned above, namely, the field of improved cooling and the field of improved reliability of SFCM mode, particularly with respect to SiC chips.

[0034] A semiconductor power module may include a power module comprising one or more sub-modules, wherein such sub-modules may be electrically connected in series and / or in parallel with each other. A semiconductor power module 10 comprising six sub-modules 11 is described in... Figure 1 As shown in the diagram. It should be understood that a power module may include more or fewer sub-modules than the power module shown.

[0035] Example submodule 11 of semiconductor power module 10 Figure 2 It is shown schematically in the middle.

[0036] In submodule n, there is a substrate 14 made of a metal such as molybdenum and surrounded by an inner frame 30 and an outer frame 31, where the frames can be made of a plastic material. Multiple semiconductor chips 12 are placed on this substrate 14. In this example, there are six chips arranged in two rows. In this figure, only one row with three chips is shown. Furthermore, the first side of the substrate 14 facing the chips 12 is covered by a first material portion 18, while the second opposite side of the substrate 14 is covered by a second material portion 20. Additionally, each chip 12 is connected to an upper plate 16 via a corresponding third material portion 22, a current bypass element 24 typically made of copper, and a spring 26. Alternatively, the copper upper plate 16 can be pressed downwards onto the upper portion of the current bypass element 24 and biased towards the lower portion of the bypass element 24 via the spring 26 to ensure current contact between the chip 12 and the upper plate 16 via the third material portion 22 and current contact between the chip 12 and the substrate 14 via the first material portion 18.

[0037] It is worth mentioning here that, Figure 2 The structure shown is just one way to implement the submodules, and the chips can be connected in series or in parallel.

[0038] Figure 3 A more detailed illustration shows one of the semiconductor chips used in semiconductor chip 12. Figure 2 The relevant parts of the structure of submodule 11 in the middle.

[0039] In this configuration, the first material portion 18 beneath the chip 12 includes a first graphene layer 32 that is in electrical and thermal contact with a first side of the substrate 14. The graphene layer 32 is advantageously 1 nm to 10 nm thick, and preferably 2 nm to 4 nm thick. The first material portion 18 also includes a first metal layer 34 with a low melting point, located above the first graphene layer 32 and below the chip 12. This melting point can be in the range of 500°C to 700°C. The layer 34, positioned above the graphene layer 32, can be an aluminum- or silver-based layer, or it can be an aluminum- or silver-based alloy, such as an aluminum-silver alloy or an aluminum-silicon carbide alloy. Therefore, this layer can be Al or an Al-Ag alloy or AlSiC, or any other suitable metal alloy with high thermal and electrical conductivity and a low melting point (e.g., <700°C or 650°C). The thermal conductivity of the first metal layer 34 can be higher than 1.5 W / cm-K and advantageously in the range of 1.5 W / cm-K to 4.5 W / cm-K, wherein the thermal conductivity can be 2.0 W / cm-K when using Al, 4.2 W / cm-K when using Ag, and in the range of 1.8 W / cm-K to 2.1 W / cm-K when using AlSiC.

[0040] The second material portion 20 further includes a second graphene layer that is in electrical and thermal contact with a second side of the substrate 14, the layer being advantageously 1 nm to 10 nm thick, and preferably 2 nm to 4 nm thick.

[0041] Furthermore, the third material portion 22 includes a second metal layer 36 having a low melting point (such as aluminum or an aluminum-silver alloy) above the chip 12, an upper substrate in the form of a layer 38 having a high melting point and good conductivity (such as molybdenum) above the layer 36, and a chip terminal contact material 40 above the layer 36, wherein the chip terminal contact 40 may be, for example, an emitter-side contact made of copper. Thus, the substrate 14 may also form a collector-side contact. It should be recognized here that other methods exist to implement the third material portion 22. The thermal conductivity of the second metal layer 36 can be higher than 1.5 W / cm-K and advantageously in the range of 1.5 W / cm-K to 4.5 W / cm-K, wherein the thermal conductivity can be 2.0 W / cm-K when using Al, 4.2 W / cm-K when using Ag, and in the range of 1.8 W / cm-K to 2.1 W / cm-K when using AlSiC.

[0042] Finally, in this embodiment, the semiconductor chip is a silicon carbide chip with a high melting point in the range of 2400K.

[0043] The power loss in a SiC chip can be high. Two graphene layers 20 and 32 with excellent thermal conductivity are provided to dissipate such heat and thus improve thermal management during normal continuous operation of the chip 12.

[0044] Therefore, graphene layers 20 and 32 are inserted around a molybdenum substrate 14, which is thus sandwiched between graphene layers 20 and 32. A comparative evaluation of 2D graphene with other conventional semiconductor materials is shown in Table I below. As can be seen, graphene exhibits superior electrical and thermal properties compared to other semiconductors such as silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), and gallium nitride (GaN).

[0045]

[0046] Table I

[0047] These properties of graphene are summarized as follows:

[0048] An extremely thin sheet of material, yet still incredibly strong (five times stronger than steel and much lighter).

[0049] Graphene is a half-metal or zero-bandgap semiconductor.

[0050] An excellent thermal conductor (even far superior to SiC, copper, diamond, etc.).

[0051] It is more transparent than ITO (i.e., indium tin oxide, used in photovoltaics and touch screen displays) above a large spectral band, and

[0052] The ease of growth / manufacturability on metal or semiconductor substrates. Growth mechanisms using various techniques are widely accepted.

[0053] The purpose of the first metal layer 34 and the second metal layer 36 having low melting points is to obtain a short-circuit fault mode. Both the first metal layer 34 and the second metal layer 36 having low melting points will melt during a short circuit and form a conductive alloy with the semiconductor chip 12.

[0054] Because there are two such metal layers on both sides of the chip, short circuits are more reliable than if there were only one such metal layer.

[0055] SiC chips are typically thinner than traditional Si-IGBT dies. Similarly, the large difference in CTE between the upper / lower metals 36 and 34 (e.g., the coefficients of thermal expansion (CTE) of Al, Ag, and AlSiC are 19, 23, and 7.5, respectively) and the SiC chip (i.e., CTE of 2.7), combined with the heat generated due to high current density and high temperature, can damage the chip surface and thus cause short-circuit conditions. Note that AlSiC (with 63% SiC by volume) has a melting point of 557°C–613°C and a thermal conductivity that remains around 1.7 W / cm-K–2.1 W / cm-K.

[0056] Therefore, two new features have been introduced.

[0057] 1: A new layer 34 of a suitable metal and / or metal alloy with low melting point and high thermal and electrical conductivity is placed under the SiC chip. This will help to achieve stable short-circuit formation (SCFM) in the event of SiC chip failure.

[0058] 2: One or two thin layers 20 and 32 of graphene material around the molybdenum base plate 14 for improved cooling and better thermal management of the power module.

[0059] Since the first layer of graphene has high electrical and thermal conductivity, it is clear that the reliability of entering SCFM mode is not compromised. Therefore, improved cooling is achieved while maintaining the reliability of entering SCFM mode under short-circuit conditions.

[0060] In a similar manner, the first metal layer has sufficiently high thermal conductivity to aid in the cooling of the graphene layer in the chip, while its ability to safely enter SCFM mode remains unaffected.

[0061] As mentioned above, the chip is advantageously a SiC chip. However, it should be recognized that the chip can also be another type of chip made of any of the aforementioned semiconductor materials, such as, for example, a Si chip.

[0062] Furthermore, semiconductor chips are advantageously implemented as switches, such as transistors like IGBTs or MOSFETs, or thyristors like IGCTs.

[0063] Based on the preceding discussion, it is evident that the present invention can be varied in many ways.

[0064] Therefore, it should be understood that the present invention is limited only by the appended claims.

Claims

1. A semiconductor power module (10), comprising Conductive and thermally conductive substrate (14), Semiconductor chip (12), said semiconductor chip being implemented as a switch and being a silicon carbide chip, A first graphene layer (32) is formed between the semiconductor chip (12) and the substrate (14), wherein the layer (32) is in electrical and thermal contact with a first side of the substrate (14). A first metal layer (34) with a low melting point is provided on a first side of the chip (12) between the chip (12) and the first graphene layer (32). A second metal layer (36) with a low melting point is provided on the second opposite side of the chip (12). The upper substrate (38) on top of the second metal layer (36), The top electrode (40) on the top of the upper substrate (38), and The second graphene layer (20) on the second opposite side of the substrate (14), in, At least one of the first metal layer (34) and the second metal layer (36) has a melting point in the range of 500°C to 700°C, and The substrate (14) forms the collector-side contact of the switch, and the top electrode (40) forms the emitter-side contact of the switch. The first metal layer and the second metal layer are configured to obtain the short-circuit fault mode of the semiconductor chip. The first metal layer and the second metal layer form a conductive alloy with the semiconductor chip to carry the load current under short-circuit fault mode conditions. The semiconductor power module further includes an upper plate (16), a current bypass element (24), and a spring (26), wherein the spring is disposed between the upper and lower parts of the current bypass element. The semiconductor chip is connected to the upper plate via the second metal layer, the upper substrate, the top electrode, the current bypass element, and the spring. The upper plate presses downward onto the upper part of the current bypass element and is biased to the lower part of the current bypass element via a spring, in order to ensure current contact between the semiconductor chip and the upper plate via the second metal layer, the upper substrate, and the top electrode, and current contact between the semiconductor chip and the substrate via the first graphene layer and the first metal layer. The semiconductor power module (10) further includes a plurality of additional semiconductor chips, each of which is connected to the substrate (14) via the first graphene layer (32).

2. The semiconductor power module (10) according to claim 1, wherein, At least the thickness of the first graphene layer (32) is in the range of 1 nm to 10 nm.

3. The semiconductor power module (10) according to claim 1, wherein, At least the thickness of the first graphene layer (32) is in the range of 2nm-4nm.

4. The semiconductor power module (10) according to claim 3, wherein, At least one of the first metal layer (34) and the second metal layer (36) has a thermal conductivity higher than 1.5 W / cm-K.

5. The semiconductor power module (10) according to claim 4, wherein, The thermal conductivity is in the range of 1.5 W / cm-K to 4.5 W / cm-K.

6. The semiconductor power module (10) according to any one of claims 1-5, wherein the first metal layer comprises a metal layer or a metal alloy layer.

7. The semiconductor power module (10) according to claim 6, wherein, The first metal layer comprises aluminum and / or silver.

8. The semiconductor power module (10) according to any one of claims 1-5, wherein, The alloy is an aluminum-silver alloy or an aluminum-silicon carbide alloy.

9. The semiconductor power module (10) according to any one of claims 1-5, wherein the substrate (14) is molybdenum.

10. The semiconductor power module according to any one of claims 1-5, wherein, Under the short-circuit fault mode conditions, a short circuit is formed between the collector-side contact and the emitter-side contact of the switch.

11. The semiconductor power module according to any one of claims 1-5, wherein, Under the short-circuit fault mode conditions, the load current is up to at least 1500A of the entire module current.

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